Chip verification method and system

Abstract

Embodiments of the present application relate to a chip verification method and system, the method comprising: performing initialization operation on the memory in the chip according to a preset operation instruction; loading a pre-compiled chip running file; initializing the minimum system of the chip, and then initializing each functional module in the chip; and after determining that the minimum system of the chip and each functional module are all initialized, performing verification operation on the chip according to the chip running file. Through the above implementation, the initialization operation on the memory in the chip is completed before the pre-compiled chip running file is loaded. Therefore, when each functional module in the chip is initialized, the initialization operation on the memory does not need to be performed again. The situation that a large amount of time is occupied due to the initialization operation on the memory when the functional module is initialized is avoided, and the utilization rate of the simulation device is greatly improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of power electronics, and particularly relate to a chip verification method and system. BACKGROUND

[0002] In the process of chip design, prototype verification of the chip is a very important link, which can find problems in the design before the chip is manufactured, and plays a crucial role in the success of chip design. Different verification platforms can be used for prototype verification of different modules and the whole system, wherein the main verification platforms include electronic design automation (EDA), emulation (a software that simulates the composition of each component in a system and truly simulates the running mechanism of the system), field programmable gate array (FPGA).

[0003] Since the scale that can be simulated by EDA is small and the simulation frequency is slow, EDA is mainly used for module-level or small system-level verification. In particular, in large-scale system-on-a-chip (SOC) design, EDA cannot meet the prototype verification of the chip, and must rely on large hardware accelerators such as emulation and FPGA.

[0004] When verifying the chip, the system in the simulation needs to be initialized first, and then the specific function can be verified. In some complex design SOC, many modules use a large number of static random access memory (SRAM) and memory units in the initialization stage. In order to ensure that the module can execute the operation instruction matched with the content in the corresponding memory when using the content in the memory, it is usually necessary to initialize the memory space such as memory unit and SRAM (if the memory does not perform the initialization operation, there may be random values or invalid contents left in the memory). Then reconfigure the memory content corresponding to the corresponding operation instruction in the memory.

[0005] However, in the prior art, when each functional module initializes the memory in the initialization stage, it takes a long time, especially in the initialization process of each functional module in a large SOC chip, it usually takes several hours or even longer to complete the zeroing operation of the memory space, which seriously reduces the efficiency of the whole chip simulation verification. For large SOC design, simulation equipment is often the most critical resource, so shortening the initialization time to improve the utilization rate of simulation equipment is the key to chip prototype verification. SUMMARY

[0006] The application provides a chip verification method and system to solve the technical problem that the initialization of the memory space corresponding to each functional module in the chip during the chip initialization process takes too long, seriously affecting the use efficiency of the simulation device for simulating and verifying the chip.

[0007] In a first aspect, the application provides a chip verification method, which is executed by a chip verification system, and the method comprises:

[0008] performing initialization operation on the memory in the chip according to a preset operation instruction;

[0009] loading a pre-compiled chip running file;

[0010] performing initialization on each functional module in the chip after the minimum system initialization of the chip;

[0011] performing verification operation on the chip according to the chip running file after determining that the minimum system and each functional module of the chip have all been initialized.

[0012] In a second aspect, the application provides a chip verification system, which comprises:

[0013] a processing module configured to perform initialization operation on the memory in the chip according to a preset operation instruction;

[0014] a loading module configured to load a pre-compiled chip running file;

[0015] the processing module is further configured to perform initialization on each functional module in the chip after the minimum system initialization of the chip;

[0016] a verification module configured to perform verification operation on the chip according to the chip running file after determining that the processing module has initialized the minimum system and each functional module of the chip.

[0017] The above technical solution provided by the embodiments of the application has the following advantages compared with the prior art:

[0018] The method provided by the embodiment of the application firstly performs initialization operation on the memory in the chip according to the preset operation instruction, and then loads the pre-compiled chip running file. After the minimum system of the chip is initialized, initialization is performed on each functional module in the chip. After it is determined that the minimum system of the chip and each functional module are all initialized, verification operation on the chip is performed according to the chip running file. According to the embodiment of the application, the initialization operation on the memory in the chip is completed before the pre-compiled chip running file is loaded. Therefore, when each functional module in the chip is initialized, the initialization operation on the memory does not need to be performed again. Therefore, the situation that a large amount of time is occupied by the initialization operation on the memory when the functional module is initialized is avoided, and the utilization rate of the simulation device is naturally greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A chip verification method flow diagram provided by the embodiment of the application;

[0020] Figure 2 A SOC system structure diagram provided by the application;

[0021] Figure 3 A structure diagram for establishing connection between the DUT and the control server provided by the application;

[0022] Figure 4 Another chip verification method flow diagram provided by the embodiment of the application;

[0023] Figure 5 Another chip verification method flow diagram provided by the embodiment of the application;

[0024] Figure 6 A chip verification method overall flow diagram provided by the application;

[0025] Figure 7 A chip verification system structure diagram provided by the embodiment of the application. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described below in connection with the drawings in the embodiments of the application. Obviously, the described embodiments are some but not all of the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the application.

[0027] For the purpose of conveniently understanding the embodiments of the present application, further explanation and description will be made in specific embodiments in combination with the accompanying drawings, which do not constitute limitation to the embodiments of the present application.

[0028] For the technical problems mentioned in the background, the embodiments of the present application provide a chip verification method, which is specifically described in Figure 1 .

[0029] Before introducing the chip verification method provided by the embodiments of the present application, first introduce a system schematic diagram of a SOC to which the embodiments of the present application are applied, which is specifically described in Figure 2 . The SOC system includes a general central processing unit CPU, some SOCs have only a single CPU, and some are CPU families to meet different use scenarios. For SOCs with different use scenarios, there are specific coprocessors to complete specific functions and tasks, and the CPU load is reduced through the coprocessor. In addition, it also includes a memory system, which is described in Figure 2 . Each coprocessor corresponds to an SRAM, and in addition to the SRAM, the memory system also includes a storage unit. In addition, in the commonly used SOC system, there are also key interfaces, such as high-speed Ethernet, ILKN, PCIe interface, low-speed serial port, etc. The key interface and the internal coprocessor module are connected through the internal interconnection bus, and the coprocessor is connected with the CPU and the storage unit through the internal interconnection network or bus.

[0030] In the chip verification system, that is, in the simulation environment, the chip in the simulation environment runs in the test device (Design under Test, referred to as DUT), such as FPGA. The control server is connected with the DUT through a high-speed interface, and the control server mainly completes the initialization configuration and verification of the chip in the simulation environment. Since there is a big difference between the chip in the simulation environment and the real running chip, in order to enable the DUT and the control server to be connected, a Speed Bridge needs to be used to match the speed. It is specifically described in Figure 3 .

[0031] In the chip verification, first need to do the necessary initialization work for the chip in the simulation environment, referred to as simulation chip, after the initialization work is completed, the specific function of the simulation chip can be verified. Generally, the initialization is divided into two parts, the first part of the initialization work is the necessary initialization of the simulation chip, which is also the minimum system initialization, this part of the initialization can be completed through the board support package (BSP) or firmware; the second part of the initialization is the initialization of other functional modules in the simulation chip, such as the initialization of some co-processors and network interfaces in the above figure, only after the completion of the second part of the initialization work, the simulation chip can work normally.

[0032] The first part of the initialization work is the premise of the second part of the initialization work, so the first part of the initialization work must be executed first, and then the second part of the initialization work can be executed. The second part of the initialization can be completed by the core in the chip verification system, or the external control server can be connected through the PCIe interface connected with the DUT to complete the initialization of the second part.

[0033] If the second part of the initialization work needs to be completed by the external control server, the PCIe interface initialization work needs to be completed during the minimum system initialization, so that the PCIe interface in the DUT acts as an EP device (EP device usually represents a serial or I / O device), and the control server acts as an RC device (used to connect CPU / memory subsystem and I / O device). After the PCIe initialization in the server system initialization stage, the RC device (control server) can perceive the corresponding EP device, add the corresponding driver, and then initialize it. The system initialization process is shown in Figure 4

[0034] Figure 4 The main components of the system initialization process include three parts: control server, Speed Bridge (high-speed interface), and DUT (simulation environment of the chip). The control server includes an APP for initializing the second part of the simulation chip and a PCIe driver for executing the APP operation instruction. The control server is connected to the Speed Bridge through the PCIe interface, and then connected to the PCIe interface in the DUT. Since there is a mapping relationship between the address of the PCIe interface and the internal address of the chip, address translation is usually required. Therefore, the address transmitted by the control server side needs to be translated through the address translation unit and connected to the internal interconnection bus. Through the internal interconnection bus, each module functional module can be accessed, and then initialized, configured and controlled.

[0035] ​In complex SoCs, many modules utilize a large amount of SRAM and memory units during the initialization phase. For example... Figure 4 The coprocessor in the simulation requires 512MB of memory to store relevant information in order to complete a function. To ensure the coprocessor can use this memory space subsequently, it needs to be initialized. However, if this memory initialization is performed during the coprocessor initialization, the technical problems described in the background will inevitably occur. Specifically, initializing the memory space during the functional module initialization will be extremely time-consuming, resulting in a frequency reduction ratio of thousands to thousands of times between the simulation and real environments. In other words, a task that takes one minute in a real environment might take thousands of minutes in a simulation. Memory initialization during the functional module initialization phase typically takes several hours or even longer.

[0036] Therefore, in this application, for example, during the functional module initialization phase, no steps are taken. Figure 4 The SRAM required by the coprocessor, as well as the memory space required by other functional modules, are initialized. However, initialization is performed at other stages using a different method. See details... Figure 1 As shown.

[0037] Figure 1 This is a schematic flowchart of a chip verification method provided by an embodiment of the present invention. The method is executed by a chip verification system, namely the DUT device mentioned above. The steps of the method include:

[0038] Step 110: Perform initialization operation on the memory in the chip according to the preset operation instructions.

[0039] Specifically, to avoid excessive time spent performing memory initialization operations during the initialization of various functional modules of the chip, which would affect the chip's verification efficiency, the initialization operation is performed directly on the chip's memory during the initial execution of the chip verification method.

[0040] Step 120: Load the pre-compiled chip runtime file.

[0041] Specifically, the chip runtime file is the file obtained by the chip verification system after compiling the Resistances-Transistors Logic (RTL) circuit in the chip.

[0042] Therefore, optionally, step 100 also needs to be performed before performing step 110:

[0043] Compile the pre-stored RTL language of the chip to obtain the chip's runtime file.

[0044] Considering that the chip running file can be continuously used when the RTL language does not change, the step 100 does not need to be executed each time in the method steps of the embodiment. Therefore, the step 100 is executed as an optional step.

[0045] Further optionally, considering that the running environment of the chip is a chip verification system, and the chip verification system also needs to perform an initialization operation, before the step 120 is executed, the method can further include:

[0046] performing an initialization operation on the chip verification system.

[0047] After the step 130, the minimum system of the chip is initialized, and each functional module of the chip is initialized.

[0048] Specifically, the initialization of the minimum system of the chip and the initialization of each functional module of the chip have been described before the embodiment of the method is introduced, and thus will not be described again.

[0049] After the step 140, it is determined that the initialization of the minimum system of the chip and each functional module is completed, and the verification operation on the chip is performed according to the chip running file.

[0050] Specifically, the initialization of the minimum system of the chip and the initialization of each functional module are prerequisites for the verification operation on the chip, and thus the verification operation on the chip is performed according to the chip running file only after it is determined that the initialization operation is completed.

[0051] The specific verification operation is not the focus of the present application, and thus will not be described again.

[0052] The chip verification method provided by the embodiment of the present application first performs an initialization operation on the memory in the chip according to a preset operation instruction, and then loads the pre-compiled chip running file. After the minimum system of the chip is initialized, each functional module of the chip is initialized. After it is determined that the initialization of the minimum system of the chip and each functional module is completed, the verification operation on the chip is performed according to the chip running file. According to the embodiment of the present application, the initialization operation on the memory in the chip is completed before the pre-compiled chip running file is loaded. Therefore, the initialization operation on the memory does not need to be performed again when each functional module in the chip is initialized. Thus, the situation that a large amount of time is occupied by the initialization operation on the memory when the functional module is initialized is avoided, and the utilization rate of the simulation device is naturally greatly improved.

[0053] On the basis of the above-mentioned embodiments, the embodiment of the present application further provides another chip verification method, and the content introduced in the above-mentioned embodiments will not be repeated in the embodiment. In the embodiment, it is considered that the bearing subject corresponding to the memory can be a virtual memory module, for example, a comprehensive module corresponding to a double data rate synchronous dynamic random access memory (DDR). Then, according to a preset operation instruction, initialization operation is performed on the memory in the chip, which can be implemented in the following manner, and details are shown in the following. Figure 5

[0054] Specifically, the chip running file includes program code corresponding to the preset operation instruction, and the program code is used to execute the preset operation instruction.

[0055] That is, when the RTL is compiled by the chip verification system, the preset operation instruction compiled by the staff can be compiled into the chip running file in the form of program code. During the compilation process, after the chip verification system reads the program code corresponding to the preset operation instruction, the preset operation instruction program code is automatically run to perform initialization operation on the memory in the chip.

[0056] That is, the method includes the following steps:

[0057] In step 510, the chip running file is read, and the program code corresponding to the preset operation instruction is obtained from the chip running file.

[0058] In step 520, the program code is run to perform initialization operation on the memory in the chip.

[0059] In this way, after the chip running file is obtained, the program code corresponding to the preset operation instruction can be directly read therefrom, and then after the program code is run, initialization operation can be performed on the memory in the chip. In a specific example, the initialization operation can be a clear operation or a full set operation. According to actual conditions, no further description is given. In the embodiment, it refers to a full clear operation.

[0060] In this way, during the compilation process, the program code for the memory initialization operation is directly edited, and after the program code is run, the initialization operation on the memory in the chip is completed. It is ensured that when the chip running file is loaded, the data in the memory is all zero, and subsequently, when the modules in the chip are initialized, the action of initializing the memory space by using software APP can be omitted, so as to greatly shorten the initialization time of the entire verification system and improve the verification efficiency of the modules, functions or the entire system.

[0061] and Figure 6 ​Corresponding to the illustrated embodiment, the embodiment of the application also provides another chip verification method embodiment, which is specifically described as follows Figure 6 In the method, the main consideration is that when the carrying body corresponding to the memory in the chip is an entity memory device, the initialization operation of the memory in the chip is performed according to the preset operation instruction.

[0062] For example, when the memory of the chip is a DDR particle, that is, the storage unit is a DDR particle, and the SRAM is obtained by DDR particle simulation. In this case, Figure 5 The corresponding embodiment will no longer be applicable. Then, how to perform the initialization operation of the memory in the chip according to the preset operation instruction? The specific solution can be seen from the following method flow, which includes the following steps.

[0063] Step 610, when performing the chip verification system initialization operation, the preconfigured preset operation instruction is acquired.

[0064] Step 620, according to the preset operation instruction, the initialization operation of the memory in the chip is performed by using the actual frequency corresponding to the entity memory device.

[0065] Specifically, the preconfigured preset operation instruction can be an operation instruction precompiled by a worker and pre-stored in a certain storage unit. The preset operation instruction is used to instruct the chip verification system to perform the initialization operation of the memory of the chip by using the actual frequency corresponding to the DDR particle. The trigger mechanism of the preset operation instruction is the chip verification system initialization operation.

[0066] Therefore, when performing the chip verification system initialization operation, the preconfigured preset operation instruction is acquired, and then the initialization operation of the memory in the chip is performed by using the actual frequency corresponding to the entity memory device according to the preset operation instruction.

[0067] Further optionally, when the carrying body corresponding to the memory in the chip is an entity memory device, since the frequency of the entity memory device is usually a frequency with G as a unit, and the frequency of the simulation environment is usually a frequency of several hundred K to several M. Therefore, after the entity memory device is accessed to the chip verification system, the entity memory device needs to be frequency-reduced to adapt the entity memory device to the simulation environment in the chip verification system.

[0068] In the embodiment, the initialization operation of the memory is not performed in the process of compiling the chip running file, but the initialization operation of the memory of the chip is performed by using the real running frequency of the DDR particle when the initialization of the chip verification system is performed, and then the compiled chip running file is loaded. The subsequent actions are the same as those of the embodiment of the chip verification method. Figure 5The operations performed in the corresponding embodiments are the same. Generally, it only takes a few minutes to clear the chip in this way, which greatly shortens the system initialization time compared to hours or even more in a simulation environment. Therefore, this way can also accelerate the chip verification work, can accelerate the iteration time between chip design and verification, and can improve the success rate of chip design.

[0069] The above is several specific embodiments of the chip verification method provided by the present application. The following describes the chip verification system embodiments provided by the present application. For details, see the following.

[0070] Figure 7 The chip verification system provided by the embodiment of the present application comprises a processing module 701, a loading module 702, and a verification module 703.

[0071] The processing module 701 is configured to perform an initialization operation on the memory in the chip according to a preset operation instruction.

[0072] The loading module 702 is configured to load a pre-compiled chip running file.

[0073] The processing module 701 is further configured to initialize each functional module in the chip after performing a minimum system initialization on the chip.

[0074] The verification module 703 is configured to perform a verification operation on the chip according to the chip running file when it is determined that the processing module 701 has completed the initialization of the minimum system and each functional module in the chip.

[0075] Optionally, the system further comprises a compiling module 704 configured to compile a pre-stored RTL language of the chip to obtain the chip running file.

[0076] Optionally, the processing module 701 is further configured to perform an initialization operation on the chip verification system.

[0077] Optionally, when the memory in the chip corresponds to a virtual memory module, the chip running file comprises program code corresponding to the preset operation instruction.

[0078] The processing module 701 is specifically configured to read the chip running file, and obtain the program code corresponding to the preset operation instruction from the chip running file.

[0079] The program code is run to perform the initialization operation on the memory in the chip.

[0080] Optionally, when the memory in the chip corresponds to a physical memory device, the processing module 701 is specifically configured to obtain the preset operation instruction pre-configured when performing the initialization operation on the chip verification system.

[0081] According to the preset operation instructions, the memory in the chip is initialized using the actual frequency corresponding to the physical memory device.

[0082] Optionally, the processing module 701 is further configured to, after the physical memory device is connected to the chip verification system, reduce the frequency of the physical memory device so that the physical memory device is adapted to the simulation environment in the chip verification system.

[0083] The functions performed by each component in the chip verification system provided in this invention have been described in detail in any of the above method embodiments, and therefore will not be repeated here.

[0084] This invention provides a chip verification system that first initializes the chip's memory according to preset operation instructions, and then loads a pre-compiled chip runtime file. After performing minimum system initialization on the chip, each functional module in the chip is initialized. Once the minimum system and all functional modules have been initialized, the chip verification operation is performed according to the chip runtime file. Through this embodiment, the memory initialization is completed before loading the pre-compiled chip runtime file. Therefore, when each functional module in the chip is initialized, there is no need to perform memory initialization again. This avoids the significant time spent on memory initialization during functional module initialization, thus greatly improving the utilization rate of the simulation equipment.

[0085] This application also provides an electronic device that carries the following: Figure 7 The chip verification system in the corresponding embodiment is used to execute the method flow corresponding to any of the above method embodiments. It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0086] The above are merely specific embodiments of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A chip verification method, characterized in that, The method is executed by a chip verification system, and the method includes: According to the preset operation instructions, the memory in the chip is initialized. Load the pre-compiled chip runtime file; After performing minimum system initialization on the chip, the functional modules in the chip are initialized. Once it is confirmed that the minimum system of the chip and each functional module have completed initialization, a verification operation on the chip is performed according to the chip's runtime file. When the memory in the chip corresponds to a virtual memory module, the chip's runtime file includes program code corresponding to the preset operation instructions. The initialization operation performed on the memory in the chip according to the preset operation instructions specifically includes: Read the chip's runtime file and obtain the program code corresponding to the preset operation instruction from the chip's runtime file; The program code is executed to perform the initialization operation on the memory in the chip.

2. The method according to claim 1, characterized in that, Before performing the memory initialization operation on the chip according to the preset operation instructions, the method further includes: The pre-stored RTL language of the chip's resistor-transistor logic circuit is compiled to obtain the chip's runtime file.

3. The method according to claim 2, characterized in that, When the carrier corresponding to the memory in the chip is a physical memory device, the initialization operation performed on the memory in the chip according to the preset operation instructions specifically includes: When performing the simulation system initialization operation, the pre-configured preset operation instructions are obtained; According to the preset operation instructions, the memory in the chip is initialized using the actual frequency corresponding to the physical memory device.

4. The method according to claim 3, characterized in that, The method further includes: After the physical memory device is connected to the chip verification system, the frequency of the physical memory device is reduced to adapt the physical memory device to the simulation environment in the chip verification system.

5. A chip verification system, characterized in that, The system includes: The processing module is used to perform initialization operations on the memory in the chip according to preset operation instructions; The loading module is used to load pre-compiled chip runtime files; The processing module is also used to initialize each functional module in the chip after performing minimum system initialization on the chip; The verification module is used to perform a verification operation on the chip according to the chip runtime file after it is determined that the processing module has completed the initialization of the chip minimum system and each functional module. When the memory in the chip corresponds to a virtual memory module, the chip's runtime file includes program code corresponding to the preset operation instructions; the processing module is specifically used for: Read the chip's runtime file and obtain the program code corresponding to the preset operation instruction from the chip's runtime file; The program code is executed to perform the initialization operation on the memory in the chip.

6. The system according to claim 5, characterized in that, The system also includes: The compilation module is used to compile the pre-stored RTL language of the resistive transistor logic circuit of the chip to obtain the chip's runtime file.

7. The system according to claim 6, characterized in that, When the memory in the chip corresponds to a physical memory device, the processing module is specifically used for: When performing the simulation system initialization operation, the pre-configured preset operation instructions are obtained; According to the preset operation instructions, the memory in the chip is initialized using the actual frequency corresponding to the physical memory device.

8. The system according to claim 7, characterized in that, The processing module is further configured to, after the physical memory device is connected to the chip verification system, reduce the frequency of the physical memory device so that the physical memory device is compatible with the simulation environment in the chip verification system.

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