Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a substrate, a single-layer connection structure on the substrate, and a multi-layer connection structure on the substrate. The multi-layer connection structure includes a plurality of first conductive layers and a plurality of second conductive layers stacked alternately. An upper surface of the multi-layer connection structure is substantially coplanar with an upper surface of the single-layer connection structure. A width of the multi-layer connection structure is smaller than a width of the single-layer connection structure.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. formal application No. 16 / 932,376, filed July 17, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device having a multilayer interconnect structure. In particular, it relates to a semiconductor device having the multilayer interconnect structure and a method for fabricating the semiconductor device. Background Technology

[0003] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components is continuously shrinking to meet the ever-increasing demands for computing power. However, this shrinking process introduces new and increasing problems, both in number and complexity. Therefore, challenges continue to emerge in improving quality, yield, performance, and reliability, while reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate; a single-layer interconnect structure disposed on the substrate; and a multilayer interconnect structure including a first conductive layer and a second conductive layer, the first conductive layer being disposed on the substrate and the second conductive layer being disposed on the first conductive layer. An upper surface of the multilayer interconnect structure is substantially coplanar with an upper surface of the single-layer interconnect structure, and the width of the multilayer interconnect structure is smaller than the width of the single-layer interconnect structure.

[0006] In some embodiments, the first conductive layer and the second conductive layer have opposing stress states.

[0007] Another embodiment of this disclosure provides a semiconductor device including a substrate; a single-layer interconnect structure disposed on the substrate; and a multilayer interconnect structure disposed on the substrate, including a plurality of first conductive layers and a plurality of second conductive layers stacked in an alternating manner. An upper surface of the multilayer interconnect structure is substantially coplanar with an upper surface of the single-layer interconnect structure, and a width of the multilayer interconnect structure is smaller than a width of the single-layer interconnect structure.

[0008] In some embodiments, the plurality of first conductive layers and the plurality of second conductive layers have relative stress states.

[0009] In some embodiments, the upper surfaces of each of the plurality of first conductive layers are rough.

[0010] In some embodiments, the thickness of the plurality of first conductive layers is greater than or equal to the thickness of the plurality of second conductive layers.

[0011] In some embodiments, the thickness of the plurality of first conductive layers is between about 5 nm and about 50 nm, and the thickness of the plurality of second conductive layers is between about 10 nm and about 150 nm.

[0012] In some embodiments, the sidewalls of the multilayer connection structure are generally vertical.

[0013] In some embodiments, the semiconductor element further includes a plurality of first spacers located on each sidewall of the multilayer interconnect structure.

[0014] In some embodiments, the semiconductor element further includes a plurality of porous spacers located on each sidewall of the multilayer interconnect structure.

[0015] In some embodiments, the porosity of the porous spacer is between about 10% and about 90%.

[0016] In some embodiments, the semiconductor element further includes a plurality of air gaps located between each sidewall of the multilayer interconnect structure and the first air gap.

[0017] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a multilayer interconnect structure on the substrate, wherein the multilayer interconnect structure includes a plurality of first conductive layers, and the plurality of first conductive layers are interleaved with a plurality of second conductive layers; and forming a single-layer interconnect structure on the substrate, wherein an upper surface of the single-layer interconnect structure is substantially coplanar with an upper surface of the multilayer interconnect structure, and a width of the single-layer interconnect structure is greater than a width of the multilayer interconnect structure.

[0018] In some embodiments, the plurality of first conductive layers and the plurality of second conductive layers have relative stress states.

[0019] In some embodiments, the step of forming the multilayer interconnect structure includes: interleaving multiple layers of first conductive material and multiple layers of second conductive material on the substrate; forming a hard mask layer on the multiple layers of first conductive material and multiple layers of second conductive material; patterning the hard mask layer; and performing an etching process using the hard mask layer as a mask to transform the multiple layers of first conductive material and multiple layers of second conductive material into the plurality of first conductive layers and the plurality of second conductive layers.

[0020] In some embodiments, the method for fabricating the semiconductor element further includes a step of forming a plurality of first spacers on each sidewall of the multilayer interconnect structure.

[0021] In some embodiments, the method for fabricating the semiconductor element further includes a step of forming a plurality of porous spacers on each sidewall of the multilayer interconnect structure.

[0022] In some embodiments, the step of forming the porous spacer includes: forming an energy-removable material layer to cover the multilayer interconnect structure; performing an anisotropic etching process to transform the energy-removable material layer into a plurality of sacrificial spacers on each sidewall of the multilayer interconnect structure; and performing an energy processing to transform the sacrificial spacers into the porous spacers.

[0023] In some embodiments, an energy source for the energy processing is heat, light, or a combination thereof.

[0024] In some embodiments, the energy-removable layer material includes a base material and a decomposable pore-forming agent material, wherein the base material includes methylsilsesquioxane, a low dielectric constant material, or silicon oxide.

[0025] Due to the design of the semiconductor device disclosed herein, the multilayer structure of this multilayer interconnect structure avoids the formation of multiple voids and is suitable for manufacturing multiple semiconductor devices with multiple small technical nodes. Furthermore, multiple porous spacers or multiple air gaps can reduce the parasitic capacitance of the semiconductor device.

[0026] The technical features and advantages of this disclosure have been broadly summarized above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0029] Figures 2 to 5 This is a cross-sectional schematic diagram of various semiconductor elements according to some embodiments of the present disclosure.

[0030] Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor element according to an embodiment of the present disclosure.

[0031] Figures 7 to 14 This is a cross-sectional schematic diagram of a process for fabricating the semiconductor device according to an embodiment of the present disclosure.

[0032] Figures 15 to 20 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0033] The reference numerals in the attached figures are explained as follows:

[0034] 1A: Semiconductor components

[0035] 1B: Semiconductor components

[0036] 1C: Semiconductor components

[0037] 1D: Semiconductor components

[0038] 1E: Semiconductor components

[0039] 10: Method

[0040] 101: Base

[0041] 103: First conductive line

[0042] 105: First Isolation Layer

[0043] 105TS: Top surface

[0044] 107: Second conductive wire

[0045] 109: Single-layer connection structure

[0046] 109S: Sidewall

[0047] 109TS: Top surface

[0048] 200: Multi-layer connection structure

[0049] 200S: Sidewall

[0050] 200TS: Top surface

[0051] 201: First conductive layer

[0052] 201-1: First conductive layer

[0053] 201-1TS: Upper surface

[0054] 201-3: First conductive layer

[0055] 201-3TS: Upper surface

[0056] 201-5: First conductive layer

[0057] 201-5TS: Upper surface

[0058] 203: Second conductive layer

[0059] 203-1: Second conductive layer

[0060] 203-3: Second conductive layer

[0061] 203-5: Second conductive layer

[0062] 301: First gap

[0063] 501: First conductive material

[0064] 503: Second conductive material

[0065] 505: Hard mask layer

[0066] 507: Photoresist layer

[0067] 509: Spacer Materials

[0068] 511: Energy-Removable Materials

[0069] 513: Sacrificing a Gap

[0070] D1: Depth

[0071] D2: Depth

[0072] S11: Steps

[0073] S13: Steps

[0074] S15: Steps

[0075] S17: Steps

[0076] W1: Width

[0077] W2: Width

[0078] Z: Direction

[0079] α: Angle Detailed Implementation

[0080] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0081] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass not only the orientations shown in the figures but also different orientations of the elements during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0082] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0083] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0084] Unless otherwise specified herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact identical orientation, layout, location, shape, size, amount, or other measure, but rather mean, within acceptable differences, that the orientation, layout, location, shape, size, amount, or other measure is substantially identical, for example, due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, "substantially the same," "substantially equal," or "substantially planar" means exactly the same, equal, or planar, or it can be the same, equal, or planar within an acceptable range of differences, for example, which can occur due to the manufacturing process.

[0085] In this disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor elements.

[0086] It should be understood that in the description of this disclosure, "above" (or "up") refers to the direction corresponding to the Z-direction arrow, while "below" (or "down") refers to the relative direction corresponding to the Z-direction arrow.

[0087] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 1A according to an embodiment of the present disclosure.

[0088] Please refer to Figure 1The semiconductor element 1A may include a substrate 101, a plurality of first conductive lines 103, a first isolation layer 105, a second conductive line 107, a single-layer connection structure 109, a multi-layer connection structure 200, and a plurality of first spacers 301.

[0089] Please refer to Figure 1 In some embodiments, substrate 101 may be a bulk semiconductor substrate, which is composed entirely of at least one semiconductor material; the bulk semiconductor substrate does not contain any dielectric, insulating layer, or conductive features. For example, the bulk semiconductor substrate may be made of an elemental semiconductor, a compound semiconductor, a non-semiconductor material, other suitable materials, or combinations thereof; the elemental semiconductor is, for example, silicon or germanium; the compound semiconductor is, for example, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors; the non-semiconductor material is, for example, soda-lime glass, fused silica, fused quartz, or calcium fluoride.

[0090] In some embodiments, substrate 101 may include an insulator-on-semiconductor structure comprising, from bottom to top, a handle substrate, an isolation layer, and an uppermost semiconductor material layer. The handle substrate and the uppermost semiconductor material layer may be made of the same material as those used in the aforementioned bulk semiconductor substrate. The isolation layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the isolation layer may be a dielectric oxide, such as silicon oxide. As another example, the isolation layer may be a dielectric nitride, such as silicon nitride or boron nitride. As yet another example, the isolation layer may comprise a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any of the following orders. The isolation layer may have a thickness between approximately 10 nm and approximately 200 nm.

[0091] In some embodiments, substrate 101 may include a plurality of dielectrics, a plurality of isolation layers, or a plurality of conductive features disposed on a bulk semiconductor substrate or an uppermost semiconductor material layer. For example, the dielectrics or isolation layers may be made of silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, the like, or combinations thereof. Each dielectric or isolation layer may have a thickness between approximately 0.5 micrometers and approximately 3.0 micrometers. The low-k dielectric material may have a dielectric constant less than 3.0 or even less than 2.5. The conductive features may be a plurality of conductive lines, a plurality of conductive vias, a plurality of conductive contacts, or the like.

[0092] In some embodiments, a plurality of device elements (not shown) may be disposed in substrate 101. For example, the device elements may be bipolar junction transistors, metal-oxide-semiconductor field-effect transistors, diodes, system large-scale integration, flash memories, dynamic random-access memories, static random-access memories, electrically erasable programmable read-only memory, image sensors, microelectromechanical systems (MEMS), active components, or passive components. The device elements may be electrically isolated from adjacent device elements by a plurality of isolation structures, such as shallow trench isolation.

[0093] Please refer to Figure 1 The first conductive line 103 may be disposed in the substrate 101. The upper surfaces of the first conductive line 103 are substantially coplanar with the upper surface of the substrate 101. It should be understood that, as Figure 1 The number of the first conductive wires 103 shown is for illustrative purposes only. For example, the first conductive wires 103 may be made of the following materials: copper, aluminum, titanium, tungsten, the like, or combinations thereof.

[0094] Please refer to Figure 1 A first insulating layer 105 may be disposed on the substrate 101. For example, the first insulating layer 105 may be made of the following materials: silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, the like, or combinations thereof. The first insulating layer 105 has a thickness between approximately 0.5 micrometers and approximately 3.0 micrometers.

[0095] Please refer to Figure 1 A single-layer connection structure 109 may be disposed in the first isolation layer 105. The upper surface 109TS of the single-layer connection structure 109 may be substantially coplanar with the upper surface 105TS of the first isolation layer 105. Each sidewall 109S of the single-layer connection structure 109 may have a slanted profile. In some embodiments, a width W2 of the single-layer connection structure 109 may gradually become wider from bottom to top along the direction Z. In some embodiments, the single-layer connection structure 109 may have a uniform slope overall. In some embodiments, an angle α between each sidewall 109S of the single-layer connection structure 109 and an upper surface 109TS of the single-layer connection structure 109 may be between 86 degrees and approximately 90 degrees. In some embodiments, the single-layer connection structure 109 may be a conductive via and may electrically connect corresponding first conductive wires 103 and second conductive wires 107. In some embodiments, the single-layer connection structure 109 may be a conductive contact point and may be electrically connected to a source / drain region in the substrate 101.

[0096] Please refer to Figure 1 A multilayer connection structure 200 may be disposed on a substrate 101. An upper surface 200TS of the multilayer connection structure 200 may be approximately coplanar with the upper surface 109TS of the single-layer connection structure 109. In some embodiments, a width W1 of the multilayer connection structure 200 may be less than or equal to the width W2 of the single-layer connection structure 109. A depth D1 of the multilayer connection structure 200 may be equal to a depth D2 of the single-layer connection structure 109. In some embodiments, the multilayer connection structure 200 may be a conductive via and may electrically connect corresponding first conductive line 103 and second conductive line 107.

[0097] It should be understood that, in the description of this disclosure, a “depth” refers to a vertical dimension of an element (i.e., a layer, groove, hole, opening, etc.) in a cross-sectional view, measured from one upper surface of the element to a lower surface; a “width” refers to a dimension of an element (i.e., a layer, groove, hole, opening, etc.) in a cross-sectional view, measured from one side surface of the element to an opposite side surface. Where indicated, the term “thickness” may be used in place of “width” and / or “depth”.

[0098] In some embodiments, the multilayer connection structure 200 may be a conductive contact point and may be electrically connected to a source / drain region in the substrate 101. In some embodiments, the multilayer connection structure 200 and the single-layer connection structure 109 may be electrically connected to the same first conductive line 103 or to different second conductive lines 107.

[0099] Please refer to Figure 1 The multilayer connection structure 200 may include a first conductive layer 201 and a second conductive layer 203. The first conductive layer 201 may be disposed on the substrate 101. The second conductive layer 203 may be disposed on the first conductive layer 201. The upper surface of the second conductive layer 203 may be regarded as the upper surface 200TS of the multilayer connection structure 200. The sidewalls of the first conductive layer 201 and the sidewalls of the second conductive layer 203 together form the sidewalls 200S of the multilayer connection structure 200. The sidewalls of the multilayer connection structure 200 may be substantially perpendicular.

[0100] It should be understood that, in the description of this disclosure, if a surface (or sidewall) is "vertical" if there is a vertical plane, then the deviation of the surface from the vertical plane will not exceed three times the root mean square roughness of the surface.

[0101] In some embodiments, the first conductive layer 201 and the second conductive layer 203 may have different stress states. For example, the first conductive layer 201 may have tensile stress, while the second conductive layer 203 may have compressive stress, or vice versa. For example, the first conductive layer 201 and the second conductive layer 203 may be made of materials including: titanium, titanium nitride, ruthenium, molybdenum, chromium, vanadium, palladium, platinum, rhodium, scandium, aluminum, niobium, niobium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, or silicides thereof. The first conductive layer 201 and the second conductive layer 203 may be made of different materials, but are not limited thereto.

[0102] The stress states of the first conductive layer 201 and the second conductive layer 203 can be controlled by different methods. For example, the stress states of the first conductive layer 201 and the second conductive layer 203 can be controlled by forming the first conductive layer 201 and the second conductive layer 203 with different materials. In particular, the first conductive layer 201 is made of a material with a higher stress state, while the second conductive layer 203 is made of a material with a lower stress state. In this example, the second conductive layer 203 with a lower stress state can have a thicker thickness than the first conductive layer 201 with a higher stress state to compensate for the stress on the first conductive layer 201 with a higher stress state.

[0103] In other examples, the stress states of the first conductive layer 201 and the second conductive layer 203 can be controlled by forming the first conductive layer 201 and the second conductive layer 203 with nitrides of different nitrogen levels. In particular, due to a more disrupted crystallization, the first conductive layer 201 can be made of a nitride with a higher nitrogen level to achieve a higher stress state. Conversely, the second conductive layer 203 can be made of a nitride with a lower nitrogen level to achieve a lower stress state. The different nitrogen levels of the first conductive layer 201 and the second conductive layer 203 can be controlled by the amount of reactant during the deposition process of the first conductive layer 201 and the second conductive layer 203. In this example, the first conductive layer 201 can have the same thickness as the second conductive layer 203, but this is not a limitation.

[0104] The first conductive layer 201 and the second conductive layer 203, with different stress states, can counteract the stress in the multilayer interconnect structure 200, or at least reduce the stress in the multilayer interconnect structure 200 to a desired level. Therefore, wafer bowing can be reduced or avoided. Consequently, the yield of the semiconductor device 1A can be improved.

[0105] Please refer to Figure 1 The first spacer 301 may be disposed on each sidewall 200S of the multilayer connection structure 200. For example, the first spacer 301 may be made of the following materials: silicon oxide, silicon nitride, silicon carbon nitride, silicon nitride oxide, or silicon oxynitride. The first spacer 301 electrically insulates the multilayer connection structure 200 from a plurality of adjacent electronic components (i.e., single-layer connection structures 109), which are disposed on both sides adjacent to the multilayer connection structure 200.

[0106] It should be understood that, in the description of this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0107] Please refer to Figure 1 The second conductive wire 107 may be disposed on the first insulating layer 105. The second conductive wire 107 may be electrically connected to the single-layer connection structure 109 and the multi-layer connection structure 200. The second conductive wire 107 may be made of the same material as the first conductive wire 103, but is not limited thereto.

[0108] Figures 2 to 5 The diagram shows cross-sectional views of various semiconductor elements 1B, 1C, 1D, and 1E according to some embodiments of the present disclosure.

[0109] It should be understood that the same or similar element numbers used throughout the drawings are for the purpose of indicating the same or similar features, elements or structures, and therefore the same or similar features, elements or structures will not be explained in detail again in each drawing.

[0110] Please refer to Figure 2 Semiconductor element 1B may have similar characteristics to, for example... Figure 1 The described structure. For example, in Figure 1 In Figure 2 The same or similar elements are identified by similar element numbers, and duplicate descriptions have been omitted.

[0111] Please refer to Figure 2The upper surface 200TS of the multilayer connection structure 200 may be approximately coplanar with the upper surface 109TS of the single-layer connection structure 109. In some embodiments, the width W1 of the multilayer connection structure 200 may be less than or equal to the width W2 of the single-layer connection structure 109. The depth D1 of the multilayer connection structure 200 may be equal to the depth D2 of the single-layer connection structure 109.

[0112] Please refer to Figure 2 The multilayer connection structure 200 may include multiple first conductive layers 201-1, 201-3, and 201-5, and multiple second conductive layers 203-1, 203-3, and 203-5. The multiple first conductive layers 201-1, 201-3, and 201-5 and the multiple second conductive layers 203-1, 203-3, and 203-5 may be stacked alternately. The sidewalls of the multiple first conductive layers 201-1, 201-3, and 201-5, together with the sidewalls of the multiple second conductive layers 203-1, 203-3, and 203-5, form the sidewalls 200S of the multilayer connection structure 200. The sidewalls of the multilayer connection structure 200 may be substantially vertical.

[0113] In some embodiments, the plurality of first conductive layers 201-1, 201-3, 201-5 and the plurality of second conductive layers 203-1, 203-3, 203-5 may have different stress states. For example, the plurality of first conductive layers 201-1, 201-3, 201-5 may have tensile stress, while the plurality of second conductive layers 203-1, 203-3, 203-5 may have compressive stress, or vice versa. For example, the plurality of first conductive layers 201-1, 201-3, 201-5 and the plurality of second conductive layers 203-1, 203-3, 203-5 may be made of materials including: titanium, titanium nitride, ruthenium, molybdenum, chromium, vanadium, palladium, platinum, rhodium, scandium, aluminum, niobium, niobium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride or silicides thereof.

[0114] The stress state of the plurality of first conductive layers 201-1, 201-3, 201-5 and the plurality of second conductive layers 203-1, 203-3, 203-5 can be controlled by forming the plurality of first conductive layers 201-1, 201-3, 201-5 and the plurality of second conductive layers 203-1, 203-3, 203-5 with different materials. In particular, the plurality of first conductive layers 201-1, 201-3, 201-5 are made of a material having a higher stress state, while the plurality of second conductive layers 203-1, 203-3, 203-5 are made of a material having a lower stress state. Compared to the plurality of first conductive layers 201-1, 201-3, and 201-5 under higher stress conditions, the plurality of second conductive layers 203-1, 203-3, and 203-5 under lower stress conditions can have a greater thickness to compensate for the stress on the plurality of first conductive layers 201-1, 201-3, and 201-5 under higher stress conditions. Specifically, the plurality of first conductive layers 201-1, 201-3, and 201-5 can have a thickness between approximately 5 nm and 50 nm. The plurality of second conductive layers 203-1, 203-3, and 203-5 can have a thickness between approximately 10 nm and approximately 150 nm.

[0115] In some embodiments, the plurality of first conductive layers 201-1, 201-3, and 201-5 may be large grain layers, while the plurality of second conductive layers 203-1, 203-3, and 203-5 may be buffer layers. For example, the large grain layers and the buffer layers may be made of materials comprising: titanium, titanium nitride, ruthenium, molybdenum, chromium, vanadium, palladium, platinum, rhodium, scandium, aluminum, niobium, niobium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, or silicides thereof. For example, the large grain layers may be made of a pure metal (i.e., tantalum), while the buffer layers may be made of a metal nitride (i.e., tantalum nitride) or a metal oxide (i.e., tantalum oxide) of a pure metal. The large grain layers may have a thickness between approximately 10 nm and approximately 30 nm. The buffer layer may have a thickness between approximately 1 nm and approximately 5 nm. The buffer layer can block the crystal structure of the underlying large crystal layer from extending upwards in the Z-direction, preventing the crystal structure from propagating through the multilayer interconnect structure 200. Therefore, the stress in the multilayer interconnect structure 200 can be reduced. Consequently, wafer bowing can be reduced or avoided.

[0116] Please refer to Figure 3 Semiconductor element 1C may have similar characteristics to, for example Figure 2 The described structure. (As in...) Figure 2 In Figure 3 The same or similar elements are identified by similar element numbers, and duplicate descriptions have been omitted.

[0117] Please refer to Figure 3 The plurality of first conductive layers 201-1, 201-3, and 201-5 may have rough upper surfaces 201-1TS, 201-3TS, and 201-5TS. The roughness of the plurality of first conductive layers 201-1, 201-3, and 201-5 is reduced by filling the air gaps at the rough upper surfaces 201-1TS, 201-3TS, and 201-5TS. The roughness of the plurality of first conductive layers 201-1, 201-3, and 201-5 may depend on the materials used and the deposition process; some materials and some deposition processes produce upper surfaces that are rougher than those produced by other materials and other deposition processes. For example, depending on plasma density, nitrogen content, or other factors, metals with high melting points or metal nitrides can produce a structure with a rough upper surface.

[0118] Please refer to Figure 4 Semiconductor element 1D can have similar characteristics to, for example... Figure 2 The described structure. (As in...) Figure 2 In Figure 4 The same or similar elements are identified by similar element numbers, and duplicate descriptions have been omitted.

[0119] Please refer to Figure 4 The porous spacer 111 may be disposed on each sidewall 200S of the multilayer connection structure 200. The first spacer 301 may be disposed on each sidewall of the porous spacer 111. In some embodiments, the first spacer 301 may be selective.

[0120] The porous spacer 111 may be made from an energy-removable material. The porous spacer 111 may comprise a skeleton and a plurality of empty spaces disposed between the skeletons. The empty spaces may be interconnected and may be filled with air. For example, the skeleton may comprise silicon oxide, a low-dielectric-constant material, or methylsilsesquioxane. The porous spacer 111 may have a porosity between approximately 10% and approximately 100%. It should be understood that when the porosity is 100%, it means that the porous spacer 111 comprises only the empty spaces, and the porous spacer 111 can be considered as a plurality of air gaps. In some embodiments, the porosity of the porous spacer 111 may be between approximately 10% and approximately 90%, or between approximately 45% and approximately 75%. The plurality of empty spaces of the porous spacer 111 may be filled with air. Therefore, for example, the dielectric constant of the porous spacer 111 can be significantly lower than that of a spacer made solely of silicon oxide. Consequently, the porous spacer 111 can significantly reduce the parasitic capacitance between the multilayer interconnect structure 200 and the single-layer interconnect structure 109. That is, the porous spacer 111 can significantly mitigate an interference effect that occurs between the electronic signals generated by the semiconductor element 1D or between the electronic signals applied to the semiconductor element 1D.

[0121] Energy-removable materials may include a material, such as a thermally decomposable material, a photodecomposable material, an electron beam decomposable material, or a combination thereof. For example, an energy-removable material may include a base material and a decomposable pore-forming material that is sacrificially removed upon exposure to an energy source.

[0122] Please refer to Figure 5 Semiconductor element 1E may have similar characteristics to, for example Figure 4 The described structure. (As in...) Figure 4 In Figure 5 The same or similar elements are identified by similar element numbers, and duplicate descriptions have been omitted.

[0123] Please refer to Figure 5 The air gap 113 can be disposed between each sidewall 200S of the multilayer connection structure 200 and the first spacer 301. The air gap 113 can significantly reduce the parasitic capacitance between the multilayer connection structure 200 and the single-layer connection structure 109. That is, the air gap 113 can significantly mitigate an interference effect that is located between the electronic signals generated by the semiconductor element 1E or between the electronic signals applied to the semiconductor element 1E.

[0124] It should be understood that the order in which the functions or steps described herein occur may differ from the order indicated in the diagrams. For example, depending on the functions or steps involved, two diagrams shown consecutively may actually be executed roughly simultaneously, or sometimes in reverse order.

[0125] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0126] Figure 6 This is a schematic flowchart of a method 10 for fabricating a semiconductor element 1B according to an embodiment of the present disclosure. Figures 7 to 14 This is a cross-sectional schematic diagram of a process for fabricating the semiconductor device 1B according to an embodiment of the present disclosure.

[0127] Please refer to Figure 6 and Figure 7 In step S11, a substrate 101 can be provided, on which multiple layers of first conductive material 501 and multiple layers of second conductive material 503 can be interleaved, a hard mask layer 505 can be formed on the multiple layers of first conductive material 501 and multiple layers of second conductive material 503, and a photoresist layer 507 can be formed on the hard mask layer 505.

[0128] Please refer to Figure 7For example, the multilayer first conductive material 501 and the multilayer second conductive material 503 can be made of the following materials: titanium, titanium nitride, ruthenium, molybdenum, chromium, vanadium, palladium, platinum, rhodium, scandium, aluminum, niobium, niobium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, or their silicides. The multilayer first conductive material 501 and the multilayer second conductive material 503 can be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, physical vapor deposition, ionized physical vapor deposition, atomic layer deposition, electroplating, or electroless plating, but are not limited thereto. It should be understood that the stacked structure of the multilayer first conductive material 501 and the multilayer second conductive material 503 can also be considered as a stacked layer.

[0129] In some embodiments, the multilayer first conductive material 501 and the multilayer second conductive material 503 may have different stress states. For example, the multilayer first conductive material 501 may have tensile stress, while the multilayer second conductive material 503 may have compressive stress, or vice versa. The stress states of the multilayer first conductive material 501 and the multilayer second conductive material 503 can be controlled by forming the multilayer first conductive material 501 and the multilayer second conductive material 503 with different materials. In particular, the multilayer first conductive material 501 may be made of a material with a higher stress state, while the multilayer second conductive material 503 may be made of a material with a lower stress state. Compared to the multilayer first conductive material 501 with a higher stress state, the multilayer second conductive material 503 with a lower stress state may have a thicker thickness to compensate for the stress on the multilayer first conductive material 501. In particular, the multilayer first conductive material 501 may have a thickness between approximately 5 nm and 50 nm. The multilayer second conductive material 503 may have a thickness between approximately 10 nm and approximately 150 nm.

[0130] In other examples, the stress states of the multilayer first conductive material 501 and the multilayer second conductive material 503 can be controlled by using nitrides with different nitrogen levels. Specifically, the multilayer first conductive material 501 can be made of nitrides with higher nitrogen levels to achieve a higher stress state due to more disrupted crystallization. Conversely, the multilayer second conductive material 503 can be made of nitrides with lower nitrogen levels to achieve a lower stress state. The different nitrogen levels of the multilayer first conductive material 501 and the multilayer second conductive material 503 can be controlled by the amount of reactant used during the deposition process of the multilayer first conductive material 501 and the multilayer second conductive material 503. In this example, each layer of first conductive material 501 can have the same thickness as each layer of second conductive material 503, but this is not a limitation.

[0131] The multilayer first conductive material 501 and the multilayer second conductive material 503, with different stress states, can counteract the stress of multiple stacked layers, or at least reduce the stress of the stacked layers to a desired level. Therefore, wafer bowing can be reduced or avoided.

[0132] In some embodiments, the multilayer first conductive material 501 may be large grain layers, and the multilayer second conductive material 503 may be a buffer layer. The large grain layers may have a thickness between approximately 10 nm and approximately 30 nm. The buffer layer may have a thickness between approximately 1 nm and approximately 5 nm. The buffer layer can block the crystal structure of the underlying large grain layers from extending upwards in the Z-direction, preventing the crystal structure from propagating through the stacked layers. Therefore, the stress in the stacked layers can be reduced. Therefore, wafer bending can be reduced or avoided.

[0133] Please refer to Figure 7 For example, the hard mask layer 505 may be made of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. A photolithography process may be performed to transform the desired pattern into a photoresist layer 507 and define a pattern of a multilayer interconnect structure 200.

[0134] Please refer to Figure 6 , Figure 8 as well as Figure 9 In step S13, the multilayer connection structure 200 can be formed from the multilayer first conductive material 501 and the multilayer second conductive material 503.

[0135] Please refer to Figure 8 An etching process can be performed to remove the exposed portion of the hard mask layer 505 in order to transform the pattern of the multilayer interconnect structure 200 on the hard mask layer 505. After the etching process, the photoresist layer 507 can be removed.

[0136] Please refer to Figure 9 An etching process can be sequentially performed to remove exposed portions of the multilayer first conductive material 501 and the multilayer second conductive material 503. Depending on the relative etching selectivity of the multilayer first conductive material 501 and the multilayer second conductive material 503, the etching process can be performed using the same chemical method to remove the multilayer first conductive material 501 and the multilayer second conductive material 503, or it can be cycled between processes customized for each material of the multilayer first conductive material 501 and the multilayer second conductive material 503. For example, fluorine-based etching can be used to remove exposed portions of the multilayer first conductive material 501, while chlorine-based etching can be used to remove exposed portions of the multilayer second conductive material 503.

[0137] Please refer to Figure 9 After the etching process, the multilayer first conductive material 501 can be transformed into multiple first conductive layers 201-1, 201-3, and 201-5, and the multilayer second conductive material 503 can be transformed into multiple second conductive layers 203-1, 203-3, and 203-5. The multiple first conductive layers 201-1, 201-3, and 201-5 and the multiple second conductive layers 203-1, 203-3, and 203-5 together form a multilayer interconnect structure 200. After forming the multilayer interconnect structure 202, a removable hard mask layer 505 is applied.

[0138] Please refer to Figure 6 , Figure 10 and Figure 11 In step S15, a plurality of first spacers 301 may be formed on each sidewall 200S of the multilayer connection structure 200.

[0139] Please refer to Figure 10 A spacer material 509 can be formed to cover the upper surface of the substrate 101, the sidewalls of the multilayer connection structure 200, and the upper surface of the multilayer connection structure 200. For example, the spacer material 509 can be made of silicon oxide, silicon nitride, silicon carbide, silicon nitride oxide, or silicon oxynitride.

[0140] Please refer to Figure 11An anisotropic etching process can be performed to remove the interstitial material 509 formed on the upper surface of the substrate 101 and the upper surface of the multilayer interconnect structure 200. After the anisotropic etching process, the interstitial material 5098 can be transformed into a plurality of first interstitials 301 on each sidewall of the multilayer interconnect structure 200.

[0141] Please refer to Figure 6 and Figures 12 to 14 In step S17, a first isolation layer 105 may be formed on the substrate 101, a single-layer connection structure 109 may be formed in the first isolation layer 105, and a second conductive line 107 may be formed on the first isolation layer 105.

[0142] Please refer to Figure 12 A first isolation layer 105 may be formed on a substrate 101. The first isolation layer 101 may cover the multilayer interconnect structure 200 and the first spacer 301. A planarization process, such as chemical mechanical polishing, may be performed until the upper surface 200TS of the multilayer interconnect structure 200 is exposed to remove excess material and provide a generally flat surface for subsequent processing steps.

[0143] Please refer to Figure 13 For example, a single-layer interconnect structure 109 can be formed in the first isolation layer 105 via a damascene process. Since the single-layer interconnect structure 109 is formed via a damascene process including an opening-filling process, it can have a larger dimension and tapered sidewalls compared to the multilayer interconnect structure 200 to avoid void formation during the opening-filling process. Specifically, the width W2 of the single-layer interconnect structure 109 can be larger than the width W1 of the multilayer interconnect structure 200. Conversely, the multilayer interconnect structure 200, formed by depositing multiple layers and removing unwanted portions, completely avoids the problem of void formation and is more suitable for semiconductor devices with smaller technology nodes, such as 20nm, 14nm, 7nm, or smaller.

[0144] Please refer to Figure 14 The second conductive line 107 may be formed on the first insulating layer 105. The second conductive line 107 may be electrically connected to the multilayer connection structure 200 and the single-layer connection structure 109.

[0145] Figures 15 to 20 This is a cross-sectional schematic diagram of a process for fabricating a semiconductor device 1D according to an embodiment of the present disclosure.

[0146] Please refer to Figure 15 An intermediate semiconductor device can be similar to Figures 7 to 9The process described is used for manufacturing. An energy-removable material 511 can be formed to cover the upper surface of the substrate 101, the sidewalls of the multilayer connection structure 200, and the upper surface of the multilayer connection structure 200. The energy-removable material 511 may comprise a material, such as a thermally degradable material, a photodegradable material, an electron beam degradable material, or a combination thereof. For example, the energy-removable material may include a base material and a degradable porous agent material that is sacrificially removed upon exposure to an energy source.

[0147] In some embodiments, the base material may include a methylsilsesquioxane base material. The decomposable pore-forming material may comprise a pore-forming organic compound, which is the base material providing porosity to the energy-removable material.

[0148] In some embodiments, the base material may be silicon dioxide. The decomposable pore-forming material may comprise multiple compounds, including multiple unsaturated bonds, such as double bonds or triple bonds. During exposure to an energy source, the unsaturated bonds of the decomposable pore-forming material may cross-link with the silicon dioxide of the base material. Thus, the decomposable pore-forming material can shrink and create multiple empty spaces, while the base material remains in situ. These empty spaces may be filled with air so that the dielectric constant of the empty spaces can be very low. In some embodiments, the base material may be a low-k dielectric material.

[0149] In some embodiments, the energy-removable material 511 may comprise a relatively high concentration of a biodegradable pore-forming agent and a relatively low concentration of a base material, but is not limited thereto. For example, the energy-removable material 511 may comprise approximately 90% or more of a biodegradable pore-forming agent and approximately 10% or less of a base material. In other embodiments, the energy-removable material 511 may comprise approximately 55% or more of a biodegradable pore-forming agent and approximately 45% or less of a base material. In other embodiments, the energy-removable material 511 may comprise 25% or more of a biodegradable pore-forming agent and approximately 75% or less of a base material. In still other embodiments, the energy-removable material 511 may comprise 100% of a biodegradable pore-forming agent and no base material is used.

[0150] Please refer to Figure 16An anisotropic etching process can be performed to remove the layer of energy-removable material 511 formed on the upper surface of the substrate 101 and the upper surface of the multilayer interconnect structure 200. After the anisotropic etching process, the layer of energy-removable material 511 can be transformed into a plurality of sacrificial spacers 513 on each sidewall of the multilayer interconnect structure 200.

[0151] Please refer to Figure 17 A layer of spacer material 509 can be formed to cover the upper surface of the substrate 101, the upper surface 200TS of the multilayer connection structure 200, and each sidewall of the sacrificial spacer 513.

[0152] Please refer to Figure 18 An anisotropic etching process can be performed to remove the interstitial material 509 formed on the upper surface of the substrate 101 and the upper surface of the multilayer interconnect structure 200. After the anisotropic etching process, the interstitial material 509 can be transformed into the sacrificial spacers 513 on each sidewall of the sacrificial spacers 513.

[0153] Please refer to Figure 19 The single-layer connection structure 109 and the second conductive line 107 can be made of a similar structure as shown in the figure. Figure 13 and Figure 14 The process described is formed by a procedure.

[0154] Please refer to Figure 20 By applying energy source Figure 17 The intermediate semiconductor element in the process enables an energy processing operation to be performed. Figure 17 The intermediate semiconductor element in the process. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the temperature of the energy processing may be between approximately 800°C and approximately 900°C. When light is used as the energy source, ultraviolet light may be applied. The energy processing may remove a decomposable porous material from the energy-removable material to create the empty spaces (pores), while the base material remains in situ. After the energy processing, the sacrificial spacer 513 may be transformed into the porous spacer 111. The base material may be transformed into a framework of the porous spacer 111, and the empty spaces may be distributed between the framework of the porous spacer 111. In some embodiments, the energy processing may be performed immediately after the formation of the first spacer 301.

[0155] One embodiment of this disclosure provides a semiconductor device including a substrate; a single-layer interconnect structure disposed on the substrate; and a multilayer interconnect structure including a first conductive layer and a second conductive layer, the first conductive layer being disposed on the substrate and the second conductive layer being disposed on the first conductive layer. An upper surface of the multilayer interconnect structure is substantially coplanar with an upper surface of the single-layer interconnect structure, and the width of the multilayer interconnect structure is smaller than the width of the single-layer interconnect structure.

[0156] Another embodiment of this disclosure provides a semiconductor device including a substrate; a single-layer interconnect structure disposed on the substrate; and a multilayer interconnect structure disposed on the substrate, including a plurality of first conductive layers and a plurality of second conductive layers stacked in an alternating manner. An upper surface of the multilayer interconnect structure is substantially coplanar with an upper surface of the single-layer interconnect structure, and a width of the multilayer interconnect structure is smaller than a width of the single-layer interconnect structure.

[0157] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, including providing a substrate; forming a multilayer interconnect structure on the substrate, wherein the multilayer interconnect structure includes a plurality of first conductive layers, and the plurality of first conductive layers are interleaved with a plurality of second conductive layers; and forming a single-layer interconnect structure on the substrate, wherein an upper surface of the single-layer interconnect structure is substantially coplanar with an upper surface of the multilayer interconnect structure, and a width of the single-layer interconnect structure is greater than a width of the multilayer interconnect structure.

[0158] Due to the design of the semiconductor device disclosed herein, the multilayer structure of the multilayer interconnect structure 200 avoids the formation of multiple voids and is suitable for manufacturing multiple semiconductor devices with multiple small technical nodes. Furthermore, the multiple porous spacers 111 or multiple air gaps 113 can reduce the parasitic capacitance of the semiconductor device 1D / 1E.

[0159] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0160] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One base; A first conductive line is disposed in the substrate and a first insulating layer is formed on the substrate; A single-layer connection structure is located on the substrate, and the single-layer connection structure is electrically connected to the first isolation layer of the first conductive wire; A multilayer connection structure is located on the substrate and includes a plurality of first conductive layers and a plurality of second conductive layers stacked in an alternating manner. The multilayer connection structure is electrically connected to the first isolation layer of the first conductive line. as well as A second conductive line is disposed on the first insulating layer, and the second conductive line is electrically connected to the single-layer connection structure and the multi-layer connection structure; The upper surface of the multi-layer connection structure is approximately coplanar with the upper surface of the single-layer connection structure, and the width of the multi-layer connection structure is smaller than the width of the single-layer connection structure. The plurality of first conductive layers and the plurality of second conductive layers have relative stress states.

2. The semiconductor device as claimed in claim 1, wherein, The upper surfaces of each of the multiple first conductive layers are rough.

3. The semiconductor device as claimed in claim 1, wherein, The thickness of the plurality of first conductive layers is greater than or equal to the thickness of the plurality of second conductive layers.

4. The semiconductor device as claimed in claim 1, wherein, The thickness of the plurality of first conductive layers is between approximately 5 nm and approximately 50 nm, and the thickness of the plurality of second conductive layers is between approximately 10 nm and approximately 150 nm.

5. The semiconductor device as claimed in claim 1, wherein, The sidewalls of this multi-layered connection structure are roughly vertical.

6. The semiconductor element of claim 1 further includes a plurality of first spacers located on each sidewall of the multilayer interconnect structure.

7. The semiconductor element of claim 6 further includes a plurality of air gaps located between each sidewall of the multilayer interconnect structure and the first spacer.

8. The semiconductor element of claim 1 further includes a plurality of porous spacers located on each sidewall of the multilayer interconnect structure.

9. The semiconductor device as claimed in claim 8, wherein, The porosity of the porous interstitial spacer is between approximately 10% and approximately 90%.

10. A method for fabricating a semiconductor device, comprising: Provide a base; A first conductive line is formed, disposed in the substrate, and a first insulating layer is formed on the substrate; A multilayer connection structure is formed on the substrate, the multilayer connection structure is electrically connected to the first isolation layer of the first conductive wire, and the multilayer connection structure includes a plurality of first conductive layers, which are formed alternately with a plurality of second conductive layers; A single-layer connection structure is formed on the substrate, the single-layer connection structure being electrically connected to the first insulating layer of the first conductive wire, wherein an upper surface of the single-layer connection structure is substantially coplanar with an upper surface of the multilayer connection structure, and the width of the single-layer connection structure is greater than the width of the multilayer connection structure; and A second conductive line is formed and disposed on the first isolation layer, and the second conductive line is electrically connected to the single-layer connection structure and the multi-layer connection structure; The plurality of first conductive layers and the plurality of second conductive layers have relative stress states.

11. The method for fabricating a semiconductor device as described in claim 10, wherein, The steps for forming this multi-layered connection structure include: Multiple layers of first conductive material and multiple layers of second conductive material are interleaved on the substrate; A hard masking layer is formed on the multilayer first conductive material and the multilayer second conductive material; Pattern the hard mask layer; and An etching process is performed, using a hard mask layer as a mask, to transform the multilayer first conductive material and the multilayer second conductive material into the plurality of first conductive layers and the plurality of second conductive layers.

12. The method for fabricating a semiconductor device as described in claim 11, further comprising: A step of forming multiple first spacers on each sidewall of the multilayer connection structure.

13. The method for fabricating a semiconductor device as described in claim 11, further comprising: A step of forming multiple porous spacers on each sidewall of the multilayer connection structure.

14. The method for fabricating a semiconductor device as described in claim 13, wherein, The step of forming the porous spacer includes: A layer of energy-removable material is formed to cover the multilayer interconnect structure; An anisotropic etching process is performed to transform the energy-removable material layer into multiple sacrificial spacers on each sidewall of the multilayer interconnect structure; and An energy process is performed to transform the sacrificial intermolecular into the porous intermolecular.

15. The method for fabricating a semiconductor device as described in claim 14, wherein, The energy source for this energy processing is heat, light, or a combination thereof.

16. The method for fabricating a semiconductor device as described in claim 15, wherein, The energy-removable material layer includes a base material and a decomposable pore-forming agent material, wherein the base material includes methylsilsesquioxane, a low dielectric constant material, or silicon oxide.

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