Wafer structure, manufacturing method and three-dimensional memory

Abstract

The present application provides a wafer structure, a manufacturing method and a three-dimensional memory, wherein the wafer structure includes: a substrate, a film layer on the substrate, a reflective pattern in or on the film layer, an interface bonding mark in an oxide layer on the film layer, the oxide layer being located on the side of the reflective pattern away from the substrate, and the reflective pattern and the interface bonding mark overlapping in their orthographic projections on the plane where the substrate is located. The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold. Since the pattern density of the set reflective pattern and the pattern density of the interface bonding mark are quite different, the amount of light reflected by the reflective pattern and the interface bonding mark after being irradiated by the light source of the bonding machine is also quite different. The light-dark contrast of the interface bonding mark under the lens is high, and the interface bonding mark can be accurately identified, thereby improving the accuracy of wafer bonding alignment.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a wafer structure, a manufacturing method and a three-dimensional memory. Background Art

[0002] Wafer bonding technology refers to the technology of tightly bonding two polished wafers together. When performing wafer bonding, the position alignment between the wafers is particularly important.

[0003] Currently, alignment between wafers is achieved by setting metal layer bonding marks. However, in actual applications, after the metal layer bonding marks on the two wafers are aligned, there are certain errors in the process of setting the interface through holes, resulting in a certain deviation between the position of the interface through holes and the preset position, making it impossible to achieve accurate alignment between the wafers.

[0004] Therefore, how to improve the accuracy of wafer alignment and bonding is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] In order to solve the above technical problems, the present application provides a wafer structure, a manufacturing method and a three-dimensional memory, which can improve the accuracy of wafer alignment and bonding.

[0006] In a first aspect, the present application provides a wafer structure, comprising:

[0007] substrate;

[0008] a film layer located on the substrate;

[0009] a reflective pattern in or on the film layer;

[0010] an interface bonding mark located in an oxide layer on the film layer; the oxide layer is located on a side of the reflective pattern away from the substrate;

[0011] The reflective pattern overlaps with the orthographic projection of the interface bonding mark on the plane where the substrate is located;

[0012] An absolute value of a difference between a pattern density of the reflective pattern and a pattern density of the interface bonding mark is greater than or equal to a critical threshold.

[0013] Optionally, the absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold, including:

[0014] The pattern density of the reflective pattern is less than or equal to a first preset threshold, and the pattern density of the interface bonding mark is greater than or equal to a second preset threshold; the second preset threshold is greater than the first preset threshold; and the difference between the second preset threshold and the first preset threshold is greater than or equal to the critical threshold;

[0015] or,

[0016] The pattern density of the reflective pattern is greater than or equal to a third preset threshold, and the pattern density of the interface bonding mark is less than or equal to a fourth preset threshold; the third preset threshold is greater than the fourth preset threshold; and the difference between the third preset threshold and the fourth preset threshold is greater than or equal to the critical threshold.

[0017] Optionally, the reflective pattern comprises a grating. Optionally, the grating comprises a plurality of grating lines arranged at intervals; and the slits between the grating lines are filled with the material of the film layer.

[0018] Optionally, the gate line is made of metal or polysilicon.

[0019] Optionally, the wafer structure includes a CMOS wafer structure or an array wafer structure;

[0020] When the wafer structure is a CMOS wafer structure, the wafer structure further includes: peripheral circuits located in the film layer and the oxide layer;

[0021] When the wafer structure is an array wafer structure, the wafer structure further includes: a storage structure located in the film layer and the oxide layer.

[0022] Optionally, the reflective pattern and the interface bonding mark are located in an area where a chip dicing line is located; and the area where the dicing line is located is located outside the storage structure.

[0023] In a second aspect, the present application provides a method for manufacturing a wafer structure, comprising:

[0024] providing a substrate;

[0025] a reflective pattern formed in or on a film layer on the substrate;

[0026] an interface bonding mark formed in an oxide layer on the film layer; the oxide layer is located on a side of the reflective pattern away from the substrate;

[0027] The reflective pattern overlaps with the orthographic projection of the interface bonding mark on the plane where the substrate is located;

[0028] An absolute value of a difference between a pattern density of the reflective pattern and a pattern density of the interface bonding mark is greater than or equal to a critical threshold.

[0029] Optionally, the reflective pattern formed in or on the film layer on the substrate includes:

[0030] When the reflective pattern is formed in the film layer, a first sub-film layer is formed on the substrate, a reflective pattern layer is formed on the first sub-film layer, and the reflective pattern layer is etched to form the reflective pattern; and a second sub-film layer is formed on the reflective pattern;

[0031] When the reflective pattern is formed on the film layer, the film layer is formed on the substrate, a reflective pattern layer is formed on the film layer, and the reflective pattern layer is etched to form the reflective pattern.

[0032] Optionally, the interface bonding mark formed in the oxide layer on the film layer; the oxide layer is located on a side of the reflective pattern away from the substrate, comprises:

[0033] When the reflective pattern is formed in the film layer, the oxide layer formed on the film layer is etched to form an interface through hole, and the interface through hole is used as the interface bonding mark;

[0034] When the reflective pattern is formed on the film layer, an oxide layer is formed on the reflective pattern, and the oxide layer is etched to form an interface through hole, and the interface through hole is used as the interface bonding mark.

[0035] In a third aspect, the present application provides a three-dimensional memory, including a wafer structure formed using the above-mentioned method for manufacturing the wafer structure.

[0036] Compared with the prior art, this application has at least the following advantages:

[0037] The present application provides a wafer structure, a manufacturing method and a three-dimensional memory, wherein the wafer structure includes: a substrate, a film layer on the substrate, a reflective pattern in or on the film layer, an interface bonding mark in an oxide layer on the film layer, the oxide layer being located on the side of the reflective pattern away from the substrate, and the reflective pattern and the interface bonding mark overlapping in their orthographic projections on the plane where the substrate is located. The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold. Since the pattern density of the set reflective pattern and the pattern density of the interface bonding mark are quite different, the amount of light reflected by the reflective pattern and the interface bonding mark after being irradiated by the light source of the bonding machine is also quite different. The light-dark contrast of the interface bonding mark under the lens is high, and the interface bonding mark can be accurately identified, thereby improving the accuracy of wafer bonding alignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of a wafer structure provided by an embodiment of the present application is shown;

[0040] Figure 2 A schematic diagram of a grating and an interface bonding mark provided in an embodiment of the present application is shown;

[0041] Figure 3 A schematic diagram of another grating and interface bonding mark provided in an embodiment of the present application is shown;

[0042] Figure 4 A flow chart of a method for manufacturing a wafer structure provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0043] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0044] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0045] As described in the background technology, wafer bonding technology refers to the technology of tightly bonding two polished wafers together. When performing wafer bonding, the position alignment between the wafers is particularly important.

[0046] At present, the method of setting metal layer bonding marks is used to achieve alignment between wafers. However, in actual applications, after the metal layer bonding marks on the two wafers are aligned, due to certain errors in the process of setting the interface through holes, the position of the interface through holes is deviated from the preset position, making it impossible to achieve accurate alignment between the wafers.

[0047] The current solution is to use the interface through-holes as interface bonding marks for alignment to improve the accuracy of wafer alignment. However, under the illumination of the bonding machine light source, the optical reflectivity of the film layer between the interface bonding mark and the bonded wafer is close, resulting in a low light-dark contrast of the interface bonding mark under the lens, making it impossible to accurately identify the interface bonding mark and reducing the accuracy of wafer alignment.

[0048] Therefore, how to improve the accuracy of wafer alignment and bonding is a technical problem that needs to be solved in this field.

[0049] In order to solve the above technical problems, the present application provides a wafer structure, a manufacturing method and a three-dimensional memory, wherein the wafer structure includes: a substrate, a film layer on the substrate, a reflective pattern in or on the film layer, an interface bonding mark in an oxide layer on the film layer, the oxide layer is located on the side of the reflective pattern away from the substrate, and the reflective pattern and the interface bonding mark overlap in their orthographic projections on the plane where the substrate is located. The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold. Since the pattern density of the set reflective pattern and the pattern density of the interface bonding mark are quite different, the pattern density and thus the amount of light reflected by the reflective pattern and the interface bonding mark after being irradiated by the light source of the bonding machine are also quite different. The light and dark contrast of the interface bonding mark under the lens is high, and the interface bonding mark can be accurately identified, thereby improving the accuracy of wafer bonding alignment.

[0050] In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0051] Exemplary Wafer Structure

[0052] See also Figure 1 , which is a schematic diagram of a wafer structure provided in an embodiment of the present application, such as Figure 1 As shown, this may include:

[0053] Substrate 101, film layer 102 on substrate 101, and reflective pattern 103 ( Figure 1 Only the case where the reflective pattern 103 is located in the film layer 102 is shown), the interface bonding mark 105 is located in the oxide layer 104 on the film layer 102, and the oxide layer 104 is located on the side of the reflective pattern 103 away from the substrate 101.

[0054] The orthographic projections of the reflective pattern 103 and the interface bonding mark 105 on the plane of the substrate 101 overlap, and the absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold. Specifically, when the pattern density of the reflective pattern 103 is less than or equal to a first preset threshold, the pattern density of the interface bonding mark 105 is greater than or equal to a second preset threshold, the second preset threshold is greater than the first preset threshold, and the difference between the second preset threshold and the first preset threshold is greater than or equal to the critical threshold. When the pattern density of the reflective pattern 103 is greater than or equal to a third preset threshold, the pattern density of the interface bonding mark 105 is less than or equal to a fourth preset threshold, the third preset threshold is greater than the fourth preset threshold, and the difference between the third preset threshold and the fourth preset threshold is greater than or equal to the critical threshold.

[0055] In the embodiment of the present application, the substrate 101 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator), or a GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate may be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, or may be a stacked structure, such as Si / SiGe, or may be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). In this embodiment, the substrate 101 is a bulk silicon substrate. Optionally, the material of the film layer 102 located on the substrate 101 may be silicon oxide or silicon nitride.

[0056] In the embodiment of the present application, a reflective pattern 103 is disposed in or on the film layer 102, and an interface bonding mark 105 is disposed in the oxide layer 104 on the film layer 102. The oxide layer 104 is located on the side of the reflective pattern 103 away from the substrate 101. At the same time, during the arrangement, the reflective pattern 103 is arranged to overlap with the orthographic projection of the interface bonding mark 105 on the plane of the substrate 101, and the pattern density of the reflective pattern 103 and the pattern density of the interface bonding mark 105 are set to be significantly different. As a result, the amount of light reflected by the reflective pattern 103 and the interface bonding mark 105 by the bonding machine light source is also significantly different. Under the lens, the light-dark contrast of the interface bonding mark 105 is high, allowing the interface bonding mark 105 to be accurately identified, thereby improving the accuracy of wafer bonding alignment.

[0057] Specifically, the absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to the critical threshold.

[0058] That is, when the pattern density of the reflective pattern 103 is less than or equal to the first preset threshold, the pattern density of the interface bonding mark 105 is greater than or equal to the second preset threshold, the second preset threshold is greater than the first preset threshold, and the difference between the second preset threshold and the first preset threshold is greater than or equal to the critical threshold.

[0059] Optionally, when the wafer structure provided in the embodiment of the present application is a CMOS wafer structure, the first preset threshold can be determined based on the total area of ​​the film layer where the reflective pattern 103 is located, and the second preset threshold can be determined based on the total area of ​​the oxide layer 104 where the interface bonding mark 105 is located.

[0060] Generally speaking, the first preset threshold can be set to 70%, that is, the pattern density of the reflective pattern 103 is less than or equal to 70%, that is, the area of ​​the reflective pattern 103 accounts for less than or equal to 70% of the total area of ​​the film layer where it is located.

[0061] Generally speaking, the second preset threshold can be set to 80%, that is, the pattern density of the interface bonding mark 105 is greater than or equal to 80%, that is, the area of ​​the interface bonding mark 105 accounts for greater than or equal to 80% of the total area of ​​the oxide layer where it is located.

[0062] That is, the smaller the pattern density of the reflective pattern 103, the stronger the light transmittance, and the weaker the ability to reflect light, so that the reflective pattern 103 seen from the lens is darker; the larger the pattern density of the interface bonding mark 105, the weaker the light transmittance, and the stronger the ability to reflect light, so that the interface bonding mark 105 seen from the lens is brighter. In the embodiment of the present application, the pattern density of the interface bonding mark 105 and the pattern density of the reflective pattern 103 are set to be quite different, so that the amount of light reflected by the reflective pattern 103 and the interface bonding mark 105 after being irradiated by the light source of the bonding machine is also quite different. Under the lens, the light and dark contrast of the interface bonding mark 105 is high, and the interface bonding mark 105 can be accurately identified, thereby improving the accuracy of wafer bonding alignment.

[0063] When the pattern density of the reflective pattern 103 is greater than or equal to the third preset threshold, the pattern density of the interface bonding mark 105 is less than or equal to the fourth preset threshold, the third preset threshold is greater than the fourth preset threshold, and the difference between the third preset threshold and the fourth preset threshold is greater than or equal to the critical threshold.

[0064] Similarly, when the wafer structure provided in the embodiment of the present application is a CMOS wafer structure, the third preset threshold can be determined based on the total area of ​​the film layer where the reflective pattern 103 is located, and the fourth preset threshold can be determined based on the total area of ​​the oxide layer 104 where the interface bonding mark 105 is located.

[0065] Generally speaking, the third preset threshold can be set to 80%, that is, the pattern density of the reflective pattern 103 is greater than or equal to 80%, that is, the area of ​​the reflective pattern 103 accounts for greater than or equal to 80% of the total area of ​​the film layer where it is located.

[0066] Generally speaking, the size of the fourth preset threshold can be set to 40%, that is, the pattern density of the interface bonding mark 105 is less than or equal to 40%, that is, the area of ​​the interface bonding mark 105 accounts for less than or equal to 40% of the total area of ​​the oxide layer where it is located.

[0067] That is, the greater the pattern density of the reflective pattern 103, the weaker the light transmittance, and the stronger the ability to reflect light, so that the reflective pattern 103 seen from the lens is brighter; the smaller the pattern density of the interface bonding mark 105, the stronger the light transmittance, and the weaker the ability to reflect light, so that the interface bonding mark 105 seen from the lens is darker. In the embodiment of the present application, the pattern density of the interface bonding mark 105 and the pattern density of the reflective pattern 103 are set to be quite different, so that the amount of light reflected by the reflective pattern 103 and the interface bonding mark 105 after being irradiated by the light source of the bonding machine is also quite different. Under the lens, the light and dark contrast of the interface bonding mark 105 is high, and the interface bonding mark 105 can be accurately identified, thereby improving the accuracy of wafer bonding alignment.

[0068] Optionally, when the wafer structure provided in the embodiment of the present application is an array wafer structure, generally speaking, the size of the first preset threshold can be set to 63%. Specifically, the density of the reflective pattern 103 can be set between 54% and 63%.

[0069] Alternatively, see Figure 2 and Figure 3 As shown, the reflective pattern 103 may include a grating, such as Figure 2 and Figure 3 As shown, the grating includes a plurality of spaced-apart grid lines, and the slits between the grid lines are filled with silicon oxide or silicon nitride. Optionally, the material of the grid lines may include metal or polysilicon, and the metal may be copper or tungsten.

[0070] Optionally, the wafer structure includes a CMOS wafer structure or an array wafer structure;

[0071] When the wafer structure is a CMOS wafer structure, the wafer structure also includes: peripheral circuits located in the film layer 102 and the oxide layer 104 ; when the wafer structure is an array wafer structure, the wafer structure also includes: storage structures located in the film layer 102 and the oxide layer 104 .

[0072] Optionally, the interface bonding mark 105 may penetrate the oxide layer 104 or may not penetrate the oxide layer 104 . This embodiment of the present application does not specifically limit this, and may be specifically set by those skilled in the art according to actual conditions.

[0073] In the embodiment of the present application, the reflective pattern 103 and the interface bonding mark 105 are located in the chip dicing area, which is located outside the storage structure. Therefore, they can be removed during the subsequent packaging and dicing to form the chip, without affecting the performance of the final chip structure.

[0074] The present application provides a wafer structure, which includes: a substrate, a film layer located on the substrate, a reflective pattern located in or on the film layer, an interface bonding mark located in an oxide layer on the film layer, the oxide layer is located on the side of the reflective pattern away from the substrate, and the reflective pattern and the interface bonding mark overlap in their orthographic projections on the plane where the substrate is located. The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold. Since the pattern density of the set reflective pattern and the pattern density of the interface bonding mark are quite different, the amount of light reflected by the reflective pattern and the interface bonding mark after being irradiated by the light source of the bonding machine is also quite different. The light-dark contrast of the interface bonding mark under the lens is high, and the interface bonding mark can be accurately identified, thereby improving the accuracy of wafer bonding alignment.

[0075] Exemplary Methods

[0076] See also Figure 4 FIG. 1 is a flow chart of a method for manufacturing a wafer structure provided in an embodiment of the present application, which may include:

[0077] S401: providing a substrate.

[0078] S402: forming a reflective pattern in or on a film layer on the substrate.

[0079] S403: forming an interface bonding mark in an oxide layer on the film layer; the oxide layer is located on a side of the reflective pattern away from the substrate.

[0080] The reflective pattern overlaps with the orthographic projection of the interface bonding mark on the plane where the substrate is located;

[0081] An absolute value of a difference between a pattern density of the reflective pattern and a pattern density of the interface bonding mark is greater than or equal to a critical threshold.

[0082] Optionally, the reflective pattern formed in or on the film layer on the substrate includes:

[0083] When the reflective pattern is formed in the film layer, a first sub-film layer is formed on the substrate, a reflective pattern layer is formed on the first sub-film layer, and the reflective pattern layer is etched to form the reflective pattern; and a second sub-film layer is formed on the reflective pattern;

[0084] When the reflective pattern is formed on the film layer, the film layer is formed on the substrate, a reflective pattern layer is formed on the film layer, and the reflective pattern layer is etched to form the reflective pattern.

[0085] Optionally, the interface bonding mark formed in the oxide layer on the film layer; the oxide layer is located on a side of the reflective pattern away from the substrate, comprises:

[0086] When the reflective pattern is formed in the film layer, the oxide layer formed on the film layer is etched to form an interface through hole, and the interface through hole is used as the interface bonding mark;

[0087] When the reflective pattern is formed on the film layer, an oxide layer is formed on the reflective pattern, and the oxide layer is etched to form an interface through hole, and the interface through hole is used as the interface bonding mark.

[0088] The present application provides a method for manufacturing a wafer structure. The wafer structure formed by the method includes:

[0089] A substrate, a film layer on the substrate, a reflective pattern in or on the film layer, an interface bonding mark in an oxide layer on the film layer, the oxide layer being located on a side of the reflective pattern away from the substrate, and the reflective pattern and the interface bonding mark overlapping in their orthographic projections on the plane of the substrate. The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold. Since the pattern density of the reflective pattern and the pattern density of the interface bonding mark are significantly different, the amount of light reflected by the reflective pattern and the interface bonding mark after being illuminated by the bonding machine light source is also significantly different. The light-dark contrast of the interface bonding mark is high under the lens, and the interface bonding mark can be accurately identified, thereby improving the accuracy of wafer bonding alignment.

[0090] On the basis of the above embodiments, an embodiment of the present application further provides a three-dimensional memory, including a wafer structure formed by using the above-mentioned method for manufacturing the wafer structure.

[0091] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from the other embodiments. In particular, the method embodiment is described briefly because it is generally similar to the wafer structure embodiment. For relevant parts, refer to the description of the method embodiment.

[0092] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A wafer structure, characterized in that: include: substrate; a film layer located on the substrate; a reflective pattern in or on the film layer; an interface bonding mark in an oxide layer on the film layer; The oxide layer is located on a side of the reflective pattern away from the substrate; The reflective pattern overlaps with the orthographic projection of the interface bonding mark on the plane where the substrate is located; The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold; the pattern density of the reflective pattern is the ratio of the area of ​​the reflective pattern to the total area of ​​the film layer in which it is located, and the pattern density of the interface bonding mark is the ratio of the area of ​​the interface bonding mark to the total area of ​​the oxide layer in which it is located; The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold, comprising: The pattern density of the reflective pattern is less than or equal to a first preset threshold, and the pattern density of the interface bonding mark is greater than or equal to a second preset threshold; the second preset threshold is greater than the first preset threshold; the difference between the second preset threshold and the first preset threshold is greater than or equal to the critical threshold; or, the pattern density of the reflective pattern is greater than or equal to a third preset threshold, and the pattern density of the interface bonding mark is less than or equal to a fourth preset threshold; the third preset threshold is greater than the fourth preset threshold; the difference between the third preset threshold and the fourth preset threshold is greater than or equal to the critical threshold.

2. The structure according to claim 1, characterized in that The light reflecting pattern includes a grating.

3. The structure according to claim 2, characterized in that The grating includes a plurality of grid lines arranged at intervals; the slits between the grid lines are filled with silicon oxide or silicon nitride.

4. The structure according to claim 3, characterized in that The gate line is made of metal or polysilicon.

5. The structure according to any one of claims 1 to 4, characterized in that: The wafer structure includes a CMOS wafer structure or an array wafer structure; When the wafer structure is a CMOS wafer structure, the wafer structure further includes: peripheral circuits located in the film layer and the oxide layer; When the wafer structure is an array wafer structure, the wafer structure further includes: a storage structure located in the film layer and the oxide layer.

6. The structure according to claim 5, characterized in that The reflective pattern and the interface bonding mark are located in the area where the chip cutting lanes are located; and the area where the cutting lanes are located is located outside the storage structure.

7. A method for manufacturing a wafer structure, characterized in that: include: providing a substrate; a reflective pattern formed in or on a film layer on the substrate; an interface bonding mark formed in an oxide layer on the film layer; The oxide layer is located on a side of the reflective pattern away from the substrate; The reflective pattern overlaps with the orthographic projection of the interface bonding mark on the plane where the substrate is located; The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold; the pattern density of the reflective pattern is the ratio of the area of ​​the reflective pattern to the total area of ​​the film layer in which it is located, and the pattern density of the interface bonding mark is the ratio of the area of ​​the interface bonding mark to the total area of ​​the oxide layer in which it is located; The absolute value of the difference between the pattern density of the reflective pattern and the pattern density of the interface bonding mark is greater than or equal to a critical threshold, comprising: The pattern density of the reflective pattern is less than or equal to a first preset threshold, and the pattern density of the interface bonding mark is greater than or equal to a second preset threshold; the second preset threshold is greater than the first preset threshold; the difference between the second preset threshold and the first preset threshold is greater than or equal to the critical threshold; or, the pattern density of the reflective pattern is greater than or equal to a third preset threshold, and the pattern density of the interface bonding mark is less than or equal to a fourth preset threshold; the third preset threshold is greater than the fourth preset threshold; the difference between the third preset threshold and the fourth preset threshold is greater than or equal to the critical threshold.

8. The method according to claim 7, characterized in that The reflective pattern formed in or on the film layer on the substrate includes: When the reflective pattern is formed in the film layer, a first sub-film layer is formed on the substrate, a reflective pattern layer is formed on the first sub-film layer, and the reflective pattern layer is etched to form the reflective pattern; and a second sub-film layer is formed on the reflective pattern; When the reflective pattern is formed on the film layer, the film layer is formed on the substrate, a reflective pattern layer is formed on the film layer, and the reflective pattern layer is etched to form the reflective pattern.

9. The method according to claim 7, characterized in that said interface bonding mark formed in the oxide layer on said film layer; The oxide layer is located on a side of the reflective pattern away from the substrate, and includes: When the reflective pattern is formed in the film layer, the oxide layer formed on the film layer is etched to form an interface through hole, and the interface through hole is used as the interface bonding mark; When the reflective pattern is formed on the film layer, an oxide layer is formed on the reflective pattern, and the oxide layer is etched to form an interface through hole, and the interface through hole is used as the interface bonding mark.

10. A three-dimensional memory, characterized in that: The invention comprises a wafer structure formed by the method according to any one of claims 7 to 9.

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