Semiconductor structure with high voltage resistor device and manufacturing method thereof

Abstract

The present application relates to the field of semiconductor integrated circuit manufacturing technology, and more specifically, to a semiconductor structure with a high-voltage resistor device and a manufacturing method thereof. The structure comprises: a base layer, the base layer comprising a drain region, a source region, and a drift region located between the drain and source regions; a first-conductivity-type high-resistance region, the first-conductivity-type high-resistance region located in the base layer and extending at least through the drain, source, and drift regions; an upper surface of the first-conductivity-type high-resistance region at the drift region location is oxidized to form a field oxide layer; the field oxide layer comprises a plurality of raised regions and a plurality of recessed regions, with one recessed region between two adjacent raised regions; and a polysilicon resistor layer, the polysilicon resistor layer spirally arranged a plurality of times on the field oxide layer, with each polysilicon resistor layer spanning the field oxide layer between the raised and recessed regions. The manufacturing method is used to manufacture the above-mentioned structure.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor structure with a high-voltage resistor device and a manufacturing method thereof. Background Art

[0002] The BCD (Bipolar-CMOS-DMOS) process integrates various devices, including bipolar devices for analog functions, CMOS devices for digital design, and DMOS devices for high-voltage and high-power structures, on the same chip. The analog bipolar devices serve as the interface between external circuits and the semiconductor's internal circuitry, the CMOS devices serve as the core for signal processing, and the DMOS devices drive external circuit loads. By integrating circuits with different functions on the same chip, the number of interconnects within the semiconductor integrated circuit system is reduced.

[0003] In the manufacturing process of ultra-high-voltage, high-resistance BCDs, in order to achieve high voltage resistance for polysilicon resistors, the polysilicon resistors are usually wound in a spiral shape on the drift region of a high-voltage field-effect transistor, which then provides the polysilicon resistor with high voltage resistance. As a result, the voltage resistance of the polysilicon resistor depends on the voltage resistance of the high-voltage field-effect transistor. Therefore, related technologies usually extend the high-voltage drift region of the high-voltage field-effect transistor to improve the voltage resistance of the device, thereby improving the voltage resistance of the polysilicon resistor.

[0004] However, the source region of the high-voltage field-effect transistor is connected to the source metal and the first polysilicon field plate, and the drain region is connected to the drain metal and the second polysilicon field plate. There is no field plate in the drift region between the first and second polysilicon field plates to regulate the electric field. Therefore, simply lengthening the drift region will only increase the withstand voltage to a limited extent. After a certain length, the withstand voltage will no longer increase, and the effectiveness of the other field plates will also deteriorate. Summary of the Invention

[0005] The present application provides a semiconductor structure with a high-voltage resistor device and a manufacturing method thereof, which can solve the limitation problem brought about by relying on lengthening the drift region to improve the voltage resistance performance of the polysilicon resistor in the related art.

[0006] In order to solve the technical problem described in the background technology, the first aspect of the present application provides a semiconductor structure with a high-voltage resistor device, wherein the semiconductor structure with a high-voltage resistor device includes:

[0007] a base layer, the base layer comprising a drain region, a source region, and a drift region located between the drain region and the source region;

[0008] a first conductive type high resistance region, the first conductive type high resistance region being located in the base layer and extending at least through the drain region, the source region, and the drift region; an upper surface of the first conductive type high resistance region at the drift region is oxidized to form a field oxide layer; the field oxide layer comprises a plurality of raised regions spaced apart by a plurality of circles and a plurality of recessed regions spaced apart by a plurality of circles, with one recessed region spaced apart from two adjacent circles of the raised regions;

[0009] A polysilicon resistance layer is spirally wound around the field oxide layer for a plurality of turns, and each turn of the polysilicon resistance layer is connected across the field oxide layer between the raised area and the recessed area.

[0010] Optionally, the polysilicon resistance layer includes a first end and a second end, and the polysilicon resistance layer is spirally wound from the first end to the second end for several turns.

[0011] Optionally, it also includes a gate polysilicon structure and a drain field plate structure;

[0012] The gate polysilicon structure is located on a side of the polysilicon resistance layer close to the source region, and the gate polysilicon structure spans the drift region and the source region;

[0013] The drain region field plate structure is located on a side of the polysilicon resistance layer close to the drain region.

[0014] In order to solve the technical problem described in the background technology, the second aspect of the present application further provides a semiconductor manufacturing method with a high-voltage resistor device, the semiconductor manufacturing method with a high-voltage resistor device comprising:

[0015] providing a semiconductor base layer;

[0016] forming a first barrier layer with a first barrier pattern on the drift region of the base layer, wherein the first barrier layer surrounds the first barrier pattern;

[0017] Performing first conductive type ion implantation on the base layer with the first barrier layer, so that a first conductive type implantation region is formed in the base layer not covered with the first barrier layer, and a non-implantation region is formed in the base layer covered with the first barrier layer;

[0018] removing the first barrier layer so that the upper surface of the base layer is exposed;

[0019] Performing high-temperature oxidation to push the well, so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection region is merged into a first conductive type high resistance region; the thickness of the oxide layer formed by the oxidation of the first conductive type injection region is greater than the thickness of the oxide layer formed by the oxidation of the non-injected region;

[0020] removing the oxide layer so that the oxidized upper surface of the base layer is exposed, and the drift region includes convex regions and concave regions that are alternately distributed;

[0021] According to the morphology of the upper surface of the base layer at the position of the drift region, the upper surface of the base layer at the position of the drift region is oxidized to form a field oxide layer with convex regions and concave regions alternately distributed;

[0022] A polysilicon resistance layer with spiral spacing is formed on the field oxide layer, so that the polysilicon resistance layer is connected across the field oxide layer between the protruding area and the recessed area.

[0023] Optionally, the step of implanting first conductive type ions into the base layer with the first barrier layer to form a first conductive type implantation region in the base layer not covered by the first barrier layer includes:

[0024] Firstly, a first ion implantation is performed on the base layer with the first barrier layer using first conductive type impurity ions;

[0025] Then, performing a second ion implantation on the base layer with the first barrier layer using first conductive type impurity ions;

[0026] A first conductive type injection region is formed in the base layer not covered by the first barrier layer.

[0027] Optionally, the step of performing a first ion implantation of the first conductive type impurity ions into the base layer having the first barrier layer includes:

[0028] The base layer with the first barrier layer is subjected to an ion ionization process with an energy of 30keV to 100keV and a concentration of 1e13 to 5e14 ions / cm 2 The first ion implantation dose.

[0029] Optionally, the step of performing a second ion implantation of the first conductive type impurity ions into the base layer having the first barrier layer comprises:

[0030] The base layer with the first barrier layer is subjected to an ion ionization process with an energy of 110keV to 1000keV and a concentration of 5e11 to 1e13 ions / cm 2 The second ion implantation with a dose of 100 μg / min was performed.

[0031] Optionally, the step of performing high-temperature oxidation to form a well, so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection region is merged into a first conductive type high resistance region; the thickness of the oxide layer formed by oxidation of the first conductive type injection region is greater than the thickness of the oxide layer formed by oxidation of the non-injected region, comprises:

[0032] In the temperature range of 1000°C to 1500°C, a high-temperature oxidation well is performed for 100 minutes to 120 minutes, so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection area is merged into a first conductive type high resistance area; the thickness of the oxide layer formed by the oxidation of the first conductive type injection area is greater than the thickness of the oxide layer formed by the oxidation of the non-injected area.

[0033] Optionally, in the step of forming a first barrier layer with a first barrier pattern on the drift region of the base layer, the first barrier layer is spaced around to form the first barrier pattern, the first barrier layer is spaced around for several circles, and the interval between two adjacent circles of the first barrier layer is 2um to 10um.

[0034] Optionally, the step of forming a first barrier layer having a first barrier pattern on the drift region of the base layer, wherein the first barrier layer is spaced around to form the first barrier pattern comprises:

[0035] A first barrier layer with a first barrier pattern is formed on the drift region of the base layer, and the first barrier layer is spirally or concentrically arranged to form the first barrier pattern.

[0036] The technical solution of the present application includes at least the following advantages: the polysilicon resistor layer located on the drift region bridges the raised area and the recessed area of the field oxide layer, so that the polysilicon resistor layer can act as a resistor on the one hand, and on the other hand, it can also serve as a field plate in the drift region to adjust the electric field in the drift region and increase the voltage resistance performance of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A flow chart of a semiconductor manufacturing method with a high-voltage resistor device provided in one embodiment of the present application is shown;

[0039] Figure 1a shows a schematic cross-sectional structure diagram of the semiconductor base layer provided in step S1;

[0040] Figure 1b A schematic diagram of a top view of an embodiment of a device formed after step S2 is completed is shown;

[0041] Figure 1c FIG2 shows a schematic top view of another embodiment of the device formed after step S2 is completed;

[0042] Figure 1d Shown Figure 1b AA-axis cross-sectional structural diagram;

[0043] Figure 1e Shows the Figure 1d A schematic diagram of a cross-sectional structure of the device after performing step S3;

[0044] Figure 1f FIG4 shows a schematic diagram of a cross-sectional structure of the device after step S4 is completed;

[0045] Figure 1g Shows the removal Figure 1f Schematic diagram of the cross-sectional structure of the device after the oxide layer is shown;

[0046] Figure 1h FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S6 is completed;

[0047] Figure 1i FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S7 is completed;

[0048] Figure 1j A schematic diagram of a cross-sectional structure of a device for forming a metal interconnection layer is shown. DETAILED DESCRIPTION

[0049] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0050] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0052] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0053] Figure 1 A flow chart of a semiconductor manufacturing method with a high voltage resistor device according to an embodiment of the present application is shown. Figure 1 It can be seen that the semiconductor manufacturing method with a high-voltage resistor device includes the following steps performed in sequence:

[0054] Step S1: providing a semiconductor base layer.

[0055] Reference Figure 1a , which shows a schematic cross-sectional structure diagram of the semiconductor substrate layer provided in step S1, Figure 1a As can be seen in FIG, the base layer 101 includes an upper surface and a lower surface relative to each other, and the base layer 101 also includes a drain region 120 for forming a device drain structure, a source region 110 for forming a device source structure, and a drift region 130 located between the drain region 120 and the source region 110. Optionally, the base layer 101 may be a silicon substrate.

[0056] Step S2: forming a first barrier layer with a first barrier pattern on the drift region of the base layer, wherein the first barrier layer is spaced around to form the first barrier pattern, and the first barrier pattern includes a barrier portion and an exposed portion, and the barrier portion and the exposed portion are alternately distributed.

[0057] The first barrier layer may be formed by spirally rotating to form the first barrier pattern, or may be formed by concentrically rotating to form the first barrier pattern.

[0058] Reference Figure 1b , which shows a schematic diagram of a top view of an embodiment of a device formed after step S2 is completed, Figure 1b As can be seen in FIG, a first barrier layer 210 is formed on the upper surface of the base layer 101. The first barrier layer 210 is located on the upper surface of the base layer 101 at the position of the drift region 130. The first barrier layer 210 spirally surrounds from one end to the other end to form the first barrier pattern.

[0059] Reference Figure 1c , which shows a schematic diagram of a top view of another embodiment of the device formed after step S2 is completed, Figure 1c As can be seen in FIG, a first barrier layer 210 is formed on the upper surface of the base layer 101. The first barrier layer 210 is located on the upper surface of the base layer 101 at the position of the drift region 130. The first barrier layer 210 includes a plurality of concentric circles, which are spaced apart to form the first barrier pattern.

[0060] like Figure 1b and Figure 1c As shown, the drain region 120 may be located in the middle of the device, the source region 110 is located outside the device, and the source region 110 is a closed ring that surrounds the drain region 120 .

[0061] Reference Figure 1d , which shows Figure 1b or Figure 1c AA-direction cross-sectional structural diagram, from Figure 1d As can be seen in FIG, the first barrier layer 210 forms a first barrier pattern, which includes barrier portions 211 and exposed portions 212, which are alternately distributed. The barrier portions 211 are portions of the first barrier layer 210 that are covered and surrounded by the spacers, and can block subsequent ion implantation. The exposed portions 212 are the spaced portions of the first barrier layer 210 that are surrounded by the spacers, and the upper surface of the base layer 101 at the locations of the exposed portions 212 is exposed.

[0062] If the first barrier layer 210 is Figure 1b The spiral spacing shown is surrounded, and the barrier portion 211 of the first barrier pattern is also surrounded by the same spiral spacing. The exposed portion 212 of the first barrier pattern is the spaced portion of the spiral spacing.

[0063] If the first barrier layer 210 is Figure 1c The concentric circles shown are spaced apart, and the barrier portion 211 of the first barrier pattern is also spaced apart by the same concentric circles. The exposed portion 212 of the first barrier pattern is the spaced portion surrounded by the concentric circles.

[0064] Optionally, the first barrier layer 210 may be a photoresist, and the first barrier layer 210 may have a first barrier pattern through a photolithography process.

[0065] Step S3: performing first conductive type ion implantation on the base layer with the first barrier layer, so that a first conductive type implantation region is formed in the base layer not covered by the first barrier layer, and a non-implantation region is formed in the base layer covered by the first barrier layer.

[0066] In this embodiment, N type is the first conductive type, and the first conductive type ion implantation is N type ion implantation. Figure 1e , which shows the Figure 1d The schematic diagram of the device cross-sectional structure after step S3 is shown. Figure 1e As can be seen in FIG1c , after N-type ion implantation is performed on the structure shown in FIG1c , an N-type implantation region 102 is formed in the base layer 101 not covered by the first barrier layer 210. Specifically, an N-type implantation region 102 is formed in the base layer 101 corresponding to the exposed portion 212 of the first barrier pattern. The N-type implantation region 102 extends downward from the upper surface of the base layer 101. Due to the blocking effect of the first barrier layer 210 at the location of the blocking portion 211 of the first barrier pattern, N-type ions are not implanted in the base layer 101 at this location, forming an unimplanted region.

[0067] Since the first barrier layer 210 is spaced and surrounded to form the first barrier pattern, and the barrier portion 211 and the exposed portion 212 are alternately distributed on the drift region 130 of the base layer 101, the N-type injection region 102 and the non-injection region in the base layer 101 at the drift region 130 are also spaced and surrounded for several circles, and the N-type injection region 102 and the non-injection region are alternately distributed, that is, one circle of the non-injection region is located between two adjacent circles of the N-type injection region 102.

[0068] During step S3, a first low-energy, high-dose ion implantation can be performed on the base layer 101 with the first barrier layer 210 using N-type impurity ions; and then a second high-energy, low-dose ion implantation can be performed on the base layer 101 with the first barrier layer 210 using N-type impurity ions; thereby forming an N-type implantation region 102 in the base layer 101 not covered by the first barrier layer 210.

[0069] The ion implantation energy of the first low-energy, high-dose ion implantation is 30keV to 100keV, and the ion implantation dose is 1e13 to 5e14 ions / cm 2 The second ion implantation with high energy and low dose has an ion implantation energy of 110keV to 1000keV and an ion implantation dose of 5e11 to 1e13 ions / cm 2 .

[0070] After the first conductive type implantation region is formed in step S3 , the first barrier layer 210 is removed.

[0071] Step S4: performing high-temperature oxidation to push the well, so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection area is integrated into the first conductive type high resistance area; the thickness of the oxide layer formed by oxidation of the first conductive type injection area is greater than the thickness of the oxide layer formed by oxidation of the non-injected area.

[0072] Reference Figure 1f , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed. In step S4, oxygen is introduced during the high-temperature trapping process, so that Figure 1e The N-type implanted region 102 is integrated into an N-type high resistance region 112, and the upper surface of the base layer 101 is oxidized to form an oxide layer 310. Different regions of the upper surface of the base layer 101 are oxidized to form the oxide layer 310 with different thicknesses. Figure 1e and Figure 1f It can be seen that the upper surface of the base layer 101 located at the N-type injection region 102 is oxidized to a higher degree, and the thickness of the formed oxide layer 310 is thicker. The upper surface of the base layer 101 located at other positions other than the N-type injection region 102 (such as the non-injection region) is oxidized to a lower degree, and the thickness of the formed oxide layer 310 is thinner.

[0073] Since the N-type implanted regions 102 and the non-implanted regions are also spaced apart by several circles, the N-type implanted regions 102 and the non-implanted regions are alternately distributed, so that the upper surface of the base layer 101 at the position of the N-type implanted regions 102 is oxidized to form a thicker oxide layer 310, and the upper surface of the base layer 101 at the position of the non-implanted regions is oxidized to form a thinner oxide layer 310, which are also spaced apart by several circles, and as shown in FIG. Figure 1f As shown, the thicker oxide layer 310 and the thinner oxide layer 310 are alternately distributed, that is, a circle of thinner oxide layer 310 is located between two adjacent circles of thicker oxide layer 310 .

[0074] Step S5: removing the oxide layer so that the oxidized upper surface of the base layer is exposed, and the drift region includes convex regions and concave regions that are alternately distributed.

[0075] Reference Figure 1g , which shows the removal Figure 1f The schematic diagram of the cross-sectional structure of the device after the oxidation layer is shown. Since the upper surface of the base layer 101 is oxidized to different degrees in step S4, especially for the drift region 130, the thicker oxide layer 310 formed by oxidation is alternately distributed with the thinner oxide layer 310 formed by oxidation. Figure 1f After the oxide layer shown is removed, the upper surface of the base layer 101 is uneven, especially for the drift region, the thicker oxide layer 310 is removed to form a recessed region 132, and the thinner oxide layer 310 is removed to form a raised region 131. The raised regions 131 and the recessed regions 132 are alternately distributed at the position of the drift region 130, and the raised regions 131 and the recessed regions 132 are also spaced apart by several circles, and a circle of raised regions 131 is located between two adjacent circles of recessed regions 132.

[0076] Step S6 , oxidizing the upper surface of the base layer at the drift region location to form a field oxide layer with convex regions and concave regions alternately distributed according to the upper surface morphology of the base layer at the drift region location.

[0077] Reference Figure 1h , which shows a schematic diagram of the cross-sectional structure of the device after step S6 is completed, Figure 1h As can be seen from the figure, the upper surface of the base layer 101 at the position of the drift region 130 is oxidized to form a field oxide layer 410. Figure 1g The upper surface morphology of the base layer 101 at the position of the drift region 130 is formed, so that the field oxide layer 410 also includes alternating convex regions 131 and concave regions 132. The convex regions 131 and the concave regions 132 are also spaced apart by several circles, and a circle of convex regions 131 is located between two adjacent circles of concave regions 132.

[0078] Optionally, you can first make Figure 1g As shown, an oxidation barrier layer is formed on the upper surface of the base layer 101 in the region other than the drift region 130, so that the upper surface of the base layer 101 at the position of the drift region 130 is exposed, so as to perform an oxidation step, so that the upper surface of the base layer 101 at the position of the drift region 130 is oxidized to form Figure 1h The field oxide layer 410 is shown. The oxidation barrier layer may be silicon nitride.

[0079] Step S7 forms a polysilicon resistance layer on the field oxide layer, so that the polysilicon resistance layer is connected across the field oxide layer between the protruding area and the recessed area.

[0080] Optionally, you can first Figure 1h A polysilicon layer is deposited on the device structure shown, and then selectively etched to form a polysilicon resistor layer. The polysilicon resistor layer is spirally spaced and spans the field oxide layer between the raised area and the recessed area.

[0081] Reference Figure 1i , which shows a schematic diagram of the cross-sectional structure of the device after step S7 is completed, Figure 1i As can be seen in the figure, the polysilicon resistor layer 510 includes a first end 511 and a second end 512. The polysilicon resistor layer 510 is spirally wound in a continuous number of circles from the first end 511 to the second end 512. Two adjacent circles of the polysilicon resistor layer 510 are spaced apart, and each circle of the polysilicon resistor layer 510 is connected between the raised area 131 and the recessed area 132 where the field oxide layer 41 is connected. That is, each circle of the polysilicon resistor layer 510 covers the field oxide layer 410 at the junction of the adjacent raised area 131 and the recessed area 132.

[0082] The polysilicon resistor layer located on the drift region bridges the raised area and the recessed area of the field oxide layer, so that the polysilicon resistor layer can act as a resistor on the one hand, and on the other hand, it can also serve as a field plate in the drift region to adjust the electric field in the drift region and increase the voltage resistance performance of the field effect transistor.

[0083] In addition, in the step of selectively etching the polysilicon layer to form the polysilicon resistance layer, the gate polysilicon structure 520 and the drain field plate structure 530 can also be formed by selectively etching the polysilicon layer. Figure 1i As can be seen, the gate polysilicon structure 520 is located on the side of the polysilicon resistance layer 510 close to the source region 110, the gate polysilicon structure 520 bridges the drift region 130 and the source region 110, and the drain field plate structure 530 is located on the side of the polysilicon resistance layer 510 close to the drain region 120.

[0084] After step S7 is completed, Figure 1i Based on the structure shown in FIG, a source structure is fabricated in the source region 110, a drain structure is fabricated in the drain region 120, and then a metal interconnection layer is fabricated to form Figure 1j In the structure shown, the first end 511 of the polysilicon resistance layer 510 is led out through the first lead 610, the second end 512 is connected to the drain field plate structure 530 and the drain structure and is led out through the second lead 620, and the gate polysilicon structure 520 is connected to the source structure and is led out through the third lead 630.

[0085] The present application also provides a semiconductor structure of a high-voltage resistor device, which can be manufactured by the semiconductor manufacturing method of the high-voltage resistor device described above.

[0086] Reference Figure 1h and Figure 1i The semiconductor structure of the manufactured high-voltage resistor device includes:

[0087] The base layer 101 includes a drain region 120 , a source region 110 , and a drift region 130 located between the drain region 120 and the source region 110 .

[0088] A first conductive type high resistance region 112 is located in the base layer 101 and extends at least through the drain region 120, the source region 110 and the drift region 130; the upper surface of the first conductive type high resistance region 112 at the position of the drift region 130 is oxidized to form a field oxide layer 410; the field oxide layer 410 includes raised regions 131 spaced apart by several circles and recessed regions 132 spaced apart by several circles, and one circle of the recessed region 132 is spaced apart between two adjacent circles of the raised regions 131.

[0089] Optionally, the plurality of circles of raised areas 131 and the plurality of circles of recessed areas 132 may be spirally spaced, with one circle of raised areas 131 located between two adjacent circles of recessed areas 132 .

[0090] In addition, the plurality of circles of raised areas 131 and the plurality of circles of recessed areas 132 may also be arranged in concentric circles, with one circle of raised areas 131 located between two adjacent circles of recessed areas 132 .

[0091] The polysilicon resistance layer 510 is spirally wound around the field oxide layer 410 for a plurality of turns, and each turn of the polysilicon resistance layer 510 is connected across the field oxide layer 410 between the protruding area 131 and the recessed area 132 .

[0092] The polysilicon resistance layer 510 includes a first end 511 and a second end 512 . The polysilicon resistance layer 510 is spirally wound from the first end 511 to the second end 512 for several consecutive turns.

[0093] Continue to refer to Figure 1i The semiconductor structure of the high-voltage resistor device further includes a gate polysilicon structure 520 and a drain field plate structure 530 .

[0094] The gate polysilicon structure 520 is located on a side of the polysilicon resistance layer 510 close to the source region 110 . The gate polysilicon structure 520 bridges the drift region 130 and the source region 110 .

[0095] The drain field plate structure 530 is located on a side of the polysilicon resistance layer 510 close to the drain region 120 .

[0096] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A semiconductor structure with a high voltage resistor device, characterized in that: The semiconductor structure with a high-voltage resistor device includes: a base layer, the base layer comprising a drain region, a source region, and a drift region located between the drain region and the source region; a first conductive type high resistance region, the first conductive type high resistance region being located in the base layer and extending at least through the drain region, the source region, and the drift region; an upper surface of the first conductive type high resistance region at the drift region is oxidized to form a field oxide layer; the field oxide layer comprises a plurality of raised regions spaced apart by a plurality of circles and a plurality of recessed regions spaced apart by a plurality of circles, with one recessed region spaced apart from two adjacent circles of the raised regions; A polysilicon resistor layer is arranged to surround the field oxide layer in a plurality of circles, and each circle of the polysilicon resistor layer is connected across the field oxide layer between the raised area and the recessed area. The spacing and surrounding manners include spiral spacing and concentric circle spacing.

2. The semiconductor structure with a high voltage resistor device according to claim 1, wherein: The polysilicon resistance layer includes a first end and a second end, and the polysilicon resistance layer spirally wraps from the first end to the second end through a plurality of consecutive turns.

3. The semiconductor structure with a high voltage resistor device according to claim 1, wherein: It also includes a gate polysilicon structure and a drain field plate structure; The gate polysilicon structure is located on a side of the polysilicon resistance layer close to the source region, and the gate polysilicon structure spans the drift region and the source region; The drain region field plate structure is located on a side of the polysilicon resistance layer close to the drain region.

4. A method for manufacturing a semiconductor device with a high voltage resistor, characterized in that: The semiconductor manufacturing method with a high-voltage resistor device includes: providing a semiconductor base layer; forming a first barrier layer with a first barrier pattern on the drift region of the base layer, wherein the first barrier layer surrounds the first barrier pattern; Performing first conductive type ion implantation on the base layer with the first barrier layer, so that a first conductive type implantation region is formed in the base layer not covered with the first barrier layer, and a non-implantation region is formed in the base layer covered with the first barrier layer; removing the first barrier layer so that the upper surface of the base layer is exposed; Performing high-temperature oxidation to push the well, so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection region is merged into a first conductive type high resistance region; the thickness of the oxide layer formed by the oxidation of the first conductive type injection region is greater than the thickness of the oxide layer formed by the oxidation of the non-injected region; removing the oxide layer so that the oxidized upper surface of the base layer is exposed, and the drift region includes convex regions and concave regions that are alternately distributed; According to the morphology of the upper surface of the base layer at the position of the drift region, the upper surface of the base layer at the position of the drift region is oxidized to form a field oxide layer with convex regions and concave regions alternately distributed; A polysilicon resistance layer with spaced surroundings is formed on the field oxide layer, so that the polysilicon resistance layer is connected across the field oxide layer between the protruding area and the recessed area, wherein the spaced surroundings include spiral spaced surroundings and concentric circle spaced surroundings.

5. The method for manufacturing a semiconductor device with a high voltage resistor according to claim 4, wherein: The step of implanting first conductive type ions into the base layer with the first barrier layer to form a first conductive type implantation region in the base layer not covered by the first barrier layer includes: Firstly, a first ion implantation is performed on the base layer with the first barrier layer using first conductive type impurity ions; Then, performing a second ion implantation on the base layer with the first barrier layer using first conductive type impurity ions; A first conductive type injection region is formed in the base layer not covered by the first barrier layer.

6. The method for manufacturing a semiconductor device with a high voltage resistor according to claim 5, wherein: The step of firstly performing a first ion implantation on the base layer with the first barrier layer using first conductive type impurity ions comprises: The base layer with the first barrier layer is subjected to an ion ionization process with an energy of 30keV to 100keV and a concentration of 1e13 to 5e14 ions / cm 2 The first ion implantation dose.

7. The method for manufacturing a semiconductor device with a high voltage resistor according to claim 5, wherein: The step of performing a second ion implantation of the first conductive type impurity ions into the base layer having the first barrier layer comprises: The base layer with the first barrier layer is subjected to an ion ionization process with an energy of 110keV to 1000keV and a concentration of 5e11 to 1e13 ions / cm 2 The second ion implantation with a dose of 100 μg / min was performed.

8. The method for manufacturing a semiconductor device with a high voltage resistor according to claim 4, wherein: The high temperature oxidation well driving is performed so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection region is merged into a first conductive type high resistance region; The step of oxidizing the first conductive type implanted region to form an oxide layer having a thickness greater than that of the oxide layer formed by oxidizing the non-implanted region comprises: In the temperature range of 1000°C to 1500°C, a high-temperature oxidation well is performed for 100 minutes to 120 minutes, so that the upper surface of the base layer is oxidized to form an oxide layer, so that the first conductive type injection area is merged into a first conductive type high resistance area; the thickness of the oxide layer formed by the oxidation of the first conductive type injection area is greater than the thickness of the oxide layer formed by the oxidation of the non-injected area.

9. The method for manufacturing a semiconductor device with a high voltage resistor according to claim 4, wherein: The first barrier layer with a first barrier pattern is formed on the drift region of the base layer. In the step of forming the first barrier pattern by circling the first barrier layer, the first barrier layer is circled several times, and the interval between two adjacent circles of the first barrier layer is 2um to 10um.

10. The method for manufacturing a semiconductor device with a high voltage resistor according to claim 4, wherein: The step of forming a first barrier layer with a first barrier pattern on the drift region of the base layer, wherein the first barrier layer is spaced around the first barrier pattern, comprises: A first barrier layer with a first barrier pattern is formed on the drift region of the base layer, and the first barrier layer is spirally or concentrically arranged to form the first barrier pattern.

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