Semiconductor device and method of manufacturing the same, memory, storage system, electronic device

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and a three-dimensional memory, and relates to the technical field of semiconductor chips, and is used for controlling the warping degree of a wafer on which the semiconductor device is arranged.The preparation method of the semiconductor device comprises the following steps: providing a three-dimensional array structure; the three-dimensional array structure comprises a substrate, a sacrificial layer arranged on one side of the substrate, and a stack structure arranged on the side of the sacrificial layer away from the substrate; forming a gate line gap penetrating through the stack structure and extending to the sacrificial layer; forming a doped polysilicon film and performing annealing treatment on the doped polysilicon film; the doped polysilicon film covers at least the inner wall of the gate line gap; forming a polysilicon film and performing annealing treatment on the polysilicon film; and the polysilicon film covers the doped polysilicon film. The semiconductor device is applied to a three-dimensional memory to realize data reading and writing operations.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor device and a preparation method thereof, a memory, a storage system and an electronic device. BACKGROUND

[0002] As the feature size of the memory cell approaches the lower limit of the process, the planar process and manufacturing technology become challenging and costly, which causes the storage density of the 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of the 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to improve the storage density by arranging the memory cells three-dimensionally above the substrate.

[0003] As the number of stacked layers in the 3D NAND increases, the overall stress of the wafer with the 3D NAND increases, which in turn causes the wafer to easily warp. This not only easily causes the film layers in the wafer to be misaligned, but also increases the difficulty of bonding in the subsequent process of bonding the wafer with the peripheral circuit. Therefore, the control of the overall stress of the wafer is becoming more and more important.

[0004] The above-mentioned 3D NAND includes an array common source (ACS) which is a structure with high conductivity requirement. At present, it is difficult to control the stress generated in the process of preparing and forming the array common source, and thus it is difficult to control the warping degree of the wafer. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, and a three-dimensional memory, for realizing the control of the warping degree of the wafer on which the semiconductor device is located.

[0006] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a preparation method of a semiconductor device is provided. The preparation method of the semiconductor device includes: providing a three-dimensional array structure; the three-dimensional array structure includes a substrate, a sacrificial layer arranged on one side of the substrate, and a stack structure arranged on a side of the sacrificial layer away from the substrate; forming a gate line gap penetrating through the stack structure and extending to the sacrificial layer; forming a doped polysilicon film and performing annealing treatment on the doped polysilicon film; the doped polysilicon film covers at least the inner wall of the gate line gap; forming a polysilicon film and performing annealing treatment on the polysilicon film; the polysilicon film covers the doped polysilicon film.

[0008] Thus, some embodiments of the disclosure provide a method for manufacturing a semiconductor device. After forming a gate line slit extending through a stack structure and extending to a sacrificial layer, at least a doped polysilicon film covering the gate line slit is formed. After annealing the doped polysilicon film to substantially eliminate the stress of the doped polysilicon film, a polysilicon film covering the doped polysilicon film is formed, so that the polysilicon film substantially fills the gap between the portions of the doped polysilicon film covering different sidewalls of the same gate line slit, and the polysilicon film has a relatively large stress. In this way, not only can the doped polysilicon film support the gate line slit and stabilize the stack structure, but also the thickness ratio between the doped polysilicon film and the polysilicon film can be adjusted to adjust the influence of the polysilicon film on the stress of the wafer as a whole, and then the warping degree of the wafer can be adjusted to control the warping degree of the wafer.

[0009] In addition, the annealing process is performed on the doped polysilicon film after the doped polysilicon film is formed, and the annealing process is performed on the polysilicon film after the polysilicon film is formed, so that the doped polysilicon film and the polysilicon film can be shaped and the structural stability of the doped polysilicon film and the polysilicon film can be improved. In this way, in the case where an annealing process needs to be used in the subsequent manufacturing process, the influence on the doped polysilicon film and the polysilicon film can be reduced, and then the influence on the warping degree of the wafer can be reduced and the stability of the process can be improved.

[0010] In some embodiments, the annealing process on the doped polysilicon film is an in-situ annealing process, and / or the annealing process on the polysilicon film is an in-situ annealing process.

[0011] In some embodiments, the ratio of the thickness of the doped polysilicon film to the thickness of the polysilicon film ranges from 10:1 to 1:10.

[0012] In some embodiments, the impurity atoms in the doped polysilicon film include phosphorus atoms.

[0013] In some embodiments, the doped polysilicon film and the polysilicon film also cover the stack structure. The method further includes removing the portions of the polysilicon film and the portions of the doped polysilicon film that cover the stack structure, and retaining the portions of the polysilicon film and the portions of the doped polysilicon film that are located in the gate line slit.

[0014] In some embodiments, before the forming of the doped polysilicon thin film, the preparation method further comprises: forming an isolation thin film covering at least the inner wall of the gate line gap. The preparation method further comprises: removing the substrate and the sacrificial layer to expose the portion of the isolation thin film extending to the sacrificial layer; etching the isolation thin film to expose the portion of the doped polysilicon thin film extending to the sacrificial layer; forming a source layer on one side of the stack structure; the source layer forms an electrical contact with the exposed portion of the doped polysilicon thin film.

[0015] In some embodiments, the three-dimensional array structure further comprises a channel structure extending through the stack structure and extending to the sacrificial layer; the channel structure comprises a storage functional layer and a channel layer arranged in sequence. After removing the substrate and the sacrificial layer, the portion of the storage functional layer extending to the sacrificial layer is also exposed; during etching the isolation thin film, the exposed portion of the storage functional layer is also etched to expose the portion of the channel layer extending to the sacrificial layer; the source layer also forms an electrical contact with the exposed portion of the channel layer.

[0016] In some embodiments, before forming the stack structure, the preparation method further comprises: sequentially laminating a first etching stop layer and a second etching stop layer on the side of the sacrificial layer away from the substrate. Removing the substrate and the sacrificial layer to expose the portion of the storage functional layer extending to the sacrificial layer and the portion of the isolation thin film extending to the sacrificial layer comprises: removing the substrate and the sacrificial layer to the first etching stop layer to expose the portion of the storage functional layer extending to the sacrificial layer and the portion of the isolation thin film extending to the sacrificial layer; etching the first etching stop layer and the exposed portion of the storage functional layer to the second etching stop layer to expose the portion of the channel layer extending to the sacrificial layer and to etch the exposed portion of the isolation thin film to expose the portion of the doped polysilicon thin film.

[0017] In some embodiments, the stack structure has a step region, and the three-dimensional array structure further comprises a virtual channel structure located in the step region, the virtual channel structure extending through the stack structure and extending to the sacrificial layer. After removing the substrate and the sacrificial layer, the portion of the virtual channel structure extending to the sacrificial layer is also exposed; during etching the first etching stop layer and the exposed portion of the storage functional layer to the second etching stop layer and etching the exposed portion of the isolation thin film, the exposed portion of the virtual channel structure is also etched; the source layer also forms a contact with the exposed portion of the virtual channel structure.

[0018] In some embodiments, before forming the isolation film covering the inner wall of the gate line slit, the preparation method further comprises: forming a first insulating film on the inner wall of the gate line slit; forming a second insulating film in the gate line slit and on the side of the laminated structure away from the substrate; the second insulating film covers the first insulating film; etching the bottom of the second insulating film and the bottom of the first insulating film to expose the sacrificial layer.

[0019] In another aspect, a semiconductor device is provided. The semiconductor device includes a source layer, a laminated structure disposed on one side of the source layer, and a doped polysilicon layer and a polysilicon layer. The laminated structure has a gate line slit extending through the laminated structure and to the source layer. The doped polysilicon layer and the polysilicon layer are disposed in the gate line slit in sequence. The doped polysilicon layer is in electrical contact with the source layer.

[0020] In some embodiments, there is an interface between the doped polysilicon layer and the polysilicon layer.

[0021] In some embodiments, the ratio of the thickness of the doped polysilicon layer to the thickness of the polysilicon layer ranges from 1:10 to 10:1.

[0022] In some embodiments, the semiconductor device further includes an isolation layer disposed between the inner wall of the gate line slit and the doped polysilicon layer. The isolation layer has a first opening, and the doped polysilicon layer is in electrical contact with the source layer through the first opening.

[0023] In some embodiments, the semiconductor device further includes a first insulating layer disposed between the inner wall of the gate line slit and the isolation layer, and a second insulating layer disposed between the first insulating layer and the isolation layer. The first insulating layer and the second insulating layer have a second opening, and the second opening and the first opening are in communication. The doped polysilicon layer is in electrical contact with the source layer through the first opening and the second opening.

[0024] In some embodiments, the semiconductor device further includes a channel structure extending through the laminated structure and to the source layer. The channel structure includes a storage functional layer and a channel layer disposed in sequence, and the storage functional layer has a third opening near a portion of the source layer. The channel layer extends to the source layer through the third opening and is in electrical contact with the source layer.

[0025] In some embodiments, the laminated structure has a step region. The semiconductor device further includes a virtual channel structure located in the step region. The virtual channel structure extends through the laminated structure and to the source layer and is in contact with the source layer.

[0026] In some embodiments, the semiconductor device further includes a second etch stop layer disposed between the source layer and the stack structure.

[0027] In another aspect, a memory is provided. The memory includes a semiconductor device as in some embodiments above.

[0028] In some embodiments, the memory includes a three-dimensional memory.

[0029] In another aspect, a memory system is provided. The memory system includes a controller and a memory as in some embodiments above. The controller is coupled to the memory and configured to control the memory to store data.

[0030] In another aspect, an electronic device is provided. The electronic device includes a memory system as in some embodiments above.

[0031] In some embodiments, the electronic device includes at least one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply.

[0032] It can be understood that the semiconductor device, the memory, the memory system and the electronic device provided by the above embodiments of the present disclosure have the beneficial effects as described above with respect to the method for manufacturing a semiconductor device, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, etc. of the products involved in the embodiments of the present disclosure.

[0034] Figure 1 A flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0035] Figure 2 A flow chart of a method for manufacturing a semiconductor device according to some other embodiments;

[0036] Figure 3 A flow chart of a method for manufacturing a semiconductor device according to still another embodiment;

[0037] Figure 4 A top view of a three-dimensional array structure according to some embodiments;

[0038] Figures 5a to 5j This is a step diagram of a method for fabricating a semiconductor device according to some embodiments;

[0039] Figure 6 for Figure 1 The flowchart shown presents a structural diagram of the semiconductor device corresponding to S400.

[0040] Figure 7 This is a structural diagram of a semiconductor device according to some embodiments;

[0041] Figure 8 This is a structural diagram of another semiconductor device according to some embodiments;

[0042] Figure 9 This is a structural diagram of yet another semiconductor device according to some embodiments;

[0043] Figure 10 This is a three-dimensional structural diagram of a three-dimensional memory according to some embodiments;

[0044] Figure 11 for Figure 10 A cross-sectional view of a string of storage cells along the DD' direction in a three-dimensional memory, as shown;

[0045] Figure 12 for Figure 10 The equivalent circuit diagram of a string of storage cells in a three-dimensional memory is shown.

[0046] Figure 13 Here is a structural diagram of a storage system according to some embodiments;

[0047] Figure 14 This is a structural diagram of another storage system according to some embodiments. Detailed Implementation

[0048] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0049] In the description of the disclosure, it needs to be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the disclosure.

[0050] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise" is to be construed as an open, inclusive meaning, i.e. as "comprising, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" and the like are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the disclosure. The illustrative representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0051] Hereinafter, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the disclosure, unless otherwise stated, the meaning of "multiple" is two or more.

[0052] In describing some embodiments, "coupled" and "connected", and their derivatives, can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

[0053] "A, B and C at least one of them" has the same meaning as "at least one of A, B or C", which includes the following combinations of A, B and C: only A, only B, only C, combination of A and B, combination of A and C, combination of B and C, and combination of A, B and C.

[0054] "A and / or B" includes the following three combinations: only A, only B, and combination of A and B.

[0055] The use of "adapted to" or "configured to" herein means an open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0056] Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more stated conditions or values can be based on additional conditions or values beyond those stated.

[0057] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0058] In the present disclosure, the meaning of "on," "over," and "above" should be interpreted in the broadest context, such that "on" means not only "directly on" but also includes the meaning of "on" with intervening features or layers therebetween, and "over" or "above" means not only "over" or "above" but also includes the meaning of "over" or "above" with no intervening features or layers therebetween (i.e., directly on).

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0060] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0061] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0062] Figures 1 to 3 A flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure; Figures 5a to 5j These are cross-sectional structural diagrams corresponding to each step in the fabrication method of a semiconductor device according to some embodiments. It should be understood that... Figures 1 to 3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figures 1 to 3 The execution order is shown below. (Followed by...) Figures 1 to 3 as well as Figures 5a to 5j The fabrication methods of the semiconductor devices in some embodiments are described.

[0063] Some embodiments of this disclosure provide a method for fabricating a semiconductor device. For example... Figure 1 As shown, the preparation method includes: S100 to S400.

[0064] S100, such as Figure 4 and Figure 5a As shown, a three-dimensional array structure 1 is provided. The three-dimensional array structure 1 includes a substrate 11, a sacrificial layer 12 disposed on one side of the substrate 11, and a stacked structure 13a disposed on the side of the sacrificial layer 12 away from the substrate 11.

[0065] Here, Figure 5a for Figure 4 The three-dimensional array structure 1 shown is a cross-sectional view along the CC' direction.

[0066] For example, the material of the substrate 11 can be single-crystal silicon (Si), single-crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds.

[0067] Exemplarily, the material of the sacrifice layer 12 can be polysilicon (p-Si). For example, a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof can be employed to form the sacrifice layer 12 on the substrate 11.

[0068] Exemplarily, as shown in FIG. 1B, the stack structure 13a includes a plurality of film layers stacked in sequence along the third direction Z. For example, the plurality of film layers includes a plurality of gate dielectric layers 131 and a plurality of gate sacrifice layers 132 alternately stacked. Here, for the purpose of more clearly describing the method of manufacturing the semiconductor device, the dielectric layer covering the topmost gate sacrifice layer 132 is referred to as a gate dielectric layer 131, which is divided into the stack structure 13a. Figure 5a

[0069] In the stack structure 13a, the thickness of each gate dielectric layer 131 can be the same or different, and the thickness of each gate sacrifice layer 132 can be the same or different, which can be set according to actual needs. In addition, in the production process of the stack structure 13a, different numbers of stacked layers correspond to different stacking heights. For example, the number of layers of the stack structure 13a can be 32, 64, or 128, and the like. The more layers of the stack structure 13a, the higher the integration, and the more the number of storage units formed therefrom. The number of stacked layers and the stacking height of the stack structure 13a can be designed according to actual storage needs, which is not limited in the present disclosure.

[0070] For example, the gate dielectric layer 131 and the gate sacrifice layer 132 can have different etching selectivities. In this way, in subsequent processes, the gate dielectric layer 131 can be retained, and the gate sacrifice layer 132 can be removed to form a sacrifice gap between any two adjacent gate dielectric layers 131, so as to facilitate subsequent filling of a conductive material in the sacrifice gap to form a gate layer 133.

[0071] Optionally, the material of the gate dielectric layer 131 includes silicon oxide, and the material of the gate sacrifice layer 132 includes silicon nitride.

[0072] Of course, the stack structure 13a can also include a plurality of gate dielectric layers 131 and a plurality of gate layers 133 alternately stacked. In this way, the process of removing the gate sacrifice layer 132 and filling the conductive material can be avoided.

[0073] S200, as shown in FIG. 2A, the method includes: Figure 4 and Figure 5a ​As shown, the gate line slit GLS is formed through the above-mentioned stack structure 13a and extends to the sacrificial layer 12.

[0074] As an example, the above-mentioned gate line slit GLS can be formed by using a dry etching process or a wet etching process. In this case, the sacrificial layer 12 can be used as an etching stop layer for controlling the opening variation of the gate line slit GLS. In this way, the etching of the gate line slit GLS can be stopped by the sacrificial layer 12, so as to avoid the extension of the gate line slit GLS into the substrate 11.

[0075] It can be understood that, as shown in Figure 4 The number of the gate line slit GLS can be multiple, for example.

[0076] As an example, the above-mentioned multiple gate line slits GLS can extend along the first direction X and are sequentially and spacedly distributed along the second direction Y. The stack structure 13a includes multiple memory block regions B, and one memory block region B is arranged between any two adjacent gate line slits GLS, i.e., each memory block region B is separated by the gate line slit GLS. Figure 4 As shown in a top view of a three-dimensional array structure, two memory block regions B separated by the gate line slit GLS are schematically shown. Of course, the arrangement of the gate line slit GLS is not limited to this.

[0077] It should be noted that, as shown in Figure 5b In the case that the above-mentioned stack structure 13a includes multiple gate dielectric layers 131 and multiple gate sacrificial layers 132 which are alternately stacked, the gate line slit GLS can be used as an etching channel to remove the gate sacrificial layer 132 through the gate line slit GLS. Here, for example, a wet etching process can be used to remove the gate sacrificial layer 132 in the stack structure 13a through the gate line slit GLS, so as to form multiple sacrificial gaps.

[0078] For example, after the formation of the sacrificial gap, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form a gate layer 133 in the sacrificial gap. The material of the gate layer 133 can be at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon and silicide.

[0079] Optionally, before the formation of the gate layer 133 in the sacrificial gap, a thin film deposition process can be used to form a gate blocking layer 134 on the inner wall of the gate line slit GLS and the sacrificial gap. The material of the gate blocking layer 134 can include a material with a high dielectric constant, such as aluminum oxide.

[0080] Further, a thin film deposition process can be used to form a bonding layer 135 on the side surface of the gate blocking layer 134 facing the sacrificial gap. The material of the bonding layer 135 can include tantalum nitride or titanium nitride, for example.

[0081] By setting the adhesion layer 135, the adhesion between the gate barrier layer 134 and the gate layer 133 formed in subsequent processes can be increased.

[0082] Optionally, after forming the gate barrier layer 134 and the adhesion layer 135, the adhesion layer 127 and the part of the gate layer 133 located in the gate line slit GLS can be removed, for example, by using a wet etching process.

[0083] Optionally, as shown in FIG. 1C, the three-dimensional array structure 1 can further include a sacrificial silicon oxide layer 14 disposed between the substrate 11 and the sacrificial layer 12. Figure 5a

[0084] Illustratively, the material of the sacrificial silicon oxide layer 14 can be silicon oxide. For example, the sacrificial silicon oxide layer 14 can be formed on the substrate 11 by using a thin film deposition process of CVD, PVD, ALD or any combination thereof.

[0085] S300, as shown in FIG. 2A, a doped polysilicon film 2a is formed, and the doped polysilicon film 2a is subjected to an annealing process. The doped polysilicon film 2a at least covers the inner wall of the gate line slit GLS. Figure 5e

[0086] Illustratively, the impurity atoms in the doped polysilicon film 2a include phosphorus atoms. Of course, the impurity atoms are not limited to phosphorus atoms, and can also include arsenic atoms or nitrogen atoms, for example. The concentration of the impurity atoms can be selected according to actual needs.

[0087] Illustratively, the doped polysilicon film 2a can be formed by using a thin film deposition process of CVD, PVD, ALD or any combination thereof.

[0088] For example, the formed doped polysilicon film 2a can cover the inner wall of the gate line slit GLS; or, as shown in FIG. 2A, the formed doped polysilicon film 2a can cover the inner wall of the gate line slit GLS while covering the layer structure 13a. Figure 5e

[0089] That is, the formed doped polysilicon film 2a covers the side wall and the bottom of the gate line slit GLS. The side wall of the gate line slit GLS has a plurality of side walls, and the doped polysilicon film 2a can include a plurality of doped polysilicon sub-portions, which respectively cover different side walls of the gate line slit GLS, and there are gaps between the doped polysilicon sub-portions covering the same side wall of the gate line slit GLS, and the doped polysilicon film 2a does not fill the gate line slit GLS.

[0090] Illustratively, after forming the doped polysilicon film 2a, the doped polysilicon film 2a can be subjected to an annealing process. ​​​

[0091] It should be noted that after the annealing treatment of the doped polysilicon film 2a, not only the doped polysilicon film 2a can be shaped, but also the gate line gap GLS can be supported to ensure the structural stability of the laminated structure 13a. In addition, stress can be released through the above-mentioned gap, so that the doped polysilicon film 2a after the annealing treatment has smaller stress or substantially no stress, thereby avoiding affecting the warping degree of the wafer.

[0092] S400, as shown in the figure, a polysilicon film 3a is formed, and the polysilicon film 3a is annealed. The polysilicon film 3a covers the doped polysilicon film 2a. Figure 5f

[0093] Exemplarily, the polysilicon film 3a can be formed by using a thin film deposition process of CVD, PVD, ALD or any combination thereof. As shown in the figure, the formed polysilicon film 3a substantially fills the above-mentioned gap and is located on the side surface of the doped polysilicon film 2a away from the substrate 11, thereby forming a cover for the doped polysilicon film 2a as a whole. Figure 5f

[0094] Optionally, as shown in the figure, during the deposition of the polysilicon film 3a, one or more air gaps can be formed in the polysilicon film 3a by controlling the deposition process. Figure 5f

[0095] Exemplarily, after the polysilicon film 3a is formed, the polysilicon film 3a can be annealed. After the annealing treatment of the polysilicon film 3a, the polysilicon film 3a can be shaped.

[0096] Figure 6 The structure diagram of the semiconductor device corresponding to the above-mentioned S400 can be seen from the figure, the structure of the doped polysilicon film 2a and the polysilicon film 3a, and the boundary of the two is relatively clear. Among them, the polysilicon film 3a has an air gap inside. Figure 6

[0097] It should be noted that the undoped polysilicon has a large stress. Since the polysilicon film 3a substantially fills the above-mentioned gap, the polysilicon film 3a still has a large stress after the annealing treatment of the polysilicon film 3a. The stress of the polysilicon film 3a will change the stress of the wafer as a whole, and then change the warping degree of the wafer.

[0098] ​​​​Since the doped polysilicon film 2a has a small stress or substantially no stress, i.e., has substantially no influence on the warping degree of the wafer, and the polysilicon film 3a has a large stress, the thickness ratio between the doped polysilicon film 2a and the polysilicon film 3a can be adjusted, and the proportion of the portions of the doped polysilicon film 2a and the polysilicon film 3a located in the gate line slits GLS can be adjusted, so that the proportion of the portion of the polysilicon film 3a located in the gate line slits GLS can be adjusted, the stress of the wafer as a whole can be changed, and the warping degree of the wafer can be adjusted.

[0099] For example, when the thickness ratio between the doped polysilicon film 2a and the polysilicon film 3a is large, the proportion of the portion of the polysilicon film 3a located in the gate line slits GLS is small, the stress change of the wafer as a whole is small, and the warping degree of the wafer changes little. When the thickness ratio between the doped polysilicon film 2a and the polysilicon film 3a is small, the proportion of the portion of the polysilicon film 3a located in the gate line slits GLS is large, the stress change of the wafer as a whole is large, and the warping degree of the wafer changes greatly.

[0100] In this way, before the doped polysilicon film 2a and the polysilicon film 3a are formed, the warping degree of the wafer can be detected, the adjustment amount of the warping degree of the wafer can be determined according to the detection result, the thickness ratio between the doped polysilicon film 2a and the polysilicon film 3a can be determined, and it can be ensured that, after the doped polysilicon film 2a and the polysilicon film 3a are formed, the warping degree of the wafer is within a predetermined range, so that the control of the warping degree of the wafer is realized.

[0101] For example, in the case where the gate line slits GLS extend along the first direction X and are arranged at intervals along the second direction Y, the stress of the polysilicon film 3a can change the stress of the wafer in the second direction Y, and further change the warping degree of the wafer in the second direction Y, and change the warping degree of the wafer in the direction parallel to the plane in which the substrate 11 is located. In this way, by adjusting the thickness ratio between the doped polysilicon film 2a and the polysilicon film 3a, and adjusting the proportion of the portions of the doped polysilicon film 2a and the polysilicon film 3a located in the gate line slits GLS, the stress of the wafer in the second direction Y can be changed by the polysilicon film 3a, the warping degree of the wafer in the second direction Y can be adjusted, and the warping degree of the wafer in the direction parallel to the plane in which the substrate 11 is located can be adjusted.

[0102] Therefore, the method for manufacturing a semiconductor device provided by some embodiments of the present disclosure can form a doped polysilicon film 2a covering at least the gate line slit GLS after forming the gate line slit GLS through the stack structure 13a and extending to the sacrificial layer 12, and then perform annealing on the doped polysilicon film 2a to substantially eliminate the stress of the doped polysilicon film 2a, and then form a polysilicon film 3a covering the doped polysilicon film 2a, so that the polysilicon film 3a substantially fills the gap between the portions of the doped polysilicon film 2a covering different sidewalls of the same gate line slit GLS, and the polysilicon film 3a can have a larger stress. In this way, not only can the doped polysilicon film 2a be used to support the gate line slit GLS and stabilize the structure of the stack structure 13a, but also the thickness ratio between the doped polysilicon film 2a and the polysilicon film 3a can be adjusted to adjust the influence of the polysilicon film 3a on the stress of the wafer as a whole, and then the warping degree of the wafer can be adjusted to control the warping degree of the wafer.

[0103] In addition, the annealing process can be performed on the doped polysilicon film 2a after the doped polysilicon film 2a is formed, and the annealing process can be performed on the polysilicon film 3a after the polysilicon film 3a is formed, so that the doped polysilicon film 2a and the polysilicon film 3a can be shaped and the structural stability of the doped polysilicon film 2a and the polysilicon film 3a can be improved. In this way, in the case where an annealing process needs to be used in the subsequent manufacturing process, the influence on the doped polysilicon film 2a and the polysilicon film 3a can be reduced, and then the influence on the warping degree of the wafer can be reduced and the stability of the process can be improved.

[0104] In some embodiments, the ratio of the thickness of the doped polysilicon film 2a to the thickness of the polysilicon film 3a ranges from 10:1 to 1:10.

[0105] For example, the ratio of the thickness of the doped polysilicon film 2a to the thickness of the polysilicon film 3a can be 10:1, 5:1, 5:2, 1:1, 1:2, 1:4, 1:7 or 1:10, etc.

[0106] The portions of the doped polysilicon film 2a and the polysilicon film 3a located in the gate line slit GLS constitute an array common source. By setting the ratio of the thickness of the doped polysilicon film 2a to the thickness of the polysilicon film 3a to the above range, not only the conductive performance of the array common source can be ensured, but also the effective change of the stress of the array common source on the wafer as a whole and the effective adjustment of the warping degree of the wafer can be ensured.

[0107] In some embodiments, the annealing process performed on the doped polysilicon film 2a adopts an in-situ annealing process. And / or, the annealing process performed on the polysilicon film 3a adopts an in-situ annealing process.

[0108] That is, the present disclosure can anneal the doped polysilicon film 2a by using an in-situ annealing process. Alternatively, the present disclosure can anneal the polysilicon film 3a by using an in-situ annealing process. Alternatively, the present disclosure can anneal the doped polysilicon film 2a by using an in-situ annealing process, and anneal the polysilicon film 3a by using an in-situ annealing process.

[0109] By annealing the doped polysilicon film 2a by using an in-situ annealing process, the doped polysilicon film 2a can be shaped first. In this way, in the subsequent process of forming the polysilicon film 3a, the phenomenon of impurity atoms in the doped polysilicon film 2a precipitating can be avoided, and thus the undesirable phenomenon of bump defects can be avoided.

[0110] By annealing the polysilicon film 3a by using an in-situ annealing process, the polysilicon film 3a can be annealed after being formed, without removing the semiconductor device from the corresponding device, thereby improving the production efficiency.

[0111] In some embodiments, the polysilicon film 3a also covers the laminated structure 13a in the case that the doped polysilicon film 2a also covers the laminated structure 13a.

[0112] Based on this, in some examples, as shown in Figure 3 The preparation method provided by the present disclosure further includes: S500.

[0113] S500, as shown in Figure 5g The part of the polysilicon film 3a covering the laminated structure 13a and the part of the doped polysilicon film 2a covering the laminated structure 13a are removed, and the part of the polysilicon film 3a located in the gate line gap GLS and the part of the doped polysilicon film 2a located in the gate line gap GLS are reserved.

[0114] For example, the polysilicon film 3a and the doped polysilicon film 2a can be etched by using a dry etching process (such as a gas etching process) or chemical mechanical planarization (CMP). For example, in one preparation process, the part of the polysilicon film 3a covering the laminated structure 13a and the part of the doped polysilicon film 2a covering the laminated structure 13a can be removed to expose the laminated structure 13a.

[0115] For example, the part of the polysilicon film 3a located in the gate line gap GLS can be referred to as a polysilicon layer 3, and the part of the doped polysilicon film 2a located in the gate line gap GLS can be referred to as a doped polysilicon layer 2. The polysilicon layer 3 and the doped polysilicon layer 2 can constitute an array common source.

[0116] In some embodiments, such as Figure 2 As shown, in the above S300, before forming the doped polycrystalline silicon thin film 2a, the preparation method provided in this disclosure further includes: S290.

[0117] S290, such as Figure 5d As shown, an isolation film 4a is formed that at least covers the inner wall of the gate line gap GLS.

[0118] For example, the material of the insulating film 4a can be an oxide. The oxide is, for example, silicon oxide.

[0119] For example, the isolation film 4a can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof.

[0120] For example, the formed isolation film 4a can cover the inner wall of the gate line gap GLS; or, as Figure 5d As shown, the formed isolation film 4a can cover the inner wall of the gate line gap GLS while also covering the stacked structure 13a.

[0121] That is, the formed isolation film 4a will cover the sidewalls and bottom of the gate line slot GLS. The isolation film 4a may include multiple isolation sub-parts, which respectively cover different sidewalls of the gate line slot GLS, and there are gaps between the isolation sub-parts covering the same sidewall of the gate line slot GLS, so the isolation film 4a does not completely fill the gate line slot GLS.

[0122] like Figure 5e As shown, after forming the isolation film 4a and the doped polysilicon film 2a, the isolation film 4a can not only separate the doped polysilicon film 2a and the gate line gap GLS, thus preventing the doped polysilicon film 2a and the gate layer 133 from forming an electrical contact, but also separate the doped polysilicon film 2a and the sacrificial layer 12, thus preventing the doped polysilicon film 2a and the sacrificial layer 12 from forming a contact.

[0123] Based on this, in some examples, such as Figure 3 As shown, the preparation method provided in this disclosure also includes: S600 to S800.

[0124] S600, such as Figure 5h As shown, the substrate 11 and the sacrificial layer 12 are removed, exposing the portion of the isolation film 4a that extends to the sacrificial layer 12.

[0125] For example, CMP, dry etching, or wet etching processes can be used to remove the substrate 11. For instance, when using CMP to remove the substrate 11, a CMP machine can be used to grind the substrate 11 until it is removed. The sacrificial silicon oxide layer 14 can serve as a stop layer for the CMP process, which helps control the process uniformity during substrate removal.

[0126] For example, a wet etching process can be used to remove the sacrificial layer 12.

[0127] For example, if the three-dimensional array structure 1 further includes a sacrificial silicon oxide layer 14 disposed between the substrate 11 and the sacrificial layer 12, the sacrificial silicon oxide layer 14 can be removed using a wet etching process. The sacrificial layer 12 can serve as an etching stop layer for the wet etching process to remove the sacrificial silicon oxide layer 14.

[0128] For example, the semiconductor device can be inverted before removing the substrate 11 and the sacrificial layer 12, and then the substrate 11 and the sacrificial layer 12 can be etched away.

[0129] S700, such as Figure 5i As shown, the isolation film 4a is etched to expose the portion of the doped polysilicon film 2a that extends to the sacrificial layer 12.

[0130] For example, the isolation film 4a can be etched using a wet etching process.

[0131] For example, such as Figure 5i As shown, during the etching process of the isolation film 4a, for example, only a portion of the isolation film 4a can be etched to expose the bottom of the doped polysilicon film 2a.

[0132] Here, the portion of the isolation film 4a that remains after etching can be referred to as the isolation layer 4.

[0133] S800, such as Figure 5j As shown, a source layer 5 is formed on one side of the stacked structure 13a. This source layer 5 forms an electrical contact with the exposed portion of the doped polysilicon thin film 2a.

[0134] For example, the source layer 5 can be made of polycrystalline silicon. For instance, the source layer 5 can be deposited on one side of the stacked structure 13a using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0135] For example, the aforementioned source layer 5 covers the exposed portion of the doped polysilicon thin film 2a and contacts the exposed portion of the doped polysilicon thin film 2a to form an electrical connection.

[0136] In the process of applying a voltage to one of the plurality of memory block regions B, a coupling phenomenon is likely to occur in another memory block region B adjacent to the one, affecting the voltage of the another memory block region B. By forming an electrical contact between the exposed portion of the doped polysilicon film 2a and the source layer 5, a shielding effect can be formed between the two adjacent memory block regions B, effectively improving the above-mentioned coupling phenomenon.

[0137] For example, after the source layer 5 is formed, the source layer 5 can be doped by an ion implantation process, and the lattice damage of the material caused by the ion implantation process can be repaired by a laser annealing process, and the implanted dopants can be activated. Of course, the method of forming the source layer 5 is not limited thereto.

[0138] In some embodiments, as shown in Figure 5a The three-dimensional array structure 1 further includes a channel structure 15 extending through the stack structure 13a and extending to the sacrificial layer 12. As shown in Figure 4 Each memory block region B can be provided with a plurality of channel structures 15.

[0139] For example, as shown in Figure 5a The channel structure 15 includes a storage function layer 151 and a channel layer 152 arranged in sequence. For example, the storage function layer 151 includes a blocking layer, a charge trapping layer, and a tunneling layer arranged in sequence from the outside to the inside.

[0140] Optionally, the material of the blocking layer can be silicon oxide, the material of the charge trapping layer can be silicon nitride, the material of the tunneling layer can be silicon oxide, and the material of the channel layer 152 can be polysilicon. The blocking layer, the charge trapping layer, the tunneling layer, and the channel layer 152 can form a “SONO” structure.

[0141] In some examples, as shown in Figure 5h In the above S600, after the substrate 11 and the sacrificial layer 12 are removed, a portion of the storage function layer 151 extending to the sacrificial layer 12 is also exposed.

[0142] Since the channel structure 15 extends to the sacrificial layer 12, after the substrate 11 and the sacrificial layer 12 are removed, a portion of the channel structure 15 extending to the sacrificial layer 12 is naturally exposed. Since the storage function layer 151 in the channel structure 15 surrounds the channel layer 152, a portion of the storage function layer 151 in the channel structure 15 is exposed.

[0143] In some examples, as shown in Figure 5i In the above S700, in the process of etching the isolation film 4a, a portion of the storage function layer 151 exposed is also etched, and a portion of the channel layer 152 extending to the sacrificial layer 12 is exposed.

[0144] That is, during the process of etching the isolation film 4a using wet etching, the exposed portion of the storage function layer 151 (that is, the portion of the storage function layer 151 extending to the sacrificial layer 12) can be further etched away by controlling the etching time, so that the portion of the channel layer 152 extending to the sacrificial layer 12 is exposed, so that the channel layer 152 has a larger exposed area.

[0145] In some examples, such as Figure 5j As shown, in the above S800, the source layer 5 also forms an electrical contact with the exposed portion of the channel layer 152.

[0146] That is, the aforementioned source layer 5 also covers the exposed portion of the channel layer 152 and contacts the exposed portion of the channel layer 152 to form an electrical connection. The fact that the source layer 5 surrounds the exposed portion of the channel layer 152 allows for a larger contact area between the source layer 5 and the channel layer 152, which is beneficial for increasing the reliability of the contact connection.

[0147] In some embodiments, such as Figure 5a As shown, in S100 above, before forming the stacked structure 13a, the fabrication method provided in this disclosure further includes: sequentially stacking a first etch stop layer 16 and a second etch stop layer 17 on the side of the sacrificial layer 12 away from the substrate 11. In some embodiments, after sequentially forming the first etch stop layer 16 and the second etch stop layer 17 on the side of the sacrificial layer 12 away from the substrate 11, the stacked structure 13a is formed on the side of the second etch stop layer 17 away from the first etch stop layer 16.

[0148] For example, a first etch stop layer 16 can be formed on the side of the sacrificial layer 12 away from the substrate 11 using a thin film deposition process of CVD, PVD, ALD, or any combination thereof; a second etch stop layer 17 can be formed on the side of the first etch stop layer 16 away from the substrate 11 using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. It should be noted that the selection of the materials of the first etch stop layer 16 and the second etch stop layer 17 should achieve a predetermined etch selectivity ratio with the materials of the subsequent structures to be etched (e.g., the channel structure 15 and the isolation film 4a).

[0149] Optionally, the first etch stop layer 16 can be made of silicon oxide. The second etch stop layer 17 can be made of polysilicon.

[0150] Based on this, in some examples, in the above S600, the substrate 11 and the sacrificial layer 12 are removed to expose the portion of the storage function layer 151 extending to the sacrificial layer 12 and the portion of the isolation film 4a extending to the sacrificial layer 12, including: S610 to S620.

[0151] S610, such asFigure 5h As shown, the substrate 11 and the sacrificial layer 12 are removed to the first etch stop layer 16, exposing the portion of the storage function layer 151 extending to the sacrificial layer 12, and exposing the portion of the isolation film 4a extending to the sacrificial layer 12.

[0152] The process of removing the substrate 11 and the sacrificial layer 12 can be referred to the descriptions in some of the above examples, and will not be repeated here.

[0153] For example, during the process of removing the sacrificial layer 12 using a wet etching process, the etching can be stopped at the first etching stop layer 16 by selecting a predetermined etchant.

[0154] Optionally, if the material of the first etch stop layer 16 is the same as the material of the charge barrier layer in the channel structure 15 (e.g., both are made of silicon oxide), the etching can be stopped at the barrier layer of the channel structure 15 during the removal of the sacrificial layer 12 using a wet etching process, thereby exposing the portion of the functional layer 151 of the channel structure 15 that extends to the sacrificial layer 12.

[0155] By adding a first etch stop layer 16, it is beneficial to control the process uniformity during the removal of the substrate 11 and the sacrificial layer 12.

[0156] S620, such as Figure 5i As shown, the first etch stop layer 16 and the exposed portion of the storage function layer 151 are etched to the second etch stop layer 17, the exposed portion of the channel layer 152 extending to the sacrificial layer 12 is exposed, and the exposed portion of the isolation film 4a is etched, as well as the exposed portion of the doped polysilicon film 2a is exposed.

[0157] For example, the first etch stop layer 16, the exposed portion of the storage function layer 151, and the exposed portion of the isolation film 4a can be etched and removed simultaneously in the same etching process.

[0158] In this step, for example, only the exposed portion of the isolation film 4a (i.e., the bottom of the isolation film 4a) can be removed to expose the bottom of the doped polycrystalline silicon film 2a.

[0159] For example, during the process of etching the first etch stop layer 16 and the exposed portion of the storage function layer 151 using a wet etching process, the etching can be stopped at the second etch stop layer 17 by selecting a predetermined etchant.

[0160] Optionally, if the material of the second etch stop layer 17 is the same as the material of the channel layer 152 in the channel structure 15 (e.g., both are made of polysilicon), the etching can be stopped at the channel layer 152 during the process of removing the first etch stop layer 16 using a wet etching process, thereby exposing the portion of the channel layer 152 that extends to the sacrificial layer 12.

[0161] By adding a second etch stop layer 17, it is beneficial to control the process uniformity during the removal of the first etch stop layer 16 and the storage function layer 151, thereby making it easier to extend the exposed portion of the channel layer 152 into the source layer 5, and improving the contact effect between the source layer 5 and the channel layer 152.

[0162] In some embodiments, such as Figure 5a As shown, the stacked structure 13a has a stepped region A, and the portion of the stacked structure 13a located in the stepped region A can be stepped. The three-dimensional array structure 1 also includes a virtual channel structure 18 located in the stepped region A. The virtual channel structure 18 penetrates the stacked structure 13a and extends to the sacrificial layer 12.

[0163] For example, the material of the virtual channel structure 18 can be silicon oxide. For instance, the virtual channel structure 18 can be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof.

[0164] Optionally, the virtual channel structure 18 is used to provide mechanical support, but does not form a storage function layer and channel layer with storage function.

[0165] Based on this, in some examples, such as Figure 5h As shown, in the above S600, after removing the substrate 11 and the sacrificial layer 12, a portion of the virtual channel structure 18 extending to the sacrificial layer 12 is also exposed.

[0166] Since the virtual channel structure 18 extends to the sacrificial layer 12, the portion of the virtual channel structure 18 extending to the sacrificial layer 12 can be naturally exposed after the substrate 11 and the sacrificial layer 12 are removed.

[0167] In some examples, such as Figure 5i As shown, in the above S700, during the process of etching the exposed portions of the first etch stop layer 16 and the storage function layer 151 to the second etch stop layer 17, and etching the exposed portions of the isolation film 4a, the exposed portions of the virtual channel structure 18 are also etched.

[0168] That is, during the process of etching the first etch stop layer 16, the exposed portion of the storage function layer 151 and the isolation film 4a using a wet etching process, the exposed portion of the virtual channel structure 18 can be further etched away by controlling the etching time, etc.

[0169] In some examples, such as Figure 5j As shown, in the above S800, the source layer 5 also forms an electrical contact with the exposed portion of the virtual channel structure 18.

[0170] That is, the source layer 5 also covers and contacts the exposed portion of the dummy channel structure 18, forming an electrical connection.

[0171] In some embodiments, as shown in FIG. 2B, before S290, i.e., before forming the isolation film 4a covering at least the inner wall of the gate line slit GLS, the preparation method provided by the present disclosure further comprises S250-S270. Figure 2

[0172] S250, as shown in FIG. 2B, a first insulating film 6a is formed on the inner wall of the gate line slit GLS. Figure 5b

[0173] For example, the first insulating film 6a can be formed by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0174] For example, the first insulating film 6a can cover the sidewall and bottom of the gate line slit GLS.

[0175] S260, as shown in FIG. 2B, a second insulating film 7a is formed in the gate line slit GLS and on the side of the laminated structure 13a away from the substrate 11. The second insulating film 7a covers the first insulating film 6a. Figure 5b

[0176] For example, the second insulating film 7a can be formed by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0177] For example, the second insulating film 7a can be located on the side of the laminated structure 13a away from the substrate 11 while covering the first insulating film 6a.

[0178] By providing the first insulating film 6a and the second insulating film 7a, the subsequently formed doped polysilicon film 2a and the gate line slit GLS can be separated, avoiding the doped polysilicon film 2a and the gate layer 133 from forming an electrical contact, and further avoiding the polysilicon film 2a and the gate layer 133 from forming a short circuit.

[0179] S270, as shown in FIG. 2B, the bottom of the second insulating film 7a and the bottom of the first insulating film 6a are etched to expose the sacrificial layer 12. Figure 5c For example, the bottom of the second insulating film 7a and the bottom of the first insulating film 6a can be etched by a dry etching process to form a second opening K2 penetrating through the second insulating film 7a and the first insulating film 6a. The second opening K2 exposes the sacrificial layer 12.

[0180]

[0181] ​​​​For example, after etching the bottom of the second insulating film 7a and the bottom of the first insulating film 6a, the remaining part of the second insulating film 7a can be referred to as a second insulating layer 7, and the remaining part of the first insulating film 6a can be referred to as a first insulating layer 6.

[0182] By etching the bottom of the second insulating film 7a and the bottom of the first insulating film 6a, the subsequently formed doped polysilicon film 2a and the sacrificial layer 12 are separated by the isolation film 4a, which can simplify the process flow and reduce the difficulty in the subsequent process of exposing the part of the doped polysilicon film 2a extending to the sacrificial layer 12.

[0183] Some embodiments of the present disclosure provide a semiconductor device 100. The semiconductor device 100 can be formed by using the method for manufacturing a semiconductor device described above, for example. As shown in Figures 7 to 9 The semiconductor device 100 can include a source layer 5, a stack structure 13, a doped polysilicon layer 2, and a polysilicon layer 3, for example. The doped polysilicon layer 2 and the polysilicon layer 3 together form an array common source, for example.

[0184] In some examples, as shown in Figures 7 to 9 The stack structure 13 is disposed on one side of the source layer 5. The stack structure 13 can include a plurality of film layers stacked in a third direction Z. The plurality of film layers can include a plurality of gate dielectric layers 131 and a plurality of gate layers 133 stacked alternately, for example. The gate layers 133 can serve as word lines in the semiconductor device 100.

[0185] For example, as shown in Figure 4 The stack structure 13 has a gate line slit GLS extending through the stack structure 13 and to the source layer 5. The gate line slit GLS extends in a first direction X and separates the stack structure 13 into a plurality of memory block regions B separated by the gate line slit GLS.

[0186] In some examples, as shown in Figures 7 to 9 The doped polysilicon layer 2 and the polysilicon layer 3 are disposed in the gate line slit GLS in sequence. The doped polysilicon layer 2 can cover the sidewalls and the bottom of the gate line slit GLS and directly contact the source layer 5 to form an electrical connection. The polysilicon layer 3 can be located in the doped polysilicon layer 2, separated from the sidewalls and the bottom of the gate line slit GLS, and separated from the source layer 5.

[0187] For example, the material of the source layer 5 can include P-type doped polysilicon or N-type doped polysilicon. This can not only provide support for the structures disposed on one side of the source layer 5 (such as the stack structure 13 and / or the array common source, etc.), but also achieve electrical connections between the structures in contact with the source layer 5 (such as the array common source and / or the channel structure 15).

[0188] In some examples, as shown in FIG. 2, the doped polysilicon layer 2 has a void, and the polysilicon layer 3 is filled in the void of the doped polysilicon layer 2 and substantially fills the void of the doped polysilicon layer 2. Figures 7 to 9 For example, the side surface of the doped polysilicon layer 2 away from the source layer 5 is level with the side surface of the polysilicon layer 3 away from the source layer 5.

[0189] Before the polysilicon layer 3 is formed in the void of the doped polysilicon layer 2, the doped polysilicon layer 2 can release stress in the void between itself, and only have a small stress or substantially no stress, and only have a small impact or substantially no impact on the warping degree of the wafer on which the doped polysilicon layer 2 is located.

[0190] Since the polysilicon layer 3 is located in the doped polysilicon layer 2 and substantially fills the void of the doped polysilicon layer 2, the polysilicon layer 3 still has a large stress. The stress can change the stress of the wafer in the second direction Y, and further change the warping degree of the wafer in the second direction Y, and change the warping degree of the wafer in the X-Y direction.

[0191] By adjusting the thickness ratio between the doped polysilicon layer 2 and the polysilicon layer 3, the proportion of the doped polysilicon layer 2 and the polysilicon layer 3 in the gate line gap GLS can be adjusted, so that the proportion of the polysilicon layer 3 in the gate line gap GLS can be adjusted, the stress of the wafer in the second direction Y can be changed, the warping degree of the wafer in the second direction Y can be adjusted, and the warping degree of the wafer in the X-Y direction can be adjusted.

[0192] In this way, the thickness ratio between the doped polysilicon layer 2 and the polysilicon layer 3 (that is, the thickness of the polysilicon layer 3) can be determined according to the warping degree of the wafer before the array common source is formed, so that the warping degree of the wafer is ensured to be within a predetermined range after the array common source is formed, and the control of the warping degree of the wafer is realized.

[0193] The semiconductor device 100 provided by the embodiments of the present disclosure can achieve the same beneficial effects as those achieved by the above-mentioned embodiments, and details are not repeated here.

[0194] In some embodiments, the doped polysilicon layer 2 and the polysilicon layer 3 have an interface therebetween.

[0195] Since the doped polysilicon layer 2 and the polysilicon layer 3 are formed by using different materials and in different steps, respectively, the doped polysilicon layer 2 and the polysilicon layer 3 can have an interface therebetween.

[0196] For example, the interface between the doped polysilicon layer 2 and the polysilicon layer 3 is clear and easy to observe and distinguish.

[0197] This is conducive to ensuring the independence between the doped polysilicon layer 2 and the polysilicon layer 3, and the structural stability, so that the stress in the polysilicon layer 3 is basically only present in the polysilicon layer 3, and the respective roles of the doped polysilicon layer 2 and the polysilicon layer 3 are avoided from being confused.

[0198] In some embodiments, the ratio of the thickness of the doped polysilicon layer 2 to the thickness of the polysilicon layer 3 ranges from 1:10 to 10:1.

[0199] For example, the ratio between the thickness of the doped polysilicon layer 2 and the thickness of the polysilicon layer 3 can be 10:1, 5:1, 5:2, 1:1, 1:2, 1:4, 1:7, or 1:10, etc.

[0200] By setting the ratio between the thickness of the doped polysilicon layer 2 and the thickness of the polysilicon layer 3 to the above range, not only the conductive performance of the array common source can be ensured, but also the overall wafer stress can be effectively changed by using the array common source, and the wafer warping degree can be effectively adjusted in a larger range.

[0201] In some embodiments, as shown in Figures 7 to 9 The semiconductor device 100 further includes an isolation layer 4 disposed between the inner wall of the gate line slit GLS and the doped polysilicon layer 2. The isolation layer 4 has a first opening K1 through which the doped polysilicon layer 2 is in electrical contact with the source layer 5.

[0202] In some examples, as shown in Figures 7 to 9 The first opening K1 can be located at the bottom of the isolation layer 4. The inner wall of the gate line slit GLS refers to the sidewall of the gate line slit GLS. That is, the isolation layer 4 covers the sidewall of the gate line slit GLS and exposes a portion of the source layer 5 through the first opening K1.

[0203] For example, a portion of the isolation layer 4 is also located on the side of the stack structure 13 away from the source layer 5, covering the stack structure 13.

[0204] For example, as shown in Figures 7 to 9 The bottom of the doped polysilicon layer 2 can extend to the source layer 5 through the first opening K1 and directly contact the source layer 5 to form an electrical connection.

[0205] By providing the isolation layer 4, the doped polysilicon layer 2 and the gate line slit GLS can be separated by the isolation layer 4, so as to avoid the doped polysilicon layer 2 and the gate layer 133 from forming an electrical contact. By providing the first opening K1 in the isolation layer 4, the bottom of the doped polysilicon layer 2 can be prevented from being isolated, so as to facilitate the doped polysilicon layer 2 to form an electrical contact with the source layer 5 through the first opening K1.

[0206] In some embodiments, as Figures 7 to 9As shown, the semiconductor device 100 further comprises a first insulating layer 6 disposed between the inner wall of the gate line slit GLS and the isolation layer 4, and a second insulating layer 7 disposed between the first insulating layer 6 and the isolation layer 4. The first insulating layer 6 and the second insulating layer 7 have a second opening K2, and the second opening K2 and the first opening K1 are in communication. The doped polysilicon layer 2 is in electrical contact with the source layer 5 through the first opening K1 and the second opening K2.

[0207] In some examples, as shown in Figures 7 to 9 The second opening K2 can be located at the bottom of the first insulating layer 6. The inner wall of the gate line slit GLS refers to the sidewall of the gate line slit GLS. That is, the first insulating layer 6 covers the sidewall of the gate line slit GLS and exposes a part of the source layer 5 through the second opening K2.

[0208] In some examples, as shown in Figures 7 to 9 The second opening K2 can also be located at the bottom of the second insulating layer 7. The second insulating layer 7 can cover the sidewall of the first insulating layer 6 and expose a part of the source layer 5 through the second opening K2. The isolation layer 4 covers the first insulating layer 6 and the second insulating layer 7.

[0209] For example, as shown in Figures 7 to 9 A part of the second insulating layer 7 also covers the stack structure 13 away from the source layer 5. In the case that the semiconductor device 100 further comprises the isolation layer 4, the part of the second insulating layer 7 is located between the stack structure 13 and the isolation layer 4.

[0210] For example, as shown in Figures 7 to 9 The bottom of the doped polysilicon layer 2 can extend to the source layer 5 through the first opening K1 and the second opening K2 at the same time, directly contact and form electrical connection with the source layer 5.

[0211] By disposing the first insulating layer 6 and the second insulating layer 7, the doped polysilicon layer 2 and the gate line slit GLS can be further separated by the first insulating layer 6 and the second insulating layer 7, so as to avoid electrical contact between the doped polysilicon layer 2 and the gate layer 133. By disposing the second opening K2 in the first insulating layer 6 and the second insulating layer 7, the bottom of the doped polysilicon layer 2 can be prevented from being isolated, and the doped polysilicon layer 2 can be facilitated to form electrical contact with the source layer 5 through the first opening K1 and the second opening K2.

[0212] In some embodiments, as shown in Figure 8 and Figure 9 The semiconductor device 100 further comprises a channel structure 15 extending through the stack structure 13 and extending to the source layer 5. The channel structure 15 comprises a storage functional layer 151 and a channel layer 152 disposed in sequence.

[0213] The materials and structures of the storage functional layer 151 and the channel layer 152 can refer to the descriptions of some of the above embodiments, which will not be repeated here.

[0214] In some examples, as shown in Figure 8 and Figure 9 The part of the storage functional layer 151 close to the source layer 5 is provided with a third opening K3, and the channel layer 152 extends to the source layer 5 through the third opening K3 and is in electrical contact with the source layer 5.

[0215] In some examples, as shown in Figure 8 and Figure 9 The third opening K3 can be located at the bottom of the storage functional layer 151. The storage functional layer 151 can expose a part of the source layer 5 through the third opening K3.

[0216] For example, as shown in Figure 8 and Figure 9 The bottom of the channel layer 152 can extend to the source layer 5 through the third opening K3 and directly contact the source layer 5 to form an electrical connection.

[0217] In some embodiments, as shown in Figure 9 The stack structure 13 has a stepped region. The part of the stack structure 13 located in the stepped region can be stepped. The specific topography of the part of the stack structure 13 located in the stepped region can be selected according to actual needs, which is not limited in the present disclosure.

[0218] In some examples, as shown in Figure 9 The semiconductor device 100 further includes a virtual channel structure 18 located in the stepped region. The virtual channel structure 18 penetrates the stack structure 13 and extends to the source layer 5 and contacts the source layer 5.

[0219] For example, the number of virtual channel structures 18 can be multiple. The multiple virtual channel structures 18 can provide support for the gate dielectric layer 131 in the stack structure 13.

[0220] In some embodiments, as shown in Figures 7 to 9 The semiconductor device 100 further includes a second etching stop layer 17 arranged between the source layer 5 and the stack structure 13.

[0221] By arranging the second etching stop layer 17, it is beneficial to control the process uniformity in the process of removing the storage functional layer 151 and the isolation film 4a.

[0222] As shown in Figure 10 Some embodiments of the present disclosure provide a memory 1000. The memory 1000 includes the semiconductor device 100 as described in any of the above embodiments.

[0223] The semiconductor device 100 included in the memory 1000 provided in some embodiments of this disclosure has the same structure and beneficial effects as the semiconductor device 100 provided in some of the above embodiments, and will not be described again here.

[0224] In some embodiments, the memory 1000 described above may include a three-dimensional memory.

[0225] Based on this, in some examples, such as Figure 10 As shown, in the semiconductor device 100 included in the memory 1000, the plurality of gate dielectric layers 131 (not shown) and the plurality of gate layers 133 in the stacked structure 13 can extend along the first direction X. Along the third direction Z, the lowermost gate layer 133 of the plurality of gate layers 133 is configured as a source select gate SGS, the uppermost gate layer 133 of the plurality of gate layers 133 is configured as a drain select gate SGD, and the gate layer 133 located in the middle layer of the plurality of gate layers 133 is configured as a plurality of word lines WL (see reference). Figure 11 (WL1 to WL4 in the middle).

[0226] In some examples, such as Figure 10 As shown, the channel structure 15 connects the word lines WL in series to form a memory cell string 200.

[0227] like Figure 12 As shown, one storage cell string 200 is equivalent to the storage capacity of multiple planar storage cells. Therefore, the memory 1000 can provide a large storage capacity.

[0228] The memory 1000 includes an array of memory cell strings 200 in the XY plane.

[0229] In some examples, such as Figure 11 As shown, the memory 1000 also includes a drain select gate contact SGD CNT, a source select gate contact SGS CNT, a source contact SL CNT, a word line contact WL CNT, and a bit line contact BL CNT. The drain select gate contact SGD CNT is electrically connected to the drain select gate SGD; the source select gate contact SGS CNT is electrically connected to the source select gate SGS; the source contact SL CNT is electrically connected to the source contact SL; each word line contact WL CNT is electrically connected to a word line WL, thus allowing each word line contact WL CNT to address each memory cell string 200 independently; each bit line contact BL CNT is electrically connected to the top of a memory cell string 200, thus allowing each bit line contact BL CNT to address each memory cell string 200 independently.

[0230] In some examples, such as Figure 11As shown, the memory 1000 further includes a bit line BL, which is electrically connected with the memory cell string 200 through a bit line contact BLCNT.

[0231] In some examples, the memory 1000 further includes a peripheral device disposed on one side of the semiconductor device 100, and an interconnection layer disposed between the semiconductor device 100 and the peripheral device.

[0232] Some embodiments of the present disclosure provide a storage system 2000. As shown in Figure 13 and Figure 14 The storage system 2000 includes a controller 300 and the memory 1000 as described in any of the above embodiments. The controller 300 can be coupled to the memory 1000 and configured to control the memory 1000 to store data.

[0233] For example, the storage system 2000 can be integrated into various types of storage devices, such as included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 2000 can be applied to and packaged into different types of electronic products, such as a mobile phone, a computer (including but not limited to a desktop computer, a laptop computer, a tablet computer, a vehicle computer, etc.), a television, a set-top box, a game console, a printer, a positioning device, a vehicle-mounted device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage.

[0234] Optionally, as shown in Figure 13 The storage system 2000 can include the controller 300 and one memory 1000. The storage system 2000 can be integrated into a memory card.

[0235] The memory card includes any one of a PC Card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, or a UFS.

[0236] Optionally, as shown in Figure 14As shown, the storage system 2000 can include a controller 300 and a plurality of memories 1000. The storage system 2000 can be integrated into a solid state drive (SSD).

[0237] In the storage system 2000, for example, the controller 300 can be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0238] For another example, the controller 300 is configured to operate in a high duty cycle environment, such as an SSD or an eMMC used as a data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0239] In some embodiments, the controller 300 can be configured to manage data stored in the memories 1000 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 can also be configured to control operations of the memories 1000, such as read, erase, and program operations. In some embodiments, the controller 300 can also be configured to manage various functions related to data stored or to be stored in the memories 1000, including at least one of bad block management, garbage collection, logical to physical address translation, wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes related to data read from or written to the memories 1000.

[0240] Of course, the controller 300 can also perform any other suitable functions, such as formatting the memories 1000. For example, the controller 300 can communicate with an external device (e.g., a host) through at least one of various interface protocols.

[0241] It should be noted that the interface protocols include at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.

[0242] The memories 1000 included in the storage system 2000 provided by some embodiments of the present disclosure have the same structure and advantages as the memories 1000 provided by some embodiments described above, which will not be repeated here.

[0243] Some embodiments of the present disclosure further provide an electronic device. The electronic device comprises the storage system 2000 as described in some embodiments above.

[0244] The storage system 2000 comprised by the electronic device provided by some embodiments of the present disclosure has the same structure and beneficial effects as the storage system 2000 provided by some embodiments above, which will not be repeated here.

[0245] In some embodiments, the electronic device described above comprises at least one of the following: a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply.

[0246] As used in the present disclosure, whether a component (e.g., a layer, structure, or device) is "on", "above", or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined with respect to a substrate of the semiconductor device in a third direction Z when the substrate is in a lowest plane of the semiconductor device. Throughout the present disclosure, the same concept is applied to describe the spatial relationship.

[0247] The above only describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements within the technical scope disclosed by the present disclosure can be easily conceived by those skilled in the art, which shall be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The preparation method comprises: providing a three-dimensional array structure; the three-dimensional array structure comprises a substrate, a sacrificial layer arranged on one side of the substrate, and a stack structure arranged on a side of the sacrificial layer away from the substrate; forming a gate line slit extending through the stack structure and to the sacrificial layer; forming a doped polysilicon film and annealing the doped polysilicon film; the doped polysilicon film covers at least the inner wall of the gate line slit; forming a polysilicon film and annealing the polysilicon film; the polysilicon film covers the doped polysilicon film.

2. The production method according to claim 1, characterized by, The annealing of the doped polysilicon film adopts an in-situ annealing process; and / or The annealing of the polysilicon film adopts an in-situ annealing process.

3. The preparation method according to claim 1, characterized in that, The ratio of the thickness of the doped polysilicon film to the thickness of the polysilicon film ranges from 10:1 to 1:

10.

4. The method of claim 1, wherein, The impurity atoms in the doped polysilicon film comprise phosphorus atoms.

5. The preparation method according to claim 1, characterized in that, The doped polysilicon film and the polysilicon film also cover the stack structure; The preparation method further comprises: removing the part of the polysilicon film and the part of the doped polysilicon film covering the stack structure, and retaining the part of the polysilicon film and the part of the doped polysilicon film in the gate line slit.

6. The production method according to any one of claims 1 to 5, characterized by, Before the forming of the doped polysilicon film, the preparation method further comprises: forming an isolation film covering at least the inner wall of the gate line slit; The preparation method further comprises: removing the substrate and the sacrificial layer to expose the part of the isolation film extending to the sacrificial layer; etching the isolation film to expose the part of the doped polysilicon film extending to the sacrificial layer; forming a source layer on one side of the stack structure; the source layer forms an electrical contact with the exposed part of the doped polysilicon film.

7. The production method according to claim 6, wherein The three-dimensional array structure further comprises a channel structure extending through the stack structure and to the sacrificial layer; the channel structure comprises a storage functional layer and a channel layer arranged in sequence; After the removal of the substrate and the sacrificial layer, the part of the storage functional layer extending to the sacrificial layer is also exposed; In the process of etching the isolation film, the part of the storage functional layer exposed is also etched to expose the part of the channel layer extending to the sacrificial layer; The source layer also forms an electrical contact with the exposed part of the channel layer.

8. The production method according to claim 7, characterized by, Before the forming of the stack structure, the preparation method further comprises: stacking a first etching stop layer and a second etching stop layer in sequence on a side of the sacrificial layer away from the substrate; removing the substrate and the sacrificial layer to expose the part of the storage functional layer extending to the sacrificial layer and the part of the isolation film extending to the sacrificial layer, comprising: removing the substrate and the sacrificial layer to the first etching stop layer to expose the part of the storage functional layer extending to the sacrificial layer and the part of the isolation film extending to the sacrificial layer; etching the exposed part of the first etching stop layer and the storage functional layer to the second etching stop layer, exposing the part of the channel layer extending to the sacrificial layer, and etching the exposed part of the isolation film to expose the part of the doped polysilicon film.

9. The production method according to claim 8, characterized by, The stack structure has a step region, and the three-dimensional array structure further comprises a virtual channel structure located in the step region, the virtual channel structure penetrating through the stack structure and extending to the sacrificial layer; After the substrate and the sacrificial layer are removed, the part of the virtual channel structure extending to the sacrificial layer is also exposed; In the process of etching the exposed part of the first etching stop layer and the storage functional layer to the second etching stop layer, and etching the exposed part of the isolation film, the exposed part of the virtual channel structure is also etched; The source layer also forms contact with the exposed part of the virtual channel structure.

10. The method of claim 6, wherein, Before the isolation film forming to cover at least the inner wall of the gate line gap, the preparation method further comprises: forming a first insulating film on the inner wall of the gate line gap; forming a second insulating film in the gate line gap and on the side of the stack structure away from the substrate; the second insulating film covers the first insulating film; etching the bottom of the second insulating film and the bottom of the first insulating film to expose the sacrificial layer.

11. A semiconductor device, characterized by comprising: The semiconductor device comprises: a source layer; a stack structure arranged on one side of the source layer; the stack structure has a gate line gap penetrating through the stack structure and extending to the source layer; and a doped polysilicon layer and a polysilicon layer arranged in the gate line gap in sequence; the doped polysilicon layer is in electrical contact with the source layer; wherein the doped polysilicon layer and the polysilicon layer are respectively subjected to annealing treatment.

12. The semiconductor device of claim 11, wherein, The doped polysilicon layer and the polysilicon layer have a boundary surface therebetween.

13. The semiconductor device of claim 11, wherein, The ratio of the thickness of the doped polysilicon layer to the thickness of the polysilicon layer ranges from 1:10 to 10:

1.

14. The semiconductor device of claim 11, wherein, The semiconductor device further comprises an isolation layer arranged between the inner wall of the gate line gap and the doped polysilicon layer; The isolation layer has a first opening; The doped polysilicon layer is in electrical contact with the source layer through the first opening.

15. The semiconductor device of claim 14, wherein, The semiconductor device further comprises: a first insulating layer arranged between the inner wall of the gate line gap and the isolation layer; and a second insulating layer arranged between the first insulating layer and the isolation layer; wherein the first insulating layer and the second insulating layer have a second opening, the second opening and the first opening are in communication; The doped polysilicon layer is in electrical contact with the source layer through the first opening and the second opening.

16. The semiconductor device of claim 11, wherein, The semiconductor device further comprises a channel structure penetrating through the stack structure and extending to the source layer; The channel structure comprises a storage functional layer and a channel layer arranged in sequence, the part of the storage functional layer close to the source layer is provided with a third opening, and the channel layer extends to the source layer through the third opening and is in electrical contact with the source layer.

17. The semiconductor device of claim 11, wherein, The stack structure has a step region; The semiconductor device further comprises a virtual channel structure located in the step region; The virtual channel structure extends through the stack structure and to the source layer and is in contact with the source layer.

18. The semiconductor device of claim 11, wherein, The semiconductor device further includes a second etch stop layer disposed between the source layer and the stack structure.

19. A memory, comprising: The memory includes the semiconductor device of any one of claims 11-18.

20. The memory of claim 19, wherein, The memory includes a three-dimensional memory.

21. A storage system, characterized by The storage system includes a controller and the memory of claim 19 or 20. The controller is coupled to the memory and configured to control the memory to store data.

22. An electronic device, comprising: The electronic device includes the storage system of claim 21.

23. The electronic device of claim 22, wherein, The electronic device includes at least one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device, and a mobile power supply.

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