Electronic device and method of manufacturing the same

Abstract

The present invention discloses an electronic device and a manufacturing method thereof. The electronic device includes an array substrate. The array substrate includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtered layer, a second sputtered layer and a third sputtered layer. The second insulating layer is located on the second conductive layer. The second sputtered layer is located between the first sputtered layer and the third sputtered layer, the second sputtered layer includes a first metal element, the first sputtered layer includes a first metal element and a second metal element, and the third sputtered layer includes a first metal element and a third metal element.

Description

Technical Field

[0001] The present invention relates to a device and a manufacturing method thereof, and in particular to an electronic device and a manufacturing method thereof. Background Art

[0002] Generally, the connection pads of display panels are made of double or multiple metal layers. In order to reduce the peeling of the metal layer from the insulating layer, a molybdenum (Mo) layer is usually set between the two adjacent metal layers to strengthen the coverage. However, when the connection pads are bonded to the conductive terminals of the electronic components, there may be a problem of poor bonding strength, which affects the yield rate. Summary of the invention

[0003] The present invention provides an electronic device which can have a better yield rate.

[0004] The invention provides a method for manufacturing an electronic device, which can improve the bonding strength and the yield of the electronic device.

[0005] The electronic device of the present invention includes an array substrate. The array substrate includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and includes a first sputtered layer, a second sputtered layer and a third sputtered layer. The second insulating layer is located on the second conductive layer. The second sputtered layer is located between the first sputtered layer and the third sputtered layer, the second sputtered layer includes a first metal element, the first sputtered layer includes a first metal element and a second metal element, and the third sputtered layer includes a first metal element and a third metal element.

[0006] The manufacturing method of the electronic device of the present invention comprises providing an array substrate, the array substrate comprises a substrate, a first conductive layer, a first insulating layer, a second conductive layer and a second insulating layer. The substrate has a substrate surface. The first conductive layer is located on the substrate surface. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer and comprises a first sputtered layer, a second sputtered layer and a third sputtered layer. The second insulating layer is located on the second conductive layer. Among them, the second sputtered layer is located between the first sputtered layer and the third sputtered layer, the second sputtered layer comprises a first metal element, the first sputtered layer comprises a first metal element and a second metal element, and the third sputtered layer comprises a first metal element and a third metal element. An electronic component is provided. The electronic component comprises a component body and a conductive terminal arranged on the component body. At least the array substrate is brought into contact with the electronic component so that at least part of the second conductive layer in the array substrate and part of the conductive terminal in the electronic component form a conductive connection structure.

[0007] Based on the above, the electronic device of the present invention has an array substrate, and the second conductive layer of the array substrate includes a first sputtered layer, a second sputtered layer and a third sputtered layer. Since the first sputtered layer is in direct contact with the first insulating layer, and the first sputtered layer includes a first metal element and a second metal element, the coverage of the second conductive layer and the insulating layer can be strengthened to avoid peeling from the insulating layer, thereby having a better yield. Since the third sputtered layer is located on the second sputtered layer, the second sputtered layer is protected by the third sputtered layer, which can solve the problem of easy oxidation of the surface of the second sputtered layer. In addition, the manufacturing method of the electronic device of the present invention, the conductive connection structure formed by the contact between the array substrate and the electronic element can have good bonding strength, thereby improving the yield of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 4D is a partial schematic diagram of a partial manufacturing process of an electronic device according to a first embodiment of the present invention;

[0009] Figures 5 and 6 It is a partial schematic diagram of a partial manufacturing process of an electronic device according to a second embodiment of the present invention.

[0010] Explanation of symbols

[0011] 10A, 10B: Electronic devices

[0012] 100: array substrate

[0013] 101: Base material

[0014] 101a: Substrate surface

[0015] 110: first conductive layer

[0016] 112, 142: first sputtering layer

[0017] 114, 144: second sputtering layer

[0018] 120: first insulating layer

[0019] 130: Semiconductor layer

[0020] 140: second conductive layer

[0021] 140a: Connection pad

[0022] 140b: Routing

[0023] 146: The third sputtering layer

[0024] 150: Second insulation layer

[0025] 160: Conductive connection structure

[0026] 160a: District 1

[0027] 160b: District 2

[0028] 200: Electronic components

[0029] 202: Component body

[0030] 204: Conductive terminal

[0031] CH: Channel

[0032] A-A', B-B': section line

[0033] D: Drain

[0034] G: Gate

[0035] OP1: First opening

[0036] S: Source

[0037] T: Active components

[0038] V1: conduction structure DETAILED DESCRIPTION

[0039] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. is magnified for clarity. Throughout the specification, the same reference numerals represent the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to another element, or an intermediate element may also exist. On the contrary, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may be the presence of other elements between two elements.

[0040] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the "first element", "component", "region", "layer" or "portion" discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings of this document.

[0041] The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and / or "include" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0042] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, the elements described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in one figure is turned over, the elements described as being "below" or "beneath" other elements will be oriented as being "above" the other elements. Therefore, the exemplary terms "below" or "below" can include both above and below orientations.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0044] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances, can be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include shape deviations that result, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0045] Figures 1A to 4D1 is a partial schematic diagram of a partial manufacturing process of an electronic device according to a first embodiment of the present invention. Figure 1A , Figure 2A , Figure 3A and Figure 4A It is a partial top view schematic diagram of a part of the manufacturing process of the electronic device according to the first embodiment of the present invention, Figures 1B to 1D , FIG. 2B to FIG. 2D and FIG. 3B to FIG. 3D It is a partial cross-sectional schematic diagram of a part of the manufacturing process of the electronic device according to the first embodiment of the present invention. Figure 1B , Figure 2B , Figure 3B and Figure 4B Can correspond to Figure 1A , Figure 2A , Figure 3A and Figure 4A The position of the section line A-A'. Figure 1C , Figure 2C , Figure 3C and Figure 4C Can correspond to Figure 1A , Figure 2A , Figure 3A and Figure 4A The position of the section line B-B'. Figure 1D , Figure 2D , Figure 3D and Figure 4D Can correspond to Figure 1A , Figure 2A , Figure 3A and Figure 4A The positions of the section lines in other undrawn areas.

[0046] Please refer to Figures 1A to 1D , providing a substrate 101. The material of the substrate 101 may include glass, plastic, composite material or other suitable materials, but the present invention is not limited thereto. The substrate 101 has a substrate surface 101a. The substrate surface 101a may include an active (active) area and a non-active (passive) area. An active element may be formed or configured on the active area, and the active element is away from the non-active area. The active element is, for example, a thin film transistor, but the present invention is not limited thereto. Taking this embodiment as an example, Figure 1B , 1C is in the range corresponding to the inactive zone, Figure 1D is within the range corresponding to the active zone.

[0047] In one embodiment, a suitable film layer (eg, an insulating layer called a buffer layer) may be present on the substrate surface 101 a of the substrate 101 , but the present invention is not limited thereto.

[0048] Please continue to refer to Figures 1A to 1D, forming a first conductive layer 110 on the substrate surface 101a. The first conductive layer 110 may include a first sputtered layer 112 and a second sputtered layer 114. The first sputtered layer 112 is located between the substrate 101 and the second sputtered layer 114. The first sputtered layer 112 includes a first metal element and a second metal element (e.g., an alloy including the first metal element and the second metal element). The second sputtered layer 114 includes the first metal element but does not include the second metal element. The second metal element is different from the first metal element. The first metal element is, for example, copper, but the present invention is not limited thereto. The second metal element is, for example, nickel, iron, indium, antimony, bismuth, silver, gold, palladium, platinum, etc., but the present invention is not limited thereto. The thickness of the first conductive layer 110 may be between 500 nanometers (nanometer; nm) and 1500 nm.

[0049] Please refer to Figure 1D , within the range corresponding to the active region, a portion of the first conductive layer 110 can constitute at least one gate G.

[0050] Please refer to FIG. 2A to FIG. 2D , forming a first insulating layer 120 on the substrate surface 101a and covering the first conductive layer 110. Figure 2B and Figure 2C In the embodiment, the first insulating layer 120 partially covers the first conductive layer 110, so that a portion of the surface of the first conductive layer 110 is exposed. Figure 2D In the embodiment, the first insulating layer 120 completely covers the first conductive layer 110 .

[0051] In one embodiment, the first insulating layer 120 or a portion of the first insulating layer 120 (eg, Figure 2D The illustrated portion) may be referred to as a gate insulating layer (GI layer), but the present invention is not limited thereto.

[0052] Please refer to FIG. 3A to FIG. 3D, forming a second conductive layer 140 on the first insulating layer 120. The second conductive layer 140 includes a first sputtered layer 142, a second sputtered layer 144 and a third sputtered layer 146 stacked in sequence, wherein the second sputtered layer 144 is located between the first sputtered layer 142 and the third sputtered layer 146. The first sputtered layer 142 includes a first metal element and a second metal element (e.g., an alloy of the first metal element and the second metal element). The third sputtered layer 146 includes a first metal element and a third metal element (e.g., an alloy of the first metal element and the third metal element). The second sputtered layer 144 includes the first metal element, but does not include the second metal element or the third metal element. The third metal element is different from the first metal element. The third metal element is, for example, nickel, iron, indium, antimony, bismuth, silver, gold, palladium, platinum, etc., but the present invention is not limited thereto. The present invention does not limit the third metal element to be the same or different from the second metal element. The thickness of the second conductive layer 140 is between 500nm and 1500nm.

[0053] Since the first sputtered layer 142 is in direct contact with the first insulating layer 120 and includes the first metal element and the second metal element and / or an alloy of the first metal element and the second metal element, it helps to improve the coverage between the second conductive layer 140 and the first insulating layer 120 and reduce the peeling of the second conductive layer 140 from the first insulating layer 120.

[0054] exist Figure 3B , Figure 3C In the embodiment, part of the second conductive layer 140 is embedded in the first insulating layer 120 and directly contacts part of the first conductive layer 110 to form a conductive structure V1. Through the corresponding conductive structure V1, part of the first conductive layer 110 can be electrically connected to part of the second conductive layer 140. In other words, within the range corresponding to the inactive region, part of the second conductive layer 140 is embedded in the first insulating layer 120 to form a conductive structure V1 electrically connected to part of the first conductive layer 110.

[0055] Please refer to Figure 3D In the range corresponding to the active region, part of the second conductive layer 140 can constitute at least one source S and at least one drain D, and the source S and the drain D are separated from each other. Before forming the second conductive layer 140 on the first insulating layer 120, a semiconductor layer 130 can be formed on the first insulating layer 120, and part of the semiconductor layer 130 can constitute at least one channel CH. The gate G, the channel CH, the source S and the drain D can constitute an active device T, that is, at least part of the first conductive layer 110, part of the semiconductor layer 130 and part of the second conductive layer 140 can constitute an active device T.

[0056] In the present embodiment, the active element T may be a bottom gate thin film transistor (bottom gate TFT), but the present invention is not limited thereto. In an unillustrated embodiment, a portion of the first conductive layer 110, a portion of the semiconductor layer 130, and a portion of the second conductive layer 140 may constitute other types of active elements (such as, but not limited to, top gate thin film transistors (top gate TFT)). In an unillustrated embodiment, a portion of the first conductive layer 110 and a portion of the second conductive layer 140 may constitute other types of elements (such as capacitors or other suitable passive elements).

[0057] Please refer to 4A to 4D , forming a second insulating layer 150 on the second conductive layer 140. The second insulating layer 150 covers the second conductive layer 140. The second insulating layer 150 has a first opening OP1 (see Figure 4B ) to expose the surface of the second conductive layer 140. The second conductive layer 140 exposed by the first opening OP1 can be used as a connection pad 140a for connecting with other components. For example, the first opening OP1 exposes the surface of the third sputtered layer 146 of the second conductive layer 140. In one embodiment, since the second sputtered layer 144 of the second conductive layer 140 is protected by the third sputtered layer 146, the possibility of oxidation or moisture absorption of the second sputtered layer 144 can be reduced.

[0058] After the above manufacturing process, the array substrate 100 can be substantially manufactured. In addition, the array substrate 100 can be a part of the electronic device 10A.

[0059] Please refer to 4A to 4D, the electronic device 10A includes an array substrate 100. The array substrate 100 includes a substrate 101, a first conductive layer 110, a first insulating layer 120, a second conductive layer 140 and a second insulating layer 150. The substrate 101 has a substrate surface 101a, including an active area and an inactive area. The first conductive layer 110 is located on the substrate surface 101a, the first insulating layer 120 is located on the first conductive layer 110, the second conductive layer 140 is located on the first insulating layer 120, and the second insulating layer 150 is located on the second conductive layer 140. Among them, the second conductive layer 140 includes a first sputtered layer 142, a second sputtered layer 144 and a third sputtered layer 146 stacked in sequence. The second sputtered layer 144 is located between the first sputtered layer 142 and the third sputtered layer 146. The first sputtered layer 142 includes a first metal element and a second metal element (such as: an alloy of the first metal element and the second metal element). The third sputtering layer 146 includes the first metal element and the third metal element (e.g., an alloy of the first metal element and the third metal element). The second sputtering layer 144 includes the first metal element, but does not include the second metal element or the third metal element. The first metal element is, for example, copper, but the present invention is not limited thereto. The second metal element or the third metal element is, for example, nickel, iron, indium, antimony, bismuth, silver, gold, palladium, platinum, etc., but the present invention is not limited thereto. The thickness of the first conductive layer 110 or the thickness of the second conductive layer 140 is between 500nm and 1500nm.

[0060] Since the first sputtered layer 142 includes the first metal element and the second metal element (e.g., an alloy of the first metal element and the second metal element), and the first sputtered layer 142 directly contacts the first insulating layer 120, the coverage between the second conductive layer 140 and the first insulating layer 120 can be improved, and the peeling of the second conductive layer 140 from the first insulating layer 120 can be reduced.

[0061] The second insulating layer 150 has a first opening OP1 in a range corresponding to the inactive region (see Figure 4B ) to expose the surface of the second conductive layer 140, and the exposed second conductive layer 140 forms a connection pad 140a for connecting with other components. Figure 4C As shown, a portion of the second conductive layer 140 can be used as a wiring 140b for transmitting signals.

[0062] In the range corresponding to the active region, the array substrate 100 may further include a semiconductor layer 130 (see Figure 4D The semiconductor layer 130 is located between the first insulating layer 120 and the second conductive layer 140. A portion of the first conductive layer 110, a portion of the semiconductor layer 130, and a portion of the second conductive layer 140 may constitute an active device T.

[0063] From another perspective, the array substrate 100 may include a connection pad 140a, a trace 140b and an active element T. It should be understood that Figures 4A to 4D The pattern, quantity or position of the connection pads 140a, traces 140b and active components T of the array substrate 100 are only for illustration and are not intended to limit the present invention. The pattern, quantity or position of the connection pads 140a, traces 140b and active components T may be configured according to actual needs.

[0064] Figures 5 and 6 The electronic device 10B of this embodiment is similar to the electronic device 10A of the first embodiment, and similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and description thereof is omitted. Figures 5 and 6 Can be a continuation Figure 4B A cross-sectional schematic diagram of the manufacturing process.

[0065] Please refer to Figure 5 , providing an array substrate.

[0066] In this embodiment, the array substrate used is the array substrate 100 of the above-mentioned embodiment. Therefore, the same or similar reference numerals or terms are used in the subsequent drawings or descriptions, and the repeated contents are not repeated. Figure 5 In places not shown, the array substrate 100 may further include connection pads 140a, traces 140b or active components T (such as 4A to 4D However, the present invention is not limited thereto.

[0067] In an embodiment not shown, the array substrate used may be an array substrate similar to the array substrate 100 .

[0068] Please continue to refer to Figure 5 , an electronic component 200 is provided. The electronic component 200 includes a component body 202 and a conductive terminal 204 disposed on the component body 202.

[0069] The component body 202 may be, for example, a light emitting diode (LED) or other suitable components, but the invention is not limited thereto.

[0070] The conductive terminal 204 is, for example, a solder ball, but the present invention is not limited thereto. The conductive terminal 204 includes a fourth metal element. The fourth metal element may be different from the first metal element, the second metal element and / or the third metal element. For example, the fourth metal element may be tin, but the present invention is not limited thereto.

[0071] Please refer to Figure 6, making the array substrate 100 contact the electronic component 200. Then, at least a portion of the second conductive layer 140 in the array substrate 100 and at least a portion of the conductive terminals 204 in the electronic component 200 form a conductive connection structure 160.

[0072] For example, at least a portion of the conductive terminals 204 in the electronic component 200 may directly contact a portion of the second conductive layer 140 through the first opening OP1 of the array substrate 100. Then, after a portion of the conductive terminals 204 contact a portion of the second conductive layer 140, at least a heating step may be performed to form the conductive connection structure 160.

[0073] In one embodiment, the conductive connection structure 160 may be an intermetallic compound (IMC). For example, the conductive connection structure 160 may be an intermetallic compound including at least a first metal element and a fourth metal element, but the present invention is not limited thereto. Figure 6 In the figure, the shape or range of the conductive connection structure 160 may be schematically depicted, and may vary accordingly according to the parameters of the manufacturing process (such as: heating time and / or temperature, the type of metal element used, the pressure applied when the array substrate 100 and the electronic element 200 are in contact, etc.). In addition, the boundary of the conductive connection structure 160 (such as: the contact surface between the conductive connection structure 160 and the conductive terminal 204, the second conductive layer 140 and / or the first conductive layer 110) may be an irregular shape or a non-planar surface.

[0074] In this embodiment, the conductive connection structure 160 may also directly contact a portion of the first conductive layer 110. That is, after a portion of the conductive terminal 204 contacts a portion of the second conductive layer 140, at least a heating step may be performed to form a portion of the conductive terminal 204, a portion of the first conductive layer 110, and a portion of the second conductive layer 140 to form the conductive connection structure 160.

[0075] In the present embodiment, since the second conductive layer 140 includes the first sputtered layer 142, the second sputtered layer 144 and the third sputtered layer 146 stacked in sequence, and the first sputtered layer 142 includes the first metal element and the second metal element (e.g., an alloy of the first metal element and the second metal element), the third sputtered layer 146 includes the first metal element and the third metal element (e.g., an alloy of the first metal element and the second metal element), and the second sputtered layer 144 includes the first metal element but does not include the second metal element or the third metal element, it is possible to make it easier for a portion of the first conductive layer 110 and a portion of the second conductive layer 140 to form an intermetallic compound with the conductive terminal 204 of the electronic element 200. In this way, the bonding strength between the array substrate 100 and the electronic element 200 can be improved. In addition, since the first sputtered layer 142 is in direct contact with the first insulating layer 120, it is helpful to improve the coverage between the second conductive layer 140 and the first insulating layer 120, and the peeling of the second conductive layer 140 from the first insulating layer 120 can be reduced.

[0076] In one embodiment, the fourth metal element includes tin, and the first metal element, the second metal element and / or the third metal element do not include molybdenum. It is difficult for tin and molybdenum to form an intermetallic compound. If it is difficult to form an intermetallic compound, the bonding strength may be reduced.

[0077] In the present embodiment, the conductive terminals 204 disposed on the component body 202 may be different in size or shape before or after the array substrate 100 and the electronic component 200 are attached; and / or, the conductive layer (e.g., the second conductive layer 140 or the first conductive layer 110) of the array substrate 100 may be different in size or shape before or after the array substrate 100 and the electronic component 200 are attached. For example, after the array substrate 100 and the electronic component 200 are attached, part of the conductive layer of the array substrate 100 may form a conductive connection structure 160 with part of the conductive terminals 204, and the material of the conductive connection structure 160 is slightly different from the material of the conductive layer (e.g., the material of the conductive connection structure 160 includes an element not included in the conductive layer), and the material of the conductive connection structure 160 is slightly different from the material of the conductive terminal 204 (e.g., the material of the conductive connection structure 160 includes an element not included in the conductive layer). However, for ease of representation, the same names or symbols are still used to describe the elements or components before or after the array substrate 100 and the electronic component 200. Ordinary technicians in this field should be able to understand the semantic statements similar to fuzzy logic and the corresponding concepts.

[0078] After the above manufacturing processes, the manufacturing of the electronic device 10B of this embodiment can be substantially completed.

[0079] Please refer to Figure 6The electronic device 10B includes an array substrate 100 , an electronic component 200 and a conductive connection structure 160 .

[0080] In a direction perpendicular to the substrate surface 101a, the conductive connection structure 160 includes a first region 160a and a second region 160b, and the first region 160a is closer to the substrate surface 101a than the second region 160b. In the first region 160a, the first metal element has a first ratio to the fourth metal element (e.g., the relative molar number of the first metal element in the detection range or its derivative unit / the relative molar number of the fourth metal element in the detection range or its derivative unit; the same applies to the following); in the second region 160b, the first metal element has a second ratio to the fourth metal element, and the first ratio is greater than the second ratio. In one embodiment, the first ratio is, for example, 3 / 1, and the second ratio is, for example, 6 / 5, but the present invention is not limited thereto. In one embodiment, the type or content of the element can be obtained directly or indirectly by energy-dispersive X-ray spectroscopy (EDX / EDS) analysis, but the present invention is not limited thereto.

[0081] In one embodiment, in the conductive connection structure 160 , the ratio of the first metal element to the fourth metal element may gradually decrease from the first region 160 a to the second region 160 b .

[0082] Since the electronic device 10B has the conductive connection structure 160 , the bonding between the array substrate 100 and the electronic element 200 can be strengthened, thereby improving the yield of the electronic device 10B.

[0083] It should be understood that the present invention Figure 6 The cross-sectional view of a portion of the electronic device 10B is schematically shown. Figure 6 Although the first conductive layer 110 is not shown, the electronic device 10B may include the first conductive layer 110 in other unshown locations, and may also include structures such as the aforementioned connection pads 140 a , traces 140 b , or active components T, but the present invention is not limited thereto.

[0084] In summary, the electronic device of the present invention has an array substrate, and the second conductive layer of the array substrate includes a first sputtered layer, a second sputtered layer and a third sputtered layer stacked in sequence. Since the first sputtered layer is in direct contact with the first insulating layer, and the first sputtered layer includes the first metal element and the second metal element and / or an alloy of the first metal element and the second metal element, the coverage of the second conductive layer and the insulating layer can be strengthened to prevent the second conductive layer from peeling off from the insulating layer, thereby having a better yield. Since the third sputtered layer is located on the second sputtered layer, the second sputtered layer is protected by the third sputtered layer, which can solve the problem of easy oxidation of the surface of the second sputtered layer. In addition, the manufacturing method of the electronic device of the present invention, the conductive connection structure formed by the contact between the array substrate and the electronic element can have good bonding strength, thereby improving the yield of the electronic device.

[0085] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any common technical heat source described in the art may be slightly modified and embellished without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. An electronic device, comprising: An array substrate comprises: a substrate having a substrate surface; A first conductive layer is located on the surface of the substrate; a first insulating layer, located on the first conductive layer; A second conductive layer, located on the first insulating layer and comprising a first sputtered layer, a second sputtered layer and a third sputtered layer; and A second insulating layer is located on the second conductive layer, wherein: The second sputtered layer is located between the first sputtered layer and the third sputtered layer; The second sputtered layer includes a first metal element; The first sputtered layer includes the first metal element and the second metal element; and The third sputtered layer includes the first metal element and the third metal element; An electronic component, comprising a component body and a conductive terminal disposed on the component body; and A conductive connection structure directly connects the conductive terminal and the second conductive layer, wherein in a direction perpendicular to the surface of the substrate, the conductive connection structure includes a first region and a second region, wherein: The first region is closer to the surface of the substrate than the second region; The conductive terminal includes a fourth metal element; In the first region, the first metal element has a first ratio to the fourth metal element; in the second region, the first metal element has a second ratio to the fourth metal element; and The first ratio is greater than the second ratio.

2. The electronic device as claimed in claim 1, wherein: The first sputtered layer includes an alloy of the first metal element and the second metal element; The second sputtered layer does not include the second metal element or the third metal element; and / or the third sputtered layer includes an alloy of the first metal element and the third metal element.

3. The electronic device as claimed in claim 2, wherein the array substrate further comprises a semiconductor layer, and the substrate comprises an active region and an inactive region, wherein: In a range corresponding to the inactive area, at least a portion of the second conductive layer constitutes a connection pad; and In a range corresponding to the active region, at least a portion of the first conductive layer, a portion of the semiconductor layer, and a portion of the second conductive layer constitute an active device. 4 . The electronic device as claimed in claim 3 , wherein within a range corresponding to the inactive region, a portion of the second conductive layer is embedded in the first insulating layer to form a conductive structure electrically connected to a portion of the first conductive layer. 5 . The electronic device as claimed in claim 1 , wherein a thickness of the first conductive layer or a thickness of the second conductive layer is between 500 nm and 1500 nm. The electronic device as claimed in claim 1 , wherein the conductive connection structure is also directly connected to the first conductive layer. 7 . The electronic device as claimed in claim 1 , wherein a ratio of the first metal element to the fourth metal element gradually decreases from the first region to the second region.

8. A method for manufacturing an electronic device, comprising: An array substrate is provided, the array substrate comprising: a substrate having a substrate surface; A first conductive layer is located on the surface of the substrate; a first insulating layer, located on the first conductive layer; A second conductive layer, located on the first insulating layer and comprising a first sputtered layer, a second sputtered layer and a third sputtered layer; and A second insulating layer is located on the second conductive layer, wherein: The second sputtered layer is located between the first sputtered layer and the third sputtered layer; The second sputtered layer includes a first metal element; The first sputtered layer includes the first metal element and the second metal element; and The third sputtered layer includes the first metal element and the third metal element; An electronic component is provided, comprising a component body and a conductive terminal disposed on the component body; and At least the array substrate is brought into contact with the electronic component, so that at least part of the second conductive layer in the array substrate and part of the conductive terminals in the electronic component form a conductive connection structure, wherein the conductive connection structure directly connects the conductive terminals and the second conductive layer, In a direction perpendicular to the surface of the substrate, the conductive connection structure includes a first region and a second region, wherein: The first region is closer to the surface of the substrate than the second region; The conductive terminal includes a fourth metal element; In the first region, the first metal element has a first ratio to the fourth metal element; in the second region, the first metal element has a second ratio to the fourth metal element; and The first ratio is greater than the second ratio.

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