Etching method of polysilicon structure with rough surface
By forming a consistent dielectric layer and anti-reflection layer on the polysilicon plate and etching in combination with the photolithography process, the residual problem caused by the undulation of the dielectric layer is solved, and smooth etching of the polysilicon surface is achieved, avoiding silicon perforation.
Patent Information
- Application Number
- CN202111219428.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-10-20
- Publication Date
- 2025-02-11
- Estimated Expiration
- 2041-10-20
AI Technical Summary
In the prior art, when etching polysilicon plates, the residual caused by the ups and downs of the dielectric layer, which easily blocks further etching of polysilicon, and overetching may lead to the problem of silicon perforation.
An etching method using a rough surface polysilicon structure, including forming a consistent dielectric layer on the polysilicon layer, covering the anti-reflection layer, defining the etching pattern through a photolithography process, and performing a first etching to remove the anti-reflection layer and part of the dielectric The layer is formed, and a smooth first etch stop surface is followed by an isotropic second etching to remove the remaining dielectric layer and polysilicon layer.
Effectively remove dielectric layer residues, avoid blocking polysilicon etching, ensure smooth surface of polysilicon, and avoid silicon perforation.
Smart Images
Figure CN114023879B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a polysilicon structure etching method. Background Art
[0002] DTC (Deep Trench Capacitance) is used to store charge and usually includes Figure 1 In the multi-layer polysilicon plate 110 shown, a dielectric layer 120 is formed between two adjacent layers of the polysilicon plate 110 . The material of the dielectric layer 120 may be an oxide layer made by a thermal oxidation process.
[0003] In order to enable the DTC to store more charge, this can be achieved by increasing the surface area of the polysilicon plate. In the related art, a method of roughening the surface of the polysilicon plate can be used to effectively increase the surface of the polysilicon plate.
[0004] However, since the related technology increases the surface roughness of the polysilicon plate, the morphology of the dielectric layer between two adjacent layers of polysilicon plates also fluctuates with the roughness of the surface of the polysilicon plate, forming a protrusion or depression. Therefore, when etching polysilicon, the dielectric layer at the protrusion or depression is difficult to be etched away, and the dielectric layer that is not etched away will block the subsequent etching of the polysilicon plate, leaving polysilicon residue. If an over-etching solution is used to avoid polysilicon residue, it is easy to have an adverse effect on the morphology of the polysilicon plate, and even silicon penetration problems may occur. Summary of the invention
[0005] The present application provides an etching method for a polysilicon structure with a rough surface, which can solve the problem that the over-etching solution used in the related art to remove polysilicon residues can easily have an adverse effect on the morphology of the polysilicon plate and cause silicon penetration.
[0006] In order to solve the technical problem described in the background technology, the present application provides a method for etching a polysilicon structure with a rough surface, and the method for etching a polysilicon structure with a rough surface comprises the following steps:
[0007] Providing at least one layer of polysilicon structure with a rough surface, wherein the polysilicon structure comprises a polysilicon layer with a rough surface and a dielectric layer covering the rough surface of the polysilicon layer, and the morphology of the dielectric layer is consistent with the morphology of the rough surface of the polysilicon layer;
[0008] so that an anti-reflection layer is formed on the dielectric layer;
[0009] By means of a photolithography process, an etching pattern is defined on the reflective layer, wherein the etching pattern includes an etching area and a protection area;
[0010] Based on the etching pattern, performing a first etching to remove the anti-reflection layer at the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth;
[0011] Based on the etching pattern, performing an isotropic second etching to remove the remaining dielectric layer at the etching area;
[0012] Based on the etching pattern, the polysilicon layer at the etching area is removed by etching.
[0013] Optionally, under the same etching conditions, the etching rate of the anti-reflection layer is greater than the etching rate of the dielectric layer.
[0014] Optionally, under the same etching conditions, the etching rate of the anti-reflection layer is 6 to 8 times the etching rate of the dielectric layer.
[0015] Optionally, the step of etching and removing the polysilicon layer at the etching area based on the etching pattern includes:
[0016] Based on the etching pattern, etching the main body of the polysilicon layer from the upper surface of the polysilicon layer at the etching area at a first etching rate to form a second etching stop surface located in the polysilicon layer;
[0017] Based on the etching pattern, etching the bottom of the polysilicon layer starting from the second etching stop surface at a second etching rate;
[0018] Based on the etching pattern, the remaining polysilicon in the polysilicon layer is etched away at a third etching rate.
[0019] Optionally, under the same etching conditions, the second etching rate is greater than the first etching rate.
[0020] Optionally, under the same etching conditions, the third etching rate is greater than the second etching rate.
[0021] Optionally, the step of performing an isotropic second etching based on the etching pattern to remove the remaining dielectric layer at the etching area includes:
[0022] Based on the etching pattern, an isotropic second etching is performed with a source power ranging from 200 W to 500 W to etch away the remaining dielectric layer at the etching area.
[0023] Optionally, the step of performing an isotropic second etching based on the etching pattern to remove the remaining dielectric layer at the etching area includes:
[0024] Based on the etching pattern, an isotropic second etching is performed with a bias voltage in a voltage range of -10V to 10V to etch away the remaining dielectric layer at the etching area.
[0025] The technical solution of the present application includes at least the following advantages: by performing a first etching based on an etching pattern, the anti-reflection layer at the etching area is etched away to form a first etching stop surface located in the dielectric layer, and the surface of the first etching stop surface is smooth; based on the etching pattern, an isotropic second etching is performed to remove the remaining dielectric layer at the etching area, so that the dielectric layer on the rough surface of the polysilicon layer can be completely etched away, avoiding the residual dielectric layer at the interface of some depressions or protrusions, and further in the process of etching the polysilicon layer, the etching of the polysilicon will not be blocked by the residual dielectric layer, so that the surface of the polysilicon after etching is smooth. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0027] Figure 1 A schematic diagram of a cross-sectional structure of a DTC in the related art is shown;
[0028] Figure 2 A method for etching a polysilicon structure with a rough surface provided by an embodiment of the present application is shown;
[0029] Figure 2a A schematic cross-sectional structure diagram of a polysilicon structure with a rough surface provided by an embodiment of the present application is shown;
[0030] Figure 2b Shown in Figure 2a A schematic diagram of a cross-sectional structure of a device after an anti-reflection layer is coated on the basis of FIG.
[0031] Figure 2c Shown in Figure 2b A schematic diagram of a cross-sectional structure of a device on which an etching pattern is formed;
[0032] Figure 2d Shown based on Figure 2c A schematic diagram of a cross-sectional structure of a device formed after the etching pattern shown is subjected to a first etching;
[0033] Figure 2e After the second etching, the Figure 2d A schematic diagram of a cross-sectional structure of a device showing the remaining dielectric layer at the etching area;
[0034] Figure 3a A schematic diagram of a cross-sectional structure of the device after step S261 is completed is shown;
[0035] Figure 3b A schematic diagram of a cross-sectional structure of the device after step S262 is completed is shown;
[0036] Figure 3c FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S263 is completed. DETAILED DESCRIPTION
[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0038] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0039] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0040] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0041] Figure 2 The flowchart of the etching method of the rough surface polysilicon structure provided by an embodiment of the present application is shown. Figure 2 It can be seen that the etching method of the rough surface polysilicon structure includes the following steps performed in sequence:
[0042] Step S21: providing at least one layer of polysilicon structure with a rough surface.
[0043] A layer of the polysilicon structure includes a polysilicon layer with a rough surface and a dielectric layer covering the rough surface of the polysilicon layer, and the morphology of the dielectric layer is consistent with the rough surface of the polysilicon layer.
[0044] Reference Figure 2a , which shows a schematic cross-sectional structure diagram of a rough surface polysilicon structure provided by an embodiment of the present application. Figure 2a As can be seen from the figure, the present embodiment provides two layers of polysilicon structures stacked one above the other, namely, a first polysilicon structure 201 located at the upper layer and a second polysilicon structure 202 located at the lower layer. Each layer of polysilicon structure 201, 202 includes a polysilicon layer 210 with a rough surface, and a dielectric layer 220 covering the rough surface layer of the polysilicon layer 210, and the morphology of the dielectric layer 220 is consistent with the morphology of the rough surface of the polysilicon layer 210.
[0045] The dielectric layer 220 may be an oxide layer grown by a thermal oxidation process. The thickness of the dielectric layer 220 may range from to
[0046] The thickness range of the first polysilicon structure 201 and the second polysilicon structure 202 can be to
[0047] Step S22: forming an anti-reflection layer on the dielectric layer.
[0048] In the photolithography process, light interference occurs when the exposure light reaches the interface between the layer to be etched and the photoresist layer, thereby forming a standing wave effect and multiple exposures inside the photoresist layer. This causes the key dimension CD of the etched pattern formed after development of the photoresist layer to be uncontrollable, and wavy or jagged defects appear on the side walls of the etched pattern, which has an adverse effect on the subsequent polysilicon etching step based on the etched pattern.
[0049] Reference Figure 2b , which shows that in Figure 2a Schematic diagram of the cross-sectional structure of the device after coating the anti-reflection layer on the basis of Figure 2b It can be seen from the figure that before coating the photoresist, the anti-reflection layer 230 is spin-coated on the dielectric layer 220 of the first polysilicon structure 201.
[0050] The anti-reflection layer 230 absorbs the photolithography reflected light during exposure, reduces the light interference problem, avoids the standing wave effect and multiple exposure inside the photoresist layer, and makes the side wall of the etched pattern smooth.
[0051] Optionally, the anti-reflective layer 230 may be a BARC (Bottom Anti-Reflective Coating) with a thickness ranging from to
[0052] Step S23: defining an etching pattern on the reflective layer through a photolithography process, wherein the etching pattern includes an etching area and a protection area.
[0053] Reference Figure 2c , which shows that in Figure 2b A schematic diagram of a cross-sectional structure of a device on which an etching pattern is formed. Figure 2c It can be seen that in Figure 2b The anti-reflection layer 230 is coated with a photoresist 300, and after the photoresist 300 is etched by photolithography, the photoresist 30 defines an etching pattern. The etching pattern includes an etching area 310 and a protection area 320. The surface of the anti-reflection layer 230 at the etching area 310 is exposed and not covered with the photoresist 300, while the anti-reflection layer 230 at the protection area 320 is covered with the photoresist 300, and the photoresist 300 can protect the polysilicon structure at the protection area 320 from being etched.
[0054] Optionally, the thickness of the photoresist 300 may be to
[0055] Step S24: performing a first etching based on the etching pattern to remove the anti-reflection layer at the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth.
[0056] Reference Figure 2d , which shows that based on Figure 2c The schematic diagram of the cross-sectional structure of the device formed after the first etching of the etching pattern shown. Figure 2d It can be seen that after the first etching, the anti-reflection layer 230 located in the etching area 310 and part of the dielectric layer 220 of the first polysilicon structure 201 are etched away, so that the first etching stop surface 410 of the first etching is located in the dielectric layer 220 of the first polysilicon structure 201, and the surface of the first etching stop surface 410 is smooth.
[0057] Exemplarily, under the same etching condition, the etching rate of the anti-reflection layer is greater than the etching rate of the dielectric layer, so that a smooth first etching stop surface 410 can be formed when etching the undulating interface between the anti-reflection layer 230 and the dielectric layer 220 .
[0058] Optionally, under the same etching conditions, the etching rate of the anti-reflection layer 230 is 6 to 8 times the etching rate of the dielectric layer 220 .
[0059] The first etching may be performed using an etching gas including hydrobromic acid HBr and oxygen O 2 .
[0060] Step S25: performing an isotropic second etching based on the etching pattern to remove the remaining dielectric layer at the etching area.
[0061] Reference Figure 2e , which shows that after the second etching, the Figure 2d The schematic diagram of the cross-sectional structure of the device of the remaining dielectric layer at the etching area shown in FIG. Figure 2e It can be seen that, since the second etching adopts an isotropic etching process, the remaining dielectric layer 220 on the rough surface polysilicon layer 210 at the etching area 310 can be completely etched away, avoiding the dielectric layer 220 remaining at the interface of some depressions or protrusions. After the second etching is completed, the upper surface of the polysilicon layer 210 of the first polysilicon structure 201 is exposed.
[0062] Illustratively, during the second etching process, the etching source power range can be 200W to 500W, and the bias voltage can be -10V to 10V, so that the remaining dielectric layer 220 on the rough surface polysilicon layer 210 can be completely etched away, avoiding the residual dielectric layer 220 at some recessed or protruding interfaces.
[0063] Step S26: etching and removing the polysilicon layer at the etching area based on the etching pattern.
[0064] In this embodiment, a first etching is performed based on an etching pattern to remove the anti-reflection layer at the etching area, thereby forming a first etching stop surface located in the dielectric layer, and the surface of the first etching stop surface is smooth; an isotropic second etching is performed based on the etching pattern to remove the remaining dielectric layer at the etching area, so that the dielectric layer on the rough surface of the polysilicon layer can be completely etched away, avoiding the residual dielectric layer at the interface of some depressions or protrusions, and further, in the process of etching the polysilicon layer, the etching of the polysilicon will not be blocked by the residual dielectric layer, so that the surface of the polysilicon after etching is smooth.
[0065] In order to completely etch and remove the polysilicon layer 210 of the first polysilicon structure 201 at the location of the etching area 310, the process of performing step S26: etching and removing the polysilicon layer at the location of the etching area based on the etching pattern may include the following steps performed in sequence:
[0066] Step S261: Based on the etching pattern, etching the main body of the polysilicon layer is performed starting from the upper surface of the polysilicon layer at the etching area at a first etching rate to form a second etching stop surface located in the polysilicon layer.
[0067] Reference Figure 3a , which illustrates a schematic diagram of the cross-sectional structure of the device after step S261 is completed. Figure 3a It can be seen that in Figure 2e Step S261 is performed based on the device structure shown, so that the main part of the polysilicon layer 210 of the first polysilicon structure 201 from the upper surface downward is etched away to form a second etch stop surface 420 located in the polysilicon layer 210. The second etch stop surface 420 is still a certain distance away from the lower surface of the polysilicon layer 210.
[0068] Step S262: etching the bottom of the polysilicon layer starting from the second etch stop surface at a second etch rate based on the etch pattern.
[0069] Reference Figure 3b , which shows a schematic diagram of the cross-sectional structure of the device after step S262 is completed. Figure 3b It can be seen that in Figure 3a Step S262 is performed based on the device structure shown, so that the bottom of the polysilicon layer 210 from the second etch stop surface 420 downward is etched away.
[0070] However, since the first polysilicon structure 201 is located on the rough surface of the second polysilicon structure 202, the lower surface of the polysilicon layer 210 of the first polysilicon structure 201 is uneven and rough. Therefore, after the bottom etching of the polysilicon layer 210 is completed starting from the second etching stop surface 420 at the second etching rate, there is still polysilicon remaining in the depression on the upper surface of the second polysilicon structure 202 that has not been etched away.
[0071] Step S263: etching and removing the remaining polysilicon in the polysilicon layer at a third etching rate based on the etching pattern.
[0072] Reference Figure 3c , which shows a schematic diagram of the device cross-sectional structure after step S263 is completed. Figure 3c It can be seen that in Figure 3b Step S263 is performed based on the device structure shown in FIG. Figure 3b The remaining polysilicon of the polysilicon layer 210 at the middle etched region 310 is completely etched away.
[0073] Optionally, under the same etching conditions, the second etching rate is greater than the first etching rate, and under the same etching conditions, the third etching rate is greater than the second etching rate.
[0074] In this embodiment, the polysilicon layer of the first polysilicon structure is sequentially etched at three different etching rates, so that the polysilicon layer can be completely etched away to avoid residue while preventing damage to the polysilicon layer morphology and avoiding silicon penetration.
[0075] After etching the polysilicon layer of the first polysilicon structure at the etching area, the above steps S22 to S26 and S261 to S263 may be repeated to etch the first polysilicon structure 202, which will not be described in detail herein.
[0076] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for etching a polysilicon structure with a rough surface, characterized in that: The etching method of the polysilicon structure with a rough surface comprises the following steps: Providing at least one layer of polysilicon structure with a rough surface, wherein the polysilicon structure comprises a polysilicon layer with a rough surface and a dielectric layer covering the rough surface of the polysilicon layer, and the morphology of the dielectric layer is consistent with the morphology of the rough surface of the polysilicon layer; so that an anti-reflection layer is formed on the dielectric layer; By means of a photolithography process, an etching pattern is defined on the reflective layer, wherein the etching pattern includes an etching area and a protection area; Based on the etching pattern, performing a first etching to remove the anti-reflection layer at the etching area to form a first etching stop surface in the dielectric layer, wherein the surface of the first etching stop surface is smooth; Based on the etching pattern, performing an isotropic second etching to remove the remaining dielectric layer at the etching area; Based on the etching pattern, etching and removing the polysilicon layer at the etching area; The step of etching and removing the polysilicon layer at the etching area based on the etching pattern comprises: Based on the etching pattern, etching the main body of the polysilicon layer from the upper surface of the polysilicon layer at the etching area at a first etching rate to form a second etching stop surface located in the polysilicon layer; Based on the etching pattern, etching the bottom of the polysilicon layer starting from the second etching stop surface at a second etching rate; Based on the etching pattern, etching and removing the remaining polysilicon in the polysilicon layer at a third etching rate; Under the same etching conditions, the second etching rate is greater than the first etching rate; Under the same etching conditions, the third etching rate is greater than the second etching rate.
2. The etching method for a polysilicon structure having a rough surface as claimed in claim 1, characterized in that: Under the same etching conditions, the etching rate of the anti-reflection layer is greater than the etching rate of the dielectric layer.
3. The etching method of a polysilicon structure with a rough surface as claimed in claim 2, characterized in that: Under the same etching conditions, the etching rate of the anti-reflection layer is 6 to 8 times that of the dielectric layer.
4. The etching method for a rough-surfaced polysilicon structure according to claim 1, characterized in that: The step of performing an isotropic second etching based on the etching pattern to etch away the remaining dielectric layer at the etching area comprises: Based on the etching pattern, an isotropic second etching is performed with a source power ranging from 200 W to 500 W to etch away the remaining dielectric layer at the etching area.
5. The etching method of a polysilicon structure with a rough surface as claimed in claim 4, characterized in that: The step of performing an isotropic second etching based on the etching pattern to etch away the remaining dielectric layer at the etching area comprises: Based on the etching pattern, an isotropic second etching is performed with a bias voltage in a voltage range of -10V to 10V to etch away the remaining dielectric layer at the etching area.
Citation Information
Patent Citations
Preparation method of electrode
CN111517272A
Forming method of roughened polysilicon film
JP1996213554A