Compact mixed-signal multiply-accumulate engine based on non-volatile memory

Abstract

A multiply accumulate method and architecture is disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally regulates an equivalent conductance of individual networks in the plurality of networks to map the equivalent conductance of each individual network to a single weight within a neural network. A first partial selection of weights within the neural network is mapped to the equivalent conductances of the networks in the columns to enable multiply and accumulate operations to be calculated by mixed signal computation. The logic updates the mappings to select a second partial selection of weights to calculate further multiply and accumulate operations, and the mappings and the calculation operations are repeated until all calculations for the neural network are complete.

Description

Background Art

[0001] The present disclosure relates generally to machine learning accelerators and, more particularly, to a mixed-signal multiply-accumulate engine for improving the efficiency of machine learning operations.

[0002] A crossbar architecture based on non-volatile memory (NVM) provides an alternative mechanism for performing multiply-accumulate (MAC) operations in machine learning algorithms, particularly neural networks. Mixed-signal approaches using NVM bit cells rely on Ohm's law to implement multiplication operations by exploiting the resistive properties of emerging NVM technologies, such as phase-change memory (PCM), resistive random access memory (RRAM), associative electron random access memory (CeRAM), and others. Applying a voltage bias across an NVM bit cell generates a current proportional to the product of the conductance of the NVM element and the voltage bias across the cell.

[0003] The currents from multiple such bit cells can then be added in parallel to perform a cumulative sum. Thus, the combination of Ohm's law and Kirchhoff's current law performs multiple MAC operations in parallel. When implemented in the digital domain using explicit multipliers and adders, these can be energy intensive.

[0004] According to the present disclosure, improved NVM crossbar architectures are provided that provide energy-efficient acceleration of analog computing operations while reducing the attendant area and throughput impacts inherent in known approaches. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:

[0006] Figure 1A and Figure 1B Describe high-level representations of neural networks;

[0007] Figure 2 This is a diagram of the convolution operation within a single layer of a convolutional neural network;

[0008] Figure 3 is a depiction of an architecture for performing convolution operations using an NVM cross structure;

[0009] Figure 4 is a schematic circuit for digitally encoding weights using conductance according to an embodiment of the present disclosure; and

[0010] Figure 5 is the architecture of a multiply-accumulate engine according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Specific embodiments of the present disclosure will now be described in detail with respect to the accompanying drawings. For simplicity and clarity of explanation, reference numerals may be repeated in the accompanying drawings to indicate corresponding or similar elements, where deemed appropriate. In addition, many specific details are set forth in order to provide a thorough understanding of the examples described herein. However, it will be understood by those of ordinary skill in the art that the examples described herein may be practiced without these specific details. In other cases, well-known methods, procedures, and components are not described in detail to avoid obscuring the examples described herein. Furthermore, this specification should not be considered to limit the scope of the examples described herein.

[0012] It should be understood that the examples and corresponding figures used herein are for illustrative purposes only. Different configurations and terminology may be used without departing from the principles expressed herein. For example, components and modules may be added, deleted, modified, or arranged in different connections without departing from these principles.

[0013] In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In other cases, well-known features have not been described in detail to avoid unnecessarily complicating this specification.

[0014] It should be understood that the terms used herein are for the purpose of describing various embodiments according to the present disclosure, and are not intended to be restrictive. As used herein, the term "a / an" is defined as one or more than one. As used herein, the term "plurality" is defined as two or more than two. As used herein, the term "another" is defined as at least a second or more. As used herein, the terms "include" and / or "have" are defined as including (i.e., open language). As used herein, the term "coupled" is defined as connected, but not necessarily directly and not necessarily mechanically connected. The term "provided" is defined in this article with its broadest meaning, for example, as a whole or simultaneously or within a certain period of time, begins to become / become a physical existence, becomes available and / or is supplied to someone or something in multiple parts.

[0015] As used herein, the terms "about," "approximately," or "substantially" apply to all numerical values, whether or not such values ​​are explicitly indicated. Such terms generally refer to a range of numbers that one skilled in the art would consider equivalent to the recited value (i.e., having the same function or result). These terms may include numbers rounded to the nearest significant figure. In this document, any reference to the term "longitudinally" should be understood to mean in a direction corresponding to the direction of elongation of a personal computing device from one terminal end to the opposite terminal end.

[0016] Figure 1A and Figure 1Bis a graph of a neural network. Figure 1A An example of a neural network 100 is shown, which generally includes a plurality of input neurons 1021, 1022, ..., 102 N (where “N” is any suitable number), hidden layers 1041, 1042, ... 104 N (where "N" is any suitable number) and output neurons 1061, 1062, ... 106 N (where "N" is any suitable number).

[0017] Figure 1B Depicts the corresponding weights W1, W2, W n-1 ,…,W n X1, X2, X3, X n-1 ,…,X n (where "n" is any suitable number) represents a plurality of input activations 108(a), 108(b), 108(c), 108(d), ..., 108(n), corresponding to Figure 1A Each neuron 1021, 1022, ..., 102 N The activation function 112 for the corresponding neuron outputs an output activation Y, which may be, but is not limited to, a step function H whose output Y is a constant value when the input is above a threshold and is zero (or a different constant value) when the input is below the same threshold.

[0018] Figure 2 200. The convolution operation within a single layer of a convolutional neural network (CNN) 200 is shown. In this example, there are multiple filters "M" 2021, 2022, and 202 N And multiple input channels. A single filter across “C” input feature maps 2041, 2042 and 204 in different channels N Convolution is performed to produce “M” output feature maps 2061, 2062, and 206 corresponding to a single filter N Therefore, there are multiple output feature maps, each corresponding to a separate filter. Figure 2 In the illustration, it is assumed that the filter size is 2x2 and the input feature map size is 6x6. Therefore, for Figure 2 As shown in the specific diagram, the total number of operations is 2x2xCx(5x5)xM.

[0019] Figure 3 An architecture 300 is illustrated that shows how such operations can be implemented using an NVM crossbar structure 302. Figure 2 Reference numerals are repeated to identify identical components.

[0020] In the crossbar structure 302, the weights of the convolutional filters are programmed as individual bit cells W 0 11 、W 0 12 、W 0 21 、W 0 22 (As shown in 3021). Due to the wide separation between the low resistance state (LRS) and the high resistance state (HRS), it is useful to encode multiple linearly separated resistance levels within a single bit cell. For example, in the case of CeRAM, the ratio of HRS / LRS is at least 2 orders of magnitude. Therefore, encoding 4 bits (or 16 levels) of resistance is possible. The digital-to-analog converter (DAC) 302 is then used to convert the input characteristic map 3061... N The digital word is converted into an analog voltage, which is then applied across the NVM cell. The resulting current is therefore proportional to the dot product of the input word and the weight. These individual currents are then summed in parallel on the bit line. Once the summed current signal is generated on the bit line, it can be digitized again using an analog-to-digital converter (ADC), and a bias addition, scaling, and activation function 320 can be applied to the resulting digital word to obtain an output activation.

[0021] exist Figure 3 In

[15] , the mapping of a CNN to an NVM crossbar structure using M filters and C input channels is illustrated. In the prior art, the weights ω are assumed to be static, i.e., they are programmed into the crossbar structure once and generally do not change during the inference operation. Typical NVM elements (e.g., phase change memory and resistive RAM) have a limited write "endurance"—i.e., a limited number of times these NVM elements can be written (e.g., approximately 10 8 times), after which the crossbar structure may exhibit functional failure. Other NVM elements such as magnetic RAM and CeRAM show promise for relatively high endurance (nearly 10 12 ), but continuous operation still results in a limited lifespan. Therefore, such lifespan limitations place significant constraints on accelerator architectures that rely on updating weights with each inference cycle. For example, for an Internet of Things (IoT) accelerator operating at 100 MHz, a 10 8 The durability of the accelerator has a lifespan of 1 second and has a 12The accelerator has an endurance of 10,000 seconds or 4 days (worst-case, peak usage). Therefore, such weights cannot be streamed from external DRAM and must be fixed on-chip. In addition, to perform the update operation, the NVM bit cells may be subject to high write power and the resulting expensive power consumption. Therefore, the write phase can be problematic and take a long time to complete.

[0022] Such an arrangement differs from SRAM behavior (which has significantly higher write endurance) and is not suitable for reprogramming weights during inference. Therefore, the entire network is unfolded into an on-chip crossbar structure and is fixed during inference. While this has the advantage of eliminating DRAM power consumption, it may undesirably limit the maximum size of the network that can be programmed on-chip. In addition, this also typically incurs an area penalty because mapping larger networks involves instantiating a crossbar structure with a capacity of megabits. This consumes higher area and makes the chip more prone to failure due to yield losses. In addition, instantiating multiple crossbar structures involves instantiating multiple ADCs / DACs, all of which need to be programmed, trimmed, and drift compensated.

[0023] A method and architecture for performing multiply-accumulate computations in a neural network are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Additional control circuitry is provided that adjusts the equivalent conductance of individual networks in the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first selection of weights within the neural network are mapped to the equivalent conductances of the networks in the tiled columns to enable computation of multiplication and accumulation operations using mixed-signal computation. Control logic updates the mappings to select a second selection of weights to compute additional multiplication and accumulation operations, and then repeats the mappings and computation operations until the desired computation for the neural network is complete. In some embodiments, the neural network is of a size that can be fully mapped to the plurality of networks of non-volatile memory elements.

[0024] According to another embodiment, the multiply-accumulate architecture includes a plurality of transistors and resistors operable to select the plurality of weights as binary weights represented by conductances.

[0025] According to yet another embodiment, the non-volatile memory resistor is operable to specifically perform calculations.

[0026] According to another embodiment, the multiply-accumulate is implemented in the analog mixed-mode domain.

[0027] According to one embodiment, the external random access memory is provided off-chip, and the plurality of weights are streamed from the external random access memory.

[0028] According to another embodiment, the external random access memory is one of a dynamic random access memory and a pseudo-static random access memory.

[0029] According to another embodiment, an analog-to-digital converter operable to multiplex the outputs of corresponding tile columns is provided.

[0030] According to yet another embodiment, the neurons are composed of a plurality of tiled columns.

[0031] According to yet another embodiment, an associative electronic random access memory operable to perform multiply-accumulate operations is provided.

[0032] According to another embodiment, a method for multiply-accumulate operations in a network is provided. The method includes, in a plurality of networks of non-volatile memory elements arranged in tiled columns: digitally adjusting equivalent conductances of individual networks in the plurality of networks to map the equivalent conductances of each individual network to individual weights within a neural network, a first portion of a selected set of weights within the neural network being mapped to the equivalent conductances of the networks in the tiled columns to enable computation of multiplication and accumulation operations by mixed-signal computation; updating the mappings to select a second portion of a selected set of weights to compute additional multiplication and accumulation operations; and repeating the mappings and computation operations until all computations for the neural network are complete.

[0033] The present disclosure provides a solution for energy-efficient acceleration of analog computations. Specifically, it combines the fundamental separation between computational operations and storage operations in NVM. According to embodiments of the present disclosure, an NVM crossbar structure is used for computational operations. Therefore, instead of instantiating explicit MACs and accumulators, analog domain multiplication and accumulation are provided according to embodiments of the present disclosure. Since traditionally fixed weights cannot be switched using digital logic, these weights can now be exchanged at high frequencies (as fast as the frequency at which transistors can switch) independently of explicit reprogramming.

[0034] The weight encoding is performed in the digital domain, which increases the robustness to variations. Figure 4, depicts a representation of a schematic circuit 400 illustrating weights digitally encoded using conductance. The circuit 400 is shown as a schematic diagram and includes a plurality of resistors R1442, R2446, R3450, R4454 and transistors represented by T1440, T2444, T3448, and T4452. The circuit 400 is merely illustrative and may be configured with any suitable combination of resistors and transistors according to embodiments of the present disclosure. Each equivalent weight is formed using an equivalent network of conductances. In Figure 4 In the specific example shown, a parallel network of NVM elements is shown, where each element has a conductance "G." Thus, a 4-bit digital bus can be switched between 1G, 2G, 3G, and 4G conductances, thereby achieving a 2-bit weight. Similarly, 8 resistors can achieve a 3-bit weight, and 16 resistors can achieve a 4-bit weight.

[0035] Alternatively, the conductance itself can be programmed to be binary weighted. In one scheme of weight coding, the generated on-LRS resistance for CeRAM can operate independently of reprogramming. According to an embodiment of the present disclosure, the computation phase and the storage phase are separated into different categories. NVM resistance can be used for computational purposes. The weight memory is streamed from an external storage location such as DRAM or PSRAM. The MAC operation is thus implemented in a compact manner by utilizing CeRAM / NVM elements with their own selector means and independent of explicit multipliers. Each circuit 400 corresponds to a separate network within the neural network, such as Figure 5 As further illustrated in

[0015] As described in co-pending U.S. patent application Ser. No. 15 / 884,612, assigned to the assignee of the present application, the disclosure of which is incorporated herein by reference, NVM / CeRAM elements are a specific type of random access memory formed (completely or partially) from correlated electron material (CEM). CeRAM can exhibit abrupt conductive or insulating state transitions caused by electron correlation rather than solid-state structural phase changes (e.g., such as caused by filament formation and conduction in resistive RAM devices). In contrast to melting / solidification or filament formation, the abrupt conductor / insulator transition in CeRAM can be in response to quantum mechanical phenomena.

[0036] The quantum mechanical transition between insulating and conducting states in CeRAM can be understood in terms of the Mott transition. In a Mott transition, a material can switch from an insulating state to a conducting state if the Mott transition conditions are met. When a critical carrier concentration is achieved such that the Mott criterion is met, a Mott transition occurs, and the state changes from high resistance / impedance (or capacitance) to low resistance / impedance (or capacitance).

[0037] The "state" or "memory state" of a CeRAM element may depend on the impedance state or the conductive state of the CeRAM element. In this context, "state" or "memory state" means a detectable state of a memory device that indicates a value, symbol, parameter, or condition (to provide just a few examples). In a particular implementation, the memory state of a memory device may be detected based at least in part on signals detected at terminals of the memory device during a read operation. In another implementation, a memory device may be in a particular memory state to represent or store a particular value, symbol, or parameter by applying one or more signals across terminals of the memory device during a "write operation."

[0038] A CeRAM element may include a material sandwiched between conductive terminals. The material can be switched between the aforementioned conductive and insulating states by applying a specific voltage and current across the terminals. The material of the CeRAM element sandwiched between the conductive terminals can be placed in an insulating state by applying a first programming signal across the terminals having a reset voltage and a reset current at a reset current density, or can be placed in a conductive state by applying a second programming signal across the terminals having a set voltage and a set current at a set current density.

[0039] Now refer to Figure 5 , illustrates an architecture 500 of a MAC engine according to an embodiment of the present disclosure, wherein MAC calculations are specifically performed in the analog mixed-mode domain and other operations are implemented in the digital domain. The architecture 500 includes a plurality of networks 5011, 5012, 5013, 501 N , the plurality of networks are part of a network 503, which resides on Figure 1A and Figure 1B The entire neural network 100 shown in FIG5 is 5011, 5012 ..., 501 N The number of tiles 5021 and 5022 is illustrative. In this embodiment, a crossbar architecture is not employed. Instead, each neuron as depicted in the illustrative embodiment is divided into a plurality of tile columns 5021 and 5022. Again, while two tile columns 5021 and 5022 are shown for illustrative purposes, the number of tile columns may be any suitable number. By inputting DACIN0 (5201) ... DACIN_N (520 n ) is coupled to each column digital weight control logic block 5041 and 504 N These configure the corresponding weights in the multiple mixed mode MAC engines forming each network, the multiple mixed mode MAC engines being represented by blocks 5061, 5062, 5063 and 5064, each corresponding to Figure 4The circuit 400 is shown in FIG. 4. The MAC operation is performed using known analog / mixed signal (MX) methods and the result is digitized on the ADC and an output activation is generated at the quantization and bias block 508. A single ADC can further be used to multiplex between various neurons. Each column of the architecture 500 operates as an accumulator and each selected CeRAM equivalent bit cell can operate as a MAC engine. According to an embodiment of the present disclosure, the architecture digitally regulates individual networks 5011, 5012, 5013, 5014, 5015, 5016, 5017, 5018, 5019, 5020, 5021, 5022, 5023, 5024, 5025, 5026, 5027, 5028, 5029, 5030, 5031, 5032, 5033, 5034, 5035, 5036, 5037, 5038, 5039, 5040, 5041, 5042, 5043, 5044, 5045, 5046, 5047, 5048, 5049, 5050, 5051, 5052, 5053, 5054, 5055 N The equivalent conductance of each individual network is mapped to a single weight W within the neural network 100, as Figure 1A and Figure 1B As shown, the weights of the first selection within the neural network 300 are mapped to the networks 5011, 5012, 5013, 501 in the tile columns 5021 and 5022. N The equivalent conductance of is obtained to enable the multiplication and accumulation operations to be calculated by mixed-signal computation. The mapping is updated to select weights of a second portion of the selected set to calculate additional multiplication and accumulation operations, and the mapping and calculation operations are repeated until all desired computations for the neural network are completed.

[0040] In a variation of the above embodiment, a compact programmable MAC engine can also be provided in combination with a smaller fully fixed equivalent, where the fully fixed equivalent is configured to filter out DRAM traffic and operate as a conventional analog MAC engine. This is suitable for most networks because they are no longer limited by on-chip NVM capacity. The fully programmable analog MAC engine can also be turned on or enabled in the case of larger neural networks.

[0041] In summary, the present disclosure advantageously provides the following functionality:

[0042] Instead of mapping all weights to a crossbar structure, weights are streamed from external DRAM, and the crossbar structure is used to perform low-precision MAC calculations with very high efficiency. Thus, embodiments of the present disclosure separate the "compute in storage" approach into compute-only operations. It has been discovered that by using resistors only for computation, improved energy efficiency is achieved.

[0043] NVM elements can only operate as resistors, and non-volatility is not required. Therefore, embodiments according to the present disclosure can use polysilicon resistors, plastic electronic devices (without PMOS), and pull-up resistors.

[0044] The scheme disclosed herein uses selector transistors to access specific weight values. This enables digital weight reprogramming independent of explicit reprogramming of the NVM elements themselves, significantly reducing area requirements. By enabling analog circuit reuse, it involves instantiating only a small number of ADCs / DACs, reducing the engineering complexity of the design.

[0045] The disclosed reuse scheme enables designs to scale to essentially any net size, reducing the limitations on the maximum size of nets that can be addressed by analog mixed-signal methods.

[0046] Finally, the approach can be extended to crossbar structures based on magnetoresistive random access memory (MRAM).

[0047] Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the system. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0048] Embodiments of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0049] Some portions of the detailed description, such as the procedures, may be presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. An algorithm may generally be considered to be a set of steps leading to a desired result. These steps are those requiring physical transformations or manipulations of physical quantities. Although not necessarily, these quantities typically take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Primarily for reasons of common usage, it has proven convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0050] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise expressly indicated by the following discussion, it should be understood that throughout this specification, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "deriving" or "displaying" refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage, transmission, or display devices.

[0051] The operations described herein may be performed by a device. The device may be specially constructed for the desired purpose, or the device may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions. As used herein, a computer-readable storage medium should not be interpreted as being a transient signal in itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse transmitted through a fiber optic cable), or an electrical signal transmitted by a wire.

[0052] Accordingly, embodiments and features of the present disclosure are listed in the following numbered items:

[0053] 1. A method for performing multiply-accumulate operations in a neural network, comprising: in a plurality of networks of non-volatile memory elements arranged in tiled columns: digitally adjusting equivalent conductances of individual networks in the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network, a first selected set of weights within the neural network being mapped to the equivalent conductances of the networks in the tiled columns to enable computation of multiplication and accumulation operations by mixed-signal computation; updating the mappings to select a second selected set of weights to compute additional multiplication and accumulation operations; and repeating the mapping and the computation operations until computation for the neural network is complete.

[0054] 2. The method of item 1, wherein the selection of weights is a binary weight expressed in conductance.

[0055] 3. The method according to item 1 further includes: performing the multiplication and accumulation calculations in the neural network using the non-volatile memory elements, and storing the weights externally in the non-volatile memory elements.

[0056] 4. The method of clause 3, wherein the non-volatile memory resistor is operable to specifically perform the multiplication and accumulation calculations.

[0057] 5. The method according to item 1 further includes: implementing the multiplication and accumulation calculation in an analog mixed mode domain.

[0058] 6. The method of item 1, further comprising: streaming the weights from an external memory.

[0059] 7. The method according to item 6, wherein the external memory is one of a dynamic random access memory and a pseudo-static random access memory.

[0060] 8. The method of item 1, further comprising: multiplexing the outputs of the respective tile columns via an analog-to-digital converter.

[0061] 9. The method according to item 1, wherein the neurons are composed of a plurality of tiled columns.

[0062] 10. The method of claim 1, wherein the multiply-accumulate operation is performed using associative electronic random access memory (CeRAM).

[0063] 11. An architecture for performing multiply-accumulate computations in a neural network, comprising: a plurality of networks of non-volatile memory elements arranged in tiled columns; logic that digitally adjusts equivalent conductances of individual ones of the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network, a first selection of weights within the neural network being mapped to the equivalent conductances of the networks in the tiled columns to enable computation of multiplication and accumulation operations via mixed-signal computation; and logic that updates the mappings to select a second selection of weights to compute additional multiplication and accumulation operations, and repeating the mappings and computation operations until computation for the neural network is complete.

[0064] 12. The architecture of item 11, further comprising: a plurality of transistors and resistors operable to select a plurality of weights as binary weights represented by conductance.

[0065] 13. The architecture of item 11, wherein the weights are stored externally to the non-volatile memory elements.

[0066] 14. The architecture of item 13, wherein the non-volatile memory resistor is operable to specifically perform computations.

[0067] 15. The architecture of claim 11, wherein the multiply-accumulate is implemented in the analog mixed-mode domain.

[0068] 16. The architecture according to item 11 further includes: an external memory, which is set outside the chip, and the plurality of weights are accessed from the external memory.

[0069] 17. The architecture of item 16, wherein the external memory is one of a dynamic random access memory and a pseudo-static random access memory.

[0070] 18. The architecture of clause 11, further comprising an analog-to-digital converter operable to multiplex the outputs of the respective columns.

[0071] 19. The architecture of item 11, wherein the neurons are composed of a plurality of tiled columns.

[0072] 20. The architecture of item 11 further comprising: an associated electronic random access memory (CeRAM) operable to perform the multiply-accumulate operation.

[0073] 21. The architecture of claim 11, wherein the neural network has a size that fully maps to the plurality of networks of the non-volatile memory element.

[0074] In accordance with the foregoing, a method and architecture for multiply-accumulate operations in a network are disclosed. Having thus described the disclosure of the present application in detail and with reference to embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope as defined in the appended claims below:

Claims

1. A method for performing a multiplication-accumulation operation in a neural network, comprising: For an individual network of the plurality of networks of non-volatile memory elements arranged in one or more tiled columns, the individual network comprising a plurality of selectable parallel elements and each parallel element having a predetermined conductance value: digitally reprogramming the equivalent conductance of the separate network, the digitally reprogramming comprising selecting one or more parallel elements of the separate network to map the equivalent conductance of the separate network to a single weight of a first partial selection of weights within the neural network; performing mixed-signal computations using the one or more tiled columns to compute a multiply and accumulate operation by applying an analog voltage on each net to produce a first resultant current in each tiled column; and The reprogramming and the computing operations are repeated until the computing for the neural network is completed.

2. The method according to claim 1, wherein The weights of the selections are binary weights expressed in conductance.

3. The method according to claim 1, further comprising: The multiplication and accumulation calculations are performed in the neural network using the separate network, and the weights are stored outside the separate network.

4. The method according to claim 3, wherein: Individual networks in a tile column are operable to specifically perform the multiply and accumulate calculations.

5. The method according to claim 1, wherein One or more parallel elements of a network include a resistor and a select transistor, wherein selecting a parallel element of the one or more parallel elements of the separate network includes selecting the plurality of weights using the select transistor and the resistor.

6. The method according to claim 1, further comprising: The weights are streamed from external memory.

7. The method according to claim 6, wherein: The external memory is one of a dynamic random access memory and a pseudo-static random access memory.

8. The method according to claim 1, further comprising: The outputs of the corresponding tile columns are multiplexed through analog-to-digital converters.

9. The method according to claim 1, wherein: The neurons of the neural network are composed of a plurality of tiled columns.

10. The method according to claim 1, wherein The plurality of optional parallel elements of the individual networks include associative electronic random access memory (CeRAM).

11. The method according to claim 1, wherein A nonvolatile memory element of the nonvolatile memory elements is capable of operating as a resistor.

12. An architecture for performing multiply-accumulate computations in a neural network, comprising: a plurality of networks of nonvolatile memory elements arranged in tiled columns, each network comprising a plurality of selectable parallel elements and each parallel element having a predetermined conductance value; logic configured to digitally program the equivalent conductance of individual networks of the plurality of networks, wherein: The digitally programming includes: for each individual network, selecting one or more parallel elements of the individual network to map the equivalent conductance of the individual network to a single weight of a first partial selection of weights of the neural network; The digitally programming enables computation of multiplication and accumulation operations via mixed-signal computations when voltage bias is applied to networks in the first or more tiled columns; and wherein the architecture is configured to compute multiplication and accumulation operations for a plurality of selected sets of programmed partial weights until computations for the neural network are complete.

13. The architecture of claim 12, wherein: The plurality of selectable parallel elements in the network include a plurality of transistors and resistors, wherein the plurality of transistors and resistors are operable to select a plurality of weights as binary weights represented by conductance.

14. The architecture of claim 12, wherein: The optional parallel element comprises a non-volatile memory element, and wherein the weights of the neural network are stored externally to the non-volatile memory element.

15. The architecture of claim 14, wherein: Individual networks in a tile column can operate to specifically perform multiply and accumulate calculations.

16. The architecture of claim 12, further comprising: An external memory is provided outside the chip, wherein the plurality of weights are accessed from the external memory.

17. The architecture of claim 16, wherein: The external memory is one of a dynamic random access memory and a pseudo-static random access memory.

18. The architecture of claim 12, further comprising: An analog-to-digital converter is operable to multiplex outputs of the corresponding tile columns.

19. The architecture of claim 12, wherein: Neurons of the neural network are composed of tile columns of the one or more tile columns.

20. The architecture of claim 12, the selectable parallel element comprising an associative electronic random access memory (CeRAM), the CeRAM operable to perform the multiply-accumulate operation.

21. The architecture of claim 12, wherein: The neural network has a size that fully maps to the plurality of networks.

22. The architecture of claim 12, wherein: A nonvolatile memory element of the nonvolatile memory elements is capable of operating as a resistor.

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