Silicon carbide substrate and method for manufacturing silicon carbide substrate

Abstract

The silicon carbide substrate is a silicon carbide substrate having a circular first main surface provided with an orientation plane and a second main surface opposite to the first main surface. The first main surface has the center of a circle when the shape of the first main surface before the orientation plane is provided is set as a circle. The first main surface has first two ends in a first radial direction, and the first two ends in the first radial direction are two intersection points of the first imaginary straight line and the periphery of the first main surface when a first imaginary straight line extending in the first radial direction through the center of the circle is assumed to be provided in the first radial direction of the first main surface. The first main surface has second two ends in a second radial direction, and the second two ends in the second radial direction are two intersection points of the second imaginary straight line and the periphery of the first main surface when a second imaginary straight line extending in the second radial direction through the center of the circle is assumed to be provided in a second radial direction orthogonal to the first radial direction of the first main surface. The first main surface has a central area obtained by excluding a first area and a second area, the first area being an area within 5 mm from each of the first two ends in the first radial direction to the inside of the first main surface, and the second area being an area within 5 mm from each of the second two ends in the second radial direction to the inside of the first main surface. When the central area of ​​the first main surface is divided into a plurality of square areas so that the square area having the largest side length of 5 mm completely constitutes a square, the average LTV value of the plurality of first square areas is less than 0.75 μm, and the plurality of first square areas are arranged in a ring shape in a manner so as to be located at the outermost side relative to the center of the circle and constitute the outermost periphery.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide substrate and a method for manufacturing a silicon carbide substrate. This application claims priority based on Japanese patent application No. 2019-110318 filed on June 13, 2019. All the contents described in the Japanese patent application are cited in this specification by reference. Background Art

[0002] Japanese Patent Application Laid-Open No. 2016-139685 (Patent Document 1) discloses a method for manufacturing a single-crystal silicon carbide substrate, including a step of chemically mechanically polishing a main surface of a single-crystal silicon carbide substrate that has been mechanically polished.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-139685 Summary of the invention

[0006] The silicon carbide substrate involved in the present disclosure is a silicon carbide substrate having a circular first main surface provided with an orientation flat and a second main surface opposite to the first main surface. The first main surface has the center of a circle when the shape of the first main surface before the orientation flat is provided is set as a circle. The first main surface has two first ends in a first radial direction, and the first two ends in the first radial direction are two intersection points of the first imaginary straight line and the periphery of the first main surface when a first imaginary straight line extending in the first radial direction through the center of the circle is assumed to be provided in the first radial direction of the first main surface. The first main surface has two second ends in a second radial direction, and the second two ends in the second radial direction are two intersection points of the second imaginary straight line and the periphery of the first main surface when a second imaginary straight line extending in the second radial direction through the center of the circle is assumed to be provided in the second radial direction orthogonal to the first radial direction of the first main surface. The first main surface has a central area obtained by excluding a first area and a second area, the first area being an area within 5 mm from each of the first two ends in the first radial direction to the inside of the first main surface, and the second area being an area within 5 mm from each of the second two ends in the second radial direction to the inside of the first main surface. When the central area of ​​the first main surface is divided into a plurality of square areas so that the square area having the largest side length of 5 mm completely constitutes a square, the average LTV value of the plurality of first square areas is less than 0.75 μm, and the plurality of first square areas are arranged in a ring shape in a manner so as to be located at the outermost side relative to the center of the circle and constitute the outermost periphery.

[0007] The method for manufacturing a silicon carbide substrate according to the present disclosure includes: a step of slicing an ingot made of a silicon carbide single crystal to form a silicon carbide single crystal wafer; a step of chamfering the silicon carbide single crystal wafer by cutting the corner of the silicon carbide single crystal wafer; a step of roughly polishing both main surfaces of the chamfered silicon carbide single crystal wafer; a step of chemically mechanically polishing the first two main surfaces of the roughly polished silicon carbide single crystal wafer at least once using a polishing cloth and a polishing liquid; and a step of chemically mechanically polishing the second two main surfaces of the silicon carbide single crystal wafer after the chemical mechanical polishing of the first two main surfaces using a polishing cloth and a polishing liquid different from those used in the step of chemical mechanical polishing of the first two main surfaces. In at least one of the step of chemical mechanical polishing the first two main surfaces and the step of chemical mechanical polishing the second two main surfaces, the effective surface area ratio A of the polishing cloth used for polishing the Si surface of the silicon carbide single crystal wafer is si The effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer c The following equations (6) to (8) are satisfied. In at least one of the first step of chemical mechanical polishing both main surfaces and the second step of chemical mechanical polishing both main surfaces, the polishing rate R of the Si surface of the silicon carbide single crystal wafer is si The polishing rate R of the C surface of the silicon carbide single crystal wafer c The ratio (R si / R c ) is greater than or equal to 0.6 and less than or equal to 1.4.

[0008] A si ≥80 and A c ≥80…Formula (6)

[0009] A si >90 and A c <90…Formula (7)

[0010] 1<(A si / A c )<1.25…Formula (8) BRIEF DESCRIPTION OF THE DRAWINGS

[0011] [ Figure 1 ] Figure 1 This is a schematic top view of the silicon carbide substrate according to the first embodiment.

[0012] [ Figure 2 ] Figure 2 For along Figure 1 II-II is a schematic enlarged view of the cross section obtained.

[0013] [ Figure 3 ] Figure 3 This is a schematic top view of a silicon carbide substrate according to the second embodiment.

[0014] [ Figure 4 ] Figure 4 For along Figure 3 A schematic enlarged view of the cross section obtained from IV-IV.

[0015] [ Figure 5 ] Figure 5 This is a schematic top view of a silicon carbide substrate according to Embodiment 3.

[0016] [ Figure 6 ] Figure 6 For along Figure 5 VI-VI is a schematic enlarged view of the cross section obtained.

[0017] [ Figure 7 ] Figure 7 This is a schematic top view of a silicon carbide substrate according to a fourth embodiment.

[0018] [ Figure 8 ] Figure 8 For along Figure 7 A schematic enlarged view of the cross section obtained from VIII-VIII.

[0019] [ Fig. 9 ] Fig. 9 This is a flowchart of a method for manufacturing a silicon carbide substrate according to the fifth embodiment.

[0020] [ Fig.10 ] Fig.10 This is a schematic plan view of the entire surface of an example of a polishing cloth used in the first and second main surface chemical mechanical polishing steps.

[0021] [ Fig.11 ] Fig.11 This is a flowchart of a method for manufacturing a silicon carbide substrate according to a sixth embodiment.

[0022] [ Fig.12 ] Fig.12 Graphs showing calculation results of average values ​​of LTVs of the first square region, the second square region, the third square region, the fourth square region, and the fifth square region of the silicon carbide substrates of Experimental Examples 1 to 3. FIG. DETAILED DESCRIPTION

[0023] [Problems to be Solved by the Present Disclosure]

[0024] An object of the present disclosure is to provide a silicon carbide substrate having improved flatness of the substrate periphery.

[0025] [Effects of the Present Disclosure]

[0026] According to the present disclosure, it is possible to provide a silicon carbide substrate having improved flatness of the substrate periphery.

[0027] [Description of Embodiments of the Present Disclosure]

[0028] First, embodiments of the present disclosure will be described by way of examples.

[0029] (1) A silicon carbide substrate according to the present disclosure comprises a circular first main surface provided with an orientation flat and a second main surface opposite to the first main surface, wherein the first main surface has the center of the circle when the shape of the first main surface before the orientation flat is provided is set to a circle, the first main surface has two first end portions in a first radial direction, the first two first end portions in the first radial direction being two intersection points of the first imaginary straight line and the periphery of the first main surface when a first imaginary straight line passing through the center of the circle and extending in the first radial direction is assumed to be provided in the first radial direction of the first main surface, and the first main surface has two second end portions in a second radial direction, the second two end portions in the second radial direction being two intersection points of the second imaginary straight line passing through the center of the circle and extending in the second radial direction when a second imaginary straight line passing through the center of the circle and extending in the second radial direction is assumed to be provided in a second radial direction orthogonal to the first radial direction of the first main surface. When the second imaginary straight line is formed, the two intersection points of the second imaginary straight line and the periphery of the first main surface are formed, the first main surface has a central area obtained by excluding the first area and the second area, the first area is an area within 5 mm from each of the first two ends in the first radial direction to the inside of the first main surface, the second area is an area within 5 mm from each of the second two ends in the second radial direction to the inside of the first main surface, when the central area of ​​the first main surface is divided into a plurality of square areas so that the square areas with the largest number of sides having a length of 5 mm completely constitute a square, the average value of the LTV of the plurality of first square areas is 0.75 μm or less, and the plurality of first square areas are the plurality of square areas arranged in a ring shape so as to be located at the outermost side relative to the center of the circle and constitute the outermost periphery. By having the average value of the LTV of the plurality of first square areas be 0.75 μm or less, a silicon carbide substrate having improved flatness of the substrate periphery can be provided.

[0030] (2) In the silicon carbide substrate of (1), an average value of the LTV of the plurality of first square regions may be greater than or equal to 0.1 μm. When the average value of the LTV of the plurality of first square regions is greater than or equal to 0.1 μm, the flatness of the silicon carbide substrate periphery can be improved.

[0031] (3) The average value of LTV of the plurality of second square regions among the plurality of square regions may be 0.4 μm or less, and the plurality of second square regions are arranged adjacent to the first square regions on the inner side of the first radial direction or the inner side of the second radial direction of the plurality of first square regions, and are arranged in a ring shape so as to constitute the inner circumference of a ring constituted by the plurality of first square regions. When the average value of LTV of the plurality of second square regions is 0.4 μm or less, the flatness of the periphery of the silicon carbide substrate tends to be improved.

[0032] (4) In the silicon carbide substrate of (3), the average value of the LTV of the plurality of second square regions may be greater than or equal to 0.1 μm. When the average value of the LTV of the plurality of second square regions is greater than or equal to 0.1 μm, the flatness of the silicon carbide substrate periphery can be improved.

[0033] (5) The average value of LTV of the plurality of third square regions among the plurality of square regions may be 0.3 μm or less, and the plurality of third square regions are arranged adjacent to the second square regions on the inside of the first radial direction or the inside of the second radial direction of the plurality of second square regions, and are arranged in a ring shape so as to constitute the inner circumference of a ring formed by the plurality of second square regions. When the average value of LTV of the plurality of third square regions is 0.3 μm or less, the flatness of the periphery of the silicon carbide substrate tends to be improved.

[0034] (6) In the silicon carbide substrate of (5), the average value of the LTV of the plurality of third square regions may be greater than or equal to 0.1 μm. When the average value of the LTV of the plurality of third square regions is greater than or equal to 0.1 μm, the flatness of the silicon carbide substrate periphery can be improved.

[0035] (7) The average value of LTV of the plurality of fourth square regions among the plurality of square regions may be 0.25 μm or less, and the plurality of fourth square regions are arranged adjacent to the third square regions on the inner side of the first radial direction or the inner side of the second radial direction of the plurality of third square regions, and are arranged in a ring shape so as to constitute the inner circumference of a ring formed by the plurality of third square regions. When the average value of LTV of the plurality of fourth square regions is 0.25 μm or less, the flatness of the periphery of the silicon carbide substrate tends to be improved.

[0036] (8) In the silicon carbide substrate of (7), the average value of the LTV of the plurality of fourth square regions may be greater than or equal to 0.1 μm. When the average value of the LTV of the plurality of fourth square regions is greater than or equal to 0.1 μm, the flatness of the silicon carbide substrate periphery can be improved.

[0037] (9) The method for manufacturing a silicon carbide substrate according to the present disclosure comprises: a step of slicing an ingot composed of a silicon carbide single crystal to form a silicon carbide single crystal wafer; a step of chamfering the silicon carbide single crystal wafer by cutting the corners of the silicon carbide single crystal wafer; a step of roughly grinding both main surfaces of the chamfered silicon carbide single crystal wafer; a step of chemically mechanically polishing the first two main surfaces of the silicon carbide single crystal wafer at least once using a polishing cloth and a polishing liquid; and a step of chemically mechanically polishing the second two main surfaces of the silicon carbide single crystal wafer after the chemical mechanical polishing of the first two main surfaces using a polishing cloth and a polishing liquid different from those used in the step of chemically mechanical polishing the first two main surfaces, wherein in at least one of the step of chemically mechanical polishing the first two main surfaces and the step of chemically mechanical polishing the second two main surfaces, the effective surface area ratio A of the polishing cloth used for grinding the Si surface of the silicon carbide single crystal wafer is si The effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer is c The following formulas (6) to (8) are satisfied, and in at least one of the steps of chemically mechanically polishing the first two main surfaces and chemically mechanically polishing the second two main surfaces, the polishing rate R of the Si surface of the silicon carbide single crystal wafer is si The polishing rate R of the C surface of the silicon carbide single crystal wafer is c The ratio (R si / R c ) is 0.6 or more and 1.4 or less. The method for manufacturing a silicon carbide substrate according to the present disclosure can manufacture a silicon carbide substrate having improved flatness of the substrate periphery.

[0038] A si ≥80 and A c ≥80…Formula (6)

[0039] A si >90 and A c <90…Formula (7)

[0040] 1<(A si / A c )<1.25…Formula (8)

[0041] [Details of embodiments of the present disclosure]

[0042] Hereinafter, the details of the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0043] <Implementation method 1>

[0044] Figure 1 1 is a schematic top view of a silicon carbide substrate 10 according to Embodiment 1. Figure 1 As shown in the schematic plan view of , silicon carbide substrate 10 according to Embodiment 1 has first main surface 11. Orientation flat 13 is provided on first main surface 11.

[0045] The first main surface 11 has two end portions 10a and 10b in the first radial direction 101. The two end portions 10a and 10b in the first radial direction 101 of the first main surface 11 are two intersection points of the first imaginary straight line 101a and the periphery of the first main surface 11 when a first imaginary straight line 101a extending in the first radial direction 101 is assumed to be provided on the first main surface 11.

[0046] The first imaginary straight line 101a is an imaginary straight line extending in the first radial direction 101 through the center 45a of the first main surface 11. The center 45a of the first main surface 11 refers to the center when the shape of the first main surface 11 is set to a circle (for example, when it is set to a circle before the orientation flat surface 13 is set). The first radial direction 101 can be set to any direction of the first main surface 11, for example.

[0047] The first main surface 11 has two end portions 10c and 10d in the second radial direction 102. The two end portions 10c and 10d in the second radial direction 102 of the first main surface 11 are two intersection points of the second imaginary straight line 102a and the periphery of the first main surface 11 when a second imaginary straight line 102a extending in the second radial direction 102 is assumed to be provided on the first main surface 11.

[0048] The second imaginary straight line 102 a is an imaginary straight line that passes through the center 45 a of the first major surface 11 and extends in the second radial direction 101 . The second radial direction 102 is a direction orthogonal to the first radial direction 101 .

[0049] The first main surface 11 has first regions 51a and 51b within 5 mm from both ends 10a and 10b in the first radial direction 101 of the first main surface 11. The first main surface 11 has second regions 51c and 51d within 5 mm from both ends 10c and 10d in the second radial direction 102 of the first main surface 11. The first main surface 11 has a central region 50, which is a region obtained by excluding the first regions 51a and 51b and the second regions 51c and 51d from the entire region of the first main surface 11.

[0050] For example Figure 1As shown, the central area 50 is divided into a plurality of square areas with a side length of 5 mm. The central area 50 is divided into a plurality of square areas so that the square area with the largest side length of 5 mm is obtained. As square areas, only areas that completely form a square are identified. Areas that do not completely form a square due to the lack of a part, etc. are not identified as square areas.

[0051] The outermost square region among the plurality of square regions obtained by dividing the central region 50 is defined as the first square region 41. The first square region 41 is a square region that forms a complete square among the plurality of square regions obtained by dividing the central region 50, and is the outermost square region located in the central region 50.

[0052] For example, in Figure 1 In the example shown, the region 410a is located outside the central region 50 (on the peripheral side of the first main surface 11) relative to the first square region 41 in the first radial direction 101. In addition, the region 410b is located outside the central region 50 relative to the first square region 41 in the second radial direction 102. Figure 1 As shown, the regions 410a and 410b do not completely form a square and are therefore not considered to be square regions.

[0053] Therefore, the first square area 41 is identified as the first square area 41 constituting the outermost periphery. The central area 50 includes a plurality of first square areas 41. Figure 1 As shown, the plurality of first square regions 41 are arranged in a ring shape so as to constitute the outermost periphery of the plurality of square regions of the central region 50 .

[0054] Figure 2 For along Figure 1 Schematic enlarged view of the cross section obtained in II-II. Figure 2 : The LTV (Local Thickness Variation) of the first square area 41 is shown. The LTV of the first square area 41 is a value obtained by subtracting the height T1 from the second main surface 12 to the lowest point 41a of the first main surface 11 from the height T2 of the first square area 41 from the second main surface 12 to the highest point 41b of the first main surface 11 when the entire second main surface 12 opposite to the first main surface 11 is adsorbed on a flat adsorption surface.

[0055] That is, the LTV of the first square area 41 is calculated according to the following formula (1).

[0056] LTV of the first square area 41 = |T2-T1| ... Formula (1)

[0057] LTV is an index that quantitatively represents the flatness of first main surface 11 of silicon carbide substrate 10. LTV can be measured by using, for example, "Tropel Flat Master (registered trademark)" manufactured by Corning Tropel.

[0058] The LTV is measured for each of the plurality of first square regions 41 at the outermost periphery of the plurality of square regions constituting the central region 50. Then, an average value of the LTV is calculated from the measured values ​​of the LTV of each of the plurality of first square regions 41. The average value of the LTV is regarded as the average value of the LTV of the plurality of first square regions 41 of the silicon carbide substrate 10 according to the first embodiment.

[0059] The average LTV of the plurality of first square regions 41 of the silicon carbide substrate 10 according to Embodiment 1 is 0.75 μm or less. This indicates that the flatness of the periphery of the silicon carbide substrate 10 according to Embodiment 1 is improved compared to conventional silicon carbide substrates. Thus, in the silicon carbide substrate 10 according to Embodiment 1, the device fabrication region can be expanded to a region closer to the periphery of the first main surface 11 of the silicon carbide substrate 10 than in conventional silicon carbide substrates, and therefore more devices can be fabricated from one silicon carbide substrate 10.

[0060] <Implementation method 2>

[0061] Figure 3 1 is a schematic plan view of a silicon carbide substrate 10 according to Embodiment 2. Silicon carbide substrate 10 according to Embodiment 2 is characterized in that an average value of LTV of second square regions 42 is 0.4 μm or less.

[0062] The second square region 42 is a square region that is arranged inside the first radial direction 101 or inside the second radial direction 102 of each of the first square regions 41 among the plurality of square regions obtained by dividing the central region 50 , and is located adjacent to the first square region 41 .

[0063] The plurality of square regions obtained by dividing the central region 50 includes a plurality of second square regions 42. Figure 3 As shown, the second square region 42 is arranged in a ring shape so as to constitute the inner circumference of the ring formed by the first square region 41 .

[0064] Figure 4 For along Figure 3 A schematic enlarged view of the cross section obtained from IV-IV. Figure 4: The LTV of the second square area 42 is shown in FIG. The LTV of the second square area 42 is a value obtained by subtracting a height T3 from the second main surface 12 to the lowest point 42a of the first main surface 11 from a height T4 of the second square area 42 from the second main surface 12 to the highest point 42b of the first main surface 11 when the entire second main surface 12 opposite to the first main surface 11 is adsorbed onto a flat adsorption surface.

[0065] That is, the LTV of the second square area 42 is calculated according to the following formula (2).

[0066] The LTV of the second square area 42 = |T4-T3| ... Formula (2)

[0067] The LTV is measured for each of the plurality of second square regions 42 arranged in a ring shape so as to constitute the inner circumference of the ring of the first square region 41. Then, the average value of the LTV is calculated from the measured values ​​of the LTV of each of the plurality of second square regions 42. The average value of the LTV is regarded as the average value of the LTV of the plurality of second square regions 42 of the silicon carbide substrate 10 according to the second embodiment.

[0068] The average value of LTV of the plurality of second square regions 42 of the silicon carbide substrate 10 according to Embodiment 2 is 0.4 μm or less. When the average value of LTV of the second square region 42 is 0.4 μm or less, the average value of LTV of the first square region 41 adjacent to the outside of the second square region 42 also tends to have a low value. This indicates that the flatness of the periphery of the silicon carbide substrate 10 according to Embodiment 2 is improved.

[0069] Therefore, in the silicon carbide substrate 10 involved in the second embodiment, the device manufacturing region can be expanded to a region closer to the periphery of the first main surface 11 of the silicon carbide substrate 10 compared to the conventional silicon carbide substrate, so more devices can be manufactured from one silicon carbide substrate 10.

[0070] The descriptions other than the above in Embodiment 2 are the same as those in Embodiment 1, and thus the descriptions thereof are omitted.

[0071] <Implementation method 3>

[0072] Figure 5 1 is a schematic plan view of silicon carbide substrate 10 according to Embodiment 3. Silicon carbide substrate 10 according to Embodiment 3 is characterized in that an average value of LTV of third square regions 43 is 0.3 μm or less.

[0073] The third square region 43 is a square region that is arranged inside the first radial direction 101 or inside the second radial direction 102 of each second square region 42 among the plurality of square regions obtained by dividing the central region 50 , and is located adjacent to the second square region 42 .

[0074] The plurality of square regions obtained by dividing the central region 50 includes a plurality of third square regions 43. Figure 5 As shown, the third square region 43 is arranged in a ring shape so as to constitute the inner circumference of the ring formed by the second square regions 42 .

[0075] Figure 6 For along Figure 5 VI-VI is a schematic enlarged view of the cross section obtained. Figure 6 : The LTV of the third square area 43 is shown in FIG. The LTV of the third square area 43 is a value obtained by subtracting a height T5 from the second main surface 12 to the lowest point 43a of the first main surface 11 from a height T6 of the third square area 43 from the second main surface 12 to the highest point 43b of the first main surface 11 when the entire second main surface 12 opposite to the first main surface 11 is adsorbed onto a flat adsorption surface.

[0076] That is, the LTV of the third square area 43 is calculated according to the following formula (3).

[0077] The LTV of the third square area 43 = |T6-T5| ... Formula (3)

[0078] The LTV is measured for each of the plurality of third square regions 43 arranged in a ring shape so as to constitute the inner circumference of the ring of the second square region 42. Then, the average value of the LTV is calculated from the measured values ​​of the LTV of each of the plurality of third square regions 43. The average value of the LTV is regarded as the average value of the LTV of the plurality of third square regions 43 of the silicon carbide substrate 10 according to the third embodiment.

[0079] The average value of LTV of the plurality of third square regions 43 of the silicon carbide substrate 10 according to Embodiment 3 is 0.3 μm or less. When the average value of LTV of the third square region 43 is 0.3 μm or less, the average value of LTV of the second square region 42 adjacent to the outside of the third square region 43 and the average value of LTV of the first square region 41 adjacent to the outside of the second square region 42 also tend to have low values. This indicates that the flatness of the periphery of the silicon carbide substrate 10 according to Embodiment 3 is improved.

[0080] Therefore, in the silicon carbide substrate 10 involved in the third embodiment, the device manufacturing region can be expanded to a region closer to the periphery of the first main surface 11 of the silicon carbide substrate 10 compared to the conventional silicon carbide substrate, so more devices can be manufactured from one silicon carbide substrate 10.

[0081] The descriptions other than those described above in Embodiment 3 are the same as those in Embodiments 1 and 2, and thus the descriptions thereof are omitted.

[0082] <Implementation method 4>

[0083] Figure 7 1 is a schematic plan view of a silicon carbide substrate 10 according to Embodiment 4. The silicon carbide substrate 10 according to Embodiment 4 is characterized in that an average value of LTV of the fourth square region 44 is 0.25 μm or less.

[0084] The fourth square region 44 is a square region that is arranged inside the first radial direction 101 or inside the second radial direction 102 of each third square region 43 among the plurality of square regions obtained by dividing the central region 50 , and is located adjacent to the third square region 43 .

[0085] The plurality of square regions obtained by dividing the central region 50 includes a plurality of fourth square regions 44. Figure 7 As shown, the fourth square region 44 is arranged in a ring shape so as to constitute the inner circumference of the ring formed by the third square regions 43 .

[0086] Figure 8 For along Figure 7 A schematic enlarged view of the cross section obtained from VIII-VIII. Figure 8 : The LTV of the fourth square area 44 is shown in FIG. The LTV of the fourth square area 44 is a value obtained by subtracting a height T7 from the second main surface 12 to the lowest point 44a of the first main surface 11 from a height T8 of the fourth square area 44 from the second main surface 12 to the highest point 44b of the first main surface 11 when the entire second main surface 12 opposite to the first main surface 11 is adsorbed onto a flat adsorption surface.

[0087] That is, the LTV of the fourth square area 44 is calculated according to the following formula (4).

[0088] The LTV of the fourth square area 44 = |T8-T7| ... Formula (4)

[0089] The LTV is measured for each of the plurality of fourth square regions 44 arranged in a ring shape so as to constitute the inner circumference of the ring of the third square region 43. Then, the average value of the LTV is calculated from the measured values ​​of the LTV of each of the plurality of fourth square regions 44. The average value of the LTV is regarded as the average value of the LTV of the plurality of fourth square regions 44 of the silicon carbide substrate 10 involved in the fourth embodiment.

[0090] The average value of LTV of the plurality of fourth square regions 44 of the silicon carbide substrate 10 according to the fourth embodiment is 0.25 μm or less. When the fourth square region 44 has high flatness, the average value of LTV of the third square region 43 adjacent to the outside of the fourth square region 44, the average value of LTV of the second square region 42 adjacent to the outside of the third square region 43, and the average value of LTV of the first square region 41 adjacent to the outside of the second square region 42 also tend to have low values. This indicates that the flatness of the periphery of the silicon carbide substrate 10 according to the third embodiment is improved.

[0091] Thus, in the silicon carbide substrate 10 involved in the fourth embodiment, the device manufacturing region can be expanded to a region closer to the periphery of the first main surface 11 of the silicon carbide substrate 10 compared to the conventional silicon carbide substrate, so that more devices can be manufactured from one silicon carbide substrate 10.

[0092] In addition, Figure 8 The LTV of the fifth square area 45 at the center 45a of the first main surface 11 is shown in FIG. The LTV of the fifth square area 45 is a value obtained by subtracting the height T9 of the lowest point 45c from the second main surface 12 to the first main surface 11 from the height T10 of the fifth square area 45 from the highest point 45b from the second main surface 12 to the first main surface 11 in a state where the entire second main surface 12 opposite to the first main surface 11 is adsorbed on a flat adsorption surface. For example, Figure 7 As shown, the fifth square region 45 is composed of squares with a side length of 5 mm. The intersection of the diagonal lines of the squares constituting the fifth square region 45 is the center 45a.

[0093] That is, the LTV of the fifth square area 45 is calculated according to the following formula (5).

[0094] LTV of the fifth square area 45 = |T10-T9| ... Formula (5)

[0095] The descriptions other than the above in the fourth embodiment are the same as those in the first to third embodiments, and thus the descriptions thereof are omitted.

[0096] In Embodiments 1 to 4, the average value of the LTV of at least one region selected from the group consisting of first square region 41, second square region 42, third square region 43, and fourth square region 44 can be set to 0.1 μm or more. In this case, the flatness of the peripheral edge of silicon carbide substrate 10 according to Embodiments 1 to 4 tends to be improved.

[0097] <Implementation method 5>

[0098] Fig. 9 This is a flowchart of a method for manufacturing a silicon carbide substrate according to the fifth embodiment.

[0099] like Fig. 9 As shown, in the method for manufacturing a silicon carbide substrate according to Embodiment 5, first, a slicing step S1 is performed. The slicing step S1 can be performed by slicing an ingot made of a silicon carbide single crystal manufactured by a sublimation method, for example, using a wire saw.

[0100] Next, a chamfering step S2 is performed. The chamfering step S2 can be performed, for example, by cutting the corners of the silicon carbide single crystal wafer obtained in the slicing step S1.

[0101] Next, a rough polishing step S3 is performed. The rough polishing step S3 can be performed, for example, by mechanically polishing both main surfaces of the silicon carbide single crystal wafer after the chamfering step S2. Examples of mechanical polishing include grinding and lapping.

[0102] Next, the first both main surface chemical mechanical polishing step S4 is performed. The first both main surface chemical mechanical polishing step S4 can be performed by subjecting both main surfaces of the silicon carbide single crystal wafer after the rough polishing step S3 to chemical mechanical polishing (CMP: Chemical Mechanical Polishing) under the conditions shown in Table 1 below.

[0103] The first two-main-surface chemical mechanical polishing step S4 is performed as follows. First, the polishing cloths listed in Table 1 are placed on the respective surfaces of the upper platen and the lower platen. Next, the silicon carbide single crystal wafer is sandwiched between the polishing cloth of the upper platen and the polishing cloth of the lower platen, and the surface pressure listed in Table 1 is applied to the silicon carbide single crystal wafer. Next, while the polishing liquid listed in Table 1 is supplied to the upper and lower main surfaces of the silicon carbide single crystal wafer, respectively, the upper platen and the lower platen are rotated in opposite directions at the platen speeds listed in Table 1. At this time, the silicon carbide single crystal wafer between the upper platen and the lower platen is also rotated via the carrier in the same direction as that of either the upper platen or the lower platen.

[0104] It should be noted that "upper: lower = 3:2" in the "relative speed ratio" column in Table 1 indicates that the relative speed ratio of the upper platen for grinding the silicon surface (Si surface) as the upper main surface of the silicon carbide single crystal wafer relative to the rotation speed of the silicon carbide single crystal wafer and the relative speed ratio of the lower platen for grinding the carbon surface (C surface) as the lower main surface of the silicon carbide single crystal wafer relative to the rotation speed of the silicon carbide single crystal wafer (relative speed of the upper platen: relative speed of the lower platen) is 3:2. For example, assuming that the upper platen rotates clockwise at a speed of 30 rpm, the silicon carbide single crystal wafer rotates counterclockwise at a speed of 6 rpm, and the lower platen rotates counterclockwise at a speed of 30 rpm. In this case, the relative speed of the upper platen relative to the rotation speed of the silicon carbide single crystal wafer is 36 rpm (30 rpm + 6 rpm = 36 rpm), and the relative speed of the lower platen relative to the rotation speed of the silicon carbide single crystal wafer is 24 rpm (30 rpm - 6 rpm = 24 rpm). Therefore, in this case, the description in the column of “Relative Speed ​​Ratio” in Table 1 is “upper:lower=3:2 (=36 rpm:24 rpm)”.

[0105] [Table 1]

[0106]

[0107] Next, the second two-main-surface chemical mechanical polishing step S5 is performed. The second two-main-surface chemical mechanical polishing step S5 can be performed by chemically mechanically polishing the two main surfaces of the silicon carbide single crystal wafer after the first two-main-surface chemical mechanical polishing step S4 under the conditions shown in the following Table 2. It should be noted that the second two-main-surface chemical mechanical polishing step S5 is performed in the same manner as the first two-main-surface chemical mechanical polishing step S4, except that the polishing liquid and the polishing cloth are changed to the conditions in Table 2.

[0108] [Table 2]

[0109]

[0110] Fig.10 1 is a schematic plan view of the entire surface of an example of the polishing cloth 34 used in the first and second main surface chemical mechanical polishing steps S4 and S5 .

[0111] like Fig.10 As shown, the entire annular surface of the polishing cloth 34 has the following structure: a grid-shaped groove 34b that does not contribute to polishing the main surface of the silicon carbide single crystal wafer using the polishing cloth 34 is provided on an effective polishing surface 34a that contributes to polishing the main surface of the silicon carbide single crystal wafer using the polishing cloth 34.

[0112] From the viewpoint of suppressing the occurrence of cracks, defects or chipping of the silicon carbide single crystal wafer caused by CMP of both main surfaces, in at least one of the first both main surfaces chemical mechanical polishing step S4 and the second both main surfaces chemical mechanical polishing step S5, A si and A c It is preferred to satisfy the following formulas (6) to (8), and it is more preferred to satisfy the following formulas (6) to (9), wherein A si is the effective surface area ratio of the polishing cloth 34 used for polishing the Si surface of the two main surfaces of the silicon carbide single crystal wafer, and A c is the effective surface area ratio of the polishing cloth 34 used for polishing the C surface.

[0113] A si ≥80 and A c ≥80…Formula (6)

[0114] A si >90 and A c <90…Formula (7)

[0115] 1<(A si / A c )<1.25…Formula (8)

[0116] 1.02<(A si / A c )<1.05…Formula (9)

[0117] The effective surface area ratio A of the polishing cloth 34 for polishing the Si surface of the silicon carbide single crystal wafer si [%] can be calculated by the following formula (10).

[0118] Effective surface area ratio A si [%] = 100 × {(area of ​​the effective polishing surface 34a of the polishing cloth 34 for polishing the Si surface of the silicon carbide single crystal wafer [mm 2 ]) / (area of ​​the entire surface of the polishing cloth 34 [mm 2 ])}…Formula (10)

[0119] The effective surface area ratio A of the polishing cloth 34 for polishing the C-surface of the silicon carbide single crystal wafer c [%] can be calculated by the following formula (11).

[0120] Effective surface area ratio A c [%] = 100 × {(area of ​​the effective polishing surface 34a of the polishing cloth 34 for polishing the C surface of the silicon carbide single crystal wafer [mm 2 ]) / (area of ​​the entire surface of the polishing cloth 34 [mm 2 ])}…Formula (11)

[0121] It should be noted that the area of ​​the entire surface of the polishing cloth 34 in the above formula (10) and formula (11) is [mm 2 ]For example, Fig.10 The area shown here refers to the entire surface area of ​​the polishing cloth 34 when the surface of the polishing cloth 34 is viewed from above.

[0122] In addition, from the viewpoint of suppressing the occurrence of cracks, defects or fragmentation of the silicon carbide single crystal wafer caused by CMP of both main surfaces, in at least one of the first both main surfaces chemical mechanical polishing step S4 and the second both main surfaces chemical mechanical polishing step S5, the polishing rate R of the Si surface of the silicon carbide single crystal wafer is set to 0.100°. si The grinding rate R of the C surface c The ratio (R si / R c ) is preferably 0.6 or more and 1.4 or less, more preferably 0.7 or more and 1.3 or less, and further preferably 0.8 or more and 1.2 or less. It should be noted that the grinding rate represents the amount of the silicon carbide single crystal wafer ground per unit time. The grinding rate can be adjusted, for example, by adjusting the grinding conditions.

[0123] <Implementation method 6>

[0124] Fig.11 This is a flowchart of a method for manufacturing a silicon carbide substrate according to a sixth embodiment.

[0125] like Fig.11 As shown, in the method for manufacturing a silicon carbide substrate according to Embodiment 6, slicing step S1, chamfering step S2, rough grinding step S3, and first two main surface chemical mechanical polishing step S4 are also performed in sequence. The description of these steps is the same as that of Embodiment 5, so the description thereof is omitted.

[0126] The single main surface chemical mechanical polishing step S5a can be performed by chemically mechanically polishing the Si surface and the C surface of the silicon carbide single crystal wafer after the first two main surface chemical mechanical polishing step S4, one by one, under the conditions shown in Table 3 below.

[0127] The single-principal-surface chemical mechanical polishing step S5a is performed in the following manner. First, the polishing cloth listed in Table 3 is set on the surface of the table. Next, the silicon carbide single crystal wafer is held on the polishing head in a manner that the main surface of the silicon carbide single crystal wafer is opposite to the polishing cloth. Next, the polishing liquid listed in Table 3 is supplied between the polishing cloth and the main surface of the silicon carbide single crystal wafer. Next, the surface pressure listed in Table 3 is applied to the silicon carbide single crystal wafer. Here, the main surface of the polished side of the silicon carbide single crystal wafer is brought into contact with the polishing cloth. Next, the table and the polishing head are rotated in the same direction at the table rotation speed listed in Table 3. This operation is performed on the silicon carbide single crystal wafer one main surface at a time.

[0128] [Table 3]

[0129]

[0130] Example

[0131] <Experimental Example 1>

[0132] In Experimental Example 1, according to Fig. 9 The silicon carbide substrate is manufactured in the flowchart of the method for manufacturing the silicon carbide substrate. Specifically, the silicon carbide substrate is manufactured in the following manner.

[0133] First, a slicing step S1 is performed by slicing an ingot made of a silicon carbide single crystal produced by a sublimation method using a wire saw.

[0134] Next, a chamfering step S2 is performed by cutting the corners of the silicon carbide single crystal wafer obtained in the slicing step S1.

[0135] Next, a rough polishing step S3 is performed by mechanically polishing both main surfaces of the silicon carbide single crystal wafer after the chamfering step S2.

[0136] Next, under the conditions shown in Table 1 above, as described above, the first both-main-surface chemical mechanical polishing step S4 was performed by subjecting both main surfaces of the silicon carbide single crystal wafer after the rough polishing step S3 to chemical mechanical polishing.

[0137] Next, the second both-main-surface chemical mechanical polishing step S5 was performed by chemical mechanical polishing both main surfaces of the silicon carbide single crystal wafer after the first both-main-surface chemical mechanical polishing step S4 under the conditions shown in Table 2. Thus, the silicon carbide substrate of Experimental Example 1 was manufactured.

[0138] <Experimental Example 2>

[0139] In Experimental Example 2, according to Fig.11That is, in Experimental Example 2, the silicon carbide substrate of Experimental Example 2 was manufactured in the same manner as in Experimental Example 1, except that the single-main-surface chemical mechanical polishing step S5a was performed instead of the second double-main-surface chemical mechanical polishing step S5 of Experimental Example 1.

[0140] Specifically, the single-main-surface chemical mechanical polishing step S5a is performed by chemically mechanical polishing the Si surface and the C surface of the silicon carbide single crystal wafer after the first two-main-surface chemical mechanical polishing step S4 one by one under the conditions shown in Table 3 above.

[0141] <Experimental Example 3>

[0142] In Experimental Example 3, a single main surface chemical mechanical polishing process is performed under the conditions shown in Table 4 below, in which the Si surface and C surface of the silicon carbide single crystal wafer after the rough grinding process S3 are chemically mechanically polished one by one, instead of the first two main surface chemical mechanical polishing process S4. Otherwise, the silicon carbide substrate of Experimental Example 3 is manufactured in the same manner as Experimental Example 2.

[0143] [Table 4]

[0144]

[0145] <Evaluation>

[0146] The average LTV of the first square region 41, the average LTV of the second square region 42, the average LTV of the third square region 43, and the average LTV of the fourth square region 44 were calculated for the silicon carbide substrates of Experimental Examples 1 to 3. It should be noted that the LTV of the fifth square region 45 was calculated for only one region. The results are shown in Table 5 below. In addition, the LTV values ​​shown in Table 5 are plotted for each experimental example and are shown in the following figure. Fig.12 It should be noted that Fig.12 In the graph, the lower the LTV value is plotted, the flatter it is. Fig.12 In the middle, it means that the direction moves from the center of the silicon carbide substrate toward the periphery as progressing from fifth square region 45 to first square region 41 .

[0147] [Table 5]

[0148]

[0149] like Fig.12 As shown, it can be seen that the silicon carbide substrates of Experimental Examples 1 and 2 become flatter as compared with the silicon carbide substrate of Experimental Example 3 as progressing from the center to the periphery of the silicon carbide substrate.

[0150] In addition, if Fig.12 As shown, it can be seen that the silicon carbide substrate of Experimental Example 1 becomes flatter as compared with the silicon carbide substrate of Experimental Example 2 as it progresses from the center to the periphery of the silicon carbide substrate.

[0151] <Experimental Example 4>

[0152] In Experimental Example 1, the polishing rate (R si ) and the grinding rate of C surface (R c ) ratio (R si / R c ) were used to perform the first two main surface chemical mechanical polishing step S4 and the yield rate [%] of the silicon carbide single crystal wafers was evaluated. The results are shown in Table 6.

[0153] [Table 6]

[0154] <![CDATA[R si / R c ]]> Pass rate [%] Less than 0.5 or greater than 1.8 62 0.6 or more and 1.4 or less 84 0.7 or more and 1.3 or less 91 0.8 or more and 1.2 or less 94

[0155] According to the results shown in Table 6, it can be seen that from the viewpoint of improving the yield rate [%] of the silicon carbide single crystal wafer, it is preferable to reduce the polishing rate (R ) of the Si surface of the silicon carbide single crystal wafer in the first two main surface chemical mechanical polishing step S4 of Experimental Example 1 to 0. si ) and the grinding rate of C surface (R c ) ratio (R si / R c ) is set to be greater than or equal to 0.6 and less than or equal to 1.4, more preferably set to be greater than or equal to 0.7 and less than or equal to 1.3, and further preferably set to be greater than or equal to 0.8 and less than or equal to 1.2.

[0156] <Experimental Example 5>

[0157] In Experimental Example 1, the polishing rate (R si ) and the grinding rate of C surface (R c ) ratio (R si / R c The state of the silicon carbide single crystal wafer after the first two main surface chemical mechanical polishing step S4 was evaluated according to the following criteria. The results are shown in Table 7.

[0158] (Benchmark)

[0159] A… has the lowest LTV

[0160] B…LTV is small

[0161] C…LTV is below the benchmark

[0162] D…LTV deteriorates

[0163] E…bad

[0164] [Table 7]

[0165]

[0166] The numerical values ​​(1.10, 1.00, 0.70, 0.60, 0.47, 0.40, and 0.30) in the second row from the top of Table 7 represent the polishing rates (R si The values ​​in the second column from the left of Table 7 (1.80, 1.35, 1.15, 0.94, 0.80, and 0.60) represent the polishing rates (R c ). The values ​​other than these values ​​in Table 7 represent the polishing rate R of the Si surface of the silicon carbide single crystal wafer. si The grinding rate R of the C surface c The ratio (R si / R c ). The symbols A to E in Table 7 represent the results of evaluating the state of the silicon carbide single crystal wafer according to the above criteria. It should be noted that the order of E, D, C, B and A indicates that the state of the silicon carbide single crystal wafer after grinding increases in goodness.

[0167] In Experimental Example 1, the polishing rate (R si ) and the grinding rate of C surface (R c ) ratio (R si / R c The state of the silicon carbide single crystal wafer after the second chemical mechanical polishing step S5 of both main surfaces was performed was evaluated according to the above criteria. The results are shown in Table 8.

[0168] [Table 8]

[0169]

[0170] The numerical values ​​(0.27, 0.26, 0.24, 0.20, 0.19, 0.17, and 0.13) in the second row from the top of Table 8 represent the polishing rates (R si The values ​​in the second column from the left of Table 8 (0.62, 0.49, 0.46, 0.40, 0.32, and 0.25) represent the polishing rates (R c ). The values ​​other than these values ​​in Table 8 represent the polishing rate R of the Si surface of the silicon carbide single crystal wafer. si The grinding rate R of the C surface c The ratio (R si / R c ) The symbols A to E in Table 8 represent the results of evaluating the state of the silicon carbide single crystal wafer according to the above-mentioned criteria.

[0171] As shown in Tables 7 and 8, it can be seen that in each of the first two-main-surface chemical mechanical polishing step S4 and the second two-main-surface chemical mechanical polishing step S5, there is a polishing rate R of the Si surface of the silicon carbide single crystal wafer suitable for maintaining the state of the polished silicon carbide single crystal wafer well. si The grinding rate R of the C surface c The ratio (R si / R c ).

[0172] <Experimental Example 6>

[0173] By changing the effective surface area ratio A of the polishing cloth used for polishing the Si surface of the silicon carbide single crystal wafer in Experimental Example 1, si [%] Effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer c [%] ratio (A si / A c ) is performed to perform the first two main surface chemical mechanical polishing step S4, and the state of the silicon carbide single crystal wafer is evaluated based on the above-mentioned criteria A to E.

[0174] In addition, by changing the effective surface area ratio A of the polishing cloth used for polishing the Si surface of the silicon carbide single crystal wafer in Experimental Example 1, si [%] Effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer c [%] ratio (A si / A c ) is performed to perform the second both main surface chemical mechanical polishing step S5, and the state of the silicon carbide single crystal wafer is evaluated based on the above-mentioned criteria A to E.

[0175] The evaluation results of the states of these silicon carbide single crystal wafers were the same. The results are shown in Table 9.

[0176] [Table 9]

[0177]

[0178] The values ​​in the second row from the top of Table 9 (99.7, 97.7, 93.2, 90.0, 86.9, 80.8, and 63.8) represent the effective surface area ratio A of the polishing cloth used for polishing the Si surface of the silicon carbide single crystal wafer. si [%] The numerical values ​​(98.0, 93.5, 90.3, 87.2, 81.1, and 64.1) in the second column from the left of Table 9 represent the effective surface area ratio A of the polishing cloth used for polishing the C-surface of the silicon carbide single crystal wafer. c[%] The numerical values ​​other than these numerical values ​​in Table 9 represent the effective surface area ratio A of the polishing cloth used for polishing the Si surface of the silicon carbide single crystal wafer. si [%] Effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer c [%] ratio (A si / A c ) The symbols A to E in Table 9 represent the results of evaluating the state of the silicon carbide single crystal wafer according to the same criteria as in Experimental Example 5.

[0179] As shown in Table 9, it can be seen that in each of the first two-main-surface chemical mechanical polishing step S4 and the second two-main-surface chemical mechanical polishing step S5, there is an effective surface area ratio A of the polishing cloth for polishing the Si surface of the silicon carbide single crystal wafer suitable for maintaining the state of the polished silicon carbide single crystal wafer well. s [%] Effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer c [%] ratio (A si / A c ).

[0180] The embodiments disclosed this time are illustrative in all aspects and should not be considered restrictive. The scope of the present invention is indicated by the claims rather than the embodiments described above, and is intended to include all modifications within the scope and meaning equivalent to the claims.

[0181] Explanation of symbols

[0182] 10 silicon carbide substrate, 10a, 10b, 10c, 10d both ends, 11 first main surface, 12 second main surface, 13 orientation plane, 34 polishing cloth, 34a effective polishing surface, 34b groove, 41 first square area, 41a lowest point, 41b highest point, 42 second square area, 42a lowest point, 42b highest point, 43 third square area, 43a lowest point, 43b highest point, 44 fourth square area, 44a lowest point, 44b highest point point, 45 fifth square area, 45a center, 45b highest point, 45c lowest point, 50 central area, 51a, 51b first area, 51c, 51d second area, 101 first radial, 101a first imaginary straight line, 102 second radial, 102a second imaginary straight line, 410a, 410b area, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 height, S1, S2, S3, S4, S5 processes.

Claims

1. A silicon carbide substrate having a circular first main surface provided with an orientation flat and a second main surface opposite to the first main surface, wherein: The first main surface has a center of a circle when the shape of the first main surface before the orientation flat is set is set as a circle, The first main surface has two first end portions in a first radial direction, and the two first end portions in the first radial direction are two intersection points of a first imaginary straight line with a periphery of the first main surface when a first imaginary straight line passing through the center of the circle and extending in the first radial direction is assumed to be provided in the first radial direction of the first main surface. The first main surface has two second end portions in a second radial direction, and the two second end portions in the second radial direction are two intersection points of the second imaginary straight line with the peripheral edge of the first main surface when a second imaginary straight line passing through the center of the circle and extending in the second radial direction is assumed to be provided in a second radial direction orthogonal to the first radial direction of the first main surface, The first main surface has a central area obtained by excluding a first area and a second area, the first area being an area within 5 mm from each of the first two ends in the first radial direction to the inside of the first main surface, and the second area being an area within 5 mm from each of the second two ends in the second radial direction to the inside of the first main surface, When the central area of ​​the first main surface is divided into a plurality of square areas so that the square area having the largest number of sides of 5 mm that completely constitutes a square, an average value of local thickness variation of the plurality of first square areas is less than 0.75 μm, and the plurality of first square areas are arranged in a ring shape so as to be located at the outermost side relative to the center of the circle and constitute the outermost periphery, The average value of the local thickness variation of the plurality of second square areas among the plurality of square areas is less than 0.4 μm, the plurality of second square areas are arranged adjacent to the first square areas on the inner side of the first radial direction or the inner side of the second radial direction of the plurality of first square areas, and are arranged in a ring shape in a manner constituting the inner circumference of a ring constituted by the plurality of first square areas, The value obtained by dividing the average value of the local thickness variation of the plurality of first square regions by the value of the local thickness variation of the fifth square region which is a complete square centered on the center of the first main surface and has a side length of 5 mm is 69 / 20 or more and 71 / 14 or less.

2. The silicon carbide substrate according to claim 1, wherein An average value of the local thickness variation of the plurality of first square regions is greater than or equal to 0.1 μm.

3. The silicon carbide substrate according to claim 1, wherein: An average value of the local thickness variation of the plurality of second square regions is greater than or equal to 0.1 μm.

4. The silicon carbide substrate according to claim 1, wherein: The average value of the local thickness variation of the multiple third square areas among the multiple square areas is less than 0.3 μm, and the multiple third square areas are arranged adjacent to the second square areas on the first radial inner side or the second radial inner side of the multiple second square areas, and are arranged in a ring shape in such a manner as to constitute the inner circumference of a ring formed by the multiple second square areas.

5. The silicon carbide substrate according to claim 4, wherein: An average value of the local thickness variation of the plurality of third square regions is greater than or equal to 0.1 μm.

6. The silicon carbide substrate according to claim 4, wherein: The average value of the local thickness variation of the multiple fourth square areas among the multiple square areas is less than 0.25 μm, and the multiple fourth square areas are arranged adjacent to the third square areas on the inner side of the first radial direction or the inner side of the second radial direction of the multiple third square areas, and are arranged in a ring shape in such a manner as to constitute the inner circumference of a ring formed by the multiple third square areas.

7. The silicon carbide substrate according to claim 6, wherein: An average value of the local thickness variation of the plurality of fourth square regions is greater than or equal to 0.1 μm.

8. A method for manufacturing a silicon carbide substrate, wherein: The manufacturing method has the following features: a step of slicing an ingot made of a silicon carbide single crystal to form a silicon carbide single crystal wafer; a step of chamfering the silicon carbide single crystal wafer by cutting a corner of the silicon carbide single crystal wafer, a step of roughly grinding both main surfaces of the chamfered silicon carbide single crystal wafer; The step of chemically mechanically polishing the first two main surfaces of the roughly polished silicon carbide single crystal wafer at least once using a polishing cloth and a polishing liquid, and The step of performing at least one second chemical mechanical polishing of the two main surfaces of the silicon carbide single crystal wafer after the chemical mechanical polishing of the first two main surfaces using a polishing cloth and a polishing liquid different from those used in the step of chemical mechanical polishing of the first two main surfaces, wherein In at least one of the step of chemically mechanically polishing the first two main surfaces and the step of chemically mechanically polishing the second two main surfaces, an effective surface area ratio A of a polishing cloth used for polishing the Si surface of the silicon carbide single crystal wafer is si The effective surface area ratio A of the polishing cloth used for polishing the C surface of the silicon carbide single crystal wafer is c Satisfying the following equations (6) to (8), A si ≥80 and A c ≥80…Formula (6) A si >90 and A c <90…Formula (7) 1<(A si / A c )<1.25...Equation (8) In at least one of the step of chemically mechanically polishing the first two main surfaces and the step of chemically mechanically polishing the second two main surfaces, a polishing rate R of the Si surface of the silicon carbide single crystal wafer is si The polishing rate R of the C surface of the silicon carbide single crystal wafer is c The ratio (R si / R c ) is greater than or equal to 0.6 and less than or equal to 1.4.

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