A SG model of N-cascade inverter based on time division multiplexing

Abstract

The present invention provides an N-cascade inverter SG model based on time division multiplexing, wherein the transformer model is used to adopt a time division multiplexing method to sequentially use N / 2 groups of transformation parameters as input parameters, and receive a second voltage fed back by a rectifier model, and output a first voltage and a first current after transformation adjustment of the second voltage and the input parameters; the transformer model is used to receive a first voltage and a first current and a third current fed back by an inverter model, and output a third voltage, a second current and a second voltage after rectification; the inverter model is used to receive a third voltage, a second current and a three-phase load current fed back by an external motor model, and output a fourth voltage and a third current after inversion, so that the N-cascade inverter model runs in a simulation cycle of 1e‑7s, and realizes the optimal allocation of FPGA resources while ensuring the correctness of the results, the simulation results are highly consistent with simpower, and the FPGA resource occupancy rate is relatively low.

Description

Technical Field

[0001] The present invention belongs to the technical field of multi-cascade frequency converters, and more specifically, particularly relates to an N-cascade frequency converter SG model based on time division multiplexing. Background Art

[0002] In the hardware in-loop simulation test, the cascade inverter SG (System Generator) model requires a lot of calculations due to the large number of sub-transformers, which occupies a large amount of FPGA resources. As a result, the FPGA simulation device resources are insufficient to meet the complex calculations. The FPGA resource usage is often reduced by reducing the data bits of fixed-point operations or simplifying the model to ensure that the model can be compiled.

[0003] When reducing the data bits, data bit saturation may occur when the model is operating, resulting in incorrect calculation results. At the same time, since complex models involve a large number of multiplication, addition, subtraction and other operations, only streamlining the data bits of a part of the calculation logic has limited effect on reducing the occupancy of FPGA resources. It is time-consuming and labor-intensive to streamline the data bits in a large amount of calculation logic one by one. Moreover, if there are too many inverter stages, there is a situation where even if the data bits are streamlined as much as possible, they still cannot meet the FPGA resources.

[0004] Although the FPGA resource usage can be reduced by simplifying the model, that is, the current / voltage calculation of the transformer model is simply performed by the transformation ratio calculation method, it is obvious that the accuracy of the model will be reduced due to the approximate simplification of the model, especially the transient characteristics of the current / voltage of the transformer cannot be reflected through simulation. Improving the model accuracy requires increasing the data bit and calculation accuracy, and the existing FPGA resources cannot meet the needs of complex models. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide an N-cascade inverter SG model based on time division multiplexing, which is used to achieve optimal allocation of FPGA resources, with simulation results highly consistent with simpower and a high compilation pass rate.

[0006] The present application discloses a time-division multiplexing-based N-cascade inverter SG model, comprising: a transformer model, a rectifier model and an inverter model; wherein N=2n, n is a positive integer;

[0007] The transformer model is used to use N / 2 groups of transformation parameters as input parameters in sequence in a time division multiplexing manner, and receive the second voltage fed back by the rectifier model, and output the first voltage and the first current after transformation adjustment on the second voltage and the input parameters; wherein the number of transformers is N; and one group of transformation parameters includes parameters of two transformers with the same parameters;

[0008] The rectifier model is used to receive the first voltage, the first current and the third current fed back by the inverter model, and output the third voltage, the second current and the second voltage after rectification;

[0009] The inverter model is used to receive the third voltage, the second current and the three-phase load current fed back by the external motor model, and output a fourth voltage and the third current after inversion; wherein the fourth voltage acts on the external motor model.

[0010] Optionally, the transformer model is used to use N / 2 groups of transformation parameters as input parameters in sequence in a time division multiplexing manner, and receive the second voltage fed back by the rectifier model, and output the first voltage and the first current after performing transformation adjustment on the second voltage and the input parameters, specifically for:

[0011] At the i-th clock, the parameters of the i-th transformer and the (Ni)+1-th transformer are used as input parameters, and a second voltage fed back by the rectifier model is received, and the second voltage and the input parameters are transformed and adjusted to output a first voltage and a first current;

[0012] i=i+1, returns to the step of executing the i-th clock, taking the parameters of the i-th transformer and the parameters of the (Ni)+1-th transformer as input parameters, receiving the second voltage fed back by the rectifier model, and outputting the first voltage and the first current after transforming and adjusting the second voltage and the input parameters; until i+1 is greater than N / 2, the initial value of i is 1.

[0013] Optionally, N=10.

[0014] Optionally, the transformer model is used to use N / 2 groups of transformation parameters as input parameters in sequence in a time division multiplexing manner, and receive the second voltage fed back by the rectifier model, and output the first voltage and the first current after performing transformation adjustment on the second voltage and the input parameters, specifically for:

[0015] At the first clock, the parameters of the first-stage transformer and the parameters of the tenth-stage transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the first voltage and the first current are output after voltage transformation and adjustment are performed on the second voltage and the input parameters;

[0016] At the second clock, the parameters of the second-stage transformer and the parameters of the ninth-stage transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the first voltage and the first current are output after voltage transformation and adjustment are performed on the second voltage and the input parameters;

[0017] At the third clock, the parameters of the third-level transformer and the parameters of the eighth-level transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted;

[0018] At the fourth clock, the parameters of the fourth-level transformer and the seventh-level transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted;

[0019] At the 5th clock, the parameters of the 5th-level transformer and the 6th-level transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0020] Optionally, the operating step size of the transformer model is 1e-7s; the equivalent simulation step size and voltage input sampling period of the N-cascade inverter SG model are both 5e-7s.

[0021] Optionally, at the i-th clock, the parameters of the i-th transformer and the parameters of the (Ni)+1-th transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the second voltage and the input parameters are transformed and adjusted to output the first voltage and the first current, specifically for:

[0022] Input the parameters of the i-th transformer into the first transformer calculation unit, and input the parameters of the (Ni)+1-th transformer into the second transformer calculation unit;

[0023] After the first transformer calculation unit and the second transformer calculation unit perform the voltage transformation adjustment calculation, a first voltage and a first current are obtained.

[0024] Optionally, the voltage before the secondary inductance of the transformer is used as the first voltage;

[0025] The output current of the secondary winding of the transformer serves as the first current.

[0026] Optionally, the voltage after the secondary inductance of the rectifier in the rectifier model is used as the second voltage;

[0027] The bus voltage and current of the rectifier are used as the third voltage and the second current respectively.

[0028] Optionally, the output voltage of the inverter in the inverter model is used as the fourth voltage; and the output current of the inverter is used as the third current.

[0029] Optionally, the external controller outputs corresponding PWM waves to the inverter model in the order of inputting N / 2 groups of transformation parameters into the transformer model.

[0030] It can be seen from the above technical scheme that the present invention provides an N-cascade inverter SG model based on time division multiplexing, including: a transformer model, a transformer model and an inverter model; the transformer model is used to use time division multiplexing to take N / 2 groups of transformation parameters as input parameters in turn, and receive the second voltage fed back by the rectifier model, and output the first voltage and the first current after transformation adjustment of the second voltage and the input parameters; wherein the number of transformers is N; a group of transformation parameters includes parameters of two transformers with the same parameters; the transformer model is used to receive the first voltage and the first current and the third current fed back by the inverter model, and output the third voltage, the second current and the second voltage after rectification; the inverter model is used to receive the third voltage, The second current and the three-phase load current fed back by the external motor model are inverted to output the fourth voltage and the third current, and the N-cascade inverter model based on time-division multiplexing logic is realized in the simulation cycle of 1e-7s. If the V / F open-loop control strategy is used for comparative simulation, the voltage / current observation output of each observation point can be highly consistent with the simpower model, including multiple voltage and multiple current outputs; the optimal allocation of FPGA resources is achieved under the premise of ensuring the correctness of the results, and the occupancy rate of all FPGA resources is below 40%. The simulation results are highly consistent with simpower, and the FPGA resource occupancy rate is relatively low. If there is no time-division multiplexing, the resource occupancy rate is greater than 100%, and the compilation fails. At the same time, the time-division multiplexing logic can be used in the construction of other models with multiple identical calculation logics and relatively large resource occupancy. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a schematic diagram of an N-cascade inverter SG model based on time division multiplexing provided by an embodiment of the present invention;

[0033] Figure 2 It is a schematic diagram of a transformer in a time division multiplexing-based N-cascade inverter SG model provided by an embodiment of the present invention;

[0034] Figure 3 Schematic diagram of an inverter in an N-cascade inverter SG model based on time division multiplexing provided by an embodiment of the present invention;

[0035] Figure 4 It is a schematic diagram of a rectifier in a time division multiplexing-based N-cascade inverter SG model provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0038] The embodiment of the present application discloses an N-cascade inverter SG model based on time division multiplexing, which is used to solve the problem in the prior art that improving the accuracy of the model requires increasing the data bits and calculation accuracy, and the existing FPGA resources cannot meet the requirements of complex models.

[0039] The N-cascade inverter SG model based on time division multiplexing includes: a transformer model S1, a rectifier model S2 and an inverter model S3.

[0040] Wherein, N=2n, and n is a positive integer.

[0041] Specifically, the input end of the transformer model S1 serves as the input end of the N-cascade inverter SG model, and the output end of the transformer model S1 is connected to the input end of the rectifier model S2; the output end of the rectifier model S2 is connected to the input end of the inverter model S3; the output end of the inverter model S3 serves as the output end of the N-cascade inverter SG model and is connected to the input end of the motor model.

[0042] It should be noted that the rectifier model S2 feeds back voltage to the inverter model S3; the inverter model S3 feeds back current to the rectifier model S2; and the motor model feeds back current to the inverter model S3.

[0043] More specifically, the transformer model S1 is used to use time division multiplexing to take N / 2 groups of transformation parameters as input parameters in sequence, and receive the second voltage fed back by the rectifier model S2, and output the first voltage and the first current after transformation and adjustment of the second voltage and the input parameters.

[0044] There are N transformers, and a set of transformer parameters includes parameters of two transformers with the same parameters.

[0045] That is, the transformer model S1 obtains the parameters of only two transformers with the same parameters at one time, receives the second voltage fed back by the rectifier model S2, and then performs voltage transformation adjustment according to the transformer parameters and the second voltage to obtain the output first voltage and first current.

[0046] After N / 2 clocks, the calculation of the parameters of N / 2 groups of transformers is completed, that is, the calculation of the parameters of N transformers is completed.

[0047] In other words, N / 2 groups of transformers can reuse the same set of calculations, without the need to set up a corresponding calculation program for each transformer separately.

[0048] The rectifier model S2 is used to receive the first voltage and the first current and the third current fed back by the inverter model S3, and output the third voltage, the second current and the second voltage after rectification.

[0049] The inverter model S3 is used to receive the third voltage, the second current and the three-phase load current fed back by the external motor model, and output a fourth voltage and the third current after inversion; wherein the fourth voltage acts on the external motor model.

[0050] In this embodiment, the transformer model S1 is used to use time division multiplexing to sequentially use N / 2 groups of transformation parameters as input parameters, and receive the second voltage fed back by the rectifier model S2, and output the first voltage and the first current after transformation adjustment of the second voltage and the input parameters; wherein the number of transformers is N; a group of transformation parameters includes parameters of two transformers with the same parameters; the transformer model S1 is used to receive the first voltage and the first current and the third current fed back by the inverter model S3, and output the third voltage, the second current and the second voltage after rectification; the inverter model S3 is used to receive the third voltage, the second current and the three-phase load current fed back by the external motor model , after inversion, the fourth voltage and the third current are output, and the N-cascade inverter model based on time-division multiplexing logic is realized in the simulation cycle of 1e-7s. If the V / F open-loop control strategy is used for comparative simulation, the voltage / current observation output of each observation point can be highly consistent with the simpower model, including multiple voltage and multiple current outputs; the optimal allocation of FPGA resources is achieved under the premise of ensuring the correctness of the results. The occupancy rate of all FPGA resources is below 40%, the simulation results are highly consistent with simpower, and the FPGA resource occupancy rate is relatively low. If there is no time-division multiplexing, the resource occupancy rate is greater than 100%, and the compilation fails. At the same time, the time-division multiplexing logic can be used in the construction of other models with multiple identical calculation logics and relatively large resource occupancy.

[0051] In practical applications, the transformer model S1 is used to use N / 2 groups of transformation parameters as input parameters in turn in a time division multiplexing manner, and receive the second voltage fed back by the rectifier model S2, and output the first voltage and the first current after the second voltage and the input parameters are transformed and adjusted, specifically for:

[0052] At the i-th clock, the parameters of the i-th transformer and the (Ni)+1-th transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received. The first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0053] i=i+1, returns to the step of executing the i-th clock, taking the parameters of the i-th level transformer and the parameters of the (Ni)+1-th level transformer as input parameters, receiving the second voltage fed back by the rectifier model S2, and outputting the first voltage and the first current after transforming and adjusting the second voltage and the input parameters; until i+1 is greater than N / 2, the initial value of i is 1.

[0054] That is to say, the above voltage transformation adjustment is performed starting from i=1, and 1 is accumulated sequentially after the voltage transformation adjustment is completed, until the N / 2th group of transformers also completes the voltage transformation adjustment and outputs the first voltage and the first current.

[0055] In practical applications, at the i-th clock, the parameters of the i-th transformer and the (Ni)+1-th transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received. After the second voltage and the input parameters are transformed and adjusted, the first voltage and the first current are outputted. Specifically, it is used for:

[0056] The parameters of the i-th transformer are input into the first transformer calculation unit, and the parameters of the (Ni)+1-th transformer are input into the second transformer calculation unit.

[0057] After the first transformer calculation unit and the second transformer calculation unit perform the voltage transformation adjustment calculation, a first voltage and a first current are obtained.

[0058] That is to say, two transformer calculation units are used to respectively calculate the voltage and current after the two transformers are transformed and adjusted.

[0059] It should be noted that the parameters of the same group of transformers are the same, so the voltage and current calculated by the two transformer calculation units are the same. Therefore, the voltage after the two transformers are transformed and adjusted can be used as the first voltage, and the current after the two transformers are transformed and adjusted can be used as the first current.

[0060] It should be noted that according to Figure 1 It can be seen that the rectifier model S2 and the inverter model S3 also have two calculation units. Therefore, the units in different models can be matched one by one. That is to say, one calculation unit of the transformer model S1, one calculation unit of the rectifier model S2 and one calculation unit of the inverter model S3 respectively constitute a group of calculation modules; another calculation unit of the transformer model S1, another calculation unit of the rectifier model S2 and another calculation unit of the inverter model S3 respectively constitute another group of calculation modules.

[0061] A calculation module is used to calculate the corresponding parameters of the corresponding transformer, rectifier and inverter. It should be noted that the transformer, rectifier and inverter also have corresponding corresponding relationships, such as one-to-one correspondence, one-to-many correspondence and many-to-one correspondence, which will not be described one by one here, and are all within the protection scope of this application.

[0062] In practical applications, N=10, that is, the N-cascaded inverter SG model can be a 10-cascaded inverter SG model; of course, N can also be other values, which are not specifically limited here and can be determined according to actual conditions, all within the protection scope of the application.

[0063] Specifically, taking N=10 as an example, the specific working process of the transformer model S1 is described: the transformer model S1 is used to use a time division multiplexing method to sequentially use N / 2, i.e., 5 sets of transformation parameters as input parameters, and receive the second voltage fed back by the rectifier model S2, and output the first voltage and the first current after the second voltage and the input parameters are transformed and adjusted. Specifically, it is used to:

[0064] At the first clock, the parameters of the first-stage transformer and the parameters of the tenth-stage transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0065] At the second clock, the parameters of the second-stage transformer and the ninth-stage transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0066] At the third clock, the parameters of the third-level transformer and the eighth-level transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0067] At the 4th clock, the parameters of the 4th-level transformer and the 7th-level transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0068] At the 5th clock, the parameters of the 5th-level transformer and the 6th-level transformer are used as input parameters, and the second voltage fed back by the rectifier model S2 is received, and the first voltage and the first current are output after the second voltage and the input parameters are transformed and adjusted.

[0069] In practical applications, the operating step size of transformer model S1 is 1e-7s.

[0070] Taking N=10 as an example, the equivalent simulation step size and voltage input sampling period of the N-cascade inverter SG model are both 5e-7s.

[0071] That is to say, when N is not 10, the equivalent simulation step size and the voltage input sampling period of the N-cascaded inverter SG model can be calculated according to the formula N / 2*(1e-7s), which will not be elaborated here one by one. It depends on the actual situation and is within the protection scope of this application.

[0072] It should be noted that the calculus discretization model can also be applied to the N-cascade inverter SG model, and its voltage input sampling period is consistent with the voltage input sampling period of the N-cascade inverter SG model; the working process and principle of the calculus discretization model will not be described here one by one, and for details, please refer to the corresponding prior art, which are all within the protection scope of this application.

[0073] In practical applications, the voltage before the secondary inductor of the transformer is used as the first voltage; and the output current of the secondary winding of the transformer is used as the first current.

[0074] The voltage after the secondary inductance of the rectifier in the rectifier model S2 serves as the second voltage.

[0075] The bus voltage of the rectifier is used as the third voltage, and the bus current of the rectifier is used as the second current.

[0076] The output voltage of the inverter in the inverter model S3 is used as the fourth voltage; the output current of the inverter is used as the third current.

[0077] The inverter is an H-bridge topology.

[0078] The following is an example of a 10-stage cascade inverter SG model: the parameters of the 1st, 10th; 2nd, 9th; 3rd, 8th; 4th, 7th; 5th, 6th group of inverter units in each phase are the same, and 5 times of time division multiplexing are used. 5 clocks are used to calculate the 1st, 10th, 2nd, 9th, 3rd, 8th, 4th, 7th and 5th, 6th groups of inverter models in turn, that is, the input parameters of the transformer are multiplexed in pairs, and the corresponding PWM inputs in the inverter model S3 calculation are also given according to this order. Take the scenario where the 10-stage cascade inverter SG model is applied to three-phase electricity as an example. Of course, it can also be applied to other phase point electricity scenarios. No specific limitation is made here, and it can be determined according to the actual situation. All of them are within the protection scope of this application.

[0079] The first stage: the transformer model S1 is used to use the time division multiplexing method to take 5 sets of transformation parameters as input parameters in turn, and receive the second voltage fed back by the rectifier model S2, and output the first voltage and the first current after the second voltage and the input parameters are transformed and adjusted; wherein the number of transformers is 5; and one set of transformation parameters includes the parameters of two transformers with the same parameters. That is, the cascade inverter transformer model S1 is calculated in a time division multiplexing method to obtain the transformer secondary voltage, secondary current, and primary current.

[0080] The transformer consists of three windings, and its topology is shown in Figure 2 . It is recorded as primary winding 1, secondary winding 2, and secondary winding 3, where the output voltage of secondary winding 2 is used as the input voltage of the post-stage rectifier model S2. The primary winding is the first winding, the secondary winding 2 is the second winding, and the secondary winding 3 is the third winding; where, Figure 21-6 extending from the left side are interfaces; linearTransformer1, linearTransformer2 and linearTransformer3 are transformers, which can be linear transformers; A, B, C represent phase A, phase B and phase C of three-phase electricity respectively, and U1a, U1b, U1c are similar, representing phase A, phase B and phase C of three-phase electricity respectively.

[0081] In the transformer model S1, the input three-phase voltage is U a , U b , U c ; The three-phase current of secondary winding 2 is I A , I B , I C , which is the first current mentioned above; the secondary winding 3 currents are I1, I2, I3 respectively; the primary winding current is I PA , I PB , I PC .U SECAB , U SECBC , U SECCA is the feedback line voltage of the rectifier model S2, that is, the voltage after the output secondary winding inductance, which is the above-mentioned second voltage, U secAB , U secBC , U secCA is the voltage before the output secondary inductor, that is, it is the above-mentioned first voltage; U am , U bm , U bm is the primary excitation voltage of the three phases A, B, and C; K1 and K2 are the transformation ratios of the two secondary windings to the primary winding; R PA , R PB , R PC is the three-phase primary winding resistance, L PA , L PB , L PC is the three-phase primary winding inductance, R A2 , R B2 , R C2 is the three-phase second winding resistance, L A2 , L B2 , L C2 is the three-phase second winding inductance, R A3 , R B3 , R C3 is the three-phase third winding resistance, L A3 , L B3 , L C3 is the inductance of the three-phase third winding, that is, the transformation parameters may include: K1, K2 are the transformation ratios of the two secondary windings to the primary winding; R PA , R PB , RPC is the three-phase primary winding resistance, L PA , L PB , L PC is the three-phase primary winding inductance, R A2 , R B2 , R C2 is the three-phase second winding resistance, L A2 , L B2 , L C2 is the three-phase second winding inductance, R A3 , R B3 , R C3 is the three-phase third winding resistance, L A3 , L B3 , L C3 It is the three-phase third winding inductance, etc.

[0082] Since time division multiplexing is used to implement the calculation, each clock calculates two transformer modules of each phase inverter. The transformer calculation of the 10-level inverter requires a total of 5 clocks to complete one operation. The model operation step is 1e-7s, so the model equivalent simulation step is 5e-7s, and the sampling period of the calculus discretization model in the model needs to be set to 5e-7s. In order to ensure the consistency of the clock, the voltage input sampling rate of the model needs to be changed to 5e-7s, while the actual calculation period remains 1e-7s.

[0083] The calculation method for each transformer is the same. The first clock calculates the 1st and 10th level transformers. Then the same logic is used to calculate the 2nd, 9th, 3rd, 8th, 4th, 7th, 5th, 6th level transformers in sequence. Each calculation updates the corresponding transformer parameters. The specific calculation steps for each transformer model S1 are as follows:

[0084] From the secondary current relationship, we can get:

[0085]

[0086] From the secondary voltage relationship, we can get:

[0087]

[0088] The input voltage of the rectifier, that is, the voltage before the secondary winding inductance, the first voltage, can be calculated by formula (3):

[0089]

[0090] The three-phase current of the second winding can be obtained by formula (4):

[0091]

[0092] Correspondingly, the third winding current can be obtained from the secondary current relationship formula (4) by substituting the corresponding parameters.

[0093] The primary current can be calculated using the current formula (5):

[0094]

[0095] Three-phase excitation voltage U am , U bm , U cm It can be solved by formula (6):

[0096]

[0097] Combining the above formulas (1)-(6), we can calculate U SECAB , U SECBC , U SECCA , that is, the voltage after the output secondary winding inductance, and the input three-phase voltage U a , U b , U c , and then the primary / secondary three-phase current and the input voltage U of the rectifier model S2 can be solved secAB , U secBC , U secCA , that is, the voltage before the output secondary inductor.

[0098] In the second stage, the rectifier model S2 is used to receive the first voltage and the first current and the third current fed back by the inverter model S3, and output the third voltage, the second current and the second voltage after rectification. That is, the rectifier model S2 takes the secondary three-phase current and the secondary inductor voltage of the transformer model S1 as input, outputs the bus voltage and current to the inverter model S3 as input, and outputs the transformer secondary inductor voltage as the transformer model S1 input. The specific implementation method is as follows:

[0099] First, the current is calculated: when the phase current of the secondary winding 2 is greater than 0, this phase is connected and the current is equal to the phase current; otherwise, it is disconnected and the current is 0. The total current of the DC bus bridge IDC, that is, the second current, that is, I in each secondary winding 2 A , I B , I C The sum is the sum of all currents in the on-state. It should be noted that the phase current is any phase current among the three-phase currents.

[0100] According to the load current I rectifier Calculate the DC bus voltage U dc , that is, the third voltage, is used as the input of the inverter model S3 and is calculated according to formula (7):

[0101]

[0102] Where, C is the bus capacitance value of the inverter, and I rectifier Current fed back to the motor model.

[0103] Secondly, the voltage calculation can be performed according to the following table logic:

[0104] First, calculate the voltage per phase to ground according to the following table, where U secAB , U secBC , U secCA is the voltage before the secondary inductor of transformer model S1, I A , I B , I C is the secondary output current of the transformer model S1, which is the output of the transformer model S1 in the first stage. The diode is turned off by comparing with the threshold. The threshold in the model is ±1A. See Table 1-Table 3:

[0105] Table 1:U A- The value of

[0106]

[0107] Table 2:U B- The value of

[0108]

[0109] Table 3: U C- The value of

[0110]

[0111] Then, the second voltage required for transformer model S1 calculation is calculated according to formula (8).

[0112] U SECAB =U B- -U A-

[0113] U SECBC =U C- -U B-

[0114] U SECCA =U A- -U C- Formula (8)

[0115] Among them, UA- is the voltage after the first phase secondary inductor in the rectifier model S2; UB- is the voltage after the second phase secondary inductor in the rectifier model S2; UC- is the voltage after the third phase secondary inductor in the rectifier model S2. It should be noted that this application is explained using three-phase electricity as an example, so the voltage and current are both three-phase; when this application is applied to other phase electricity, such as five-phase, its specific formula process will not be repeated here one by one, and it is all within the protection scope of this application.

[0116] like Figure 4 As shown, it shows the structure of the rectifier in the rectifier model S2. Among them, the three phases of the rectifier unit receive three-phase electricity through corresponding inductors respectively; A, B, C represent the A phase, B phase and C phase of the three-phase electricity respectively; + represents the positive pole, - represents the negative pole, and 1-3 extending from the left side of the figure are all interfaces.

[0117] In the third stage, the inverter model S3 is used to receive the third voltage, the second current and the three-phase load current fed back by the external motor model, and output the fourth voltage and the third current after inversion; wherein the fourth voltage acts on the external motor model. Specifically, the inverter model S3 calculation consists of a voltage calculation part and a current calculation part, and the specific implementation method is as follows:

[0118] The inverter model S3 uses an H-bridge inverter, and its topology is shown in Figure 3 Q1, Q2, Q3 and Q4 are all switch tubes, U dc is the DC bus voltage in the inverter, U o is the output voltage of the inverter, + represents the positive pole and - represents the negative pole.

[0119] The input of the voltage calculation part is DC voltage, that is, the rectifier model S2 calculates the DC bus voltage output of the rectifier, and the four bridge arm control signals g1, g2, g3, g4, and the load current i Load and current threshold i yuzhi . Among them, g1 and g2 control the on and off of the upper and lower switches of the left bridge arm; that is, g1 controls the on and off of switch Q1, and g2 controls the on and off of switch Q2; g3 and g4 control the on and off of the upper and lower switches of the right bridge arm; that is, g3 controls the on and off of switch Q3, and g4 controls the on and off of switch Q4. The output voltage difference between the left and right bridge arms to the ground, that is, Uleft bridge arm-Uright bridge arm=calculate the inverter output voltage, and the load current i Load and current threshold i yuzhi is a constant.

[0120] The left and right bridge arm voltage to ground judgment logic is shown in Table 4-Table 5:

[0121] Table 4: Left bridge arm voltage to ground judgment logic

[0122]

[0123] Table 5: Right bridge arm voltage to ground judgment logic

[0124]

[0125] Since each sub-inverter requires four PWM input signals g1, g2, g3, and g4, the model is built using time division multiplexing. The entire model is calculated in 5 simulation cycles. In each cycle, the A, B, and C three-phase inverters 1, 10; 2, 9; 3, 8; 4, 7; 5, 6 groups of inverter PWM are input in turn to calculate the voltage output of the corresponding sub-inverter. After the calculation is completed, they are added to obtain the total three-phase voltage output of the inverter, that is, the fourth voltage output.

[0126] The input of the current calculation part is the feedback phase current I of the motor Load , according to the bridge arm PWM signal and feedback current, the output current of each phase is determined as the load current input I of the rectifier model S2 rectifier , that is, the load current input I rectifier is the third current, which is brought into the rectifier model S2 for calculation. The calculation logic is shown in Table 6:

[0127] Table 6: Load current input calculation logic

[0128]

[0129] It should be noted that after the third stage, the motor model will also perform corresponding calculations, and the specific implementation method is as follows:

[0130] The voltage output calculated in the third stage is used as the voltage input of the motor. The motor model can be any motor. The fed-back three-phase load current of the motor is brought into the inverter model S3 for calculation to complete the closed-loop calculation of the cascade inverter.

[0131] The features recorded in the various embodiments in this specification can be replaced or combined with each other, and the same and similar parts between the various embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative work.

[0132] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0133] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An N-cascade inverter SG model based on time division multiplexing, characterized in that: include: Transformer model, rectifier model and inverter model; wherein N=2n, n is a positive integer; The transformer model is used to use N / 2 groups of transformation parameters as input parameters in sequence in a time division multiplexing manner, and receive the second voltage fed back by the rectifier model, and output the first voltage and the first current after transformation adjustment on the second voltage and the input parameters; wherein the number of transformers is N; and one group of transformation parameters includes parameters of two transformers with the same parameters; The rectifier model is used to receive the first voltage, the first current and the third current fed back by the inverter model, and output the third voltage, the second current and the second voltage after rectification; The inverter model is used to receive the third voltage, the second current and the three-phase load current fed back by the external motor model, and output a fourth voltage and the third current after inversion; wherein the fourth voltage acts on the external motor model.

2. The N-cascade inverter SG model based on time division multiplexing according to claim 1 is characterized in that: The transformer model is used to use N / 2 groups of transformation parameters as input parameters in sequence in a time division multiplexing manner, and receive the second voltage fed back by the rectifier model, and output the first voltage and the first current after performing transformation adjustment on the second voltage and the input parameters, specifically for: At the i-th clock, the parameters of the i-th transformer and the (Ni)+1-th transformer are used as input parameters, and a second voltage fed back by the rectifier model is received, and the second voltage and the input parameters are transformed and adjusted to output a first voltage and a first current; i=i+1, returning to the step of executing the i-th clock, taking the parameters of the i-th transformer and the parameters of the (Ni)+1-th transformer as input parameters, receiving the second voltage fed back by the rectifier model, and performing voltage transformation adjustment on the second voltage and the input parameters to output the first voltage and the first current; Until i+1 is greater than N / 2, the initial value of i is 1.

3. The N-cascade inverter SG model based on time division multiplexing according to claim 2 is characterized in that: N＝10。 4. The N-cascade inverter SG model based on time division multiplexing according to claim 3 is characterized in that: The operation step size of the transformer model is 1e-7s; the equivalent simulation step size and voltage input sampling period of the N-cascade inverter SG model are both 5e-7s.

5. The N-cascade inverter SG model based on time division multiplexing according to claim 3 is characterized in that: At the i-th clock, the parameters of the i-th transformer and the parameters of the (Ni)+1-th transformer are used as input parameters, and the second voltage fed back by the rectifier model is received, and the second voltage and the input parameters are transformed and adjusted to output the first voltage and the first current, specifically used for: Input the parameters of the i-th transformer into the first transformer calculation unit, and input the parameters of the (Ni)+1-th transformer into the second transformer calculation unit; After the first transformer calculation unit and the second transformer calculation unit perform the voltage transformation adjustment calculation, a first voltage and a first current are obtained.

6. The N-cascade inverter SG model based on time division multiplexing according to claim 1 is characterized in that: The voltage before the secondary inductance of the transformer is used as the first voltage; The output current of the secondary winding of the transformer serves as the first current.

7. The N-cascade inverter SG model based on time division multiplexing according to claim 1 is characterized in that: The voltage after the secondary inductance of the rectifier in the rectifier model is used as the second voltage; The bus voltage and current of the rectifier are used as the third voltage and the second current respectively.

8. The N-cascade inverter SG model based on time division multiplexing according to claim 1 is characterized in that: The output voltage of the inverter in the inverter model is used as the fourth voltage; and the output current of the inverter is used as the third current.

9. The N-cascade inverter SG model based on time division multiplexing according to claim 8, characterized in that: The external controller outputs corresponding PWM waves to the inverter model in the order of N / 2 groups of transformation parameters input into the transformer model.

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