Multilayer ceramic sintered body substrate, electronic device, chip resistor, and manufacturing method

Abstract

The present disclosure provides a laminated ceramic sintered body substrate for electronic devices, an electronic device, a chip resistor, and a method for manufacturing a chip resistor. The laminated ceramic sintered body substrate for electronic devices includes a ceramic sintered body substrate and a planarization film provided on an upper surface of the ceramic sintered body substrate, the planarization film containing a thermally conductive filler.

Description

Technical Field

[0001] This disclosure relates to a multilayer ceramic sintered substrate for electronic devices, electronic devices, chip resistors, and a method for manufacturing chip resistors. Background Technology

[0002] A portion of an electronic device, such as a chip resistor, is formed on a ceramic sintered substrate exhibiting high strength and insulation. For example, a thin-film chip resistor includes an insulating substrate, a pair of upper electrodes disposed at both ends of the upper surface of the insulating substrate, and a resistive element disposed on the upper surface of the insulating substrate and connected between the pair of upper electrodes.

[0003] The chip resistor further comprises: a protective film configured to at least cover the resistive element; a pair of end face electrodes disposed on both ends of an insulating substrate in a manner electrically connected to a pair of upper electrodes; and a plating layer formed on a portion of the upper electrodes and the surface of the pair of end face electrodes.

[0004] In the manufacturing of the aforementioned electronic devices, after forming multiple structures including resistors on the surface of a large ceramic sintered substrate, the substrate is cut into a grid pattern by a cutting blade, or a grid pattern of dividing grooves is pre-formed on the ceramic sintered substrate, and the substrate is divided along the dividing grooves to obtain a single-piece element.

[0005] However, since ceramic sintered substrates are manufactured by sintering ceramic particles together with various binders, the surface of the ceramic sintered substrate has fine unevenness and undulations caused by the shape of the ceramic particles, resulting in a rough surface. This leads to the problem of unstable shapes for the surface electrodes and resistors formed on the surface of the ceramic sintered substrate. In particular, when surface electrodes and resistors are formed into thin films on the surface of the ceramic sintered substrate using film deposition processes and photolithography, the surface electrodes and resistors, being thin films, are affected by the surface condition of the alumina substrate, resulting in localized deformation, uneven film thickness, cracks, etc., thus causing deviations and defects in performance.

[0006] To solve the above problems, for example, Patent Document 1 proposes a technique in which an alumina substrate itself contains a trace amount of silica glass, a glass coating is formed on the entire surface of the alumina substrate, and an upper electrode, a resistor, etc. are formed on the glass coating.

[0007] Prior art literature

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2017-168749 Summary of the Invention

[0010] The embodiments of this disclosure relate to a multilayer ceramic sintered substrate for electronic devices, comprising: a ceramic sintered substrate; and a planarization film disposed on the upper surface of the ceramic sintered substrate, comprising a thermally conductive filler. Attached Figure Description

[0011] Figure 1 This is a schematic cross-sectional view of a laminated ceramic sintered substrate for electronic devices according to one embodiment of this disclosure.

[0012] Figure 2 This is a schematic cross-sectional view of a chip resistor according to one embodiment of the present disclosure.

[0013] Figure 3 This is a chip resistor according to one embodiment of the present disclosure. Figure 2 Schematic diagram of XX cross section.

[0014] Figure 4 This is an example of a scanning electron microscope image showing a cross-section of a laminated ceramic sintered substrate for electronic devices in the embodiment.

[0015] Figure 5 This is a graph showing the thermal simulation results confirming the effect of the planarization film with thermally conductive filler in the embodiment.

[0016] Figure 6 This is an example diagram of a ceramic sintered substrate.

[0017] Figure 7 This is a graph showing the thermal conductivity and coefficient of linear expansion of representative ceramics, etc.

[0018] Symbol Explanation

[0019] 1: Ceramic sintered substrate;

[0020] 2: Planarization film;

[0021] 3: Thermally conductive filler;

[0022] 4: Resistor;

[0023] 5: Upper electrode;

[0024] 6: Lower electrode;

[0025] 7: End face electrode;

[0026] 8: Protective film;

[0027] 11: Laminated ceramic sintered substrate;

[0028] 21: Chip resistor. Detailed Implementation

[0029] In recent years, electronic devices, such as those used in automotive applications, have demanded higher reliability and increased power output in harsh environments. Consequently, the thermal load on the components of these electronic devices has increased, thus requiring appropriate external heat dissipation.

[0030] In the alumina substrate and glass coating constituting the chip resistor in Patent Document 1, the thermal conductivity of the alumina substrate is, for example, 26 W / (m·K), while the thermal conductivity of the glass (SiO2) is, for example, about 0.01 W / (m·K). The thermal conductivity of the glass coating is much lower than that of the alumina substrate. Therefore, under high thermal loads on the component structure, heat dissipation is insufficient, which may result in deterioration of component characteristics and ultimately breakage.

[0031] This disclosure was made in view of the above, and its purpose is to provide electronic devices such as chip resistors with excellent heat dissipation and to suppress the adverse effects on characteristics caused by the unevenness of the surface of the ceramic sintered body substrate, a method for manufacturing chip resistors, and a laminated ceramic sintered body substrate for use in electronic devices such as chip resistors.

[0032] In order to achieve electronic devices such as chip resistors with excellent heat dissipation and to suppress the adverse effects on characteristics caused by the surface unevenness of the ceramic sintered body substrate, in particular, we have conducted in-depth research on laminated ceramic sintered body substrates used in such electronic devices. The results showed that it is sufficient to have the aforementioned laminated ceramic sintered body substrate having a ceramic sintered body substrate and a planarization film containing thermally conductive filler disposed on the upper surface of the ceramic sintered body substrate. Furthermore, hereinafter, "laminated ceramic sintered body substrate for electronic devices" will sometimes be referred to simply as "laminated ceramic sintered body substrate".

[0033] According to embodiments of the present disclosure, it is possible to provide electronic devices such as chip resistors with excellent heat dissipation and to suppress adverse effects on characteristics caused by unevenness on the surface of the ceramic sintered body substrate, a method for manufacturing chip resistors, and a laminated ceramic sintered body substrate for use in electronic devices such as chip resistors.

[0034] Hereinafter, the laminated ceramic sintered substrate and the chip resistor having the laminated ceramic sintered substrate according to the embodiments of this disclosure will be described with reference to the accompanying drawings. Figure 1 The following description will be provided. Furthermore, the embodiments of this disclosure are not limited to those shown in the following figures, and appropriate modifications can be made without compromising the effects of this disclosure. In the following description, the same structural parts are labeled with the same symbols, and descriptions are omitted where appropriate.

[0035] [Laminated ceramic sintered substrate]

[0036] First, use Figure 1 The laminated ceramic sintered body substrate in one embodiment of the present disclosure will be described. The laminated ceramic sintered body substrate 11 in one embodiment of the present disclosure has… Figure 1 The structure shown is such that a planarization film 2 containing thermally conductive filler 3 is formed on the entire upper surface of the laminated ceramic sintered substrate 11.

[0037] (Ceramic sintered substrate)

[0038] The type of ceramic in the ceramic sintered body substrate 1 is not limited. For example, a ceramic sintered body substrate may be used as a substrate having... Figure 6 The physical properties of the ceramic sintered body substrates shown in Table 1 include alumina substrates, alumina-zirconia substrates, silicon nitride substrates, and aluminum nitride substrates. The preferred ceramic sintered body substrate is an alumina substrate. Furthermore, even if the type of ceramic is the same, differences in the particle size of the ceramic particles and the density of the ceramic particles in the ceramic sintered body can sometimes result in physical properties that differ from the values ​​in Table 1.

[0039] The aforementioned ceramic sintered substrate 1 is manufactured by mixing various ceramic particles and a binder, forming the mixture, and then sintering it. The surface of the ceramic sintered substrate has unevenness due to the shapes of the ceramic particles constituting the sintered body. As an example of a ceramic sintered substrate, the surface roughness Ra of an alumina substrate (A476) manufactured by Kyocera Corporation is 0.3 to 0.5 micrometers, and the surface roughness Ra of an alumina substrate (A493) with another product number is 0.05 to 0.08 micrometers. In embodiments of this disclosure, a planarization film is provided on the upper surface of the aforementioned ceramic sintered substrate 1 as described below, thereby enabling, for example, the provision of upper electrodes and resistors regardless of the surface condition of the ceramic sintered substrate.

[0040] (Planarization film)

[0041] In embodiments of this disclosure, a planarization film 2 is formed on the upper surface of the ceramic sintered substrate 1. By forming the planarization film 2, the material constituting the planarization film 2 is filled into the recesses on the surface of the ceramic sintered substrate 1, and the unevenness of the surface of the planarization film 2 becomes smaller than that of the surface of the ceramic sintered substrate 1. Therefore, according to embodiments of this disclosure, the upper electrode and the resistor can be formed on the surface of the planarization film 2, which suppresses unevenness, without being affected by the surface condition of the ceramic sintered substrate 1.

[0042] The material constituting the parent phase (substrate) of the planarization film 2 (hereinafter sometimes referred to as the "substrate material") is not particularly limited. During the manufacture of the planarization film 2, it tends to change shape due to firing at high temperatures; therefore, the substrate material is preferably a material with a small difference in thermal expansion coefficient compared to the aforementioned ceramic sintered substrate. Examples of the parent phase of the planarization film 2 include silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0043] (The thermally conductive filler contained in the planarization film)

[0044] The primary requirement for the thermally conductive filler 3 is high thermal conductivity. The thermal conductivity needs to be higher in the planarization film 2 due to the presence of the thermally conductive filler 3 compared to a planarization film without the thermally conductive filler 3. Therefore, the thermally conductive filler 3 needs to exhibit higher thermal conductivity than the parent phase of the planarization film 2.

[0045] The material constituting the thermally conductive filler 3 is not particularly limited as long as it meets the above-mentioned characteristics. As the thermally conductive filler, for example, one or more compounds selected from the group consisting of zinc oxide (ZnO), magnesium oxide (MgO), barium oxide (BeO), aluminum nitride (AlN), boron nitride (BN), silicon nitride (SiNx), and diamond can be used.

[0046] exist Figure 7 Table 2 shows the thermal conductivity and coefficient of linear expansion of representative ceramics, etc. When the parent phase of the planarization film 2 is, for example, silicon dioxide (SiO2 (molten)), the thermal conductivity of this parent phase is 1.3 W / (m·K), so the material constituting the thermally conductive filler 3 needs to be a material with a thermal conductivity higher than 1.3 W / (m·K). Furthermore, when the parent phase of the planarization film 2 is, for example, alumina (Al2O3), the thermal conductivity of this parent phase is 32 W / (m·K), so the material constituting the thermally conductive filler 3 needs to be a material with a thermal conductivity higher than 32 W / (m·K). Table 2 also provides representative examples of the thermal conductivity and coefficient of linear expansion of representative ceramics, etc., but the thermal conductivity and coefficient of linear expansion described below may sometimes exhibit different values ​​due to the manufacturing methods and structures of various companies.

[0047] The size, such as the average particle size, of the thermally conductive filler 3 is not particularly limited. Since the surface unevenness of the ceramic sintered substrate is at the level of several μm, the average particle size of the thermally conductive filler 3 is preferably 10 μm or less, more preferably 2 μm or less. It is further preferred that the average particle size of the thermally conductive filler 3 is less than or equal to the average particle size of the ceramic particles constituting the parent phase of the planarization film 2. This is because if the particle size of the thermally conductive filler 3 is significantly larger than the size of the ceramic particles constituting the parent phase of the planarization film 2 or the surface unevenness of the ceramic sintered substrate 1, the surface roughness of the planarization film 2 increases, sometimes making smoothing difficult. The average particle size of the thermally conductive filler used in the planarization film formation and the average particle size of the particles used in the parent phase formation can be determined by photographic observation based on dynamic light scattering, laser diffraction, BET method, or scanning electron microscopy (SEM) or transmission electron microscopy (TEM).

[0048] In the formation of the planarization film, it is preferable to use a thermally conductive filler with an average particle size less than the average particle size of the parent phase particles used to form the planarization film. For example, commercially available fillers ranging from tens of nm to tens of μm can be used as this thermally conductive filler. The average particle size of the thermally conductive filler 3 in the planarization film 2 is substantially the same as the average particle size of the thermally conductive filler used in the formation of the planarization film. The average particle size of the thermally conductive filler 3 in the planarization film 2 and the average particle size of the ceramic particles constituting the parent phase of the planarization film 2 can be determined by means of photographic observation using a scanning electron microscope (SEM). In determining the average particle size of the thermally conductive filler 3 in the planarization film 2, elemental analysis can also be used to distinguish between the thermally conductive filler 3 and the parent phase of the planarization film 2.

[0049] The shape of the thermally conductive filler 3 is not particularly limited. Examples of shapes for the thermally conductive filler 3 include spherical, fibrous, polygonal, flat, and scaly shapes. Depending on the shape of the thermally conductive filler 3, when it appears on the outermost surface of the planarization film 2, the surface roughness may sometimes increase. Therefore, the shape of the thermally conductive filler 3 can be selected based on the unevenness of the ceramic sintered substrate 1, the thickness of the planarization film 2, and the desired thermal conductivity.

[0050] The thermally conductive filler is preferably electrically insulating. That is, the inherent volume resistivity of the thermally conductive filler is preferably greater than 10 Ω·cm. +13 Ω / cm. In applications requiring voltage withstand characteristics, such as those found in chip resistors, using conductive materials, such as metal particles, as the thermally conductive filler creates a conductive path, which degrades the voltage withstand characteristics and is therefore not preferred.

[0051] There is no particular limitation on the proportion of thermally conductive filler 3 in the planarization film 2. A higher proportion of thermally conductive filler 3 in the planarization film 2 results in higher thermal conductivity, but the proportion of the parent phase in the planarization film 2 is relatively reduced, and the strength of the planarization film 2 is prone to decrease. Therefore, the proportion of thermally conductive filler 3 in the planarization film 2 can be appropriately determined according to the required thermal conductivity and strength of the planarization film 2.

[0052] As the thermally conductive filler 3, multiple types of thermally conductive fillers with at least one different material, size, and shape can be used. For example, by combining thermally conductive fillers with different particle sizes and shapes, the effect of filling the voids in the planarized film can be obtained, the effective density can be increased, and the thermal conductivity can be increased.

[0053] The surface of a typical sintered ceramic substrate has unevenness at a level of several μm. Therefore, the thickness of the planarization film is preferably greater than or equal to the height of the unevenness on the sintered ceramic substrate. The thickness of the planarization film also depends on the height of the unevenness, but is preferably, for example, 1.0 μm or more. There is no particular limitation on the upper limit of the thickness of the planarization film, but the thickness of the planarization film can be, for example, set to 20 μm or less.

[0054] The method for forming a planarization film 2 containing thermally conductive filler 3 on a ceramic sintered substrate 1 is not particularly limited. From the viewpoint that the unevenness of the surface of the ceramic sintered substrate is efficiently filled by the material constituting the planarization film 2 and a planarization film 2 in which thermally conductive filler 3 is dispersed is formed, it is preferable to form the planarization film by the sol-gel method. The sol-gel method is a type of ceramic synthesis method, and compared with conventional melting and sintering methods, it can produce planarization films at lower temperatures. Furthermore, since the raw materials are in a solution state, it is possible to produce planarization films with thinner thicknesses.

[0055] For forming the planarization film 2 containing the thermally conductive filler 3 as disclosed herein, particles for forming the parent phase of the planarization film 2 and the thermally conductive filler 3 for improving the thermal conductivity of the planarization film are mixed in a sol solution.

[0056] In the formation of the planarization film, as mentioned above, it is preferable to use a thermally conductive filler with an average particle size less than the average particle size of the parent phase forming particles of the planarization film to easily achieve smoothing.

[0057] Regarding the aforementioned thermally conductive filler 3, various pretreatments, such as surface modification, can be performed before mixing it with the particles formed from the parent phase used for planarizing the film 2. Examples of such pretreatments include hydrophilization treatment, hydrophobic treatment, or adjustment of surface charge. Through such pretreatment, advantages such as improved dispersibility of the thermally conductive filler and uniform thermal conductivity in the planarized film can be obtained.

[0058] [Electronic Components]

[0059] In embodiments of this disclosure, there are electronic devices having the aforementioned multilayer ceramic sintered substrate for electronic devices. Examples of such electronic devices include chip resistors.

[0060] use Figure 2 as well as Figure 3 A chip resistor in one embodiment of this disclosure will be described. Figure 2 This is a schematic cross-sectional view of a chip resistor according to one embodiment of this disclosure. Figure 3 It is the aforementioned Figure 2 A schematic cross-sectional view of the XX section. This chip resistor is located at... Figure 1 The resistive element, etc., is formed on the laminated ceramic sintered substrate 11 shown. Therefore, for... Figure 2 The description of the laminated ceramic sintered substrate 11 is omitted.

[0061] In one embodiment of this disclosure, the chip resistor 21 has... Figure 2 The structure shown is such that the chip resistor 21 comprises: a multilayer ceramic sintered body substrate 11 for electronic devices, having a ceramic sintered body substrate 1 and a planarization film 2 containing thermally conductive filler 3; a resistive element 4 and a pair of upper electrodes 5 disposed on the side of the planarization film 2 opposite to the side of the ceramic sintered body substrate 1; and a pair of end electrodes 7 disposed in the stacking direction of the multilayer ceramic sintered body substrate 11 and the upper electrodes 5, connected to their ends.

[0062] The aforementioned resistive element 4 is disposed on the upper surface of the laminated ceramic sintered substrate 11 and connected between a pair of upper electrodes 5. The pair of upper electrodes 5 are disposed at both ends of the upper surface of the laminated ceramic sintered substrate 11 for electronic devices on which the resistive element 4 is formed. Figure 2 As shown, a pair of lower electrodes 6 can also be disposed at both ends of the back surface of the laminated ceramic sintered substrate 11 opposite to the upper surface. A pair of end face electrodes 7 are disposed at both ends of the laminated ceramic sintered substrate 11 in a manner electrically connected to a pair of upper electrodes 5. Furthermore, although the aforementioned... Figure 2 The chip resistor 21 illustrated herein is provided with a lower electrode 6, but the chip resistors involved in this disclosure may also not have a lower electrode 6.

[0063] The resistive element 4 can be selected from materials that meet the target resistivity and temperature coefficient of resistance (TCR). As an example, materials with a low TCR include thin-film materials primarily composed of Ni, Cr, Al, and Si, such that the Ni / Cr ratio is 45 / 55 to 55 / 45 by weight, Al contains 10 to 18% by weight relative to the total weight, and Si contains 2 to 6% by weight relative to the total weight. Other examples of materials for the resistive element include materials with a high TCR. Materials with a high TCR include pure metals of Pt, Ni, and Cu, and alloys containing 50% by weight or more of each metal, such as Pt-Co alloys. Resistive elements formed from these materials can function as surface mount resistors and can also be used as resistive elements for temperature measurement.

[0064] Alternatively, an adjustment slot for adjusting the resistance value can be provided in the resistor body 4, and the resistor body 4 can also have, for example, a groove for adjusting the resistance value. Figure 3 Such a tortuous structure (bent shape) 4a.

[0065] Regarding the heat generated in the resistor 4, as the main path, heat is dissipated from the end electrode 7 to the substrate on which the chip resistor 21 is mounted, via the resistor 4 or the laminated ceramic sintered substrate 11 below the resistor 4. The material of the resistor 4 is determined according to the required electrical characteristics, and therefore it is difficult to determine the material from the viewpoint of improving heat dissipation. Therefore, in order to improve the heat dissipation performance of the laminated ceramic sintered substrate 11, which is another path, in order to expand the operating temperature range and increase the applied power, it is useful to improve the heat dissipation performance of the chip resistor.

[0066] In particular, when the resistor 4 has a tortuous structure 4a, the heat generated at the center of the resistor 4, especially the tortuous structure 4a, is dissipated only through the resistor, requiring a very long path through the resistor. In such cases where heat dissipation from the resistor alone is difficult, the embodiment of this disclosure, in which the laminated ceramic sintered substrate 11 is connected to the resistor 4, improves heat dissipation, allowing full utilization of the effects brought about by the embodiment of this disclosure.

[0067] The thickness of the planarization film 2 is preferably greater than the thickness of the resistive element 4. As a result, the heat capacity of the planarization film 2 becomes greater than that of the resistive element 4, and consequently, the temperature of the planarization film 2 easily becomes lower than that of the resistive element 4, enabling efficient heat dissipation.

[0068] The upper electrode 5 is not particularly limited as long as it meets the characteristics of the target resistor. As an example, a thin film electrode made of Cu-based alloys such as Cu or CuNi can be used. This thin film electrode can be formed, for example, by methods based on sputtering, electron beam evaporation, or resistance heating evaporation. In addition, in order to improve the adhesion between the thin film electrode and the planarization film 2, a metal thin film such as Cr, Ti, or Ni can be used as the adhesion layer as the lower layer of the thin film electrode.

[0069] As described Figure 2 As shown, when a lower electrode 6 is provided, the lower electrode 6 is not particularly limited as long as it meets the characteristics of the target resistor. As an example, a thin-film electrode made of Cu-based alloys such as Cu or CuNi can be cited. This thin-film electrode can be formed, for example, by methods based on sputtering, electron beam evaporation, or resistance heating evaporation. Furthermore, to improve the adhesion between the thin-film electrode and the ceramic sintered substrate 1, a metal thin film such as Cr, Ti, or Ni can be used as the adhesion layer as the lower layer of the thin-film electrode.

[0070] A pair of end-face electrodes 7 are electrodes disposed on both end faces of the laminated ceramic sintered substrate 11 and electrically connected to the upper surfaces of a pair of upper electrodes 5, and are formed, for example, of Ag. The end-face electrodes 7 can be formed, for example, by printing onto a material composed of Ag and resin. Alternatively, they can be formed by sputtering onto a metal material. In the case of forming a pair of lower electrodes 6, the pair of end-face electrodes 7 are also connected to the pair of lower electrodes 6.

[0071] To improve the heat dissipation effect of the laminated ceramic sintered substrate 11, it is preferable that at least one of the upper electrode 5 and the end electrode 7 is in contact with the planarization film 2, and more preferably both the upper electrode 5 and the end electrode 7 are in contact with the planarization film 2. Regarding the contact area between the planarization film 2 and the upper electrode 5 and the end electrode 7, in particular, the larger the contact area between the planarization film 2 and the end electrode 7, the more heat moves from the planarization film 2 to the end electrode 7, which serves as the final heat dissipation path, thus enabling effective heat dissipation.

[0072] The protective film 8 is formed to protect the resistor 4 from the effects of oxygen and humidity. Materials for the protective film 8 can include resins, Al2O3, SiNx, and other inorganic compounds. Alternatively, both resins and inorganic compounds can be used.

[0073] Although the above Figure 2 as well as Figure 3 Although not shown, a plating layer can be further formed on the upper surface of the aforementioned end-face electrode 7. This plating layer can be formed using conventional methods.

[0074] According to the laminated ceramic sintered substrate in the embodiments of this disclosure, heat generated from the component structure formed on the ceramic sintered substrate can be effectively dissipated to the outside, suppressing adverse effects caused by the unevenness of the ceramic sintered substrate. Therefore, by using the laminated ceramic sintered substrate according to the embodiments of this disclosure in electronic devices, the temperature characteristics of the electronic devices can be improved and the occurrence of component defects can be suppressed. Furthermore, if the laminated ceramic sintered substrate according to the embodiments of this disclosure is used in resistors, the usable temperature range and rated power can be expanded.

[0075]

Example

[0076] The embodiments described below illustrate the implementation of this disclosure in more detail. The implementation of this disclosure is not limited to the following embodiments and can be implemented with appropriate modifications that conform to the foregoing and the spirit described below, all of which are included within the scope of the technology disclosed.

[0077] (Example 1)

[0078] The following manufacturing method is used to produce laminated ceramic sintered substrates.

[0079] First, as the substrate for ceramic sintering, an alumina substrate with excellent heat resistance and insulation properties is used, and it is inexpensive to obtain.

[0080] A planarization film was formed on the aforementioned ceramic sintered substrate as follows: First, AlN nanoparticles (center diameter 100 nm, determined by scanning electron microscopy) prepared by thermal plasma method were added to polysilazane (NN120, manufactured by Merck Co., Ltd.), and stirred to achieve uniform dispersion, thereby preparing a planarization film forming solution. Then, the planarization film forming solution was treated with a spin coater at 3000 rpm for 20 seconds. Afterward, it was dried on a hot plate set to 100°C for 30 seconds, and then sintered in an electric drying oven at 700°C for 12 hours to form a planarization film containing AlN nanoparticles as a thermally conductive filler and with a silica substrate.

[0081] A cross-section of a laminated ceramic sintered substrate having a planarization film on a ceramic sintered substrate, as described above, was observed using a scanning electron microscope (S-5000, Hitachi High Technology Co., Ltd.). An example of the scanning electron microscope image is shown below. Figure 4 From. Figure 4It has been confirmed that, regarding the laminated ceramic sintered substrate involved in the embodiments of this disclosure, the unevenness of the alumina substrate surface indicated by dashed line A is filled by the material constituting the planarization film, as shown by dashed line B, and the surface of the planarization film is smoother than the surface of the alumina substrate indicated by dashed line A.

[0082] (Example 2)

[0083] For the multilayer ceramic sintered substrate produced in Example 1, a resistive element was formed as described below, and a chip resistor was manufactured.

[0084] A thin film composed of NiCrAlSi alloy was fabricated on a planarized film of a laminated ceramic sintered substrate by sputtering. Next, a resistive body was obtained by patterning the thin film into a tortuous structure using photolithography (resist coating, drying, exposure, development, etching, and resist stripping). Subsequently, a heat treatment was performed at 300°C for 5 hours to obtain a given temperature coefficient of resistance (TCR).

[0085] Furthermore, an upper electrode is formed on the planarization film as described above. First, a CuNi alloy film is formed on the planarization film by sputtering, followed by the aforementioned photolithography. The film formation by sputtering can be performed instead of photolithography, allowing film to be formed only in the desired areas using a metal mask.

[0086] Furthermore, a lower electrode is formed on the side of the alumina substrate opposite to the surface where the upper electrode is formed, similarly to the upper electrode. That is, a CuNi alloy film is formed by sputtering, followed by the aforementioned photolithography. The film formation performed by sputtering can be used instead of photolithography, allowing film formation only in the desired areas using a metal mask.

[0087] Next, a metal oxide film is formed on the resistive body by sputtering as a protective film. In this embodiment, an Al2O3 film is formed as the protective film, but as long as the protective performance can be achieved, it can also be a metal oxide film other than Al2O3, such as SiNx.

[0088] Regarding the processes up to this point, in order to improve efficiency, multiple layers of the aforementioned resistors, upper electrodes, lower electrodes, and protective films are formed on a large alumina substrate.

[0089] Next, in order to obtain individual chip resistors, a large alumina substrate with the aforementioned multiple layers is cut to obtain individual chips. Then, in order to form the end electrodes of each chip, a conductive paste containing Ni-based metal particles or Ag-based metal particles and a resin as a binder is coated onto the ends of the stacked ceramic sintered substrate, the upper electrode, and the lower electrode, and then cured. Subsequently, an electroplating process is performed to form Ni and Sn layers, thereby obtaining chip resistors.

[0090] (Example 3)

[0091] To evaluate the performance of the aforementioned chip resistors, thermal simulations were performed. ANSYS (ANSYS Inc.) was used as the simulation software.

[0092] The thermal simulation was performed with the chip resistor mounted on the Cu pad pattern on the printed circuit board using solder. The chip resistor measures 1 mm × 0.5 mm × 0.3 mm. The main structure of the chip resistor is the same as in Example 2. Specifically, an alumina substrate is used as the ceramic sintered body substrate, and the planarization film on the alumina substrate has a thickness of 5 μm and a thermal conductivity of 120 W / (m·K). The resistive element on the planarization film has a thickness of 1 μm and a thermal conductivity of 120 W / (m·K), with CuNi used as the upper electrode and Ni used as the end electrode. Furthermore, Example 3 differs from Example 2 in that it does not have a lower electrode, but the presence or absence of a lower electrode does not significantly affect the self-generated heat of the component obtained through thermal simulation.

[0093] Furthermore, as a comparative example, a simulation was also performed on a model of a 5 μm thick alumina layer with a thermal conductivity of 26 W / (m·K) (thermal conductivity of alumina) and no thermally conductive filler. The results were then presented in [the relevant section]. Figure 5 As shown in the image.

[0094] Figure 5 These are stability simulation results for the cases of forming a planarization film containing thermally conductive filler with a thermal conductivity of 120 W / (m·K) and forming a planarization film without thermally conductive filler with a thermal conductivity of 26 W / (m·K). At an input power of 0.2 W, approximately 3.2 times the assumed rated input power, a decrease of approximately 4.8% in element self-heating temperature was observed, from 72.9°C without thermally conductive filler to 69.5°C with thermally conductive filler. This verifies the effects of the embodiments of this disclosure.

[0095] Furthermore, in the above embodiment 3, due to simulation limitations, the film thickness of the resistive element was set to 1 μm. However, in actual chip resistors, there are cases where the film thickness of the resistive element is as thin as tens of nm. When the film thickness is so thin, heat dissipation cannot be expected solely through the resistive element. In such cases, it is believed that the superior heat dissipation effect exhibited by the laminated ceramic sintered substrate of this disclosure can be more significantly utilized.

[0096] (Example 4)

[0097] In Example 4, a chip resistor was obtained in which the resistive element was made of Pt, and the etching and heat treatment conditions in the process were changed. The chip resistor used a multilayer ceramic sintered substrate with the same structure as in Examples 1 and 2, except for the etching and heat treatment conditions. By adopting this chip resistor structure, it was confirmed that smoothing could be achieved, and that the advantage of a large thermal conductivity (TCR) of the resistive element could be effectively utilized for temperature measurement. Furthermore, it was confirmed that due to the high thermal conductivity of the multilayer ceramic sintered substrate itself, the resistance value's responsiveness to external temperature changes was improved.

[0098] Industrial availability

[0099] The laminated ceramic sintered substrate disclosed herein exhibits excellent heat dissipation and can suppress adverse effects on characteristics caused by unevenness or irregularity of the ceramic sintered substrate. Therefore, it is useful as a substrate component for use in electronic devices. Furthermore, it is also useful as a chip resistor utilizing the aforementioned laminated ceramic sintered substrate.

Claims

1. A laminated ceramic sintered body substrate for electronic devices, comprising: a ceramic sintered body substrate; and a planarization film provided on an upper surface of the ceramic sintered body substrate, containing a thermally conductive filler, the thermally conductive filler being one or more compounds selected from the group consisting of zinc oxide ZnO, magnesium oxide MgO, barium oxide BeO, boron nitride BN, silicon nitride SiNx, and diamond, a mother phase of the planarization film including silicon dioxide SiO2 or aluminum oxide Al2O3.

2. The laminated ceramic sintered body substrate for electronic devices according to claim 1, wherein the ceramic sintered body substrate is an aluminum oxide sintered body substrate.

3. The laminated ceramic sintered body substrate for electronic devices according to claim 1 or 2, wherein the thermally conductive filler is electrically insulating.

4. An electronic device, comprising the laminated ceramic sintered body substrate for electronic devices according to any one of claims 1 to 3.

5. A chip resistor, comprising: the laminated ceramic sintered body substrate for electronic devices according to any one of claims 1 to 3; a resistance body and a pair of upper electrodes provided on a surface of the planarization film of the laminated ceramic sintered body substrate for electronic devices opposite to the ceramic sintered body substrate side; and a pair of end surface electrodes provided so as to contact end portions of the laminated ceramic sintered body substrate for electronic devices, the upper electrodes in a laminating direction thereof.

6. The chip resistor according to claim 5, wherein a thickness of the planarization film is greater than a thickness of the resistance body.

7. The chip resistor according to claim 5 or 6, wherein the resistance body has a meandering configuration.

8. The chip resistor according to claim 5 or 6, wherein the planarization film is in contact with at least one of the upper electrodes and the end surface electrodes.

9. A method of manufacturing a chip resistor, the method of manufacturing a chip resistor according to any one of claims 5 to 8, wherein a planarization film is formed by a sol-gel method.

10. The method of manufacturing a chip resistor according to claim 9, wherein in the formation of the planarization film, a thermally conductive filler having an average particle diameter smaller than an average particle diameter of particles for forming a mother phase of the planarization film is used. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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