Fan-out package structure

Abstract

Embodiments of the present application provide a fan-out package structure, comprising: a substrate; a first electronic component and a second electronic component on the substrate; a reinforcing structure on the substrate and surrounding all sidewalls of the first electronic component and the second electronic component, the reinforcing structure being integral. The purpose of the present application is to provide a fan-out package structure to at least achieve improved yield of the fan-out package structure.

Description

Technical Field

[0001] Embodiments of this application relate to fan-out packaging structures. Background Technology

[0002] Currently, in post-chip process fan-out packaging structures, especially in fan-out chip-on-substrate (FOCOS) packaging structures, there is a problem of filler material cracking. During high-temperature processes, the filler material expands, causing delamination and cracking at the interface between it and electronic components, which then leads to further damage. Summary of the Invention

[0003] In view of the problems existing in related technologies, the purpose of this invention is to improve the yield of fan-out packaging structures.

[0004] An embodiment of this application provides a fan-out package structure, including: a substrate; a first electronic component and a second electronic component located on the substrate; and a reinforcing structure located on the substrate and surrounding all sidewalls of the first electronic component and the second electronic component, wherein the reinforcing structure is integral.

[0005] In some embodiments, it further includes a filler layer located between the substrate and the first electronic component and the second electronic component.

[0006] In some embodiments, the reinforcing structure has a plurality of openings, and a filling layer is located in the openings.

[0007] In some embodiments, the first portion of the opening is located on the inner sidewall of the reinforcing structure facing the first electronic component or the second electronic component.

[0008] In some embodiments, the filling layer located in the first portion of the opening is in contact with the first electronic component or the second electronic component.

[0009] In some embodiments, the filler layer fills the lower portion of the opening.

[0010] In some embodiments, it further includes: a molding layer located on the upper surface of the first electronic component and the second electronic component, the molding layer filling the upper portion of the opening.

[0011] In some embodiments, the system further includes a circuit layer located between the substrate and the reinforcement structure, with a filler layer contacting the upper surface of the circuit layer.

[0012] In some embodiments, the sidewalls of the circuit layer and the sidewalls of the molding layer are flush.

[0013] In some embodiments, the lateral dimension of the substrate is larger than the lateral dimension of the circuit layer.

[0014] In some embodiments, the reinforcing structure is higher than the first electronic component and the second electronic component.

[0015] In some embodiments, the reinforcing structure is higher than the second electronic element and lower than the first electronic element.

[0016] In some embodiments, in a top view, the adjacent sidewalls of the first electronic component and the second electronic component are parallel.

[0017] In some embodiments, the active surfaces of the first and second electronic components face the substrate.

[0018] Embodiments of this application also provide a method for forming a fan-out package structure, comprising: providing a reinforcing structure; disposing a first electronic component and a second electronic component within a first cavity and a second cavity of the reinforcing structure, wherein the reinforcing structure contacts the first electronic component and the second electronic component; and disposing the reinforcing structure, the first electronic component, and the second electronic component on a substrate.

[0019] In some embodiments, placing the first electronic component and the second electronic component within the first cavity and the second cavity includes: heating the reinforcing structure; placing the first electronic component and the second electronic component within the first cavity and the second cavity; and cooling the reinforcing structure such that the reinforcing structure and the first electronic component and the second electronic component come into contact.

[0020] In some embodiments, the lateral dimension of the first cavity is larger than the lateral dimension of the second cavity.

[0021] In some embodiments, the reinforcing structure includes fibers.

[0022] In some embodiments, the lateral dimensions of the first cavity and the second cavity gradually decrease from top to bottom.

[0023] In some embodiments, the sidewalls of the first cavity and the second cavity are inclined.

[0024] In some embodiments, the first electronic component and the second electronic component are flush with the bottom surface of the reinforcing structure. Attached Figure Description

[0025] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0026] Figures 1 to 23 The process of forming a fan-out package structure according to an embodiment of this application is shown.

[0027] Figures 24 to 27 A schematic diagram of a fan-out package structure according to different embodiments of this application is shown. Detailed Implementation

[0028] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0029] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0030] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0031] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0032] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0033] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0034] During the heating process, the bending stress of the fan-out package structure is amplified to the effective stress (amplified to 1.5 to 3 times) by the stress concentration factor. During both heating and cooling, the bending stress is caused by the thermal torque. The stress concentration factor Kt at the corner of the electronic component is 1.5 to 3.

[0035] The fan-out packaging structure and its formation method of this application will be described in detail below with reference to the accompanying drawings.

[0036] See Figure 1 The release layer 12 is located on the first carrier 10, and the reinforcing structure 14 is disposed on the release layer 12. The first carrier 10 may be a glass carrier substrate, a ceramic carrier substrate, etc. The first carrier 10 may be a wafer, thereby allowing multiple encapsulation structures to be formed simultaneously on the first carrier 10. The release layer 12 may be formed of a polymer-based material, which may be removed from the above structure along with the first carrier 10 in subsequent steps. In some embodiments, the release layer 12 is a thermally release material based on epoxy resin that loses its adhesiveness upon heating, such as a photothermal conversion (LTHC) release coating. In other embodiments, the release layer 12 may be a UV adhesive that loses its adhesiveness upon exposure to UV light. The release layer 12 may be dispensed and cured in liquid form, may be a laminated film laminated on the first carrier 10, or may be similar. The top surface of the release layer 12 may be horizontal and may have a high degree of flatness. The reinforcing structure 14 has a first cavity 16 and a second cavity 18. In some embodiments, the material of the reinforcing structure 14 includes synthetic glass (CTE: 4-7), TiO2 (CTE: 4-5), AlSiC (CTE: 6.5-7), Fe2O3 (CTE: 4-5), Cr alloy (CTE: 6-6.5), AlN (CTE: 4-5), CaO (CTE: 5-6), SiC (CTE: 4.2-4.8), W alloy (CTE: 4.5-5), Si3N4 (CTE: 3.5-4), NiO (CTE: 4-5), carbon fiber composite (CTE: 3.5-4), Al2O3 (CTE: 4-5), Si (CTE: 2.6-4), or combinations thereof.

[0037] See Figure 2A and Figure 2B , Figure 2A This is a top view, showing that the reinforcing structure 14 is a single piece. Figure 2B It is along Figure 2AA cross-sectional view of line A-A'. In some embodiments, the lateral dimension of the first cavity 16 is larger than the lateral dimension of the second cavity 18. In some embodiments, the reinforcing structure 14 includes fibers 20. In some embodiments, the fibers 20 are glass fibers with high structural strength. In some embodiments, the reinforcing structure 14 includes a first partial opening 22 and a second partial opening 24, the first partial opening 22 being located on the sidewalls of the first cavity 16 and the second cavity 18, and the second partial opening 24 surrounding the first cavity 16 and the second cavity 18. In some embodiments, as Figure 2A The steps shown involve placing the reinforcing structure 14 on the first carrier 10, and then using a cutter 28 to cut the reinforcing structure 14 and the first carrier 10 to form a monolithic structure. In some embodiments, only the first portion of the opening 22 exists, and the second portion of the opening 24 does not exist.

[0038] Figures 2C to 2G It shows Figure 2A Enlarged view of the dashed box 26, in which, Figure 2C The cross-section of the first opening 22 shown is rectangular. Figure 2D The cross-section of the first portion of the opening 22 shown is part of an ellipse. Figure 2E The cross-section of the first opening 22 shown is triangular. Figure 2F The cross-section of the first part of the opening 22 shown is irregular in shape. Figure 2G The cross-section of the first portion of the opening 22 shown is a row of square holes. The shape of the cross-section of the first portion of the opening 22 is not limited to the shape shown.

[0039] Figure 2H A top view is shown according to different embodiments of this application, and... Figure 2A The difference is, Figure 2A In the embodiment shown, the adjacent sidewalls of the first cavity 16 and the second cavity 18 are parallel, and the two second cavities 18 have the same size. Figure 2H In the illustrated embodiment, the adjacent sidewalls of the first cavity 16 and one of the second cavities 18 are not parallel, and the two second cavities 18 have different dimensions. In some embodiments, the number of first cavities 16 and second cavities 18 is not limited to the number shown in the figure.

[0040] See Figure 3A and Figure 3B ,in, Figure 3A It is a top view. Figure 3B It is along Figure 3A A cross-sectional view taken along line B-B'. A heating process 31 is applied to the reinforcing structure 14, causing the first cavity 16 and the second cavity 18 in the heated structure 14 to expand. A clamping member 33 is used to place the second electronic component 30 in the second cavity 18. In some embodiments, a vacuum cavity 35 is provided between the clamping member 33 and the second electronic component 30.

[0041] See Figure 4 The heating process 31 continues, and the first electronic component 40 is placed in the first cavity 16 using the clamping member 33. In some embodiments, the first electronic component 40 is an application-specific integrated circuit (ASIC) chip, and the second electronic component 30 is a high bandwidth memory (HBM) die.

[0042] See Figure 5A and Figure 5B ,in, Figure 5A It is a top view. Figure 5B It is along Figure 5A A cross-sectional view taken along the C-C' line. Cooling process 51 is performed to reduce the size of the reinforcing structure 14 to contact all sidewalls of the first electronic component 40 and the second electronic component 30. A first partial opening 22 remains between the reinforcing structure 14 and the first electronic component 40 and the second electronic component 30.

[0043] See Figure 6 The clamping member 33 is used to hold the first electronic component 40, the second electronic component 30, and the reinforcing structure 14 to detach them from the first carrier 10. In some embodiments, a vacuum cavity 35 is provided between the clamping member 33 and the first electronic component 40, the second electronic component 30, and the reinforcing structure 14.

[0044] See Figure 7 A first conductive pattern 72 is formed on the second carrier 70. In some embodiments, the material of the second carrier 70 is similar to that of the first carrier 10. In some embodiments, the material of the first conductive pattern 72 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. The first conductive pattern 72 may be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing, lamination, and / or potting.

[0045] See Figure 8 A first dielectric layer 80 is formed on the second carrier 70 and the first conductive pattern 72. In some embodiments, the first dielectric layer 80 may include a polyamide (PA) material, and the first dielectric layer 80 is subjected to an exposure process 81 for curing.

[0046] See Figure 9The first dielectric layer 80 is patterned to expose the first conductive pattern 72, and a first seed layer 90 is formed on the first conductive pattern 72 and the first dielectric layer 80. A first mask 92 is formed on the first seed layer 90. In some embodiments, the first mask 92 is a photoresist (PR), and an exposure process 91 is performed to cure the first mask 92.

[0047] See Figure 10 A first mask 92 is patterned to expose a first seed layer 90, and a first metal layer 100 is formed on the first seed layer 90. In some embodiments, the materials of the first seed layer 90 and the first metal layer 100 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. The first metal layer 100 may be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing, lamination, and / or potting.

[0048] See Figure 11 Remove the first mask 92 and pattern the first seed layer 90 using the first metal layer 100 as a mask.

[0049] See Figure 12 The second dielectric layer 126, the second seed layer 122, and the second metal layer 124 are formed using steps and processes similar to those used for the first node 80, the first seed layer 92, and the first metal layer 100. At this point, the circuit layer 120 is formed.

[0050] See Figure 13 The first electronic component 40, the second electronic component 30, and the reinforcing structure 14 are placed on the circuit layer 120 using the clamping member 33. In some embodiments, the vacuum cavity 35 is located between the clamping member 33 and the first electronic component 40, the second electronic component 30, and the reinforcing structure 14.

[0051] See Figure 14A and Figure 14B ,in, Figure 14A It is a top view. Figure 14B It is along Figure 14A A cross-sectional view of the D-D' line. The D-D' line cuts through the second portion of the opening 24. In some embodiments, an underfill layer 140 is formed between the first electronic component 40, the second electronic component 30, and the circuit layer 120. In some embodiments, the underfill layer 140 is formed in the lower portions of the first and second portion openings 22 and 24.

[0052] See Figure 15A molding layer 150 encapsulates the reinforcing structure 14, the first electronic component 40, and the second electronic component 30. In some embodiments, the molding layer 150 fills the upper portions of the first partial opening 22 (not shown in this cross-section) and the second partial opening 24. The molding layer 150 and the filler layer 140 filling the first partial opening 22 and the second partial opening 24 can increase structural strength. The first electronic component 40 and the second electronic component 30 are protected by two sealants, and the filler layer 140 has high structural strength to resist stress. In some embodiments, the molding layer 150 is not formed.

[0053] See Figure 16 Remove the second carrier 70.

[0054] See Figure 17 A third seed layer 170 is formed on the circuit layer 120, and a second mask 172 is formed on the third seed layer 170. In some embodiments, the second mask 172 is a photoresist (PR), and an exposure process 171 is performed to cure the second mask 172. In some embodiments, the material of the third seed layer 170 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. The third seed layer 170 may be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating (E'less), and / or printing, lamination, and / or potting.

[0055] See Figure 18 A second mask 172 is patterned to expose a third seed layer 170. A third metal layer 180 and solder 182 are formed on the third seed layer 170. In some embodiments, the material of the third metal layer 180 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, or combinations thereof. The third metal layer 180 may be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing, lamination, and / or potting. In some embodiments, the material of the solder 182 includes Cu.

[0056] See Figure 19 Remove the second mask 172 and pattern the third seed layer 170 using solder 182 and the third metal layer 180 as masks.

[0057] See Figure 20 Solder 182 is subjected to a reflow process 201 to form solder balls. Figures 7 to 20In the illustrated embodiment, a circuit layer 120 of a single unit is used as an example for illustration. In actual production, multiple reinforcing structures 14 and a first electronic component 40 and a second electronic component 30 are provided on the circuit layer 120. Figure 20 After the steps shown, a monolithic process is then performed to form a single-unit structure as shown in the figure.

[0058] See Figure 21 The circuit layer 120 and its structure are placed on the substrate 210. In some embodiments, the clamping member 31 holds the molding layer 150, and a vacuum cavity 35 exists between the clamping member 31 and the molding layer 150.

[0059] See Figure 22 In some embodiments, the circuit layer 120 is electrically connected to the substrate 210 via solder 182. In some embodiments, a molding compound 220 is formed between the circuit layer 120 and the substrate 210, and the molding compound encapsulates the solder 182.

[0060] See Figure 23 A back-side connector 230 is formed on the back side of the substrate 210. In some embodiments, the back-side connector 230 is a solder ball. Figures 21 to 23 In the illustrated embodiment, a single-unit substrate 210 is used as an example for illustration. In actual production, the substrate 210 is provided with multiple circuit layers 210 and reinforcing structures 14 thereon, as well as first electronic components 40 and second electronic components 30 therein. After completion... Figure 23 Following the steps shown, a monolithic process is then performed to form a single-unit fan-out package structure 2300 as shown in the figure. In some embodiments, the lateral dimension of the fan-out package structure 2300 is 50 mm to 80 mm, the height of the reinforcing structure 14 is 20 μm to 200 μm, the distance between the first electronic component 40, the second electronic component 30 and the circuit layer 120 is 5 μm to 50 μm, the ratio of the lateral dimension of the second electronic component 30 to the distance between the first electronic component 40 and the second electronic component 30 is 0.2 to 20, the coefficient of thermal expansion (CTE) of the fan-out package structure 2300 is 1 ppm to 10 ppm, the difference between the bottom surface of the reinforcing structure 14 and the first electronic component 40 and the second electronic component 30 is less than 3 μm, and the angle α between the sidewall of the reinforcing structure and the horizontal plane is 60°-90°. In some embodiments, the lateral dimensions of the first cavity 16 and the second cavity 18 gradually decrease along the direction close to the circuit layer 120.

[0061] Figure 24 It shows the relationship with Figure 23 Different implementations, in Figure 24 The first electronic component 40 includes an active surface Bailey circuit layer 120 and also includes a second connector 240 located on the first electronic component 40.

[0062] Figure 25 It shows the relationship with Figure 23 Different implementations, in Figure 25 In the middle, the first electronic component 40 is higher than the second electronic component 30 and higher than the reinforcing structure 14, and the first electronic component 40 is flush with the top surface of the molding layer 150.

[0063] Figure 26 It shows the relationship with Figure 23 Different implementations, in Figure 26 In this configuration, there is no filler layer 140. The molding layer 150 is located between the reinforcing structure 14 and the circuit layer 120 and extends over the first electronic component 40 and the second electronic component 30. The molding layer 150 fills all the space of the first partial opening 22 (this section is not shown) and the second partial opening 24.

[0064] See Figure 27 A fourth metal layer 270 is formed on the molding layer 150. The material of the fourth metal layer 270 can be Cu, Au, Ag, Al, Pd, Pt, Ni, their alloys, or combinations thereof. The fourth metal layer 270 can be formed using processes such as physical vapor deposition (PVD), sputtering, electroplating, electroless plating, and / or printing, lamination, and / or potting.

[0065] Embodiments of this application employ a low-CTE reinforcing structure 14 to firmly grip the first electronic component 40 and the second electronic component 30 and provide a flat surface to avoid concentration coefficients. Furthermore, the edges of the first electronic component 40, the second electronic component 30, and the reinforcing structure 14 are filled with a filler layer 140 and / or a molding layer 150 to seal and secure the electronic components.

[0066] The reinforcing structure 14 of this application embodiment protects the first electronic component 40 and the second electronic component 30 in the horizontal direction, reducing structural warpage. The CTE of the first electronic component 40 and the second electronic component 30 in this application embodiment is lower than the CTE of the reinforcing structure 14, the filler layer 140, and the molding layer 150. The filler layer 140 or the molding layer 150 fills the space between the first electronic component 40 and the second electronic component 30, protecting the bridging wires of the wiring layer 120 located directly below the space between the first electronic component 40 and the second electronic component. The filler layer 140 is higher than the bottom surface of the first electronic component 40 and the second electronic component 30, increasing structural strength.

[0067] In the embodiments of this application, the first electronic component 40 and the second electronic component 30 are first placed in the reinforcing structure 14 and fixed. On the one hand, the relative position between the first electronic component 40 and the second electronic component 30 can be fixed. On the other hand, the reinforcing structure 14 can absorb the stress generated by the expansion of the filler layer 140 / molding layer 150 in the subsequent thermal process.

[0068] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fan-out type packaging structure, characterized in that, include: Substrate; The first electronic component and the second electronic component are located on the substrate; A reinforcing structure is located on the substrate and surrounds all sidewalls of the first and second electronic components; the reinforcing structure is integral. The reinforcing structure has a first cavity and a second cavity, as well as a plurality of openings. The first electronic component and the second electronic component are located in the first cavity and the second cavity, respectively. A first portion of the plurality of openings is located on the inner wall of the first cavity facing the first electronic component and / or the inner wall of the second cavity facing the second electronic component, and a second portion of the plurality of openings surrounds the first cavity and the second cavity.

2. The fan-out packaging structure according to claim 1, characterized in that, Also includes: A filler layer is located between the substrate and the first electronic component and the second electronic component.

3. The fan-out packaging structure according to claim 2, characterized in that, The filling layer is located in the opening.

4. The fan-out packaging structure according to claim 3, characterized in that, The filling layer located in the first partial opening is in contact with the first electronic component or the second electronic component.

5. The fan-out packaging structure according to claim 3, characterized in that, The filling layer fills the lower portion of the opening.

6. The fan-out packaging structure according to claim 5, characterized in that, Also includes: A molding layer is located on the upper surfaces of the first electronic component and the second electronic component, and the molding layer fills the upper portion of the opening.

7. The fan-out packaging structure according to claim 6, characterized in that, Also includes: A circuit layer is located between the substrate and the reinforcing structure, and the fill layer contacts the upper surface of the circuit layer.

8. The fan-out packaging structure according to claim 7, characterized in that, The sidewalls of the circuit layer and the sidewalls of the molding layer are flush.

9. The fan-out packaging structure according to claim 7, characterized in that, The lateral dimension of the substrate is larger than the lateral dimension of the circuit layer.

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