An SV transmission control method and device for an intelligent substation merging unit

Abstract

The present invention discloses a method and device for controlling the SV transmission of a merging unit in a smart substation. The method includes the following steps: obtaining the latest transmission timestamp of the FPGA; calculating the timestamp difference between the FPGA and the CPU based on the pre-transmission timestamp of the CPU; determining whether the timestamp difference is greater than a first preset duration for a first preset number of consecutive times; if so, determining that the SV transmission of the FPGA is abnormal and performing a reset operation on the FPGA; if not, controlling the FPGA to send an SV packet. By judging the timestamp difference between the CPU and the FPGA in the merging unit to determine whether the SV transmission is normal, the problem that the SV transmission is interrupted due to the runaway of the SV transmission logic state machine of the FPGA is solved; the reliability of the SV transmission of the merging unit is improved, the reliability of the data source of the smart substation is enhanced, and the safe and stable operation of the smart substation is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent substation control, and particularly relates to a method and device for controlling the SV transmission of a merging unit in an intelligent substation. Background Art

[0002] With the wide application of intelligent substations in substations of various voltage levels, since 2012, the construction of intelligent substations has moved from the planning and pilot stage to the full-scale construction stage. During the construction of intelligent substations in the planning and pilot stage, the standards for process layer equipment have been gradually improved. The State Grid Corporation has promulgated relevant standards such as the "Technical Guide for Intelligent Substations" and the "Technical Specification for Relay Protection in Intelligent Substations". The standards clearly state that protection should directly sample, that is, the so-called sampling point-to-point method. The equipment in operation has been running for nearly 10 years. Facing various on-site operating environments, in harsh operating environments, in addition to the hardware being damaged due to long years of use, there are occasionally problems with the suspension of SV transmission. As the data source for protection criteria, the merging unit has a great impact on the reliable operation of intelligent substations.

[0003] Intelligent substations have high requirements for the time synchronization, time keeping, and sampling value transmission of the merging unit. A constant temperature crystal oscillator must be used. The constant temperature crystal oscillator operates at 120°C for a long time. In abnormal working conditions such as harsh electromagnetic interference, the crystal oscillator occasionally jitters. When the frequency is multiplied to 100M through the IP core inside the FPGA chip (the IP core is the intellectual property core or intellectual property module), after long-term statistics, it is found that the deviation of 2ms per second occurs. Calculated based on 4000 frames of data per second on average, the dispersion of each frame of SV data will have a deviation of 0.5us. If calculated according to the non-average principle, the interval deviation of individual frame messages may be greater than 10us, which affects the tick count of the data sent by the FPGA and poses a risk of the FPGA timing running wild and the state machine running wild, and further leads to the risk of SV data suspension. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a method and device for controlling the SV transmission of a merging unit in an intelligent substation. By judging the time scale difference between the CPU and the FPGA in the merging unit to determine whether the SV transmission is normal, it solves the problem that the SV transmission logic state machine of the FPGA runs wild and causes the SV transmission to be interrupted; improves the reliability of the SV transmission of the merging unit, enhances the reliability of the data source of the intelligent substation, and ensures the safe and stable operation of the intelligent substation.

[0005] To solve the above technical problems, the first aspect of the embodiments of the present invention provides a method for controlling the SV transmission of a merging unit in an intelligent substation, including the following steps:

[0006] Obtain the latest transmission time scale of the FPGA;

[0007] Calculate the time stamp difference between the FPGA and the CPU according to the pre-transmission time stamp of the CPU;

[0008] Judge whether the time stamp difference is greater than the first preset duration for the first preset number of consecutive times;

[0009] If so, determine that the FPGA sends SV abnormally, and perform a reset operation on the FPGA;

[0010] If not, control the FPGA to send the SV packet.

[0011] Further, before obtaining the latest transmission time stamp of the FPGA, it further includes:

[0012] Judge whether the FPGA is performing a reset operation;

[0013] If so, exit the SV transmission;

[0014] If not, calculate the time stamp difference between the FPGA and the CPU.

[0015] Further, before performing the reset operation on the FPGA, it further includes:

[0016] Judge whether the number of times of the reset operation is greater than the second preset number of times;

[0017] If so, send a failure report of the SV transmission;

[0018] If not, perform the reset operation on the FPGA.

[0019] Further, after performing the reset operation on the FPGA, it further includes:

[0020] Clear the number of times that the time stamp difference exceeds the first preset duration, and clear the number of times of the reset operation.

[0021] Correspondingly, a second aspect of the embodiment of the present invention provides an SV transmission control device for an intelligent substation merging unit, including:

[0022] An acquisition module, which is used to acquire the latest transmission time stamp of the FPGA;

[0023] A calculation module, which calculates the time stamp difference between the FPGA and the CPU according to the pre-transmission time stamp of the CPU;

[0024] A first judgment module, which is used to judge whether the time stamp difference is greater than the first preset duration for the first preset number of consecutive times;

[0025] A control module, which is used to determine that the FPGA sends SV abnormally and perform a reset operation on the FPGA when the time scale difference is continuously greater than a first preset duration for a first preset number of times;

[0026] The control module is further used to control the FPGA to send the SV packet when the time scale difference is not continuously greater than the first preset duration for the first preset number of times.

[0027] Further, the intelligent substation merging unit SV sending control device further includes:

[0028] A second judgment module, which is used to judge whether the FPGA is performing a reset operation;

[0029] When the FPGA is performing a reset operation, the control module controls the FPGA to exit the SV sending;

[0030] When the FPGA is not performing a reset operation, the acquisition module acquires the latest sending time scale of the FPGA.

[0031] Further, the intelligent substation merging unit SV sending control device further includes:

[0032] A third judgment module, which is used to judge whether the number of reset operations is greater than a second preset number;

[0033] When the number of reset operations is greater than the second preset number, the control module sends a failure report of the SV sending;

[0034] When the number of reset operations is less than or equal to the second preset number, the control module performs the reset operation on the FPGA.

[0035] Further, after performing the reset operation on the FPGA, the control module also clears the number of times that the time scale difference exceeds the first preset duration and clears the number of reset operations.

[0036] Correspondingly, a third aspect of the embodiments of the present invention provides an electronic device, including: at least one processor; and a memory connected to the at least one processor; wherein, the memory stores instructions executable by the one processor, and the instructions are executed by the one processor to enable the at least one processor to execute the above-mentioned intelligent substation merging unit SV sending control method.

[0037] Correspondingly, a fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, on which computer instructions are stored, and when the instructions are executed by a processor, the above-mentioned intelligent substation merging unit SV sending control method is implemented.

[0038] The above technical solution of the embodiment of the present invention has the following beneficial technical effects:

[0039] By judging the time scale difference between the CPU and the FPGA in the merging unit to determine whether the SV transmission is normal, the problem that the SV transmission interruption occurs due to the runaway of the SV transmission logic state machine of the FPGA is solved; the reliability of the SV transmission of the merging unit is improved, the reliability of the data source of the intelligent substation is enhanced, and the safe and stable operation of the intelligent substation is guaranteed. Description of the Drawings

[0040] Figure 1 is a flowchart of the SV transmission control method for the merging unit of the intelligent substation provided by the embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the reset mechanism architecture for the CPU and the FPGA to cooperate to control the SV transmission provided by the embodiment of the present invention;

[0042] Figure 3 is a logic diagram of the SV transmission control for the merging unit of the intelligent substation provided by the embodiment of the present invention;

[0043] Figure 4 is a block diagram of the modules of the SV transmission control device for the merging unit of the intelligent substation provided by the embodiment of the present invention.

[0044] Reference Signs:

[0045] 1. Acquisition module, 2. Calculation module, 3. First judgment module, 4. Control module, 5. Second judgment module, 6. Third judgment module. Detailed Embodiments

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention.

[0047] Please refer to Figure 1 and Figure 2 , the first aspect of the embodiment of the present invention provides a method for controlling the SV transmission of the merging unit of an intelligent substation, including the following steps:

[0048] S200. Obtain the latest transmission time scale of the FPGA.

[0049] S300. Calculate the time scale difference between the FPGA and the CPU based on the pre-transmission time scale of the CPU.

[0050] S400, determine whether the time stamp difference is continuously greater than the first preset duration for the first preset number of times.

[0051] S500, if so, determine that the FPGA sends SV abnormally and perform a reset operation on the FPGA.

[0052] S600, if not, control the FPGA to send SV packet assembly.

[0053] Furthermore, before obtaining the latest transmission time stamp of the FPGA, it also includes:

[0054] S110, determine whether the FPGA is performing a reset operation.

[0055] S120, if so, exit SV transmission.

[0056] S130, if not, calculate the time stamp difference between the FPGA and the CPU.

[0057] Furthermore, before performing a reset operation on the FPGA, it also includes:

[0058] S510, determine whether the number of reset operations is greater than the second preset number of times.

[0059] S520, if so, send an SV transmission failure report.

[0060] S530, if not, perform a reset operation on the FPGA.

[0061] Furthermore, after performing a reset operation on the FPGA, it also includes:

[0062] S700, clear the number of times the time stamp difference exceeds the first preset duration and clear the number of reset operations.

[0063] Please refer to Figure 3 , in this embodiment, the CPU interacts with the FPGA for control signals and data signals through the bus. The CPU uses a common crystal oscillator to judge the tick count sent by the FPGA. The FPGA uses a temperature-controlled crystal oscillator to convert the original 100M clock into a 40M clock signal through an IP core to generate the SV transmission tick count, greatly increasing the time processing margin of the FPGA data signal by frequency reduction. The specific reset mechanism is as follows:

[0064] (1) Add a reset SV transmission logic function to the FPGA part: The FPGA provides the latest SV transmission tick (for the CPU to read); provides an FPGA reset SV transmission logic interface (for the CPU to write a reset command); according to the reset command, the FPGA performs a reset operation: clears the SV receive and transmit buffers and related registers and variables, re-initializes the DM9000 chip, and self-clears the reset command; the FPGA provides a flag indicating that the SV transmission logic is being reset (for the CPU to determine that the FPGA reset operation is completed); the overall function of the FPGA program is downclocked from 100M to 40M.

[0065] (2) In the CPU part, determine the SV transmission exception of the FPGA chip and reset the FPGA after an exception. The specific requirements are as follows: In the CPU software SV transmission logic, determine whether the CPU pre-transmission timestamp is consistent with the actual transmission timestamp of the FPGA; if the absolute value of the difference between the CPU pre-transmission timestamp and the latest transmission timestamp of the FPGA is greater than the first preset duration (10us) for the first preset number of times (3 times) continuously, it is confirmed that the FPGA transmits SV abnormally; when it is confirmed that the SV transmission is abnormal, write a reset command to the FPGA and no longer write SV data to the FPGA buffer until the FPGA reset is completed; determine that the FPGA initializes the DM9000 and start sending SV data to the FPGA buffer; if the reset count is greater than 3 times, no longer reset and report a "SV transmission failure" report.

[0066] The present invention proposes a method for improving the reliability of SV transmission in an intelligent substation merging unit. By assisting the mode to control the FPGA state machine and the reset mechanism of the DM9000 (taking the DM9000 chip as an example in this embodiment, but not limited to this chip), through downclocking the FPGA main program, the cooperative reset mechanism of the CPU and the FPGA, and the initialization of the DM9000 chip, it solves the problem that the 100M clock doubled inside the FPGA jitters due to the crystal oscillator clock jitter, which in turn causes the SV transmission logic state machine of the FPGA to run away and the SV transmission to interrupt. It improves the reliability of the SV transmission of the merging unit, enhances the reliability of the data source of the intelligent substation, and ensures the safe and stable operation of the intelligent substation.

[0067] Correspondingly, please refer to Figure 4, in the second aspect of the embodiments of the present invention, a control device for SV transmission of an intelligent substation merging unit is provided, including: an acquisition module 1, a calculation module 2, a first judgment module 3, and a control module 4. Among them, the acquisition module 1 is used to acquire the latest transmission timestamp of the FPGA. The calculation module 2 calculates the timestamp difference between the FPGA and the CPU based on the pre-transmission timestamp of the CPU. The first judgment module 3 is used to judge whether the timestamp difference is greater than a first preset duration for a first preset number of consecutive times. The control module 4 is used to determine that the FPGA sends SV abnormally and perform a reset operation on the FPGA when the timestamp difference is greater than the first preset duration for a first preset number of consecutive times. The control module 4 is further used to control the FPGA to send SV packets when the timestamp difference is not greater than the first preset duration for a first preset number of consecutive times.

[0068] Further, the control device for SV transmission of the intelligent substation merging unit further includes: a second judgment module 5. The second judgment module 5 is used to judge whether the FPGA is performing a reset operation. The control module 4 controls the FPGA to exit SV transmission when the FPGA is performing a reset operation. The acquisition module 1 acquires the latest transmission timestamp of the FPGA when the FPGA is not performing a reset operation.

[0069] Further, the control device for SV transmission of the intelligent substation merging unit further includes: a third judgment module 6. The third judgment module 6 is used to judge whether the number of reset operations is greater than a second preset number. The control module 4 sends an SV transmission failure report when the number of reset operations is greater than the second preset number. The control module 4 performs a reset operation on the FPGA when the number of reset operations is less than or equal to the second preset number.

[0070] Further, after performing a reset operation on the FPGA, the control module 4 also clears the number of times the timestamp difference exceeds the first preset duration and clears the number of reset operations.

[0071] Correspondingly, in the third aspect of the embodiments of the present invention, an electronic device is provided, including: at least one processor, and a memory connected to at least one processor. Among them, the memory stores instructions executable by one processor, and the instructions are executed by one processor to enable at least one processor to execute the above-mentioned method for controlling SV transmission of the intelligent substation merging unit.

[0072] Correspondingly, in the fourth aspect of the embodiments of the present invention, a computer-readable storage medium is provided, on which computer instructions are stored, and when the instructions are executed by a processor, the above-mentioned method for controlling SV transmission of the intelligent substation merging unit is implemented.

[0073] An embodiment of the present invention aims to protect an SV sending control method and device for an intelligent substation merging unit. The method includes the following steps: obtaining the latest sending timestamp of the FPGA; calculating the timestamp difference between the FPGA and the CPU based on the pre-sending timestamp of the CPU; determining whether the timestamp difference is greater than a first preset duration for a first preset number of consecutive times; if so, determining that the FPGA sends SV abnormally and performing a reset operation on the FPGA; if not, controlling the FPGA to send an SV packet. The above technical solution has the following effects:

[0074] By determining whether the SV sending is normal by judging the timestamp difference between the CPU and the FPGA in the merging unit, the problem that the SV sending is interrupted due to the runaway of the SV sending logic state machine of the FPGA is solved; the reliability of the SV sending of the merging unit is improved, the reliability of the data source of the intelligent substation is enhanced, and the safe and stable operation of the intelligent substation is ensured.

[0075] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0076] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0077] These computer program instructions can also be stored in a computer-readable memory capable of guiding a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means realizes the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are executed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions for implementing the steps of the function specified in one process or a plurality of processes and / or blocks Figure 1 one process or a plurality of processes and / or blocks Figure 1 in one block or a plurality of blocks.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications or equivalent replacements can still be made to the specific embodiments of the present invention. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A method for controlling the SV transmission of a merging unit in an intelligent substation, characterized in that, It includes the following steps: Obtain the latest transmission timestamp of the FPGA; Calculate the timestamp difference between the FPGA and the CPU based on the pre-transmission timestamp of the CPU; Determine whether the timestamp difference is greater than the first preset duration for the first preset number of consecutive times; If so, determine that the FPGA sends SV abnormally, and perform a reset operation on the FPGA; If not, control the FPGA to send the SV packet; Before obtaining the latest transmission timestamp of the FPGA, it further includes: Determine whether the FPGA is performing a reset operation; If so, exit the SV transmission; If not, calculate the timestamp difference between the FPGA and the CPU; Before performing the reset operation on the FPGA, it further includes: Determine whether the number of reset operations is greater than the second preset number; If so, send a failure report for SV transmission; If not, perform the reset operation on the FPGA.

2. The intelligent substation merging unit SV sending control method according to claim 1, wherein After performing the reset operation on the FPGA, it further includes: Clear the number of times the timestamp difference exceeds the first preset duration, and clear the number of reset operations.

3. An SV sending control device for an intelligent substation merging unit, characterized in that It includes: An acquisition module for obtaining the latest transmission timestamp of the FPGA; A calculation module for calculating the timestamp difference between the FPGA and the CPU based on the pre-transmission timestamp of the CPU; A first judgment module for determining whether the timestamp difference is greater than the first preset duration for the first preset number of consecutive times; A control module for determining that the FPGA sends SV abnormally and performing a reset operation on the FPGA when the timestamp difference is greater than the first preset duration for the first preset number of consecutive times; The control module is further configured to control the FPGA to send the SV packet when the timestamp difference is not greater than the first preset duration for the first preset number of consecutive times; It further includes: A second judgment module for determining whether the FPGA is performing a reset operation; The control module controls the FPGA to exit the SV transmission when the FPGA is performing a reset operation; The acquisition module obtains the latest transmission timestamp of the FPGA when the FPGA is not performing a reset operation; It further includes: A third judgment module for determining whether the number of reset operations is greater than the second preset number; The control module sends a failure report for SV transmission when the number of reset operations is greater than the second preset number; The control module performs the reset operation on the FPGA when the number of reset operations is less than or equal to the second preset number.

4. The intelligent substation merging unit SV transmission control device according to claim 3, characterized in that After the control module performs a reset operation on the FPGA, it also clears the number of times the timestamp difference exceeds the first preset duration and clears the number of reset operations.

5. An electronic device, characterized in that, It includes: At least one processor; and a memory connected to the at least one processor; wherein, the memory stores instructions executable by the one processor, and the instructions are executed by the one processor to enable the at least one processor to execute the intelligent substation merging unit SV sending control method according to claim 1 or 2.

6. A computer-readable storage medium, characterized in that, Stored thereon are computer instructions, which, when executed by a processor, implement the intelligent substation merging unit SV sending control method according to claim 1 or 2.

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