A phase-locked loop oscillator circuit

Abstract

The present invention discloses a phase-locked loop (PLL)-like oscillator circuit, comprising: a voltage generating circuit; a voltage comparison circuit, whose negative input terminal is connected to the first output terminal of the voltage generating circuit and whose output terminal is connected to the input terminal of a voltage-to-current module; an oscillator, whose input terminal is connected to the output terminal of the voltage-to-current module and the second output terminal of the voltage generating circuit; a current-to-voltage module, connected in parallel between the output terminal of the voltage-to-current module and the input terminal of the oscillator; and a filter circuit, whose input terminal is connected between the two output-side inverters of the oscillator and whose output terminal is connected to the positive input terminal of the voltage comparison circuit. The present invention can ensure that the chip output frequency remains stable even without an external reference frequency input, and has the advantages of being resistant to power supply voltage, temperature, and process fluctuations.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, in particular to a phase-locked loop (PLL)-like ring oscillator circuit. Background Art

[0002] In the field of integrated circuit design, the frequency signal generating circuit plays a very core role. The frequency signal generating circuit is used to provide the most basic frequency signal to other modules on the circuit board. The frequency signal generating circuit includes the following two structures: one is the phase-locked loop circuit and the other is the oscillator circuit. The internal structure of the phase-locked loop circuit is complex and has a frequency feedback loop, such as Figure 1 As shown. The traditional phase-locked loop circuit includes a phase frequency detector (PFD), a current source I1, a PMOS transistor P1, an NMOS transistor N1, a current source I2, a capacitor C1, a resistor R1, a capacitor C2, a voltage-controlled oscillator (VCO), and a frequency divider FP. The power supply port of the phase frequency detector (PFD) is connected to the power supply VDD, the ground port of the phase frequency detector (PFD) is connected to the ground GND, the output signal of the phase frequency detector (PFD) is a voltage signal VT, the negative input port of the phase frequency detector (PFD) is a reference frequency signal FC, which is provided by an external crystal oscillator device. The positive electrode of the current source I1 is connected to the power supply VDD, the negative electrode of the current source I1 is connected to the source of the PMOS transistor P1, the gate of the PMOS transistor P1 is connected to the voltage signal VT, the drain of the PMOS transistor P1 is connected to the voltage signal VCTR, the gate of the NMOS transistor N1 is connected to the voltage signal VT, and the drain of the NMOS transistor N1 is connected to the voltage signal VCTR. The source of NMOS transistor N1 is connected to the positive terminal of current source I2, the negative terminal of current source I2 is grounded GND, the positive terminal of capacitor C1 is connected to voltage signal VCTR, the negative terminal of capacitor C1 is grounded GND, the positive terminal of resistor R1 is connected to voltage signal VCTR, the negative terminal of resistor R1 is connected to the positive terminal of capacitor C2, the negative terminal of capacitor C2 is grounded GND, the power supply terminal of voltage-controlled oscillator VCO is connected to power supply VDD, the ground terminal of voltage-controlled oscillator VCO is grounded GND, the output signal of voltage-controlled oscillator VCO is frequency signal OUT, the input of voltage-controlled oscillator VCO is connected to voltage signal VCTR, the power supply terminal of frequency divider FP is connected to power supply VDD, the ground terminal of frequency divider FP is grounded GND, the output signal of frequency divider FP is feedback frequency signal FB, the feedback frequency signal FB is connected to the positive input terminal of phase frequency detector PFD, and the input of frequency divider FP is connected to frequency signal OUT. The internal structure of the phase-locked loop circuit is complex and has a frequency feedback loop. The frequency of the output signal is compared with the frequency of the reference signal to form a control voltage, which is then used to adjust the output frequency. This results in a stable frequency output that is less affected by voltage fluctuations. However, this circuit requires a crystal oscillator to provide an off-chip frequency reference signal, and crystal oscillators cannot be integrated into CMOS processes, making their use extremely inconvenient.

[0003] The oscillator circuit does not require an off-chip reference signal and is simple to design. However, the traditional oscillator circuit is greatly affected by power supply voltage, temperature, and process fluctuations, such as Figure 2 As shown. The traditional oscillator circuit includes inverter A1, inverter A2, inverter A3, inverter A4, inverter A5, inverter A6, inverter A7, and NMOS tube N1. The gate of NMOS tube N1 is voltage signal VCTR, which is used to control the output signal frequency of the oscillator. The source of NMOS tube N1 is grounded GND, the drain of NMOS tube N1 is voltage signal VC, the power port of inverter A1 is connected to power supply VDD, the ground port of inverter A1 is connected to voltage signal VC, the output of inverter A1 is connected to the input of inverter A2, the power port of inverter A2 is connected to power supply VDD, the ground port of inverter A2 is connected to voltage signal VC, the output of inverter A2 is connected to the input of inverter A3, and the power port of inverter A3 is connected to power supply VDD. The ground port of inverter A3 is connected to voltage signal VC, the output of inverter A3 is connected to the input of inverter A4, the power port of inverter A4 is connected to power supply VDD, the ground port of inverter A4 is connected to voltage signal VC, the output of inverter A4 is connected to the input of inverter A5, the power port of inverter A5 is connected to power supply VDD, the ground port of inverter A5 is connected to voltage signal VC, the output of inverter A5 is connected to the input of inverter A1, the power port of inverter A6 is connected to power supply VDD, the ground port of inverter A6 is connected to ground GND, the output of inverter A6 is connected to the input of inverter A7, the input of inverter A6 is connected to the output of inverter A5, the power port of inverter A7 is connected to power supply VDD, the ground port of inverter A7 is connected to ground GND, and the output of inverter A7 is frequency signal OUT. When the power supply voltage changes, the charge and discharge time of the inverter will also change, and thus the switching frequency of the node voltage will also change. Due to the lack of a phase-locked loop-like feedback loop, the chip's output frequency signal is uncontrolled. Introducing a bandgap reference signal as a reference signal, forming a phase-locked loop control similar to a phase-locked loop, can, to some extent, compensate for frequency offsets caused by power supply voltage and temperature fluctuations. However, the locking process is prone to loss of control, resulting in reduced chip yields. It also fails to address issues caused by process fluctuations, making it unusable in applications requiring high frequency signal stability.

[0004] In summary, in the application context where there is no reference frequency input and the output frequency is required to be stable, traditional frequency signal generation circuits are difficult to solve the problem of the oscillator chip output frequency resisting voltage and frequency process fluctuations. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a phase-locked loop oscillator circuit in view of the shortcomings of the existing technology, which solves the problem of the oscillator chip output frequency resisting voltage frequency process fluctuations without a reference frequency input.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is: a phase-locked loop oscillator circuit, comprising:

[0007] voltage generating circuit;

[0008] A voltage comparison circuit, wherein the negative input terminal is connected to the first output terminal of the voltage generating circuit, and the output terminal is connected to the input terminal of the voltage-to-current module;

[0009] An oscillator, whose input end is connected to the output end of the voltage-to-current module and the second output end of the voltage generating circuit;

[0010] A current-to-voltage module is connected in parallel between the output terminal of the voltage-to-current module and the input terminal of the oscillator;

[0011] The filter circuit has an input end connected between the two output-side inverters of the oscillator and an output end connected to the positive input end of the voltage comparison circuit.

[0012] This invention solves the challenge of oscillator chip output frequency immunity to voltage and frequency process fluctuations without a reference frequency input, while simultaneously offering the advantages of stable frequency output and ease of use of traditional phase-locked loop (PLL) circuits. Using a PLL-like circuit structure, the invention designs an internal voltage signal within the chip to resist voltage and frequency process fluctuations. This signal is used as a reference signal for feedback control of the output frequency, achieving stable output.

[0013] The voltage generation circuit includes a reference source voltage signal generation circuit and an anti-fluctuation characteristic voltage signal generation circuit; the reference source voltage signal generation circuit is connected to the input side of the anti-fluctuation characteristic voltage signal generation circuit; and the anti-fluctuation characteristic voltage signal generation circuit is connected to the voltage comparison circuit. The anti-fluctuation characteristic voltage signal generation circuit of the present invention generates a voltage signal for anti-fluctuation characteristics, eliminating the disadvantage of traditional phase-locked loop chips requiring external reference signal input, greatly simplifying the chip's usage requirements.

[0014] The reference source voltage signal generating circuit includes a PMOS transistor P2; the source of the PMOS transistor P2 is connected to a power supply, the gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P2, the gate of the PMOS transistor P3 is connected to the gate of the PMOS transistor P2, the source of the PMOS transistor P3 is connected to the power supply, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the gate of the NMOS transistor N4, the gate of the NMOS transistor N4 is connected to the drain of the NMOS transistor N4, the gate of the NMOS transistor N4 is connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N4 is connected to the emitter of the transistor Q2, the collector and base of the transistor Q2 are both grounded, the source of the NMOS transistor N3 is connected to the emitter of the transistor Q1, the collector and base of the transistor Q1 are both grounded, and the gate of the PMOS transistor P2 is connected to the anti-fluctuation characteristic voltage signal generating circuit. To generate a signal that is independent of process voltage and temperature fluctuations, the present invention first uses a common reference source voltage signal generation circuit to generate a reference voltage signal. This reference voltage signal does not fluctuate with power supply voltage or temperature, but does with process fluctuations. Using this reference voltage signal for coarse regulation can significantly reduce frequency deviations caused by process fluctuations.

[0015] To ensure that the voltage signal does not fluctuate with the process and to generate a signal that does not fluctuate with the power supply voltage, temperature, and process, the anti-fluctuation characteristic voltage signal generating circuit includes a PMOS transistor P4; the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P2; the source of the PMOS transistor P4 is connected to the power supply, the drain of the PMOS transistor P4 is connected to the emitter of the transistor Q3, and the collector and base of the transistor Q3 are both grounded; the positive input terminal of the operational amplifier is connected between the drain of the PMOS transistor P4 and the emitter of the transistor Q3; the positive input terminal of the operational amplifier is connected between the gate of the NMOS transistor N5 and the negative electrode of the resistor R9, the positive electrode of the resistor R9 is connected to the power supply, the gate of the NMOS transistor N5 is connected to the drain of the NMOS transistor N5, and the source of the NMOS transistor N5 is grounded; the output terminal and negative input terminal of the operational amplifier are grounded.

[0016] The filtering circuit comprises a high-pass filter and a smoothing filter connected in series; the input end of the high-pass filter is connected between the two output-side inverters of the oscillator.

[0017] The oscillator includes an input-side inverter and an output-side inverter; the input-side inverter includes multiple inverters, wherein the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the third inverter, and so on, and the output of the last inverter is connected to the input of the first inverter; the power supply ports of the multiple inverters are all connected to the power supply; the ground ports of the multiple inverters are all connected to the drain of the NMOS tube; the output-side inverter includes two inverters connected in series, wherein the input end of one inverter is connected between the last inverter of the input-side inverter and the first inverter; the power supply ports of the output-side inverter are all connected to the power supply; the gate of the NMOS tube is connected to the output end of the voltage-to-current module and the second output end of the voltage generating circuit; the source of the NMOS tube is connected to the output-side inverter.

[0018] The voltage-to-current module includes a PMOS transistor P1 and an NMOS transistor N1; the source of the PMOS transistor P1 is connected to the negative electrode of the first current source, the gate of the PMOS transistor P1 is connected to the output end of the voltage comparison circuit, and the drain of the PMOS transistor P1 is connected to the input end of the oscillator; the source of the NMOS transistor N1 is connected to the positive electrode of the second current source, the gate of the NMOS transistor N1 is connected to the output end of the voltage comparison circuit, and the drain of the NMOS transistor N1 is connected to the input end of the oscillator.

[0019] The current-to-voltage module includes a first capacitor, which is connected in parallel with a branch formed by a second capacitor and a resistor in series; one end of the first capacitor and one end of the resistor are connected between the output end of the voltage-to-current module and the input end of the oscillator.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] First, when the power supply voltage, temperature, and process fluctuate, the chip has a dynamic feedback structure (including a filter circuit, a voltage comparison circuit, and a voltage-to-current module) that can adjust the circuit output frequency in real time, so that the circuit output frequency signal remains stable and has anti-fluctuation characteristics;

[0022] Second, the regulation modes are divided into coarse and fine regulation. Coarse regulation involves the anti-fluctuation characteristic voltage generation circuit (voltage generation circuit) following process fluctuations, adjusting the oscillator's tail current via the process fluctuation voltage signal VI to adjust the output frequency. First, when process fluctuations occur, for example, when process fluctuations lean toward the FF (NMOS fast, PMOS fast) corner, the voltage value of the process fluctuation voltage signal VI output by the anti-fluctuation characteristic voltage generation circuit increases. Simultaneously, the FF corner process fluctuations can cause the oscillator's output frequency to significantly exceed the desired frequency. Next, the process fluctuation voltage signal VI is connected to the voltage terminal of the NMOS transistor that controls the oscillator's tail current. As the voltage value of the process fluctuation voltage signal VI increases, the threshold voltage of the NMOS transistor that controls the oscillator's tail current increases, thereby reducing the oscillator's tail current. The oscillator's tail current is positively correlated with the oscillator's output frequency, resulting in a decrease in the oscillator's output frequency. Conversely, when process fluctuations lean toward the SS (NMOS slow, PMOS slow) corner, the voltage value of the process fluctuation voltage signal VI output by the anti-fluctuation characteristic voltage generation circuit will decrease. At the same time, the SS corner process fluctuation will cause the oscillator output frequency to be significantly lower than the desired frequency. The adjustment principle at this time is the same as described above. Through the coarse adjustment loop, the output frequency deviation caused by process fluctuations is initially improved. At this time, we have only preliminarily corrected the frequency deviation caused by process fluctuations and have not yet considered the deviation caused by fluctuations such as temperature and power supply voltage. Therefore, we need to further correct the deviation amplitude of the output frequency based on the coarse adjustment. The anti-fluctuation characteristic voltage generation circuit will output an anti-fluctuation characteristic voltage signal VR that does not follow process, voltage, and temperature fluctuations. At this time, the anti-fluctuation characteristic voltage signal VR is the reference signal in the circuit. Through the dynamic feedback structure (filter circuit, oscillator, voltage-to-current module, current-to-voltage module), the oscillator's output frequency is only related to the anti-fluctuation characteristic voltage signal VR. The anti-fluctuation characteristic voltage signal VR does not fluctuate with process, voltage, and temperature, so the deviation amplitude of the output frequency is further reduced, which can significantly improve the chip yield.

[0023] Third, as electronic products continue to shrink in size, traditional phase-locked loop (PLL) chips require an external crystal oscillator to provide an additional reference frequency signal, making them unsuitable for applications requiring high volume. The present invention eliminates this drawback by eliminating the need for an additional reference frequency signal while still achieving a stable frequency output.

[0024] The present invention can ensure that the chip output frequency remains stable without external reference frequency input, and has the advantage of being resistant to power supply voltage, temperature and process fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the traditional phase-locked loop circuit structure;

[0026] Figure 2 This is a schematic diagram of a traditional oscillator circuit;

[0027] Figure 3 This is a schematic diagram of a phase-locked loop-like oscillator circuit that is resistant to voltage and frequency process fluctuations according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a circuit for generating an anti-fluctuation characteristic voltage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Figure 3 4 is a schematic diagram of a phase-locked loop oscillator circuit according to an embodiment of the present invention.

[0030] like Figure 3 As shown, the circuit of the embodiment of the present invention includes an anti-fluctuation characteristic voltage and frequency control circuit and a body voltage modulation voltage controlled oscillation circuit.

[0031] The anti-fluctuation characteristic voltage and frequency control circuit includes an anti-fluctuation characteristic voltage generating circuit VBG, a voltage comparison circuit VP, a high-pass filter circuit GT (Zhang Zhixin. Design of a high-order bandwidth adjustable switched capacitor bandpass filter [D]. Heilongjiang: Harbin Institute of Technology, 2018.) and a smoothing filter circuit PH (Teng Ying. Design of a monolithic fully integrated RC active filter [D]. Tianjin: Tianjin University, 2007.). The power supply port of the anti-fluctuation characteristic voltage generating circuit VBG is connected to the power supply VDD, the ground port of the anti-fluctuation characteristic voltage generating circuit VBG is connected to the ground GND, the output signals of the anti-fluctuation characteristic voltage generating circuit VBG are the anti-fluctuation characteristic voltage signal VR and the process fluctuation voltage signal VI, and the anti-fluctuation characteristic voltage signal VR is connected to the voltage comparison circuit VP. Input negative port; the power supply port of the voltage comparison circuit VP is connected to the power supply VDD, the ground port of the voltage comparison circuit VP is grounded GND, the output signal of the voltage comparison circuit VP is the voltage signal VT, the power supply port of the high-pass filter circuit GT is connected to the power supply VDD, the ground port of the high-pass filter circuit GT is grounded GND, the output signal of the high-pass filter circuit GT is the voltage signal V2, the input signal of the high-pass filter circuit GT is the voltage signal V1, the power supply port of the smoothing filter circuit PH is connected to the power supply VDD, the ground port of the smoothing filter circuit PH is grounded GND, the output signal of the smoothing filter circuit PH is the voltage signal VF, the voltage signal VF is connected to the input positive port of the voltage comparison circuit VP, and the input signal of the smoothing filter circuit PH is connected to the voltage signal V2.

[0032] like Figure 4The anti-fluctuation characteristic voltage generating circuit VBG includes a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, a transistor Q1, a transistor Q2, a transistor Q3, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, an operational amplifier Y1, a source of the PMOS tube P2 is connected to the power supply VDD, a gate of the PMOS tube P2 is connected to the drain of the PMOS tube P2, a gate of the PMOS tube P3 is connected to the gate of the PMOS tube P2, a source of the PMOS tube P3 is connected to the power supply VDD, and a drain of the PMOS tube P3 is connected to the gate of the PMOS tube P2. The source of NMOS tube N4 is connected to the positive electrode of resistor R8, the negative electrode of resistor R8 is connected to the emitter of transistor Q2, the collector of transistor Q2 is grounded GND, the base of transistor Q2 is grounded GND, the source of NMOS tube N3 is connected to the emitter of transistor Q1, the collector of transistor Q1 is grounded GND, the base of transistor Q1 is grounded GND, the gate of PMOS tube P2 is connected to the gate of PMOS tube P4, and P The source of MOS tube P4 is connected to the power supply VDD, the drain of PMOS tube P4 is connected to the positive electrode of resistor R2, the negative electrode of resistor R2 is connected to the emitter of transistor Q3, the collector of transistor Q3 is grounded GND, the base of transistor Q3 is grounded GND, the positive electrode of resistor R2 is connected to the process fluctuation voltage signal VI, which is a reference source voltage signal resistant to temperature and voltage changes, the positive electrode of resistor R9 is connected to the power supply VDD, the negative electrode of resistor R9 is connected to the gate of NMOS tube N5, the gate of NMOS tube N5 is connected to the drain of NMOS tube N5, the source of NMOS tube N5 is grounded GND, the negative electrode of resistor R9 is connected to the positive electrode of resistor R4, and the negative electrode of resistor R4 is connected to the negative electrode of resistor R4. Connect the positive pole of resistor R3, the negative pole of resistor R3 is grounded GND, the voltage signal VI is connected to the positive pole of resistor R5, the negative pole of resistor R5 is connected to the negative pole of resistor R4, the negative pole of resistor R5 is connected to the positive input terminal of operational amplifier Y1, the positive pole of amplifier Y1 is connected to the power supply VDD, the positive pole of amplifier Y1 is connected to the power supply VDD, the negative pole of amplifier Y1 is grounded GND, the output of amplifier Y1 is connected to the negative pole of resistor R7, the negative input terminal of amplifier Y1 is connected to the positive pole of resistor R7, the positive pole of resistor R7 is connected to the positive pole of resistor R6, the negative pole of resistor R6 is grounded GND, the output of amplifier Y1 is connected to the anti-fluctuation characteristic voltage signal VR, the anti-fluctuation characteristic voltage signal VR is a reference voltage signal that is resistant to process, temperature and voltage changes.

[0033] The body voltage modulation voltage controlled oscillation circuit includes a current source I1, a PMOS transistor P1, an NMOS transistor N1, a current source I2, a capacitor C1, a resistor R1, a capacitor C2, an inverter A1, an inverter A2, an inverter A3, an inverter A4, an inverter A5, an inverter A6, an inverter A7 and an NMOS transistor N2. The positive electrode of the current source I1 is connected to the power supply VDD, the negative electrode of the current source I1 is connected to the source of the PMOS transistor P1, the gate of the PMOS transistor P1 is connected to the voltage signal VT, the drain of the PMOS transistor P1 is connected to the voltage signal VCTR, and the gate of the NMOS transistor N1 is connected to the voltage signal VT. The drain of the NMOS tube N1 is connected to the voltage signal VCTR, the source of the NMOS tube N1 is connected to the positive electrode of the current source I2, the negative electrode of the current source I2 is grounded GND, the positive electrode of the capacitor C1 is connected to the voltage signal VCTR, the negative electrode of the capacitor C1 is grounded GND, the positive electrode of the resistor R1 is connected to the voltage signal VCTR, the negative electrode of the resistor R1 is connected to the positive electrode of the capacitor C2, the negative electrode of the capacitor C2 is grounded GND, the gate of the NMOS tube N2 is connected to the voltage signal VCTR, the source of the NMOS tube N2 is grounded GND, the drain of the NMOS tube N2 is the voltage signal VC, and the substrate of the NMOS tube N2 is connected to the process fluctuation voltage signal VI , the power port of inverter A1 is connected to the power supply VDD, the ground port of inverter A1 is connected to the voltage signal VC, the output of inverter A1 is connected to the input of inverter A2, the power port of inverter A2 is connected to the power supply VDD, the ground port of inverter A2 is connected to the voltage signal VC, the output of inverter A2 is connected to the input of inverter A3, the power port of inverter A3 is connected to the power supply VDD, the ground port of inverter A3 is connected to the voltage signal VC, the output of inverter A3 is connected to the input of inverter A4, the power port of inverter A4 is connected to the power supply VDD, the ground port of inverter A4 is connected to the voltage signal VC, the The output is connected to the input of inverter A5, the power port of inverter A5 is connected to the power supply VDD, the ground port of inverter A5 is connected to the voltage signal VC, the output of inverter A5 is connected to the input of inverter A1, the power port of inverter A6 is connected to the power supply VDD, the ground port of inverter A6 is connected to the ground GND, the output of inverter A6 is connected to the input of inverter A7, the output of inverter A6 is the voltage signal V1, the input of inverter A6 is connected to the output of inverter A5, the power port of inverter A7 is connected to the power supply VDD, the ground port of inverter A7 is connected to the ground GND, and the output of inverter A7 is the frequency signal OUT.

[0034] In an embodiment of the present invention, the anti-fluctuation characteristic voltage and frequency control circuit generates a process fluctuation voltage signal VI that responds only to process fluctuations. The process fluctuation voltage signal VI has five voltage levels: FF, FS, TT, SF, and SS, corresponding to the five process angles of the CMOS process (FF, FS, TT, SF, and SS). When the chip is manufactured, different process conditions are reflected in voltage VI. During oscillation startup, the bulk voltage modulation voltage-controlled oscillator circuit is roughly controlled by the process fluctuation voltage signal VI. The high-pass filter circuit GT and smoothing filter circuit PH of the anti-fluctuation characteristic voltage and frequency control circuit convert the frequency signal OUT into a voltage signal VF. The anti-fluctuation characteristic voltage and frequency control circuit generates an anti-fluctuation characteristic voltage signal VR. The voltage signal VF and the voltage signal VR are compared by the voltage comparison circuit VP to determine whether the output frequency deviates from the desired frequency. If VF is greater than VR, the output frequency is greater than the desired frequency; if VF is greater than VR, the output frequency is less than the desired frequency. The generated voltage VT is converted through the voltage-to-current module and the current-to-voltage module to generate the voltage VCTR. The voltage VCTR controls the NMOS tube N2 to adjust the micro-current of the oscillator, thereby controlling the frequency signal OUT.

[0035] In the embodiment of the present invention, the substrate of the NMOS transistor N2 is connected to the process fluctuation voltage signal VI, the substrates of the other NMOS transistors are connected to the ground GND, and the substrates of the PMOS transistors are connected to the power supply VDD.

[0036] The voltage and frequency control circuit and the body voltage modulation voltage controlled oscillation circuit are fully integrated in the chip, and have the characteristics of being resistant to power supply voltage fluctuations, temperature fluctuations and process fluctuations.

[0037] The NMOS transistor N1 , the NMOS transistor N2 , and the PMOS transistor P1 in the embodiment of the present invention are all NMOS transistors with common thresholds, and no additional special process is required to adjust the thresholds.

Claims

1. A phase-locked loop oscillator circuit, characterized in that: include: voltage generating circuit; A voltage comparison circuit, wherein the negative input terminal is connected to the first output terminal of the voltage generating circuit, and the output terminal is connected to the input terminal of the voltage-to-current module; An oscillator, whose input end is connected to the output end of the voltage-to-current module and the second output end of the voltage generating circuit; A current-to-voltage module is connected in parallel between the output terminal of the voltage-to-current module and the input terminal of the oscillator; a filter circuit, the input end of which is connected between the two output-side inverters of the oscillator, and the output end of which is connected to the positive input end of the voltage comparison circuit; The voltage generating circuit includes a reference source voltage signal generating circuit and an anti-fluctuation characteristic voltage signal generating circuit; the reference source voltage signal generating circuit is connected to the input side of the anti-fluctuation characteristic voltage signal generating circuit; the anti-fluctuation characteristic voltage signal generating circuit is connected to the voltage comparison circuit; The anti-fluctuation characteristic voltage signal generating circuit includes a PMOS transistor P4; the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P2; the source of the PMOS transistor P4 is connected to a power supply, the drain of the PMOS transistor P4 is connected to the emitter of the transistor Q3, and the collector and base of the transistor Q3 are both grounded; the positive input terminal of the operational amplifier is connected between the drain of the PMOS transistor P4 and the emitter of the transistor Q3; the positive input terminal of the operational amplifier is connected between the gate of the NMOS transistor N5 and the negative electrode of the resistor R9, the positive electrode of the resistor R9 is connected to the power supply, the gate of the NMOS transistor N5 is connected to the drain of the NMOS transistor N5, and the source of the NMOS transistor N5 is grounded; the output terminal and the negative input terminal of the operational amplifier are grounded.

2. The phase-locked loop oscillator circuit according to claim 1, wherein: The reference source voltage signal generating circuit includes a PMOS transistor P2; the source of the PMOS transistor P2 is connected to a power supply, the gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P2, the gate of the PMOS transistor P3 is connected to the gate of the PMOS transistor P2, the source of the PMOS transistor P3 is connected to the power supply, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the gate of the NMOS transistor N4, the gate of the NMOS transistor N4 is connected to the drain of the NMOS transistor N4, the gate of the NMOS transistor N4 is connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N4 is connected to the emitter of the transistor Q2, the collector and base of the transistor Q2 are both grounded, the source of the NMOS transistor N3 is connected to the emitter of the transistor Q1, the collector and base of the transistor Q1 are both grounded, and the gate of the PMOS transistor P2 is connected to the anti-fluctuation characteristic voltage signal generating circuit.

3. The phase-locked loop oscillator circuit according to claim 1, wherein: The filtering circuit comprises a high-pass filter and a smoothing filter connected in series; the input end of the high-pass filter is connected between the two output-side inverters of the oscillator.

4. The phase-locked loop oscillator circuit according to claim 1, wherein: The oscillator includes an input-side inverter and an output-side inverter; the input-side inverter includes multiple inverters, wherein the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the third inverter, and so on, and the output of the last inverter is connected to the input of the first inverter; the power supply ports of the multiple inverters are all connected to the power supply; the ground ports of the multiple inverters are all connected to the drain of the NMOS tube; the output-side inverter includes two inverters connected in series, wherein the input end of one inverter is connected between the last inverter of the input-side inverter and the first inverter; the power supply ports of the output-side inverter are all connected to the power supply; the gate of the NMOS tube is connected to the output end of the voltage-to-current module and the second output end of the voltage generating circuit; the source of the NMOS tube is connected to the output-side inverter.

5. The phase-locked loop oscillator circuit according to claim 1, wherein: The voltage-to-current module includes a PMOS transistor P1 and an NMOS transistor N1; the source of the PMOS transistor P1 is connected to the negative electrode of the first current source, the gate of the PMOS transistor P1 is connected to the output end of the voltage comparison circuit, and the drain of the PMOS transistor P1 is connected to the input end of the oscillator; the source of the NMOS transistor N1 is connected to the positive electrode of the second current source, the gate of the NMOS transistor N1 is connected to the output end of the voltage comparison circuit, and the drain of the NMOS transistor N1 is connected to the input end of the oscillator.

6. The phase-locked loop oscillator circuit according to any one of claims 1 to 5, characterized in that: The current-to-voltage module includes a first capacitor, which is connected in parallel with a branch formed by a second capacitor and a resistor in series; one end of the first capacitor and one end of the resistor are connected between the output end of the voltage-to-current module and the input end of the oscillator.

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