A low power consumption, high performance and small size C unit

Abstract

The present invention discloses a low-power, high-performance, small-size C unit. The C unit includes a PMOS pull-up gate, an NMOS pull-down gate, a drive gate, and a feedback gate; the drive gate and the feedback gate form a memory to lock the signal and save the data; two PMOS constitute the pull-up gate, two NMOS constitute the pull-down gate, and six MOSFETs constitute the drive gate and the feedback gate, which constitute the memory as a whole. The C unit circuit of the present invention can realize in one circuit that when two inputs are both high levels, a high level is output, and when two inputs are both low levels, a low level is output, and the other states remain unchanged. Compared with the traditional C unit logic circuit, the circuit of the present invention has more advantages in power consumption, performance, area, and compatibility.

Description

Technical Field

[0001] The invention relates to a low-power consumption, high-performance and small-size C unit, belonging to the field of integrated circuits. Background Art

[0002] Most digital systems are synchronous. In synchronous digital systems, all state flips occur at the transition edge of the synchronous clock, and the system state is stored in registers. Synchronous circuits are the dominant design method, and their mature EDA tools cover almost the entire large-scale digital integrated circuit design process, from high-level language description to a complete chip layout, with very little manual intervention. However, after the development of integrated circuit technology entered the deep submicron, the size of devices continued to shrink, the channel feature size of MOS tubes has been much smaller than 40nm, the thickness of the insulating layer is less than 1nm, and the integrated capacity of a single chip is constantly expanding. With the reduction of chip feature size, the increase of chip area and the increase of clock frequency, especially the emergence of system on chip (System on a chip, SoC), the realization of global synchronous clock has become increasingly difficult, and the power consumption problem caused by global synchronous clock has left designers helpless. For example: the useless power consumption of the clock network caused by clock flips and the clock power consumption caused by the increase of the main frequency are constantly increasing. High-speed synchronous circuit chips have concluded that the power consumption of the clock network accounts for 30-35% of the total power consumption.

[0003] For the above reasons, asynchronous circuits have regained the attention of academia and industry. Asynchronous circuits do not have a global clock, and the data between various modules of the system is completed through a handshake process between each other. In this case, the advantages of low power consumption, potential high performance and easy modularization of asynchronous integrated circuits gradually emerge. In essence, synchronous circuits are based on two basic assumptions: 1. All signals are binary; 2. All circuits share a common, discrete time, that is, a clock signal distributed throughout the circuit. Although asynchronous circuits are also binary signals, they do not have a common, discrete concept of time. Instead, the circuits handshake between different components to achieve synchronization and communication between circuits. The orderly operation of asynchronous circuits must rely on handshake signals, and the C unit is the key unit to implement the handshake signal. Traditional C units such as Figure 1 A traditional C unit structure is introduced in the book "Asynchronous Circuit Design" (Tsinghua University Press, ISBN: 9787302319153, publication date: 2013.09.01). The circuit diagram of the C unit is shown in Figure 2 As shown, it includes a pull-up gate composed of two PMOS, a pull-down gate composed of two NMOS, and a memory composed of two inverters to store signals. This traditional C unit circuit has a simple structure and fast speed, but it consumes a lot of power and is not suitable for low-power environments. Summary of the invention

[0004] In view of the above defects in the prior art, an object of the present invention is to provide a C unit with low power consumption, high performance and small size.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A low-power, high-performance, small-size C unit, comprising a PMOS pull-up gate, an NMOS pull-down gate, a drive gate, and a feedback gate; characterized in that the PMOS pull-up gate comprises a first PMOS Q1 tube and a second PMOS Q2 tube, the source and substrate of the first PMOS Q1 tube and the substrate of the second PMOS Q2 tube are all connected to a power supply voltage VDD, and the drain of the first PMOS Q1 tube is connected to the source end of the second PMOS Q1 tube; the NMOS pull-down gate comprises a first NMOS Q3 tube and a second NMOS Q4 tube, the substrate of the first NMOS Q3 tube and the substrate and source of the second NMOS Q4 tube are all grounded, the drain of the second NMOS Q4 tube is connected to the source of the first NMOS Q3 tube, and the drain of the second PMOS Q2 tube is connected to the source of the first NMOS Q3 tube. The gate of the first PMOS Q1 tube is connected to the gate of the second NMOS Q4 tube and the connection end thereof is the first signal input end In1; the gate of the second PMOS Q2 tube is connected to the gate of the first NMOS Q3 tube and the connection end thereof is the second signal input end In2; the driving gate includes a third PMOS Q5 tube, a fourth PMOS Q6 tube, a third NMOS Q7 tube and a fourth NMOS Q8 tube, the source and substrate of the third PMOS Q5 tube and the substrate of the fourth PMOS Q6 tube are both connected to the power supply voltage VDD, the gate of the third PMOS Q5 tube is grounded, the drain of the third PMOD Q5 tube is connected to the source of the fourth PMOS Q6 tube, the substrate of the third NMOS Q7 tube and the source and substrate of the fourth NMOS Q8 are both grounded, the source of the third NMOS Q7 tube is connected to the drain of the fourth NMOS Q8 tube, and the gate of the fourth NMOS Q8 tube is connected to the power supply voltage VDD; the feedback gate includes a fifth PMOS Q9 tube and a fifth NMOS Q 10 The source and substrate of the fifth PMOS Q9 tube are both connected to the power supply voltage, and the fifth NMOS Q 10 The source and substrate of the tube are connected to the ground; the gate of the fifth PMOS Q9 tube, the gate of the fifth NMOS Q 10 The gate of the tube, the drain of the fourth PMOS Q6, the drain of the third NMOS Q7, the drain of the second PMOS Q2 and the drain of the first NMOS Q3 are connected together, and the drain of the fifth PMOS Q9 tube, the drain of the fifth NMOS Q 10The drain of the tube, the gate of the fourth PMOS Q6 tube and the drain of the third NMOS Q7 tube are connected to form an output signal out.

[0007] The C unit logic circuit of the present invention can realize in one circuit that when two inputs are both at high levels, a high level is output, and when two inputs are both at low levels, a low level is output, and the other states remain unchanged. Compared with the prior art, the advantages of the present invention are: the signal is stored in a memory composed of a driving gate and a feedback gate, and the function of limiting the current is performed by the turned-on third PMOS Q5 tube and the fourth NMOS Q8 tube, thereby realizing a low power consumption effect. Therefore, under the condition of high frequency speed, it still has the characteristics of low power consumption and high stability. The circuit of the present invention has more advantages in power consumption, performance, area, and compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a traditional C unit symbol diagram;

[0009] Figure 2 This is the traditional C unit circuit diagram;

[0010] Figure 3 It is a circuit diagram of a low-power, high-performance, small-size C unit of the present invention. DETAILED DESCRIPTION

[0011] A low-power, high-performance, small-size C unit in this embodiment is Figure 3 As shown, the drive gate and the feedback gate form a memory to lock the signal and save the data. The two PMOS on the left end of the unit form a pull-up gate, the two NMOS form a pull-down gate, and the six MOSFETs in the middle and on the right form a drive gate and a feedback gate, which together form a memory. The PMOS pull-up gate includes a first PMOSQ1 tube and a second PMOSQ2 tube. The source and substrate of the first PMOSQ1 tube, as well as the substrate of the second PMOSQ2 tube, are connected to the power supply voltage VDD, which is 1.2V. The drain of the first PMOSQ1 tube is connected to the source of the second PMOSQ1 tube. The pull-down gate includes a first NMOSQ3 tube and a second NMOSQ4 tube. The substrate of the first NMOSQ3 tube and the substrate and source of the second NMOSQ4 tube are grounded. The drain of the second NMOSQ4 tube is connected to the source of the first NMOSQ3 tube, the drain of the second PMOSQ2 tube is connected to the drain of the first NMOSQ3 tube, the gate of the first PMOSQ1 tube is connected to the gate of the second NMOSQ4 tube and the connecting end thereof is the first signal input terminal In1, the gate of the second PMOSQ2 tube is connected to the gate of the first NMOSQ3 tube and the connecting end thereof is the second signal input terminal In2.

[0012] The driving gate circuit of this embodiment includes a third PMOS Q5 tube and a fourth PMOS Q6 tube, and a third NMOS Q7 tube and a fourth NMOS Q8 tube. The source and substrate of the third PMOS Q5 tube and the substrate of the fourth PMOS Q6 tube are connected to the power supply voltage VDD, the gate of the third PMOS Q5 tube is grounded, the drain of the third PMOD Q5 tube is connected to the source of the fourth PMOS Q6 tube, the substrate of the third NMOS Q7 tube and the source and substrate of the fourth NMOS Q8 are grounded, the source of the third NMOS Q7 tube is connected to the drain of the fourth NMOS Q8 tube, and the gate of the fourth NMOS Q8 tube is connected to the power supply voltage VDD.

[0013] The feedback gate circuit includes a fifth PMOS Q9 tube and a fifth NMOS Q 10 The source and substrate of the fifth PMOS Q9 tube are both connected to the power supply voltage, and the fifth NMOS Q 10 The source and substrate of the tube are connected to the ground, and the gate of the fifth PMOS Q9 tube and the gate of the fifth NMOS Q 10 The gate of the tube, the drain of the fourth PMOS Q6, the drain of the third NMOS Q7, the drain of the second PMOS Q2, and the drain of the first NMOS Q3 are all connected together, and the drain of the fifth PMOS Q9 and the drain of the fifth NMOS Q 10 The drain of the tube, the gate of the fourth PMOS Q6 tube and the drain of the third NMOS Q7 tube are connected to form an output signal out.

[0014] The working principle of the low-power, high-performance, small-size C unit in this example is as follows:

[0015] When the input signal In1 and the input signal In2 are both at high level, the first PMOS Q1 tube and the second PMOS Q2 tube in the pull-up gate are turned off, and the first NMOS Q3 tube and the second NMOS Q4 tube in the pull-down gate are turned on. At this time, the signal between the drain of the second PMOS Q2 tube and the drain of the first NMOS Q3 tube is at a low level. Since the drain of the second PMOS Q2 tube and the drain of the first NMOS Q3 tube, the gate of the fourth PMOS Q6 tube and the drain of the third NMOS Q7 tube, and the gate of the fifth PMOS Q9 tube and the drain of the fifth NMOS Q 10 The gates of the fifth PMOS Q9 tube are connected, and the low-level signal is transmitted to the gate of the fifth NMOS Q 10 The gate of the tube, at this time, the fifth PMOS Q9 tube is turned on and the output voltage is high.

[0016] When the input signal In1 and the input signal In2 are both at a low level, the first PMOS Q1 tube and the second PMOS Q2 tube in the pull-up gate are turned on, and the first NMOS Q3 tube and the second NMOS Q4 tube in the pull-down gate are turned off. At this time, the signal between the drain of the second PMOS Q2 tube and the drain of the first NMOS Q3 tube is at a high level. Since the drain of the second PMOS Q2 tube and the drain of the first NMOS Q3 tube, the gate of the fourth PMOS Q6 tube and the drain of the third NMOS Q7 tube, and the gate of the fifth PMOS Q9 tube and the drain of the fifth NMOS Q 10 The gates of the fifth PMOS Q9 tube are connected, and the high-level signal is transmitted to the gate of the fifth NMOS Q 10 The gate of the tube, at this time the fifth NMOSQ 10 The tube is turned on and the output voltage is low.

[0017] When the input signal In1 and the input signal In2 are both high and low, the first PMOS Q1 and the second PMOS Q2 in the pull-up gate must be both turned on and off, and the first NMOS Q3 and the second NMOS Q4 in the pull-down gate must also be both turned on and off. At this time, the pull-up gate and the pull-down gate are both in the off state, and there is no signal between the drain of the second PMOS Q2 and the drain of the first NMOS Q3; since the drive gate and the feedback gate form a memory that can lock the signal, the output signal at this time is the previously stored signal.

Claims

1. A low-power, high-performance, small-size C-cell, comprising a PMOS pull-up gate, an NMOS pull-down gate, a drive gate, and a feedback gate; characterized in that: The PMOS pull-up gate includes a first PMOS tube Q1 and a second PMOS tube Q2, the source and substrate of the first PMOS tube Q1 and the substrate of the second PMOS tube Q2 are connected to the power supply voltage VDD, and the drain of the first PMOS tube Q1 is connected to the source end of the second PMOS tube Q2; The NMOS pull-down gate includes a first NMOS tube Q3 and a second NMOS tube Q4, the substrate of the first NMOS tube Q3 and the substrate and source of the second NMOS tube Q4 are grounded, the drain of the second NMOS tube Q4 is connected to the source of the first NMOS tube Q3, and the drain of the second PMOS tube Q2 is connected to the drain of the first NMOS tube Q3; The gate of the first PMOS transistor Q1 is connected to the gate of the second NMOS transistor Q4 and the connection end thereof is the first signal input end In1; the gate of the second PMOS transistor Q2 is connected to the gate of the first NMOS transistor Q3 and the connection end thereof is the second signal input end In2; The driving gate includes a third PMOS tube Q5, a fourth PMOS tube Q6, a third NMOS tube Q7 and a fourth NMOS tube Q8, the source and substrate of the third PMOS tube Q5 and the substrate of the fourth PMOS tube Q6 are both connected to the power supply voltage VDD, the gate of the third PMOS tube Q5 is grounded, the drain of the third PMOS tube Q5 is connected to the source of the fourth PMOS tube Q6, the substrate of the third NMOS tube Q7 and the source and substrate of the fourth NMOS tube Q8 are both grounded, the source of the third NMOS tube Q7 is connected to the drain of the fourth NMOS tube Q8, and the gate of the fourth NMOS tube Q8 is connected to the power supply voltage VDD; The feedback gate includes a fifth PMOS transistor Q9 and a fifth NMOS transistor Q 10 The source and substrate of the fifth PMOS tube Q9 are both connected to the power supply voltage, and the fifth NMOS tube Q 10 The source and substrate of the fifth PMOS tube Q9 are connected to the ground; the gate of the fifth NMOS tube Q 10 The gate of the fourth PMOS tube Q6, the drain of the third NMOS tube Q7, the drain of the second PMOS tube Q2 and the drain of the first NMOS tube Q3 are connected together, and the drain of the fifth PMOS tube Q9, the drain of the fifth NMOS tube Q 10 The drain of the fourth PMOS tube Q6, the gate of the fourth NMOS tube Q7 and the drain of the third NMOS tube Q7 are connected to form an output signal out.

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