An Adaptive Phase Tracking Method and System

Abstract

The present invention proposes an adaptive phase tracking method and system. By combining the characteristic that the synchronization performance of the phase-locked loop is superior to that of the open-loop structure in the tracking stage, an implementation architecture of adaptive phase tracking based on dual-PLL is constructed. In the implementation process, a forward loop and a reverse loop are divided. The PLL in the forward loop is mainly used for capture, and phase locking has been achieved for the data segment before passing through the PLL; the PLL in the reverse loop has no capture stage and directly performs reverse phase tracking on the data segment. During the process of realizing adaptive phase tracking, on the one hand, according to different modulation methods, the appropriate phase discrimination algorithm is adaptively adjusted to make the dual-PLL adaptive phase tracking algorithm applicable to different modulation methods, greatly reducing the resource occupation for FPGA implementation. On the other hand, the output signals of the dual-PLL are further processed to resolve phase ambiguity, and this module is placed at the output position of the reverse PLL, making it easier to implement, so that under the condition of ensuring the minimum resource occupation, the bit error performance of the system is greatly improved.

Description

Technical Field

[0001] The present invention relates to an adaptive phase tracking method and system, and particularly relates to the field of wireless communication technology. Background Art

[0002] Carrier phase tracking is a key component in digital communication modems, and its main task is to process the residual frequency offset and random phase offset remaining after carrier frequency synchronization.

[0003] In the process of implementing phase tracking, for the case where the pilot symbols in the frame structure are known, the phase tracking can adopt an open-loop structure based on the maximum likelihood algorithm of the pilot. However, for burst signals, the pilot length is short and very sensitive to noise. If this algorithm continues to be used, it will result in the inability to correctly estimate the phase offset under low signal-to-noise ratio conditions. Therefore, the pilot-based phase tracking method is not applicable to the frame structure with extremely short pilots.

[0004] For the case where there is no pilot or the pilot is unknown in the frame structure, the phase tracking can adopt an open-loop structure based on the phase estimation algorithm of the frame header. Due to the existence of residual frequency offset and phase noise, the phase within one frame still has a large dynamic change range. Therefore, the method of directly obtaining the phase deviation of the entire frame using the frame header information is not feasible, and it is necessary to perform real-time tracking on the carrier phase change of the symbols within the frame. For the case where the carrier phase of the received signal changes dynamically, a phase-locked loop (PLL) is often used for closed-loop tracking. Since the closed-loop structure has two stages: capture and tracking, accurate estimation of the phase offset cannot be achieved during the capture stage, resulting in the inability to correctly demodulate the data in this stage. Therefore, this method is not applicable to short bursts. Summary of the Invention

[0005] Object of the Invention: To propose an adaptive phase tracking method and system, by combining the characteristics that the synchronization performance of the phase-locked loop is superior to that of the open-loop structure in the tracking stage, to solve the above problems existing in the prior art, and to complete the FPGA design and implementation of this method, meeting the requirements applicable to different modulation methods of burst structures.

[0006] Technical Solution: In the first aspect, an adaptive phase tracking method is proposed, and this method specifically includes the following steps:

[0007] Step 1: Construct an adaptive phase tracking framework structure and receive the input signal after carrier frequency offset compensation;

[0008] Step 2: Divide the received input signal into two paths for processing. One path enters the forward loop, and the other path is buffered and used for the reverse loop;

[0009] Step 3: The forward loop performs phase compensation processing on the received input signal and determines the data length of the input signal after phase compensation;

[0010] Step 4: When the data length of the input signal after phase compensation is less than the preset length L, no output is made, and the phase discriminator is adaptively controlled to apply different modulation methods according to the received control word status. An estimated value is obtained by combining the loop filter and the numerically controlled oscillator, and the process jumps to Step 3. The estimated value is used to perform phase adjustment on the input signal received in Step 1;

[0011] On the contrary, an output control signal syn_ctrl is output, and the final parameter status value of the PLL is stored, and the process jumps to Step 5;

[0012] Step 5: Initialize the loop parameters of the PLL in the reverse loop according to the final parameter status value of the PLL;

[0013] Step 6: Read the data stored in Step 2, perform reverse output on it, and perform phase tracking through the PLL after performing phase compensation processing;

[0014] Step 7: Perform de-phase ambiguity processing on the data signal after passing through the PLL;

[0015] Step 8: Output the final data.

[0016] Wherein, the PLL represents a phase-locked loop.

[0017] The PLL of the forward loop is mainly used for capture, and phase locking has been achieved before the data segment passes through the PLL; the PLL of the reverse loop has no capture stage and directly performs reverse phase tracking on the data segment, thereby giving full play to the excellent performance of the PLL in the tracking stage.

[0018] In some realizable manners of the first aspect, when the forward loop implements the phase capture and tracking process, the following steps are further included:

[0019] Step 1: Perform phase compensation on the input signal according to the status of the received input enable signal;

[0020] Step 2: Divide the input data after phase compensation into two paths for processing. One path is used to judge the data length, and the other path enters the PLL for data processing;

[0021] Step 3: When the data length of the input signal after phase compensation is less than the preset length L, no output is made, and the phase discriminator is adaptively controlled to apply different modulation methods according to the received control word status. An estimated value is obtained by combining the loop filter and the numerically controlled oscillator, and the input signal received in Step 1 is adjusted using the estimated value;

[0022] Conversely, a control signal for triggering data storage is output, and the final parameter status value of the PLL is stored.

[0023] Among them, in the process of data processing by the PLL, the following steps are further included:

[0024] Step 2.1: The phase detector selects a corresponding phase detection algorithm according to the preset control word status to adapt to different modulation methods;

[0025] Step 2.2: After the input data passes through the phase detector, a phase error is obtained;

[0026] Step 2.3: The loop filter processes the phase error and feeds the corresponding output value back to the numerically controlled oscillator;

[0027] Step 2.4: An estimated value is obtained through the processing of the numerically controlled oscillator, and the input signal is adjusted and updated using phase compensation according to the estimated value.

[0028] The phase detector is used to adaptively adjust a suitable phase detection algorithm according to different modulation methods. Further, when the real part of the input signal of the phase detector is , and the imaginary part is When

[0029] For BPSK modulation signals, the corresponding phase error The extraction expression is:

[0030]

[0031] For QPSK modulation signals, the corresponding phase error The extraction expression is:

[0032]

[0033] For 8PSK modulation signals, the corresponding phase error The extraction expression is:

[0034]

[0035] In the formula, .

[0036] When the loop filter processes the phase error, a second-order loop filter is used to filter out the high-frequency components in the output error signal of the phase detector and output ;

[0037] Further, the output The expression is:

[0038]

[0039] In the formula, represents the integral gain; represents the phase error output by the phase detector.

[0040] The numerically controlled oscillator adopts a direct digital synthesizer and obtains an estimated value based on the forward Euler integration rule. The corresponding expression is:

[0041]

[0042] In the formula, represents the proportional gain; represents the phase error output by the forward phase detector; represents the output value of the forward loop filter.

[0043] In some realizable manners of the first aspect, when the reverse loop implements the phase tracking process, the following steps are further included:

[0044] Step a: Initialize the PLL parameters in the reverse loop according to the final PLL parameters output by the forward loop;

[0045] Step b: Receive and read the data stored in the second step, perform reverse output on it, and perform phase tracking through the PLL in the reverse loop after performing phase compensation processing;

[0046] Step c: Perform de-phase ambiguity processing on the data signal after passing through the PLL;

[0047] Step d: Output the final data.

[0048] Further, when performing de-phase ambiguity processing on the data signal after passing through the PLL, further perform maximum likelihood phase ambiguity estimation using the UW code. The corresponding expression is:

[0049]

[0050] In the formula, h represents the length of the UW segment; represents the input data signal of the de-phase ambiguity module; represents the conjugate of the known UW symbol.

[0051] In some realizable ways of the first aspect, an adaptive phase tracking method is implemented through a top-level FPGA module based on dual-PLL adaptive phase tracking; this module is configured to receive including: a reset signal rst, a system clock clk, an enable signal I_data_en, a control word signal I_ctrl_word, and 12-bit wide data I_data_i, I_data_q; the corresponding outputs include: an enable signal O_pha_comp_en, 12-bit wide data O_pha_comp_i, O_pha_comp_q.

[0052] In a second aspect, an adaptive phase tracking system is proposed, which specifically includes:

[0053] A phase compensation module (PHA_SHIFT), which is configured to perform carrier phase compensation on the received input signal;

[0054] A phase-locked loop module (PLL), which is configured to receive the data signal output by the phase compensation module and capture and track it;

[0055] A data length judgment module (JUDGE), which is configured to receive the data signal output by the phase compensation module and perform statistics and judgment on the input data length;

[0056] A memory (REG_D), which is configured to store the entire data segment;

[0057] A phase ambiguity resolution module (PHA_AMBIGU), which is configured to perform ambiguity resolution processing on the input signal;

[0058] A phase detector (PD), which is configured to calculate the phase error of the input signal;

[0059] A loop filter (LF), which is configured to filter out the high-frequency components in the input phase error signal for smoothing filtering;

[0060] A numerically controlled oscillator (NCO), which is configured to generate a demodulation wave with the same frequency and phase as the input signal according to the received signal and input it into the phase compensation module;

[0061] In some realizable ways of the second aspect, after receiving the input signal, the phase compensation module performs phase compensation on the input signal according to the signal state, and on the one hand, enters two branches of the phase-locked loop module and the data length judgment module respectively in the forward loop; on the other hand, enters two branches of the phase-locked loop module and the phase ambiguity resolution module in the reverse loop.

[0062] Secondly, the phase-locked loop module captures and tracks the data signal output by the phase compensation module, and outputs a phase error value and an enable signal to enter the phase compensation module.

[0063] Thirdly, the data length judgment module receives the data signal output by the phase compensation module, counts and judges the input data length according to the signal state output by the phase-locked loop module, and updates the signal state of the trigger memory according to the judgment result.

[0064] Secondly, the phase detector adaptively adjusts the calculation method of the phase error of the phase detector by inputting a control word through the phase-locked loop module. After determining the error calculation method, the phase difference is calculated using the real and imaginary parts of the input signal. After completing the calculation of the phase error, the enable signal is pulled high, and the phase error is output to the loop filter; subsequently, the loop filter filters out the high-frequency components in the received phase error signal and feeds it back to the numerically controlled oscillator.

[0065] Finally, the numerically controlled oscillator inputs the processed data into the phase compensation module and updates the data using the estimated value, and enters a loop. After completing the calculation of the entire data segment, the data is input into the phase ambiguity resolution module for phase ambiguity resolution processing.

[0066] Beneficial effects: The present invention proposes an adaptive phase tracking method and system, which constructs an adaptive phase tracking implementation architecture based on dual PLL by combining the characteristics that the phase-locked loop has better synchronization performance than the open-loop structure in the tracking stage. On the one hand, according to different modulation methods, the appropriate phase discrimination algorithm is adaptively adjusted to make the dual PLL adaptive phase tracking algorithm applicable to different modulation methods, greatly reducing the resource occupation of FPGA implementation. On the other hand, the output signal of the dual PLL is further subjected to phase ambiguity resolution processing, and this module is placed at the output position of the reverse PLL, making it easier to implement. Thus, under the condition of ensuring the minimum resource occupation, the bit error performance of the system is greatly improved. Description of the Drawings

[0067] Figure 1 It is a flowchart of the present invention's adaptive phase tracking based on dual PLL.

[0068] Figure 2 It is a schematic diagram of the principle structure of the forward loop of the present invention.

[0069] Figure 3 It is a schematic diagram of the physical layer frame structure of the burst communication system.

[0070] Figure 4 It is a schematic diagram of the principle structure of the reverse loop of the present invention.

[0071] Figure 5 It is a schematic diagram of the top-level FPGA module of the present invention.

[0072] Figure 6 It is a partial interface timing diagram of the top-level FPGA module of the present invention.

[0073] Figure 7 This is a schematic diagram of the system structure of the present invention.

[0074] Figure 8 This is an FPGA implementation architecture diagram of the sub-module PLL for phase tracking of the present invention. Specific implementation manners

[0075] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some well-known technical features in the art are not described.

[0076] In the prior art, when implementing the phase tracking process, for the case where the pilot symbols in the frame structure are known, the phase tracking can adopt an open-loop structure based on the maximum likelihood algorithm of the pilot. However, for burst signals, the pilot length is short and very sensitive to noise. If this algorithm continues to be used, it will result in the inability to correctly estimate the phase offset under low signal-to-noise ratio conditions. Therefore, the pilot-based phase tracking method is not applicable to the frame structure with extremely short pilots.

[0077] For the case where there is no pilot or the pilot is unknown in the frame structure, the phase tracking can adopt an open-loop structure based on the phase estimation algorithm of the frame header. However, due to the existence of residual frequency offset and phase noise, there is still a large dynamic change range of the phase within one frame. Therefore, the method of directly obtaining the phase deviation of the entire frame using the frame header information is not feasible, and it is necessary to track the carrier phase change of the symbols within the frame in real time.

[0078] Therefore, for the case of the dynamic change of the carrier phase of the received signal, a phase-locked loop (PLL) is often used for closed-loop tracking. However, since the closed-loop structure has two stages: capture and tracking, the accurate estimation of the phase offset cannot be achieved during the capture stage, resulting in the inability to correctly demodulate the data in this stage. Therefore, this method is not applicable to short bursts

[0079] In one embodiment, an adaptive phase tracking method is proposed. By leveraging the characteristic that the phase-locked loop (PLL) has better synchronization performance than the open-loop structure during the tracking phase, the problems existing in the prior art are solved, and the FPGA design and implementation of this method are completed to meet the requirements applicable to different modulation methods of burst structures. For burst signals without pilots or with extremely short pilots, and with the carrier phase of the received signal at the receiving end changing dynamically, traditional phase tracking algorithms use a PLL for closed-loop tracking. Due to the capture time in the closed-loop tracking process, the data in the capture phase cannot be correctly synchronized. An adaptive phase tracking framework structure is constructed. When implementing adaptive phase tracking, the PLL in the forward loop is mainly used for capture, and the phase has been locked before the data segment passes through the PLL; the PLL in the reverse loop has no capture phase and directly performs reverse phase tracking on the data segment.

[0080] Specifically, as Figure 1 shown in the flowchart, the implementation steps of an adaptive phase tracking method are as follows:

[0081] Step 1: Construct an adaptive phase tracking framework structure and receive the input signal after carrier frequency offset compensation;

[0082] Step 2: Divide the received input signal into two paths for processing. One path enters the forward loop, and the other path enters the buffer module to buffer the input data for the reverse loop;

[0083] Step 3: The forward loop performs phase compensation processing on the received input signal and determines the data length of the input signal after phase compensation;

[0084] Step 4: When the data length of the input signal after phase compensation is less than the preset length L, no output is made, and the phase detector adaptively applies different modulation methods according to the received control word status, and combines the loop filter and the numerically controlled oscillator to obtain an estimated value. Jump to Step 3 and use the estimated value to adjust the phase of the input signal received in Step 1;

[0085] Conversely, output the control signal syn_ctrl, store the final parameter status value of the PLL, and jump to Step 5;

[0086] Step 5: Initialize the loop parameters of the PLL in the reverse loop according to the final parameter status value of the PLL;

[0087] Step 6: Read the data stored in Step 2, perform reverse output on it, and perform phase tracking through the PLL after phase compensation processing;

[0088] Step 7: Perform phase ambiguity resolution on the data signal after passing through the PLL;

[0089] Step 8: Output the final data.

[0090] In this embodiment, the PLL in the forward loop is mainly used for capture, and phase locking has been achieved for the data segment before passing through the PLL; the PLL in the reverse loop has no capture stage and directly performs reverse phase tracking on the data segment, which can give full play to the excellent performance of the PLL in the tracking stage.

[0091] In a further embodiment, the dual-PLL loop includes a forward loop and a reverse loop, where the forward loop is used for capture, and phase locking has been achieved for the data segment before passing through the PLL; the PLL in the reverse loop has no capture stage and directly performs reverse phase tracking on the data segment.

[0092] Specifically, as shown in Figure 2 , first, after receiving the input signal after carrier frequency offset compensation , perform phase compensation on it to obtain the output signal ; secondly, count the data length of the output signal ; thirdly, compare the data length of the output signal with the preset data length L; then, when the data length of the output signal is not less than the data length L, output the data cache module control signal syn_ctrl, store the final parameter status value of the dual-PLL, and input the output signal into the phase detector to obtain the phase error ; otherwise, do not output; finally, the phase error is output after passing through the loop filter , and it is fed back to the numerically controlled oscillator, and then the output is sent to the phase compensation module, and the received signal is further adjusted using the estimated value to obtain the signal after carrier phase compensation and output, entering the next cycle until the calculation of the entire data segment is completed.

[0093] Among them, as shown in Figure 3 , the physical layer frame structure in the burst communication system mainly consists of a frame header, a pilot, and data. Except for the frame header, the rest is collectively referred to as the data segment, and the length is denoted as L. The frame header and the pilot often use low-order modulation such as BPSK, ; the UW code uses QPSK modulation; the data uses modulation methods such as QPSK, 8PSK, or higher-order modulation.

[0094] During the signal transmission process, the data segment uses M-PSK modulation, that is, the transmitted data , and its expression is:

[0095]

[0096] Wherein, , .

[0097] The shaping filter and the matched filter comply with the Nyquist criterion, that is:

[0098]

[0099] After passing through the matched filter and ideal timing synchronization, the signal without inter-symbol interference, with frequency offset and phase offset, is defined as the input signal after carrier frequency offset compensation .

[0100] Specifically, assume that the received signal at the receiving end is:

[0101]

[0102] Wherein, represents the frequency offset; represents the phase offset; represents the timing error. Therefore, the signal sampled at the ideal sampling moment after passing through the matched filter is:

[0103]

[0104] Integrating the above expressions, the following expression can be obtained:

[0105]

[0106] Wherein, represents complex Gaussian white noise with a mean of 0 and a variance of ; for the term, because only takes valid values in a certain interval of , so can be replaced by , that is:

[0107]

[0108] Further integrating the above formula, the following can be obtained:

[0109]

[0110] After ideal timing synchronization, the signal with frequency offset and phase offset has the following expression:

[0111]

[0112] In this embodiment, the input control word ctrl_word is used to adaptively control the phase discrimination algorithm of the phase discriminator, so that the phase discriminator is applicable to different modulation methods.

[0113] In a further embodiment, the reverse loop in the dual-PLL loop is as Figure 4 shown. After the forward loop completes phase capture and tracking, the parameter state of the PLL in the forward loop is used to initialize the parameters of the PLL in the reverse loop, where the PLL structure of the reverse loop is the same as that of the forward loop. The input data of the reverse loop is the reverse output of the data in the data cache module, and the data in the data cache module is the cached data segment when the forward loop is working. The reverse output data enters the phase compensation module and then performs phase tracking through the PLL. Since the forward loop stage has entered the phase tracking stage and there is no capture time in the process of the reverse loop, the phase tracking is directly performed on the data segment. Therefore, the normalized loop bandwidth of the PLL in the reverse loop can be set to a smaller value to achieve the purpose of suppressing noise and reducing phase jitter. There will be phase ambiguity in the data after passing through the PLL. Therefore, in this application, phase ambiguity resolution processing is performed before data output, and the data is output .

[0114] In a further embodiment, during the process of the PLL performing data processing, the following steps are further included:

[0115] Step a: The phase detector selects a corresponding phase detection algorithm according to the preset control word state to adapt to different modulation methods;

[0116] Step b: The input data obtains a phase error after passing through the phase detector;

[0117] Step c: The loop filter processes the phase error and feeds the corresponding output value back to the numerically controlled oscillator;

[0118] Step d: An estimated value is obtained after being processed by the numerically controlled oscillator, and the input signal is adjusted and updated using phase compensation according to the estimated value.

[0119] Among them, the phase detector is used to adaptively adjust a suitable phase detection algorithm according to different modulation methods. Further, when the real part of the input signal of the phase detector is , and the imaginary part is ,

[0120] For BPSK modulation signals, the corresponding phase error extraction expression is:

[0121]

[0122] For QPSK modulation signals, the corresponding phase error extraction expression is:

[0123]

[0124] For the 8PSK modulation signal, the corresponding phase error The extraction expression is:

[0125]

[0126] In the formula, .

[0127] The loop filter is mainly used to filter out the high-frequency components in the output error signal of the phase detector, playing a role in smoothing filtering. It plays an important role in loop stability, improving noise performance, and acquisition and tracking. Therefore, when processing the phase error, the loop filter in this embodiment uses a second-order loop filter to filter out the high-frequency components in the output error signal of the phase detector and outputs ;

[0128] Furthermore, the output The expression is:

[0129]

[0130] Among them,

[0131]

[0132]

[0133]

[0134] In the formula, represents the integral gain; represents the phase error output by the phase detector; represents the normalized loop bandwidth, and the value is a positive number in the range of 0 to 1; represents the natural angular frequency; represents the damping factor; represents the phase recovery gain, which is equal to the number of samples of each symbol input to the phase-locked loop; represents the phase error detector gain, which is related to the modulation method. When the modulation method is QPSK, it is defined as 2, and when the modulation method is BPSK or 8PSK, it is defined as 1.

[0135] The numerically controlled oscillator uses a direct digital synthesizer and obtains an estimated value based on the forward Euler integration rule. The corresponding expression is:

[0136]

[0137]

[0138] In the formula, represents the proportional gain; represents the phase error output by the forward phase detector; represents the output value of the forward loop filter.

[0139] In a further embodiment, the phase ambiguity of the output signal after the dual-PLL depends on the modulation method, as shown in Table 1 below.

[0140] Table 1 Phase ambiguity of different modulation methods

[0141] Modulation method Phase ambiguity (unit: degree) BPSK 0,180 QPSK 0,90,180,270 8PSK 0,45,90,135,180,225,270,3

[0142] To compensate for the phase ambiguity of the output signal of the dual-PLL, the present application performs maximum likelihood phase ambiguity estimation on the output signal after the reverse PLL using the UW code, that is:

[0143]

[0144] In the formula, h represents the length of the UW segment; represents the conjugate of the known UW symbol; represents the input data signal of the phase ambiguity resolution module.

[0145] In a further embodiment, an adaptive phase tracking method is implemented through a top-level FPGA module based on dual-PLL adaptive phase tracking. As Figure 5 shown, the module is configured to receive the reset signal rst, system clock clk, enable signal I_data_en, control word signal I_ctrl_word, and 12-bit wide data I_data_i, I_data_q; and output the enable signal O_pha_comp_en, 12-bit wide data O_pha_comp_i, O_pha_comp_q.

[0146] To adapt to the top-level FPGA module, the interface of the module is set as shown in Table 2 below.

[0147] Table 2 Interface design of the top-level module based on dual-PLL adaptive phase tracking

[0148] Interface name Signal direction Bit width (bit) Description k I 1 System clock t I 1 Reset signal, active high I_data_i I 12 Data input I path I_data_q I 12 Data output Q path I_data_en I 1 Input data enable, active high I_ctrl_word I 2 Input control word signal, 00 represents BPSK modulation, 01 represents QPSK modulation, 10 represents 8PSK modulation O_pha_comp_i O 12 Output I path data after carrier phase tracking O_pha_comp_q O 12 Output Q path data after carrier phase tracking O_pha_comp_en O 1 Modulation output data enable, active high

[0149] In a further embodiment, during the process of the top-level FPGA module implementing dual-PLL adaptive phase tracking, the timing of some interfaces is as Figure 6 shown.

[0150] In one embodiment, an adaptive phase tracking system is proposed to implement an adaptive phase tracking method. As Figure 7 shown, the system specifically includes:

[0151] Phase compensation module (PHA_SHIFT), which is configured to perform carrier phase compensation on the received input signal;

[0152] Phase-locked loop module (PLL), which is configured to receive the data signal output by the phase compensation module and capture and track it;

[0153] Data length judgment module (JUDGE), which is configured to receive the data signal output by the phase compensation module and count and judge the input data length;

[0154] Memory (REG_D), which is configured to store the entire data segment;

[0155] Phase ambiguity resolution module (PHA_AMBIGU), which is configured to perform ambiguity resolution processing on the input signal;

[0156] Phase detector (PD), which is configured to calculate the phase error of the input signal;

[0157] Loop filter (LF), which is configured to filter out the high-frequency components in the input phase error signal for smoothing filtering;

[0158] Numerically controlled oscillator (NCO), which is configured to generate a demodulation wave with the same frequency and phase as the input signal according to the received signal and input it into the phase compensation module.

[0159] Specifically, first, after receiving the input signal, the phase compensation module performs phase compensation on the input signal according to the signal state. On the one hand, it enters two branches of the phase-locked loop module and the data length judgment module respectively in the forward loop; on the other hand, it enters two branches of the phase-locked loop module and the phase ambiguity resolution module in the reverse loop. Secondly, the phase-locked loop module captures and tracks the data signal output by the phase compensation module, and outputs the phase error value and the enable signal to the phase compensation module. Thirdly, the data length judgment module receives the data signal output by the phase compensation module, counts and judges the input data length according to the signal state output by the phase-locked loop module, and updates the signal state of the trigger memory according to the judgment result. Fourthly, the phase detector adaptively adjusts the calculation method of the phase error of the phase detector through the control word input by the phase-locked loop module. After determining the error calculation method, it calculates the phase difference using the real part and the imaginary part of the input signal. After completing the calculation of the phase error, it pulls up the enable signal and outputs the phase error to the loop filter. Subsequently, the loop filter filters out the high-frequency components in the received phase error signal and feeds it back to the numerically controlled oscillator. Finally, the numerically controlled oscillator inputs the processed data into the phase compensation module and updates the data using the estimated value, and enters the loop. After completing the calculation of the entire data segment, it inputs the data into the phase ambiguity resolution module for phase ambiguity resolution processing.

[0160] In a further embodiment, the phase compensation module is configured to perform phase compensation on the carrier of the input signal. In the process of implementing the adaptive phase tracking, this module is used twice. The first time is in the forward loop. When the input enable signal I_data_en is pulled high, the phase compensation is performed on the input signals I_data_i and I_data_q. After the phase compensation is completed, the corresponding enable signal w_pha_syn_en, the output signals w_pha_syn_i and w_pha_syn_q are output, and the output signals are input into two branches of the phase-locked loop module and the data length judgment module. The second time is in the reverse loop. When the input enable signal w_rev_data_en is pulled high, after the phase compensation is performed on the input signals w_rev_data_i and w_rev_data_q, the enable signal w_pha_syn_en2, the output signals w_pha_syn_i2 and w_pha_syn_q2 are output, and the output signals are input into two branches of the phase-locked loop module and the de-phase ambiguity module.

[0161] The data length judgment module is configured to receive the data signals output by the phase compensation module and perform statistics and judgment on the input data length. When counting and judging the input data number in the forward loop, first judge the input enable signal w_pha_syn_en. When the input enable signal w_pha_syn_en is pulled high, the data length judgment module counts and judges the input data number. When the length is not less than the data segment length L, the signal state of the trigger memory is updated, that is, the control signal w_syn_ctrl state of the trigger memory is changed from the initial state of 0 to 1. At the same time, the final parameter state of the phase-locked loop module in the forward loop is stored in the register REG_M of the data length judgment module for the initialization of the PLL sub-module of the phase-locked loop module in the reverse loop; when the length is less than the data segment length L, w_syn_ctrl maintains its initial state 0.

[0162] The phase-locked loop module is configured to receive the data signals output by the phase compensation module and perform capture and tracking on them. In the process of implementing the adaptive phase tracking, this module is used twice. The first time is in the forward loop. When the input enable signal w_pha_comp_en is pulled high, the phase capture and tracking are performed on the input signals w_pha_comp_i and w_pha_comp_q, and the phase error value w_pha_est and the enable signal w_pha_en are output and enter the phase compensation module. The second time is in the reverse loop. When the input enable signal w_pha_syn_en is pulled high, the phase capture and tracking are performed on the input signals w_pha_syn_i and w_pha_syn_q, and the phase error value w_pha_est2 and the enable signal w_pha_en2 are output and enter the phase compensation module.

[0163] As Figure 8 shown, the phase detector is set to calculate the phase error of the input signal. Since the calculation method is different for different modulation methods, when w_pha_comp_en is pulled high, in this embodiment, the phase-locked loop identifies the I_ctrl_word byte of the input control word to adaptively adjust the calculation method of the phase error of the phase detector. After determining the error calculation method, the phase-locked loop calculates the phase difference using the real and imaginary parts of the input signal. After completing the calculation of the phase error, the output enable signal w_pd_en is pulled high, and w_pha_err is output and enters the loop filter.

[0164] The loop filter is set to filter out the high-frequency components in the input phase error signal for smoothing filtering; when the enable signal w_pd_en is pulled high, it performs loop filtering on the input phase error signal. After completion, the output enable signal w_lf_en is pulled high, and the frequency control word w_fre_ctrl_word is output and enters the numerically controlled oscillator.

[0165] The memory is set to store the entire data segment and is implemented using dual-port RAM. When the input enable signal I_data_en is pulled high, it starts to store the input data. When the output control signal w_syn_ctrl to the forward loop data length determination module is pulled high, this module reversely outputs the data w_rev_data_i, w_rev_data_q, and the enable signal w_rev_data_en and enters the phase compensation module.

[0166] The phase ambiguity resolution module is set to perform ambiguity resolution processing on the input signal; when the input signal w_pha_syn_en2 is pulled high, it performs phase ambiguity resolution processing on the input signal, and the output signals O_pha_comp_i and O_pha_comp_q are used as the final output of the dual-PLL adaptive phase tracking module.

[0167] In summary, an adaptive phase tracking method and system proposed in this application are divided into a forward loop and a reverse loop during implementation. By combining the characteristic that the phase-locked loop has better synchronization performance than the open-loop structure during the tracking stage, a dual-PLL adaptive phase tracking implementation architecture is constructed. On the one hand, according to different modulation methods, it adaptively adjusts the appropriate phase detection algorithm to make the dual-PLL adaptive phase tracking algorithm applicable to different modulation methods, and can flexibly switch between different modulations such as BPSK, QPSK, 8PSK, etc., greatly reducing the resource occupancy of FPGA implementation.

[0168] On the other hand, when using a dual-PLL for phase tracking, according to different modulation mode types, there will be phase ambiguities at different angles in the output signals of the dual-PLL. Therefore, the output signals of the dual-PLL are further processed to resolve the phase ambiguity, and this module is placed at the output position of the reverse PLL to make it easier to implement. Thus, under the condition of ensuring the minimum resource occupation, the bit error performance of the system is greatly improved.

[0169] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as a limitation on the present invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. An adaptive phase tracking method, characterized in that, Specifically, it includes the following steps: Step 1: Construct an adaptive phase tracking framework structure and receive the input signal after carrier frequency offset compensation; Step 2: Divide the received input signal into two paths for processing. One path enters the forward loop, and the other path is processed by caching and is used for the reverse loop; Step 3: The forward loop performs phase compensation processing on the received input signal and judges the data length of the input signal after phase compensation; Step 4: When the data length of the input signal after phase compensation is less than the preset length L, no output is made, and the phase detector adaptively applies different modulation methods according to the received control word status, and combines the loop filter and the numerically controlled oscillator to obtain an estimated value, then jumps to Step 3, and uses the estimated value to perform phase adjustment on the input signal received in Step 1; On the contrary, output the control signal syn_ctrl, store the final parameter status value of the PLL, and jump to Step 5; Step 5: Initialize the loop parameters of the PLL in the reverse loop according to the final parameter status value of the PLL; Step 6: Read the data stored in Step 2, perform reverse output on it, and perform phase tracking through the PLL after phase compensation processing; Step 7: Perform de-phase ambiguity processing on the data signal after passing through the PLL; Step 8: Output the final data; The PLL represents a phase-locked loop.

2. An adaptive phase tracking method according to claim 1, wherein When the forward loop implements the phase acquisition and tracking process, it further includes the following steps: Step 1: Perform phase compensation on the input signal according to the status of the received input enable signal; Step 2: Divide the input data after phase compensation into two paths for processing. One path judges the data length, and the other path enters the PLL for data processing; Step 3: When the data length of the input signal after phase compensation is less than the preset length L, no output is made, and the phase detector adaptively applies different modulation methods according to the received control word status, and combines the loop filter and the numerically controlled oscillator to obtain an estimated value, and uses the estimated value to adjust the input signal received in Step 1; On the contrary, output the control signal for triggering data storage and store the final parameter status value of the PLL.

3. An adaptive phase tracking method according to claim 2, It is characterized in that Among them, during the process of the PLL performing data processing, it further includes the following steps: Step 2.1: The phase detector selects the corresponding phase detection algorithm according to the preset control word status to adapt to different modulation methods; Step 2.2: The input data obtains a phase error after passing through the phase detector; Step 2.3: The loop filter processes the phase error and feeds the corresponding output value back to the numerically controlled oscillator; Step 2.4: Obtain an estimated value through the processing of the numerically controlled oscillator, and use phase compensation to adjust and update the input signal according to the estimated value.

4. An adaptive phase tracking method according to claim 2, wherein The phase detector is used to adaptively adjust the suitable phase detection algorithm according to different modulation methods; Further, when the real part of the input signal of the phase detector is , and the imaginary part is , For the BPSK modulated signal, the corresponding phase error The extraction expression is: For QPSK modulated signals, the corresponding phase error The extraction expression is: For the 8PSK modulation signal, the corresponding phase error The extraction expression is: In the formula, .

5. An adaptive phase tracking method according to claim 2, wherein When processing the phase error, the loop filter uses a second-order loop filter to filter out the high-frequency components in the output error signal of the phase detector and outputs ; Further, the output expression is: Wherein, represents the integral gain; represents the phase error output by the phase detector.

6. An adaptive phase tracking method according to claim 2, characterized in that the numerically controlled oscillator uses a direct digital synthesizer and obtains an estimated value based on the forward Euler integration rule, and the corresponding expression is: In the formula, represents the proportional gain; represents the phase error output by the forward phase detector; represents the output value of the forward loop filter.

7. An adaptive phase tracking method according to claim 1, characterized in that when the reverse loop implements the phase tracking process, it further includes the following steps: Step a: Initialize the PLL parameters in the reverse loop according to the final PLL parameters output by the forward loop; Step b: Receive and read the data stored in step two, output it reversely, and perform phase tracking through the PLL in the reverse loop after performing phase compensation processing; Step c: Perform de-phase ambiguity processing on the data signal after passing through the PLL; Step d: Output the final data.

8. An adaptive phase tracking method according to claim 7, characterized in that When performing de-phase ambiguity processing on the data signal after passing through the PLL, further use the UW code to perform maximum likelihood phase ambiguity estimation, and the corresponding expression is: Where h represents the length of the UW segment; represents the input data signal of the phase-unwrapping ambiguity module; represents the conjugate of the known UW symbol.

9. An adaptive phase tracking method according to claim 1, characterized in that An adaptive phase tracking method is implemented through a top-level FPGA module based on dual-PLL adaptive phase tracking; Furthermore, the top-level FPGA module is set to receive including: a reset signal rst, a system clock clk, an enable signal I_data_en, a control word signal I_ctrl_word, and 12-bit wide data I_data_i, I_data_q; The outputs include: an enable signal O_pha_comp_en, 12-bit wide data O_pha_comp_i, O_pha_comp_q.

10. An adaptive phase tracking system for implementing the method according to any one of claims 1-8, characterized in that, Specifically, it includes: A phase compensation module (PHA_SHIFT), which is set to perform carrier phase compensation on the received input signal; A phase-locked loop module (PLL), which is set to receive the data signal output by the phase compensation module and capture and track it; A data length judgment module (JUDGE), which is set to receive the data signal output by the phase compensation module and count and judge the input data length; A memory (REG_D), which is set to store the entire data segment; A de-phase ambiguity module (PHA_AMBIGU), which is set to perform de-ambiguity processing on the input signal; A phase detector (PD), which is set to calculate the phase error of the input signal; A loop filter (LF), which is set to filter out the high-frequency components in the input phase error signal for smoothing filtering; A numerically controlled oscillator (NCO), which is set to generate a demodulation wave with the same frequency and phase as the input signal according to the received signal and input it into the phase compensation module; Furthermore, after receiving the input signal, the phase compensation module will perform phase compensation on the input signal according to the signal state, and on the one hand, enter two branches of the phase-locked loop module and the data length judgment module in the forward loop respectively; on the other hand, enter two branches of the phase-locked loop module and the de-phase ambiguity module in the reverse loop; Secondly, the phase-locked loop module captures and tracks the data signal output by the phase compensation module, and outputs the phase error value and the enable signal into the phase compensation module; Next, the data length judgment module receives the data signal output by the phase compensation module, statistically analyzes and judges the input data length according to the signal state output by the phase-locked loop module, and updates the signal state of the trigger memory according to the judgment result; Secondly, the phase detector adaptively adjusts the calculation method of the phase error of the phase detector by inputting a control word through the phase-locked loop module. After determining the error calculation method, the phase difference is calculated using the real and imaginary parts of the input signal. After completing the calculation of the phase error, the enable signal is pulled high, and the phase error is output to the loop filter; Subsequently, the loop filter filters out the high-frequency components in the received phase error signal and feeds them back to the numerically controlled oscillator; Finally, the numerically controlled oscillator inputs the processed data into the phase compensation module, updates the data using the estimated value, and enters a loop. After completing the calculation of the entire data segment, the data is input into the phase ambiguity resolution module for phase ambiguity resolution processing.

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