General purpose digital signal processing apparatus, method and system

Abstract

The embodiment of the present application discloses a kind of general digital signal processing device, method and system.The device includes instruction module, operator calculation module and serial calculation module;Instruction module reads instruction from memory and generates operator control instruction and serial control instruction, sends operator control instruction to operator calculation module, and sends serial control instruction to serial calculation module;Operator calculation module receives operator control instruction, reads first data from memory according to operator control instruction, carries out vector calculation to first data and obtains vector calculation result and writes into memory;Serial calculation module receives serial control instruction, reads second data from memory according to serial control instruction, carries out non-vector calculation to second data and obtains non-vector calculation result and writes into memory.The embodiment of the present application can achieve the better balance of time efficiency, energy efficiency and flexibility of signal processor, and optimize the existing general digital signal processor architecture.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and more particularly to a general digital signal processing device, method and system. Background Technology

[0002] Numerous digital signal processing tasks are involved in fields such as wireless communication, digital image processing, and radar. Digital signal processing includes three basic operations: multiplication, addition, and shift operations. Various algorithms can be written as combinations of these three operations. The characteristics of digital signal processing operations are that large amounts of data undergo the same operation, its control logic is simple, and its input / output data throughput is very large.

[0003] Most existing general-purpose digital signal processors are based on the von Neumann architecture, the Harvard architecture, or their evolutions. They still use the instruction-data execution mode and do not take into account the data flow-driven characteristics of digital signal processing. As a result, these processors have low energy efficiency and time efficiency in completing digital signal processing tasks. Summary of the Invention

[0004] This invention provides a general-purpose digital signal processing device, method, and system that, by utilizing the characteristics of data stream-driven operation, achieves a good balance between time efficiency, energy efficiency, and flexibility of the signal processor, thus optimizing the existing general-purpose digital signal processor architecture.

[0005] In a first aspect, embodiments of the present invention provide a general-purpose digital signal processing device, comprising: an instruction module, an operator calculation module, and a serial calculation module;

[0006] The instruction module is configured to read instructions from memory, generate operator control instructions or serial control instructions according to the instructions, send the operator control instructions to the operator calculation module, and send the serial control instructions to the serial calculation module.

[0007] The operator calculation module is used to receive operator control instructions sent by the instruction module, read first data from the memory according to the operator control instructions, perform vector calculation on the first data and obtain vector calculation results, and write the vector calculation results into the memory;

[0008] The serial calculation module is used to receive serial control instructions sent by the instruction module, read second data from the memory according to the serial control instructions, perform non-vector calculation on the second data and obtain non-vector calculation results, and write the non-vector calculation results into the memory.

[0009] In a second aspect, embodiments of the present invention also provide a general digital signal processing method, executed by the general digital signal processing apparatus provided in the first aspect, the method comprising:

[0010] The instruction module reads instructions from the memory, generates operator control instructions or serial control instructions based on the instructions, sends the operator control instructions to the operator calculation module, and sends the serial control instructions to the serial calculation module.

[0011] The operator calculation module receives the operator control instruction sent by the instruction module, reads the first data from the memory according to the operator control instruction, performs vector calculation on the first data and obtains the vector calculation result, and writes the vector calculation result into the memory;

[0012] The serial calculation module receives the serial control command sent by the instruction module, reads the second data from the memory according to the serial control command, performs non-vector calculation on the second data and obtains the non-vector calculation result, and writes the non-vector calculation result into the memory.

[0013] Thirdly, embodiments of the present invention also provide a general-purpose digital signal processing system, including a memory and at least two data access buses, including the general-purpose digital signal processing apparatus provided in the first aspect.

[0014] The technical solution of this invention embodiment is that the operator calculation module completes the core calculation tasks in the algorithm, realizes the unification and flexible expansion of the basic operator form, realizes direct data interaction with the memory by using direct memory access, eliminates the instruction-data path bottleneck, and utilizes the characteristics of data flow drive to ensure that the instruction reception and execution processes of the serial calculation module and the operator calculation module do not affect each other, thus achieving a good balance between the time efficiency, energy efficiency and flexibility of the signal processor, and optimizing the existing general-purpose digital signal processor architecture. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a general digital signal processing device provided in Embodiment 1 of the present invention.

[0016] Figure 2 This is a schematic diagram of a general-purpose digital signal processing device provided in Embodiment 2 of the present invention.

[0017] Figure 3 This is a schematic diagram of the operation of the butterfly arithmetic operator provided in Embodiment 2 of the present invention.

[0018] Figure 4 This is a flowchart of a general digital signal processing method provided in Embodiment 3 of the present invention.

[0019] Figure 5This is a schematic diagram of the structure of a general digital signal processing system provided in Embodiment 4 of the present invention. Detailed Implementation

[0020] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it.

[0021] It should also be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention and not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but it may also have additional steps not included in the drawings. The process may correspond to a method, function, procedure, subroutine, subroutine, etc.

[0022] Example 1

[0023] Figure 1 This is a schematic diagram of the structure of a general-purpose digital signal processing device provided in Embodiment 1 of the present invention. Figure 1 As shown, the device includes: an instruction module 11, an operator calculation module 12, and a serial calculation module 13.

[0024] The instruction module 11 is used to read instructions from the memory, generate operator control instructions or serial control instructions according to the instructions, send the operator control instructions to the operator calculation module 12, and send the serial control instructions to the serial calculation module 13.

[0025] The memory stores instructions and data to be calculated. The instruction module 11 reads instructions from the memory and decodes them to generate operator control instructions or serial control instructions. The operator control instructions are sent to the operator calculation module 12 and control the operator calculation module 12 to read the first data from the data to be calculated in the memory. The serial control instructions are sent to the serial calculation module 13 and control the serial calculation module 13 to read the second data from the data to be calculated in the memory.

[0026] The operator calculation module 12 is used to receive operator control instructions sent by the instruction module 11, read first data from the memory according to the operator control instructions, perform vector calculation on the first data and obtain vector calculation results, and write the vector calculation results into the memory.

[0027] The operator calculation module 12 is used to complete the core calculation tasks in the algorithm, performing vector calculations using various basic operators of vector signal analysis. The first data, which is the data required for the core calculation tasks in the algorithm, is stored in memory. The process of the operator calculation module 12 performing vector calculations on the first data is data-stream driven. After reading the first data from memory using direct memory access, no instructions need to be sent by the instruction module 11 to complete the vector calculations on all received first data. The basic operators of vector signal analysis can perform vector calculations on multiple first data in parallel. The vector calculation result is the result required for the core calculation tasks in the algorithm.

[0028] The serial calculation module 13 is used to receive the serial control command sent by the instruction module 11, read the second data from the memory according to the serial control command, perform non-vector calculation on the second data and obtain the non-vector calculation result, and write the non-vector calculation result into the memory.

[0029] The serial computing module 13 is used to perform tasks such as simple scalar computation, program flow control, and direct memory access (GDMA) configuration. The serial computing module 13 includes a serial computing unit, a register set, and a read / write (LD / ST) unit. The serial computing unit can be a simple self-developed Reduced Instruction Set Computing (RISC) processor or a simple processor based on a RISC-V / ARM processor architecture, used to perform non-vector computation. The register set includes at least one register for storing second data read from memory by the read / write unit and non-vector computation results written by the serial computing unit. The read / write unit is used to receive serial control instructions sent by the instruction module 11, and according to the serial control instructions, read second data from memory and write it into the register, or read non-vector computation results from the register and write them into memory. The second data is the data required for computation in tasks such as simple scalar computation, program flow control, and direct memory access configuration, and is stored in memory. One serial control instruction can control the serial computing module 13 to perform non-vector computation on a piece of second data. The non-vector computation result is the computation result required for tasks such as simple scalar computation, program flow control, and direct memory access configuration.

[0030] This embodiment provides a general-purpose digital signal processing device that utilizes an operator computation module to complete the core computational tasks in the algorithm, achieving a unified and flexible expansion of the basic operator form. It uses direct memory access to achieve direct data interaction with the memory, eliminating the instruction-data path bottleneck. By leveraging the characteristics of data flow driving, the instruction reception and execution processes of the serial computation module and the operator computation module do not interfere with each other, achieving a good balance between the time efficiency, energy efficiency, and flexibility of the signal processor, and optimizing the existing general-purpose digital signal processor architecture.

[0031] In an optional embodiment of the above embodiments, the instruction module 11 and the serial computing module 13 are connected to the memory via a first data access bus, and the operator computing module 12 is connected to the memory via a second data access bus.

[0032] Alternatively, the instruction module 11 is connected to the memory via a first data access bus, and the serial calculation module 13 and the operator calculation module 12 are connected to the memory via a second data access bus;

[0033] Alternatively, the instruction module 11 may be connected to the memory via a first data access bus, the operator calculation module 12 may be connected to the memory via a second data access bus, and the serial calculation module 13 may be connected to the memory via a third data access bus.

[0034] The first data access bus can be used for data interaction between the instruction module 11 and the memory, and the second data access bus can be used for data interaction between the operator calculation module 12 and the memory. The amount of data interaction between the serial calculation module 13 and the memory is relatively small, and can be implemented by the first data access bus or the second data access bus, or by the third data access bus used for data interaction between the serial calculation module 13 and the memory.

[0035] The above embodiments provide a general-purpose digital signal processing device with multiplexed data access bus. By merging the data interaction between the serial computing module and the memory into a first data access bus or a second data access bus, the architecture of the general-purpose digital signal processing device is further optimized, and the integration complexity of the general-purpose digital signal processing device in the system is reduced.

[0036] Example 2

[0037] Figure 2 This is a schematic diagram of the structure of a general-purpose digital signal processing device provided in Embodiment 2 of the present invention. Figure 2 As shown, based on Embodiment 1, the operator calculation module 12 includes: an operator calculation unit 121 and a direct memory access controller 122.

[0038] The operator calculation unit 121 is used to perform vector calculations on the first data and obtain vector calculation results.

[0039] The operator calculation unit 121 starts performing vector calculations after receiving the first data, without requiring any instructions from the instruction module 11, and is driven by the data stream.

[0040] Optionally, the operator calculation unit 121 includes at least three basic vector signal analysis operators for performing corresponding type vector calculations on the first data and obtaining vector calculation results.

[0041] The operator computation unit 121 contains at least three basic vector signal analysis operators that include basic signal processing operations. Their combination can perform all computational tasks in the core computational task of the algorithm. The basic vector signal analysis operators are general-purpose operators.

[0042] Optionally, the at least three basic operators for vector signal analysis include: a vector scaling operator, a vector dot product operator, and a vector multiplication operator.

[0043] The combination of vector scaling operators, vector dot product operators, and vector multiplication operators can accomplish all the computational tasks required for signal processing.

[0044] Optionally, the at least three basic vector signal analysis operators further include at least one of the following: matrix multiplication operator, convolution operator, correlation operator, butterfly operation operator, polynomial operation operator, lookup table operator, accumulation operator, comparison operator, and tensor operation operator.

[0045] The matrix multiplication operator can be optimized for operations on 2×2 and 4×4 matrices, reducing the amount of external memory access. For example, the expression for the matrix multiplication operator for a 2×2 matrix is:

[0046]

[0047] Convolution operators can be used to filter signals. For example, the Finite Impulse Response (FIR) filter is a common convolution operation. The expression for the convolution operator that implements the convolution operation of an FIR filter is:

[0048]

[0049] in, These are filter coefficients, which often exhibit symmetry. Given a fixed number of multipliers, special structures are often used to support higher-order FIR filters. For example, when K is even, the convolution operator expression is:

[0050]

[0051] For example, when K is odd, the convolution operator expression is:

[0052]

[0053] The expression for the relevant operator is:

[0054]

[0055] Butterfly operators such as Figure 3 As shown, for example, two vectors are input. and After the butterfly factor is applied, the output results are two new vectors.

[0056]

[0057] and .

[0058] An enhanced form of the butterfly operator is to add two normalized multiplication coefficients C0 and C1 to the output.

[0059] The expression for polynomial operators is:

[0060]

[0061] The lookup table operator is mainly divided into two forms: finding the corresponding element in the table based on the index and outputting the index corresponding to the non-zero element in the vector.

[0062] The expression for the accumulation operator is:

[0063]

[0064] The comparison operator is used to compare corresponding elements of vectors a and b, and its expression is:

[0065]

[0066] Tensor operators are used in high-dimensional digital signal processing.

[0067] The operator computation unit 121 may also include other general-purpose vector signal analysis basic operators that can perform signal processing computation tasks, thereby enabling operator expansion. Optionally, at least two of the vector signal analysis basic operators included in the operator computation unit 121 may be hardware reused.

[0068] The above implementation method can achieve a unified and flexible expansion of the basic operator form, greatly improve the efficiency of a certain type of algorithm application of the general digital signal processing device, and has simple logic.

[0069] The direct memory access controller 122 is used to receive the operator control instruction, read the first data from the memory and write it into the operator calculation unit 121 according to the operator control instruction, and read the vector calculation result from the operator calculation unit 121 and write it into the memory.

[0070] The direct memory access controller 122 interacts directly with the memory using General Direct Memory Access (GDMA) in slave mode. Upon receiving an operator control command, the direct memory access controller 122 addresses the first data in the memory and reads it, writing it into the operator calculation unit 121. When the operator calculation unit 121 completes the vector calculation and obtains the result, the direct memory access controller 122 automatically addresses the result and writes it into the memory.

[0071] Optionally, the direct storage access controller 122 is used to write data to the next vector signal analysis basic operator after the previous vector signal analysis basic operator has completed vector calculation.

[0072] After receiving the data written by the direct memory access controller 122, the basic vector signal analysis operator begins to perform vector calculations on the data. All basic vector signal analysis operators perform vector calculations serially.

[0073] Optionally, the direct memory access controller 122 is used to write all the data in the first data that need to perform the same type of vector calculation to the corresponding type of vector signal analysis basic operator, so that the vector signal analysis basic operator can perform vector calculation on the data simultaneously.

[0074] This embodiment provides a general-purpose digital signal processing device. It utilizes an operator computation module to complete the core computational tasks in the algorithm, achieving a unified and flexible expansion of basic operator forms. Direct memory access enables direct data interaction with memory, eliminating the instruction-data path bottleneck. Leveraging the characteristics of data flow-driven processing, the instruction reception and execution processes of the serial computation module and the operator computation module do not interfere with each other, achieving a good balance between time efficiency, energy efficiency, and flexibility of the signal processor, thus optimizing the existing general-purpose digital signal processor architecture. Furthermore, by utilizing the vector signal analysis basic operators included in the operator computation unit to perform vector calculations on multiple data simultaneously, parallel computation of large amounts of data is achieved, further improving the working efficiency of the general-purpose digital signal processing device.

[0075] Example 3

[0076] Figure 4 This is a flowchart of a general digital signal processing method provided in Embodiment 3 of the present invention. This embodiment is applicable to general digital signal processing using serial computation and operator computation, and the method can be executed by the general digital signal processing apparatus provided in this embodiment of the present invention. Figure 4 As shown, this general digital signal processing method specifically includes:

[0077] Step 301: The instruction module reads instructions from the memory, generates operator control instructions or serial control instructions according to the instructions, sends the operator control instructions to the operator calculation module, and sends the serial control instructions to the serial calculation module.

[0078] Step 302: The operator calculation module receives the operator control instruction sent by the instruction module, reads the first data from the memory according to the operator control instruction, performs vector calculation on the first data and obtains the vector calculation result, and writes the vector calculation result into the memory.

[0079] Step 303: Receive the serial control command sent by the instruction module using the serial calculation module, read the second data from the memory according to the serial control command, perform non-vector calculation on the second data and obtain the non-vector calculation result, and write the non-vector calculation result into the memory.

[0080] Steps 302 and 303 are executed by the operator calculation module and the serial calculation module respectively. The execution processes do not affect each other, and the execution order is not limited.

[0081] The above embodiments utilize the operator computation module to complete the core computation tasks in the algorithm, realize the unification and flexible expansion of the basic operator form, use direct memory access to realize direct data interaction with memory, eliminate the instruction-data path bottleneck, and utilize the characteristics of data flow drive to ensure that the instruction reception and execution processes of the serial computation module and the operator computation module do not affect each other, thus achieving a good balance between the time efficiency, energy efficiency and flexibility of the signal processor, and optimizing the existing general-purpose digital signal processor architecture.

[0082] In an optional embodiment of this example, the instruction module and the serial computing module are connected to the memory via a first data access bus, and the operator computing module is connected to the memory via a second data access bus.

[0083] Alternatively, the instruction module is connected to the memory via a first data access bus, and the serial computing module and the operator computing module are connected to the memory via a second data access bus;

[0084] Alternatively, the instruction module 11 may be connected to the memory via a first data access bus, the operator calculation module 12 may be connected to the memory via a second data access bus, and the serial calculation module 13 may be connected to the memory via a third data access bus.

[0085] The above embodiments provide a general digital signal processing method that multiplexes a data access bus. By merging the data interaction between the serial computing module and the memory into a first data access bus or a second data access bus, the architecture of the general digital signal processing device is further optimized, and the integration complexity of the general digital signal processing device in the system is reduced.

[0086] In an optional embodiment of this example, the operator calculation module includes: an operator calculation unit and a direct memory access controller; wherein, the operator calculation unit is used to perform vector calculation on the first data and obtain a vector calculation result; the direct memory access controller is used to receive the operator control instruction, read the first data from the memory and write it to the operator calculation unit according to the operator control instruction, and read the vector calculation result from the operator calculation unit and write it to the memory. Step 302 specifically includes:

[0087] The direct memory access controller receives operator control instructions sent by the instruction unit, reads first data from the memory and writes it into the operator calculation unit according to the operator control instructions;

[0088] The operator calculation unit performs vector calculations on the first data to obtain the vector calculation results;

[0089] The direct memory access controller writes the vector calculation results into the memory.

[0090] Optionally, the operator calculation unit includes at least three basic vector signal analysis operators, and the step of using the operator calculation unit to perform vector calculation on the first data to obtain vector calculation results includes: using at least three basic vector signal analysis operators to perform vector calculations of the corresponding type on the first data and obtaining vector calculation results.

[0091] Optionally, the at least three basic operators for vector signal analysis include: a vector scaling operator, a vector dot product operator, and a vector multiplication operator.

[0092] Optionally, the at least three basic vector signal analysis operators further include at least one of the following: matrix multiplication operator, convolution operator, correlation operator, butterfly operation operator, polynomial operation operator, lookup table operator, accumulation operator, comparison operator, and tensor operation operator.

[0093] The above implementation method can achieve a unified and flexible expansion of the basic operator form, greatly improve the efficiency of a certain type of algorithm application of the general digital signal processing device, and has simple logic.

[0094] Optionally, the step of reading the first data from the memory and writing it into the operator calculation unit according to the operator control instruction includes: the direct memory access controller writing data to the next vector signal analysis basic operator after the previous vector signal analysis basic operator completes the vector calculation in every two vector signal analysis basic operators.

[0095] Optionally, the step of reading the first data from the memory and writing it into the operator calculation unit according to the operator control instruction further includes: the direct memory access controller writing all the data in the first data that need to perform the same type of vector calculation into the vector signal analysis basic operator of the corresponding type, so that the vector signal analysis basic operator performs vector calculation on the data simultaneously.

[0096] This implementation utilizes the operator computation module to complete the core computational tasks in the algorithm, achieving a unified and flexible expansion of the basic operator form. It employs direct memory access to enable direct data interaction with memory, eliminating the instruction-data path bottleneck. Leveraging the data flow-driven nature of the implementation, the instruction reception and execution processes of the serial computation module and the operator computation module do not interfere with each other, achieving a good balance between time efficiency, energy efficiency, and flexibility of the signal processor, thus optimizing the existing general-purpose digital signal processor architecture. The vector signal analysis basic operators included in the operator computation unit perform vector calculations on multiple data simultaneously, realizing parallel computation of large amounts of data and further improving the working efficiency of the general-purpose digital signal processing device.

[0097] Example 4

[0098] Figure 5 This is a schematic diagram of the structure of a general-purpose digital signal processing system provided in Embodiment 4 of the present invention. Figure 5 As shown, the system includes: a memory 51, at least two data access buses 52, and a general-purpose digital signal processing device 53 provided in Embodiment 1 or 2 of the present invention. This general-purpose digital signal processing system can execute the general-purpose digital signal processing method provided in Embodiment 3 of the present invention, with specific implementations corresponding to the implementation methods in the above embodiments.

[0099] The memory 51 is used to store instructions, data to be calculated, and calculation results. The memory 51 is connected to the instruction module in the general-purpose digital signal processing device 53 via a first data access bus, allowing the instruction module to read instructions from the memory 51. The memory 51 is connected to the operator calculation module in the general-purpose digital signal processing device 53 via a second data access bus, allowing the operator calculation module to read the first data from the data to be calculated from the memory 51 and write the vector calculation result into the memory 51. The memory 51 is connected to the serial calculation module in the general-purpose digital signal processing device 53 via the first, second, or third data access bus, allowing the serial calculation module to read the second data from the data to be calculated from the memory 51 and write the non-vector calculation result into the memory 51.

[0100] The at least two data access buses 52 include a first data access bus and a second data access bus. The first data access bus can be used for data interaction between the instruction module in the general-purpose digital signal processing device 53 and the memory 51. The second data access bus can be used for data interaction between the operator calculation module in the general-purpose digital signal processing device 53 and the memory 51. The amount of data interaction between the serial calculation module in the general-purpose digital signal processing device 53 and the memory 51 is relatively small and can be implemented by either the first or the second data access bus. The at least two data access buses 52 may also include a third data access bus. The data interaction between the serial calculation module in the general-purpose digital signal processing device 53 and the memory 51 can also be implemented by the third data access bus, which can be used for data interaction between the serial calculation module and the memory 51.

[0101] The general-purpose digital signal processing device 53 includes an instruction module, an operator calculation module, and a serial calculation module. The instruction module is used to read instructions from memory 51 via a first data access bus, generate operator control instructions or serial control instructions according to the instructions, send the operator control instructions to the operator calculation module, and send the serial control instructions to the serial calculation module. The operator calculation module is used to receive the operator control instructions sent by the instruction module, read first data from memory 51 via a second data access bus according to the operator control instructions, perform vector calculations on the first data and obtain a vector calculation result, and write the vector calculation result into memory 51. The serial calculation module is used to receive the serial control instructions sent by the instruction module, read second data from memory 51 via a first data access bus, a second data access bus, or a third data access bus according to the serial control instructions, perform non-vector calculations on the second data and obtain a non-vector calculation result, and write the non-vector calculation result into memory 51.

[0102] In one specific implementation of the general-purpose digital signal processing system, for example, when the system starts a data processing task, the instruction module in the general-purpose digital signal processing device 53 reads instruction S1 from memory 51 through the first data access bus of at least two data access buses 52 and decodes it to obtain a serial control instruction S1. The serial control instruction S1 is then sent to the serial calculation module in the general-purpose digital signal processing device 53. Upon receiving the serial control instruction S1, the serial calculation module reads a second piece of data from memory 51 through the first, second, or third data access bus according to the serial control instruction S1, performs a corresponding non-vector calculation on the second piece of data, obtains the non-vector calculation result, and writes the non-vector calculation result into memory 51. The instruction module then processes the serial control instruction... After S1 is sent to the serial computing module, the next instruction P1 can be read from the memory 51 and decoded to obtain the operator control instruction P1. The operator control instruction P1 is then sent to the operator computing module in the general-purpose digital signal processing device 53. Upon receiving the operator control instruction P1, the operator computing module reads multiple first data from the memory 51 through the second data access bus in at least two data access buses 52, performs corresponding vector calculations on the multiple first data, obtains the vector calculation results, and writes the vector calculation results into the memory 51. The operator computing module can perform vector calculations on multiple first data in parallel, and after reading the first data, no instruction module needs to send any instructions to complete the vector calculation, ensuring that the calculation processes of the operator computing module and the serial computing module do not interfere with each other. Following the above process, the data processing task is completed when the instruction module has read all instructions corresponding to the current data processing task from the memory 51, and the operator computing module and the serial computing module have written all calculation results into the memory 51.

[0103] The above implementation method improves data processing efficiency, allowing the operator calculation module to perform a high proportion of core algorithm calculation tasks, thereby improving the energy efficiency ratio of the calculation.

[0104] This embodiment provides a general-purpose digital signal processing system that utilizes operator computation modules to complete the core computational tasks in the algorithm, achieving a unified and flexible expansion of basic operator forms. It employs direct memory access to enable direct data interaction with memory, eliminating instruction-data path bottlenecks. Leveraging the characteristics of data flow-driven processing, the instruction reception and execution processes of the serial computation module and the operator computation module do not interfere with each other, achieving a good balance between time efficiency, energy efficiency, and flexibility of the signal processor, thus optimizing the existing general-purpose digital signal processor architecture. Furthermore, by merging the data interaction between the serial computation module and memory into a first or second data access bus, the architecture of the general-purpose digital signal processing device is further optimized, reducing the integration complexity of the general-purpose digital signal processing device within the system.

[0105] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A general-purpose digital signal processing device, characterized by comprising: The application relates to a data processing system, which comprises an instruction module, an operator calculation module and a serial calculation module. The instruction module is used for reading instructions from a memory, generating operator control instructions or serial control instructions according to the instructions, sending the operator control instructions to the operator calculation module and sending the serial control instructions to the serial calculation module. The operator calculation module is used for receiving the operator control instructions sent by the instruction module, reading first data from the memory according to the operator control instructions, performing vector calculation on the first data and obtaining vector calculation results, and writing the vector calculation results into the memory. The serial calculation module is used for receiving the serial control instructions sent by the instruction module, reading second data from the memory according to the serial control instructions, performing non-vector calculation on the second data and obtaining non-vector calculation results, and writing the non-vector calculation results into the memory. The operator calculation module comprises an operator calculation unit and a direct memory access controller. The operator calculation unit is used for performing vector calculation on the first data and obtaining vector calculation results; and the operator calculation unit is driven by a data stream. The direct memory access controller is used for receiving the operator control instructions, reading the first data from the memory according to the operator control instructions and writing the first data into the operator calculation unit, and reading the vector calculation results from the operator calculation unit and writing the vector calculation results into the memory; wherein the direct memory access controller directly interacts with the memory based on a slave mode general direct memory access, the direct memory access controller performs addressing operation on the first data in the memory after receiving the operator control instructions, reads the first data and writes the first data into the operator calculation unit, and automatically performs addressing operation on the vector calculation results when the vector calculation unit completes vector calculation and obtains the vector calculation results, and writes the vector calculation results into the memory. The operator calculation unit comprises at least three vector signal analysis basic operators which are used for performing corresponding type vector calculation on the first data and obtaining vector calculation results. The direct memory access controller is used for writing all data in the first data which need to perform the same type vector calculation into corresponding type vector signal analysis basic operators, so that the vector signal analysis basic operators simultaneously perform vector calculation on the data. The instruction module and the serial calculation module are connected with the memory through a first data access bus, the operator calculation module is connected with the memory through a second data access bus. Or, the instruction module is connected with the memory through a first data access bus, the serial calculation module and the operator calculation module are connected with the memory through a second data access bus. Or, the instruction module is connected with the memory through a first data access bus, the operator calculation module is connected with the memory through a second data access bus, and the serial calculation module is connected with the memory through a third data access bus. ​ 2. The apparatus of claim 1, wherein, The at least three vector signal analysis basic operators include a vector scaling operator, a vector dot product operator and a vector multiplication operator.

3. The apparatus of claim 2, wherein, The at least three vector signal analysis basic operators further include at least one of a matrix multiplication operator, a convolution operator, a correlation operator, a butterfly operation operator, a polynomial operation operator, a lookup table operator, an accumulation operator, a comparison operator and a tensor operation operator.

4. The apparatus of claim 1, wherein, The direct memory access controller is configured to write data to a next vector signal analysis basic operator after a previous vector signal analysis basic operator of every two vector signal analysis basic operators completes vector calculation.

5. A general digital signal processing method, characterized by, The method is performed by the universal digital signal processing device of any one of claims 1-4, and the method comprises: The instruction module reads instructions from the memory, generates operator control instructions or serial control instructions according to the instructions, sends the operator control instructions to the operator calculation module, and sends the serial control instructions to the serial calculation module; The operator calculation module receives the operator control instructions sent by the instruction module, reads first data from the memory according to the operator control instructions, performs vector calculation on the first data and obtains vector calculation results, and writes the vector calculation results into the memory; The serial calculation module receives the serial control instructions sent by the instruction module, reads second data from the memory according to the serial control instructions, performs non-vector calculation on the second data and obtains non-vector calculation results, and writes the non-vector calculation results into the memory; The operator calculation module comprises an operator calculation unit and a direct memory access controller. The operator calculation unit is configured to perform vector calculation on the first data and obtain vector calculation results, and the operator calculation unit is driven by a data stream. The direct memory access controller is configured to receive the operator control instructions, read the first data from the memory according to the operator control instructions and write the first data into the operator calculation unit, and read the vector calculation results from the operator calculation unit and write the vector calculation results into the memory; the direct memory access controller directly interacts with the memory based on a slave mode of universal direct memory access, the direct memory access controller performs addressing operation on the first data in the memory after receiving the operator control instructions, reads the first data and writes the first data into the operator calculation unit, when the operator calculation unit completes vector calculation and obtains vector calculation results, the direct memory access controller automatically performs addressing operation on the vector calculation results and writes the vector calculation results into the memory; The operator calculation unit comprises at least three vector signal analysis basic operators, the first data is calculated by the operator calculation unit to obtain vector calculation results, and the vector calculation results are obtained by using the at least three vector signal analysis basic operators to perform corresponding type vector calculation on the first data. The step of reading first data from memory and writing it into the operator calculation unit according to the operator control instruction further includes: the direct memory access controller writing all data in the first data that need to perform the same type of vector calculation into the corresponding type of vector signal analysis basic operator, so that the vector signal analysis basic operator performs vector calculation on the data simultaneously; The instruction module and the serial computing module are connected to the memory via a first data access bus, and the operator computing module is connected to the memory via a second data access bus. Alternatively, the instruction module is connected to the memory via a first data access bus, and the serial computing module and the operator computing module are connected to the memory via a second data access bus; Alternatively, the instruction module may be connected to the memory via a first data access bus, the operator calculation module may be connected to the memory via a second data access bus, and the serial calculation module may be connected to the memory via a third data access bus.

6. A general purpose digital signal processing system comprising a memory and at least two data access buses, characterized in that, Includes the general-purpose digital signal processing apparatus as described in any one of claims 1-4.

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