Semiconductor memory device

Abstract

Disclosed are a semiconductor memory device and a manufacturing method of a semiconductor memory device. A semiconductor device includes a substrate extending in a first direction and a second direction intersecting the first direction; a plurality of input / output pads provided on one side of the substrate; a first circuit adjacent to the input / output pads in the first direction; a second circuit provided farther apart from the input / output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; a plurality of first metal source patterns overlapping the first memory cell array and spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and having a width wider than a width of each of the first metal source patterns in the second direction.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memory devices and methods for manufacturing semiconductor memory devices, and more specifically, to a three-dimensional semiconductor memory device and a method for manufacturing a three-dimensional semiconductor memory device. Background Technology

[0002] Semiconductor memory devices include memory cells capable of storing data. Three-dimensional semiconductor memory devices include memory cells arranged in three dimensions, thereby reducing the area occupied by the memory cells per unit area of ​​the substrate.

[0003] In three-dimensional semiconductor memory devices, the degree of freedom in arranging the lines used to control the operation of memory cells may be limited for various reasons. Summary of the Invention

[0004] In embodiments of this disclosure, a semiconductor memory device includes: a substrate extending in a first direction and a second direction intersecting the first direction; a plurality of input / output pads disposed on one side of the substrate; a first circuit adjacent to the input / output pads in the first direction; a second circuit configured to be spaced further apart from the input / output pads in the first direction than the first circuit in the first direction; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; a plurality of first metal source patterns overlapping the first memory cell array, wherein the plurality of first metal source patterns are spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array, wherein, in the second direction, the width of the second metal source pattern is wider than the width of each of the first metal source patterns.

[0005] In embodiments of this disclosure, a semiconductor memory device includes: a bit line; a common source line overlapping the bit line; a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked between the bit line and the common source line; a channel structure penetrating the gate stack structure, wherein the channel structure extends to directly contact the common source line; and a memory pattern disposed between the channel structure and the gate stack structure, wherein the common source line includes a conductive material with a resistivity lower than that of silicon and in direct contact with the channel structure.

[0006] In embodiments of this disclosure, a method of manufacturing a semiconductor memory device includes the following steps: forming a memory cell array on a sacrificial substrate, wherein the memory cell array includes a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked on the sacrificial substrate, a channel structure penetrating the interlayer insulating layers and conductive patterns, and a memory layer extending along the surface of the channel structure; removing the sacrificial substrate to expose the memory layer; removing a portion of the memory layer to expose a first end of the channel structure; and forming a common source line at a temperature of 450°C or lower, wherein the common source line is in direct contact with the first end of the channel structure and extends to overlap with the memory cell array. Attached Figure Description

[0007] Example embodiments will now be described more fully with reference to the accompanying drawings; however, they may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure possible for those skilled in the art.

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Throughout the drawings, similar reference numerals denote similar elements.

[0009] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 A substrate is shown that is overlapped by a first memory cell array and a second memory cell array according to an embodiment of the present disclosure.

[0011] Figure 3 This is a circuit diagram illustrating a unit string according to an embodiment of the present disclosure.

[0012] Figure 4 This is a perspective view showing a memory cell array according to an embodiment of the present disclosure.

[0013] Figure 5 The layout of the upper layer according to an embodiment of this disclosure is shown.

[0014] Figure 6A It is along Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device taken along line A-A'. Figure 6B It is along Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device taken by line B-B'.

[0015] Figure 7 An enlarged cross-section of the channel layer and memory pattern according to an embodiment of the present disclosure is shown.

[0016] Figure 8A and Figure 8B The arrangement of the circuit group according to an embodiment of the present disclosure is shown.

[0017] Figure 9 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figures 10A to 10D It is shown Figure 9 A cross-sectional view of an embodiment of step ST1 shown.

[0019] Figure 11A and Figure 11B It is shown Figure 9 Cross-sectional view of the implementation of steps ST11 and ST13 shown.

[0020] Figure 12A and Figure 12B It is shown Figure 9 A cross-sectional view of an embodiment of step ST15 shown.

[0021] Figure 13 It is shown Figure 9 Cross-sectional view of the implementation of steps ST17 and ST19 shown.

[0022] Figure 14 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0023] Figure 15 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0024] The specific structural or functional descriptions disclosed herein are merely illustrative in order to describe implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be carried out in various forms and should not be construed as limited to the specific implementations set forth herein.

[0025] Hereinafter, the terms "first" and "second" are used to distinguish one component from another, rather than to indicate a specific number in the sequence of components. These terms can be used to describe various components, but components are not limited to these terms.

[0026] The embodiments provide a semiconductor memory device and a method for manufacturing a semiconductor memory device, which can improve the degree of freedom in the arrangement of lines.

[0027] Figure 1 This is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The semiconductor memory device 10 may be formed as a multi-planar structure, comprising two or more planes, each whose operation can be controlled simultaneously. In an embodiment, the semiconductor memory device 10 may include: a first memory cell array 50A, included in a first plane; a second memory cell array 50B, included in a second plane; and a circuit group 15 configured to control various operations of the first memory cell array 50A and the second memory cell array 50B. For ease of description, Figure 1 An example of a two-planar structure has been given, but this disclosure is not limited thereto. Other embodiments may include more than two planes.

[0029] Each of the first memory cell array 50A and the second memory cell array 50B may include multiple memory blocks. A memory block may include multiple cell strings. Each cell string may include multiple memory cells connected in series. Each memory cell may store one bit of data or two or more bits of data. The memory cell may be a non-volatile memory cell. In this embodiment, the memory cell may be a NAND flash memory cell.

[0030] The first memory cell array 50A can be accessed via multiple first local lines RL[A], a first common source line CSL[A], and multiple first bit lines BL[A]. The second memory cell array 50B can be accessed via multiple second local lines RL[B], a second common source line CSL[B], and multiple second bit lines BL[B].

[0031] The circuit group 15 may include a first row decoder 30A, a first page buffer 40A, a second row decoder 30B, a second page buffer 40B, and peripheral circuitry 20.

[0032] The first memory cell array 50A can be connected to the first row decoder 30A via multiple first local lines RL[A], connected to the first page buffer 40A via multiple first bit lines BL[A], and connected to the peripheral circuit 20 via the first common source line CSL[A]. The second memory cell array 50B can be connected to the second row decoder 30B via multiple second local lines RL[B], connected to the second page buffer 40B via multiple second bit lines BL[B], and connected to the peripheral circuit 20 via the second common source line CSL[B].

[0033] The peripheral circuit 20 can receive command signals CMD, address signals ADDR and control signals CTRL from external devices outside the semiconductor memory device 10, and communicate data DATA with external devices.

[0034] In response to the command signal CMD, the address signal ADDR, and the control signal CTRL, the peripheral circuit 20 can output various signals for performing programming, reading, and erasing operations on the first memory cell array 50A and the second memory cell array 50B.

[0035] Peripheral circuitry 20 may include control logic that outputs a row address RADD, a page buffer control signal PB_S, and a column address in response to an address signal ADDR and a command signal CMD. Peripheral circuitry 20 may include an operating voltage generation circuit that outputs an operating voltage Vop in response to the address signal ADDR and the command signal CMD. Peripheral circuitry 20 may include a column decoder that exchanges a data signal RW_D with a first page buffer 40A and a second page buffer 40B in response to the column address. Peripheral circuitry 20 may include an input / output circuit that exchanges data DATA with the column decoder. Peripheral circuitry 20 may include a source discharge circuit that controls the discharge of a first common source line CSL[A] and a second common source line CSL[B].

[0036] Each of the first row decoder 30A and the second row decoder 30B can transmit various operating voltages Vop generated by the peripheral circuit 20 to the first memory cell array 50A and the second memory cell array 50B in response to the row address RADD received from the peripheral circuit 20.

[0037] The first page buffer 40A and the second page buffer 40B can detect data stored in the first memory cell array 50A and the second memory cell array 50B in response to the page buffer control signal PB_S output from the peripheral circuit 20, and send the detected data as a data signal RW_D to the peripheral circuit 20. Based on the data signal RW_D received from the peripheral circuit 20, the first page buffer 40A and the second page buffer 40B can write data to the first memory cell array 50A and the second memory cell array 50B.

[0038] The first common source line CSL[A] and the second common source line CSL[B] can be discharged under the control of the peripheral circuit 20, or an active voltage can be applied to them.

[0039] As described above, the peripheral circuit 20 may include multiple sub-circuits such as control circuits, operating voltage generating circuits, column decoders, input / output circuits, source discharge circuits, and internal voltage generating circuits to control various operations of the first memory cell array 50A and the second memory cell array 50B. The arrangement of the sub-circuits can be varied.

[0040] In order to make efficient use of the limited area, the first memory cell array 50A and the second memory cell array 50B may overlap with the substrate including the circuit group 15.

[0041] Figure 2 The substrate SUB, which is overlapped by a first memory cell array 50A and a second memory cell array 50B according to an embodiment of the present disclosure, is shown. Figure 2 The first memory cell array 50A and the second memory cell array 50B shown can respectively correspond to reference. Figure 1 The first memory cell array and the second memory cell array are described.

[0042] Reference Figure 2 The substrate SUB can extend in a first direction I and a second direction II. The first direction I and the second direction II can be intersecting, meaning they are not parallel. In an embodiment, the first direction I and the second direction II can correspond to the directions facing the X-axis and Y-axis in the XYZ Cartesian coordinate system, respectively. Hereinafter, the direction intersecting the plane extending in the first direction I and the second direction II is defined as the third direction III. The third direction III can correspond to the direction facing the Z-axis in the XYZ Cartesian coordinate system.

[0043] The substrate SUB may include a reference Figure 1 The circuit group 15 described includes n-type and p-type impurities. The substrate SUB may include pad region 60, first circuit region PA1, and second circuit region PA2.

[0044] The pad area 60 can be defined on one side of the substrate SUB and is configured as an area for multiple input / output pads.

[0045] A first circuit region PA1 may be adjacent to a pad region 60 in a first direction I. The first circuit region PA1 may include a first row decoder region DA[A], a first peripheral circuit region PCA1, and a first page buffer region PBA[A]. The first peripheral circuit region PCA1 and the first page buffer region PBA[A] may be adjacent to each other in the first direction I. The first peripheral circuit region PCA1 may be located between the pad region 60 and the first page buffer region PBA[A]. Each of the first peripheral circuit region PCA1 and the first page buffer region PBA[A] may be adjacent to the first row decoder region DA[A] in a second direction II. The first row decoder region DA[A] may extend in the first direction I to face the first peripheral circuit region PCA1 and the first page buffer region PBA[A].

[0046] Compared to the first circuit region PA1, the second circuit region PA2 can be spaced further away from the pad region 60 in the first direction I. In other words, the first circuit region PA1 can be located between the pad region 60 and the second circuit region PA2. The second circuit region PA2 may include a second row decoder region DA[B], a second peripheral circuit region PCA2, and a second page buffer region PBA[B]. The second peripheral circuit region PCA2 and the second page buffer region PBA[B] can be adjacent to each other in the first direction I. The second peripheral circuit region PCA2 can be located between the first page buffer region PBA[A] and the second page buffer region PBA[B]. The second row decoder region DA[B] can be adjacent to the first row decoder region DA[A] in the first direction I. The second row decoder region DA[B] can extend in the first direction I to face the second peripheral circuit region PCA2 and the second page buffer region PBA[B].

[0047] The first memory cell array 50A may overlap with the first circuit region PA1, and the second memory cell array 50B may overlap with the second circuit region PA2. A portion of each of the first circuit region PA1 and the second circuit region PA2 may be open, without overlapping by the first memory cell array 50A and the second memory cell array 50B. In this embodiment, the side of the first circuit region PA1 adjacent to the pad region 60, the other side of the first circuit region PA1 adjacent to the second circuit region PA2, and the side of the second circuit region PA2 adjacent to the first circuit region PA1 may not overlap by the first memory cell array 50A and the second memory cell array 50B.

[0048] The first line decoder region DA[A] can be set to have a reference. Figure 1 The first row describes the decoder region 30A, and the second row decoder region DA[B] can be set to have a reference. Figure 1 The second line describes the decoder 30B region. The first page buffer region PBA[A] can be set to have a reference. Figure 1 The first page buffer 40A is described, and the second page buffer area PBA[B] can be set to have a reference. Figure 1 The area described is the second page buffer 40B.

[0049] The first peripheral circuit region PCA1 and the second peripheral circuit region PCA2 can be configured to have Figure 1 The area of ​​the peripheral circuit 20 shown. The peripheral circuit 20 may include, in addition to Figure 1The sub-circuits shown are the first page buffer 40A and the second page buffer 40B, as well as the first row decoder 30A and the second row decoder 30B. These sub-circuits can be distributed and arranged in the first peripheral circuit region PCA1 and the second peripheral circuit region PCA2.

[0050] Some sub-circuits requiring high-speed operation and minimizing voltage drop can be located in the first peripheral circuit region PCA1. In an embodiment, control circuitry, operating voltage generation circuitry, and internal voltage generation circuitry can be located in the first peripheral circuit region PCA1. (In response to reference...) Figure 1 The command signal CMD and address signal ADDR described herein are output by the control circuit for controlling the reference. Figure 1 The description includes various signals for the first row decoder 30A, the second row decoder 30B, the first page buffer 40A, the second page buffer 40B, etc. The operating voltage generation circuit may include a pump circuit and a regulator, and can generate a high voltage to program or erase the memory cells of the first memory cell array 50A and the second memory cell array 50B. The internal voltage generation circuit can generate a reference voltage, an internal power supply voltage, and an internal ground voltage for the operation of the semiconductor memory device.

[0051] Other sub-circuits not located in the first peripheral circuit region PCA1 but retained therein can be located in the second peripheral circuit region PCA2. In this embodiment, the source discharge circuit and the input / output circuit can be located in the second peripheral circuit region PCA2. The source discharge circuit can be... Figure 1 The first common source line CSL[A] shown accesses the first memory cell array 50A and can be accessed through... Figure 1 The second common source line CSL[B] shown accesses the second memory cell array 50B. The source discharge circuitry may include individually controlled... Figure 1 The transistors shown have a first common source line CSL[A] and a second common source line CSL[B]. The input / output circuitry allows data communication with external devices.

[0052] The structure of the sub-circuit distribution and arrangement is not limited to the above implementation method, and can be designed differently by taking into account the electrical characteristics of the sub-circuit and the arrangement of the lines connected to the sub-circuit.

[0053] Figure 3 This is a circuit diagram illustrating a cell string CS according to an embodiment of the present disclosure. Figure 1 and Figure 2 Each of the first memory cell array 50A and the second memory cell array 50B shown may include Figure 3 The unit string CS is shown.

[0054] Reference Figure 3The cell string CS can be connected between the common source line CSL and the bit line BL.

[0055] The cell string CS can be controlled via local lines SSLa, SSLb, WL1 to WLn, DSLa, and DSLb. Local lines SSLa, SSLb, WL1 to WLn, DSLa, and DSLb may include one or more source select lines SSLa and SSLb, multiple word lines WL1 to WLn, and one or more drain select lines DSLa and DSLb. The cell string CS may include multiple memory cells MC1 to MCn, one or more source select transistors SSTa and SSTb, and one or more drain select transistors DSTa and DSTb.

[0056] Multiple memory cells MC1 to MCn can be connected in series. The gates of the multiple memory cells MC1 to MCn can be spaced apart from each other to be connected to stacked word lines WL1 to WLn respectively.

[0057] One or more source-select transistors SSTa and SSTb can control the electrical connection between multiple memory cells MC1 to MCn and the common source line CSL. In one embodiment, the cell string CS may include one source-select transistor SSTa disposed between the common source line CSL and the multiple memory cells MC1 to MCn. However, this disclosure is not limited thereto. In another embodiment, the cell string CS may include two or more source-select transistors SSTa and SSTb disposed between the common source line CSL and the multiple memory cells MC1 to MCn and connected in series with each other. The gates of the source-select transistors SSTa and SSTb may be connected to source-select lines SSLa and SSLb, respectively.

[0058] One or more drain-select transistors DSTA and DSTb can control the electrical connection between multiple memory cells MC1 to MCn and the bit line BL. In one embodiment, the cell string CS may include one drain-select transistor DSTA disposed between the bit line BL and the multiple memory cells MC1 to MCn. However, this disclosure is not limited thereto. In another embodiment, the cell string CS may include two or more drain-select transistors DSTA and DSTb disposed between the bit line BL and the multiple memory cells MC1 to MCn and connected in series with each other. The gates of the drain-select transistors DSTA and DSTb may be connected to drain-select lines DSLa and DSLb, respectively.

[0059] Figure 4 This is a perspective view showing a memory cell array 50 according to an embodiment of the present disclosure. Figure 4 The memory cell array 50 shown can be applied to Figure 1 and Figure 2Each of the first memory cell array 50A and the second memory cell array 50B shown.

[0060] Reference Figure 4 The memory cell array 50 may include a gate stack structure GST disposed between multiple bit lines BL and a common source line CSL. The common source line CSL may extend in a first direction I and a second direction II to overlap with the multiple bit lines BL. The multiple bit lines BL may be connected to a reference... Figure 1 The described circuit group 15 and reference Figure 2 The semiconductor chips 25 of the substrate SUB are stacked. The substrate SUB can be stacked with a gate stack structure GST, and multiple bit lines BL are inserted between the substrate SUB and the gate stack structure GST. Each bit line BL can extend in a first direction I.

[0061] Each gate stack structure (GST) can be connected to multiple cell strings constituting a memory block. Each gate stack structure (GST) may include local lines SSLa, SSLb, WL1 to WLn, DSLa1, DSLa2, DSLb1, and DSLb2 extending in the second direction II. The local lines SSLa, SSLb, WL1 to WLn, DSLa1, DSLa2, DSLb1, and DSLb2 may include one or more source select lines SSLa and SSLb, multiple word lines WL1 to WLn, and one or more drain select lines DSLa1, DSLa2, DSLb1, and DSLb2.

[0062] Multiple word lines WL1 to WLn may be stacked on the third direction III and spaced apart from each other. Source select lines SSLa and SSLb may be disposed between the common source line CSL and the multiple word lines WL1 to WLn, and stacked on the third direction III and spaced apart from each other. Drain select lines DSLa1, DSLa2, DSLb1, and DSLb2 may be disposed between multiple bit lines BL and multiple word lines WL1 to WLn. Drain select lines DSLa1, DSLa2, DSLb1, and DSLb2 may be isolated into two or more groups by a first slit S1. In an embodiment, drain select lines DSLa1, DSLa2, DSLb1, and DSLb2 may include a first group of drain select lines DSLa1 and DSLb1 and a second group of drain select lines DSLa2 and DSLb2. The first group of drain select lines DSLa1 and DSLb1 may be isolated from the second group of drain select lines DSLa2 and DSLb2 by the first slit S1. The drain selection lines DSLa1 and DSLb1 of the first group can be stacked on the third-to-III axis to be spaced apart from each other. The drain selection lines DSLa2 and DSLb2 of the second group can also be stacked on the third-to-III axis to be spaced apart from each other.

[0063] The gate stack structure GST can be isolated from each other through the second slit S2. The gate stack structure GST can be overlapped by the upper line layer UL, and the common source line CSL is inserted between the gate stack structure and the upper line layer UL. The upper line layer UL may include multiple components spaced apart from each other on a plane parallel to the common source line CSL. Figure 4 The schematic location of the upper line layer UL overlapping with the common source line CSL is shown, and the layout of the components arranged in the upper line layer UL can vary.

[0064] In an implementation, the upper UL layer may include Figure 5 The figure shows a first metal source pattern 71A, a second metal source pattern 71B, and a transmission line 71C. Although not shown in the figure, in another embodiment, the first and second metal source patterns may be omitted in the upper line layer UL, and the upper line layer UL may include a transmission line overlapping with the gate stack structure GST.

[0065] Figure 5 The layout of the upper layer according to an embodiment of this disclosure is shown.

[0066] Reference Figure 5 The upper layer may include a first metal source pattern 71A, a second metal source pattern 71B, and a transmission line 71C. Each of the first metal source pattern 71A and the second metal source pattern 71B may be formed in a mesh shape.

[0067] The first metal source pattern 71A and transmission line 71C may overlap with the first memory cell array 50A. The first memory cell array 50A may be associated with, as shown in reference... Figure 2 The pad regions 60 with multiple input / output pads 61 are arranged adjacently. The first memory cell array 50A may overlap with the first circuit 15A. The first circuit 15A may be adjacent to the input / output pads 61 in the first direction I. The first metal source pattern 71A may be connected to the same circuit. Figure 6A The first common source line CSL[A] shown overlaps with the first memory cell array 50A.

[0068] The second metal source pattern 71B may overlap with the second memory cell array 50B. The second memory cell array 50B may overlap with the second circuit 15B. Compared with the first circuit 15A, the second circuit 15B may be spaced further away from the input / output pads 61 in the first direction I. The second metal source pattern 71B may be connected to the second common source line overlapping with the second memory cell array 50B. The arrangement of the second memory cell array 50B and the second common source line refers to... Figure 4 The arrangement of the common source line (CSL) and the gate stack structure (GST) is shown.

[0069] The first metal source pattern 71A, the transmission line 71C, and the second metal source pattern 71B can be parallel to... Figure 4 The substrates SUB shown are spaced apart on their planes. First metal source patterns 71A may be configured to be spaced apart in a second direction II. Second metal source patterns 71B may extend in the second direction II to face the first metal source patterns 71A. In an embodiment, the width WB of the second metal source pattern 71B in the second direction II may be formed to be wider than the width WA of each of the first metal source patterns 71A.

[0070] The first circuit 15A may include Figure 1 The circuit group 15 shown includes a first line decoder 30A and a first page buffer 40A, and may include... Figure 1 Some sub-circuits of the peripheral circuit 20 of the circuit group shown. The second circuit 15B may include... Figure 1 The circuit group 15 shown includes a second line decoder 30B and a second page buffer 40B, and may include... Figure 1 Some other sub-circuits of the peripheral circuit 20 of the circuit group shown. In an embodiment, the first circuit 15A may include some other sub-circuits provided in the reference circuit. Figure 2 The first peripheral circuit region PAC1 is described, comprising a control circuit, an operating voltage generating circuit, and an internal voltage generating circuit. The second circuit 15B may include circuits located in reference... Figure 2 The source discharge circuit and input / output circuit in the second peripheral circuit region PCA2 are described.

[0071] Each transmission line 71C can transmit the internal power supply voltage or internal ground voltage output from the internal voltage generating circuit of the first circuit 15A. The internal power supply voltage or internal ground voltage from the transmission line 71C can be transmitted via a path provided between the first memory cell array 50A and the second memory cell array 50B. Figure 6B The first contact plug CT1 shown is supplied to a sub-circuit of the first circuit 15A and another sub-circuit of the second circuit 15B. For this purpose, each transmission line 71C may include an end 71C[EG] adjacent to the input / output pad 61 and extend from the end 71C[EG] in a first direction I.

[0072] Although not shown in the figures, the metal source pattern (not shown) overlapping with the first memory cell array 50A can be formed to have a width WB as wide as the second metal source pattern 71B. Unlike what is shown in the figures, the layout of the transmission lines 71C can be designed not to overlap with the first memory cell array 50A. On the other hand, according to the embodiments of this disclosure, the first metal source patterns 71A are arranged to be spaced apart from each other in the second direction II. Therefore, some transmission lines 71C can be arranged not only between the first metal source patterns 71A but also overlapping with the first memory cell array 50A. Therefore, in the embodiments of this disclosure, the degree of freedom in arranging the transmission lines 71C is improved. Furthermore, in the embodiments of this disclosure, the layout of the transmission lines 71C can be simplified, thus reducing the difficulty level of the upper layer formation process.

[0073] Figure 6A It is along Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device taken along line A-A'. Figure 6B It is along Figure 5 The diagram shows a cross-sectional view of a semiconductor memory device taken by line B-B'.

[0074] Reference Figure 6A and Figure 6B The first memory cell array 50A may include a gate stack structure GST, a channel structure CH, and a memory pattern ML. The channel structure CH may penetrate each gate stack structure GST. The memory pattern ML may be disposed between each gate stack structure GST and the channel structure CH. Figure 5 The second memory cell array 50B shown can be configured to have a structure similar to that of the first memory cell array 50A.

[0075] Each gate stack structure (GST) may include an interlayer insulating layer (ILD) [C] and a conductive pattern (CP) alternately stacked between the bit line (BL) and the first common source line (CSL[A]). The conductive pattern (CP) can be used as... Figure 4 The local lines shown are SSL1, SSL2, WL1 to WLn, DSLa1 and DSLb1.

[0076] The channel structure CH can be in direct contact with the first common source line CSL[A]. In an embodiment, the channel structure CH may include an end EG. The end EG of the channel structure CH may protrude further than the memory pattern ML toward the first common source line CSL[A] and may extend into the interior of the first common source line CSL[A]. The channel structure CH may include a core insulating layer CO, a channel layer CL, and a doped semiconductor pattern DP.

[0077] The core insulating layer CO can extend to penetrate the interlayer insulating layer ILD[C] and the conductive pattern CP. The core insulating layer CO can overlap with the doped semiconductor pattern DP.

[0078] The channel layer CL may surround the sidewalls of the core insulating layer CO. The channel layer CL may extend between the core insulating layer CO and the first common source line CSL[A] to close the end of the core insulating layer CO facing the first common source line CSL[A]. The channel layer CL may extend to surround the sidewalls of the doped semiconductor pattern DP.

[0079] The channel layer CL may include a semiconductor layer. In one embodiment, the channel layer CL may include silicon. A portion of the end EG of the channel structure CH and a portion of the channel layer CL surrounding the doped semiconductor pattern DP may be defined as a doped region including impurities. In one embodiment, the doped region may include n-type impurities.

[0080] The doped semiconductor pattern DP may include the same impurities as the doped regions of the channel layer CL. In one embodiment, the doped semiconductor pattern DP may include n-type doped silicon.

[0081] Bit line BL can be disposed between the first memory cell array 50A and the semiconductor chip 25. Bit line BL can be connected to the channel structure CH of the first memory cell array 50A via bit line contact plugs BCT that penetrate the insulating layers 63 and 67 disposed between the gate stack structure GST and the bit line BL.

[0082] The bit-line level pad 81 can be disposed at a level substantially equal to that of the bit line BL. The bit-line level pad 81 can be formed of the same conductive material as the bit line BL. The bit-line level pad 81 can be disposed between the semiconductor chip 25 and the transmission line 71C. The bit-line level pad 81 can be spaced apart from the bit line BL by an insulating layer 69.

[0083] Semiconductor chip 25 can be connected to a first interconnect structure IC1 disposed between semiconductor chip 25 and bit line BL. Some first interconnect structures IC1 disposed between pad 81 at the bit line level and substrate SUB can be connected to pad 81 at the bit line level.

[0084] The first interconnect structure IC1 can be electrically connected to the semiconductor chip 25 via the first bonding metal 83. The first bonding metal 83 and the first interconnect structure IC1 can be buried in the first insulating structure 91.

[0085] Semiconductor chip 25 may include a substrate SUB, the substrate SUB including Figure 1 The circuit group 15, the second interconnect structure IC2 connected to the circuit group 15, and the second bonding metal connected to the second interconnect structure IC2 are shown. The circuit group 15, the second interconnect structure IC2, and the bonding metal 85 can be buried in the second insulating structure 93 of the cover substrate SUB.

[0086] Figure 5The sub-circuit of the first circuit 15A shown can be set in Figure 6A The semiconductor chip 25 shown is partially overlapped by the first memory cell array 50A. Figure 5 The sub-circuit of the second circuit 15B shown or Figure 5 Another sub-circuit of the first circuit 15A shown can be set in Figure 6B This is shown in a portion of the semiconductor chip 25. Although... Figure 6A and Figure 6B Showing includes Figure 1 The circuit group 15 shown includes the transistor TR, but in addition to the transistor TR, the circuit group 15 may also include various circuit elements such as resistors and capacitors.

[0087] Each transistor TR may include a gate insulating layer GI, a gate electrode GT, and a junction region JN. The gate insulating layer GI and the gate electrode GT may be stacked on the active region of the substrate SUB. The active region of the substrate SUB may be divided by an isolation layer ISO. The junction region JN may be defined by implanting impurities into the active region on both sides of the gate electrode GT. The junction region JN may include p-type impurities or n-type impurities.

[0088] The second interconnect structure IC2 can be disposed between the substrate SUB and the first interconnect structure IC1. The second interconnect structure IC2 can be connected to the first interconnect structure IC1 via the first bonding metal 83 and the second bonding metal 85.

[0089] The first common source line CSL[A] may overlap with the bit line BL, and the first memory cell array 50A is inserted between the first common source line CSL[A] and the bit line BL. The first common source line CSL[A] may be located between the first memory cell array 50A and the bit line BL. Figure 5 The first metal source pattern 71A shown is between the upper lines and can be between the upper layers. Figure 5 It extends in the first direction I and the second direction II as shown. Figure 5 The multiple first metal source patterns 71A shown can be connected together to the first common source line CSL[A] via source contact plugs SCT. The source contact plugs SCT can extend from the first common source line CSL[A] toward the first metal source pattern 71A.

[0090] Similar to the arrangement of the first memory cell array 50A, the first common source line CSL[A], and the first metal source pattern 71A, the second common source line can be set in... Figure 5 The connection between the second memory cell array 50B and the second metal source pattern 71B is similar to the connection structure between the first common source line CSL[A] and the first metal source pattern 71A. Figure 5The second common source line and the second metal source pattern 71B shown can be connected to... Figure 6A The source contact plug SCT shown is an electrically insulated individual source contact plug connection. The first common source line CSL[A] may be located at a level substantially equal to that of the second common source line and is formed of the same conductive material as the second common source line.

[0091] The first common source line CSL[A] may include a conductive material having a resistivity lower than that of silicon. In one embodiment, the first common source line CSL[A] may include a silicide layer. Additionally, the first common source line CSL[A] may include a conductive material capable of forming an ohmic contact with the channel layer CL. In one embodiment, the first common source line CSL[A] may include tungsten silicide or nickel silicide in direct contact with the channel layer CL of the channel structure CH. The conductive material of the first common source line CSL[A] providing the ohmic contact is in direct contact with the channel layer CL, thereby simplifying the connection structure between the channel layer CL and the first common source line CSL[A]. Tungsten silicide or nickel silicide may be formed at a temperature lower than the temperature at which electromigration (EM) occurs in the first bonding metal 83 and the second bonding metal 85. Therefore, in this disclosure, the structural stability and operational reliability of the semiconductor memory device can be improved. In one embodiment, the first bonding metal 83 and the second bonding metal 85 may include copper.

[0092] A common source line level pad 65 may be positioned at a level substantially equal to that of the first common source line CSL[A]. The common source line level pad 65 may be positioned between the transmission line 71C and the bit line level pad 81. The common source line level pad 65 may be formed of the same conductive material as the first common source line CSL[A].

[0093] The pad 65 at the common source line level can be connected to the pad 81 at the bit line level via the first contact plug CT1, and to the transmission line 71C via the second contact plug CT2.

[0094] The first contact plug CT1 may extend from the bit-line level pad 81 toward the common source line level pad. The first contact plug CT1 may be surrounded by a dummy stack structure ST[D] and insulating layers 63 and 67. In other words, the first contact plug CT1 may penetrate the dummy stack structure ST[D] and insulating layers 63 and 67. The dummy stack structure ST[D] may be located at a level substantially equal to the level of the gate stack structure GST. The dummy stack structure ST[D] may include a first dummy interlayer insulating layer ILD[D1] and a second dummy interlayer insulating layer ILD[D2]. The first dummy interlayer insulating layer ILD[D1] and the second dummy interlayer insulating layer ILD[D2] may be alternately stacked between the bit-line level pad 81 and the common source line level pad 65. The second dummy interlayer insulating layer ILD[D2] may include an insulating material different from that of the first dummy interlayer insulating layer ILD[D1], and the first dummy interlayer insulating layer ILD[D1] may include the same insulating material as the unit interlayer insulating layer ILD[C]. Insulating layers 63 and 67 may extend between the dummy stack structure ST[D] and the pad 81 at the bit line level.

[0095] The second contact plug CT2 can be positioned at a level substantially equal to that of the source contact plug SCT. The second contact plug CT2 can extend from the pad 65 at the level of the common source line toward the transmission line 71C.

[0096] The first metal source pattern 71A may include a material with a lower resistivity than the conductive material of the first common source line CSL[A], to compensate for the voltage drop caused by the resistance of the first common source line CSL[A]. Figure 5 The first metal source pattern 71A, transmission line 71C, and second metal source pattern 71B shown may comprise the same conductive material. In this embodiment, Figure 5 The first metal source pattern 71A, transmission line 71C, and second metal source pattern 71B shown may include aluminum. Figure 5 Each of the first metal source pattern 71A, the transmission line 71C, and the second metal source pattern 71B shown may further include barrier metal. In an embodiment, barrier metal may be disposed along the interface between the first metal source pattern 71A and the source contact plug SCT, and along the interface between the transmission line 71C and the second contact plug CT2, respectively.

[0097] Figure 7 An enlarged cross-section of the channel layer CL and memory pattern ML according to an embodiment of the present disclosure is shown.

[0098] Reference Figure 7 The channel layer CL can surround the sidewalls of the core insulation layer CO. The cross-section of the core insulation layer CO can have various shapes such as circular, elliptical, or polygonal.

[0099] The memory pattern ML may include a tunnel insulation layer TI, a data storage layer DS, and a barrier insulation layer BI.

[0100] The tunnel insulation layer TI may extend along the surface of the trench layer CL. The tunnel insulation layer TI may include a charge-tunable insulating material. In one embodiment, the tunnel insulation layer TI may include a silicon oxide layer.

[0101] The data storage layer DS may extend along the surface of the tunnel insulation layer TI. The data storage layer DS may include a material layer capable of storing data. In one embodiment, the data storage layer DS may include a nitride layer capable of storing data altered by the Fowler-Nordheim (FN) tunneling.

[0102] The barrier insulating layer BI may extend along the surface of the data storage layer. The barrier insulating layer BI may include an oxide layer.

[0103] Figure 8A and Figure 8B The arrangement of the circuit group according to an embodiment of the present disclosure is shown.

[0104] Reference Figure 8A and Figure 8B The circuit group can be configured to control four planes simultaneously and independently. For this purpose, the circuit group may include a first row decoder 30A' and a first page buffer 40A' connected to a first memory cell array, a second row decoder 30B' and a second page buffer 40B' connected to a second memory cell array, a third row decoder 30C' and a third page buffer 40C' connected to a third memory cell array, a fourth row decoder 30D' and a fourth page buffer 40D' connected to a fourth memory cell array, and first to fourth peripheral circuit groups 20_1, 20_2, 20_3, and 20_4. Although not shown in the figures, the first to fourth memory cell arrays may be configured to overlap with the circuit group.

[0105] Various operations of the first to fourth memory cell arrays can be controlled by the first row decoder 30A', the second row decoder 30B', the third row decoder 30C', and the fourth row decoder 30D'; the first page buffer 40A', the second page buffer 40B', the third page buffer 40C', and the fourth page buffer 40D'; and peripheral circuitry. The peripheral circuitry may include sub-circuits distributed and configured in the first to fourth peripheral circuit groups 20_1, 20_2, 20_3, and 20_4.

[0106] The first peripheral circuit group 20_1 and the third peripheral circuit group 20_3 may be arranged adjacent to the pad area 60', which includes multiple input / output pads 61'. Compared to the first peripheral circuit group 20_1 and the third peripheral circuit group 20_3, the second peripheral circuit group 20_2 and the fourth peripheral circuit group 20_4 may be arranged to be spaced further away from the pad area 60'. The first peripheral circuit group 20_1 may be located between the pad area 60' and the second peripheral circuit group 20_2, and the third peripheral circuit group 20_3 may be located between the pad area 60' and the fourth peripheral circuit group 20_4.

[0107] The first peripheral circuit group 20_1 and the third peripheral circuit group 20_3 may include sub-circuits that require high-speed operation and require minimal voltage drop. In an embodiment, the control circuit, the operating voltage generating circuit, and the internal voltage generating circuit may be distributed and arranged in the first peripheral circuit group 20_1 and the third peripheral circuit group 20_3.

[0108] The second peripheral circuit group 20_2 and the fourth peripheral circuit group 20_4 may include other sub-circuits not provided in the first peripheral circuit group 20_1 and the third peripheral circuit group 20_3. In an embodiment, the source discharge circuit and the input / output circuit may be distributed and provided in the second peripheral circuit group 20_2 and the fourth peripheral circuit group 20_4.

[0109] The first page buffer 40A' can be located between the first peripheral circuit group 20_1 and the second peripheral circuit group 20_2, and the second peripheral circuit group 20_2 can be located between the first page buffer 40A' and the second page buffer 40B'. The third page buffer 40C' can be located between the third peripheral circuit group 20_3 and the fourth peripheral circuit group 20_4, and the fourth peripheral circuit group 20_4 can be located between the third page buffer 40C' and the fourth page buffer 40D'.

[0110] The first row decoder 30A' and the third row decoder 30C' can be positioned adjacent to the pad area 60'. Compared to the first row decoder 30A' and the third row decoder 30C', the second row decoder 30B' and the fourth row decoder 30D' can be positioned further apart from the pad area 60'. The first row decoder 30A' can be positioned between the pad area 60' and the second row decoder 30B', and the third row decoder 30C' can be positioned between the pad area 60' and the fourth row decoder 30D'.

[0111] Reference Figure 8AIn this embodiment, the first peripheral circuit group 20_1, the third peripheral circuit group 20_3, the first page buffer 40A', and the third page buffer 40C' can be disposed between the first row decoder 30A' and the third row decoder 30C'. Additionally, the second peripheral circuit group 20_2, the fourth peripheral circuit group 20_4, the second page buffer 40B', and the fourth page buffer 40D' can be disposed between the second row decoder 30B' and the fourth row decoder 30D'.

[0112] Reference Figure 8B In this embodiment, the first row decoder 30A' and the third row decoder 30C' may be disposed between the first peripheral circuit group 20_1 and the third peripheral circuit group 20_3. Additionally, the second row decoder 30B' and the fourth row decoder 30D' may be disposed between the second peripheral circuit group 20_2 and the fourth peripheral circuit group 20_4.

[0113] Reference Figure 8A and Figure 8B , refer to Figure 5 The described first metal source pattern 71A and transmission line 71C may overlap with a first circuit including a first peripheral circuit group 20_1 and a first page buffer 40A'. (Refer to...) Figure 5 The described second metal source pattern 71B may overlap with a second circuit including a second peripheral circuit group 20_2 and a second page buffer 40B'. Structure and Reference Figure 5 The third metal source pattern and separate transmission line, which are structurally similar to the first metal source pattern 71A and transmission line 71C described, may overlap with a third circuit including a third peripheral circuit group 20_3 and a third page buffer 40C'. (Structure and reference) Figure 5 The fourth metal source pattern, which is structurally similar to the second metal source pattern 71B described, may overlap with the fourth circuitry including the fourth peripheral circuitry group 20_4 and the fourth page buffer 40D'.

[0114] Figure 9 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0115] Reference Figure 9 A method for manufacturing a semiconductor memory device may include: step ST1, forming a first structure including a memory cell array on a sacrificial substrate; step ST3, forming a semiconductor chip including a circuit group; step ST11, bonding the first structure and the semiconductor chip; step ST13, removing the sacrificial substrate and exposing a channel structure; step ST15, forming a first pattern group; step ST17, forming an upper contact group; and step ST19, forming a second pattern group.

[0116] The process performed after step ST11 can be performed at a temperature lower than the temperature that causes electromigration (EM) in the bonded metal. In an embodiment, the process performed after step ST11 can be performed at a temperature of 450°C or lower.

[0117] The following will refer to Figures 10A to 10D , Figure 11A and Figure 11B , Figure 12A and Figure 12B as well as Figure 13 This describes a method for manufacturing a semiconductor memory device according to embodiments of the present disclosure, illustrating various process steps. Figure 5 The method for manufacturing a semiconductor memory device is shown.

[0118] Figures 10A to 10D It is shown Figure 9 A cross-sectional view of an embodiment of step ST1 shown.

[0119] Reference Figure 10A A memory cell array 110C and a dummy stacked structure 110D can be formed on the sacrificial substrate 101.

[0120] The memory cell array 110C may include an interlayer insulating layer 111C and a conductive pattern 135 alternately stacked on a sacrificial substrate 101, a channel structure 120 penetrating the interlayer insulating layer 111C and the conductive pattern 135, and a memory layer 121 extending along the surface of the channel structure 120.

[0121] For reference Figure 6A As described, the channel structure 120 may include a channel layer 123, a core insulating layer 125, and a doped semiconductor pattern 127. The channel structure 120 may include a first end EG1 extending into the sacrificial substrate 101. The channel structure 120 may include a second end EG2 facing a direction opposite to that of the first end EG1. The second end EG2 may include the doped semiconductor pattern 127 and a portion of the channel layer 123 surrounding the doped semiconductor pattern 127. The portion of the channel layer 123 surrounded by the doped semiconductor pattern 127 may include impurities diffused from the doped semiconductor pattern 127. In an embodiment, the doped semiconductor pattern 127 and the portion of the channel layer 123 adjacent to the doped semiconductor pattern 127 may include n-type impurities.

[0122] Memory layer 121 may include Figure 7 The tunnel insulating layer TI, data storage layer DS, and barrier insulating layer BI are shown. The memory layer 121 may surround the sidewall of the channel structure 120 and extend between the channel structure 120 and the sacrificial substrate 101.

[0123] The dummy layer structure 110D may include a first dummy interlayer insulating layer 111D and a sacrificial insulating layer 113 alternately stacked on a sacrificial substrate 101. The first dummy interlayer insulating layer 111D may be disposed at a level substantially equal to that of the unit interlayer insulating layer 111C. The first dummy interlayer insulating layer 111D may include the same insulating material as the unit interlayer insulating layer 111C. The sacrificial insulating layer 113 may include an insulating material having etch selectivity relative to the first dummy interlayer insulating layer 111D and the unit interlayer insulating layer 111C. In an embodiment, the first dummy interlayer insulating layer 111D and the unit interlayer insulating layer 111C may include silicon oxide layers, and the sacrificial insulating layer 113 may include a silicon nitride layer.

[0124] In an embodiment, the process of forming the memory cell array 110C and the dummy stack-up structure 110D may include forming a preliminary stack-up structure by alternately stacking an interlayer insulating layer and a sacrificial insulating layer 113 on a sacrificial substrate 101; a step of forming a channel hole that penetrates the preliminary stack-up structure and extends into the interior of the sacrificial substrate 101; forming a memory layer 121 on the surface of the channel hole; forming a channel structure 120 that fills the central region of the channel hole opened through the memory layer 121; forming a first insulating layer 131 on the preliminary stack-up structure that extends to cover the channel structure 120; forming a slit 133 that penetrates the first insulating layer 131 and the preliminary stack-up structure; and replacing the portion of the sacrificial insulating layer 113 surrounding the channel structure 120 through the slit 133 with a conductive pattern 135. Other portions of the sacrificial insulating layer 113 that are not replaced by the conductive pattern 135 may be retained as a second dummy insulating layer constituting the dummy stack-up structure 110D. The interlayer insulation layer can be divided into a unit interlayer insulation layer 111C that overlaps with the conductive pattern 135 and a first dummy interlayer insulation layer 111D that overlaps with the remaining sacrificial insulation layer 113.

[0125] Reference Figure 10B The second insulating layer 136 can be used to fill it. Figure 10A The slit 133 is shown. The second insulating layer 136 may extend to cover the first insulating layer 131.

[0126] Subsequently, a first contact plug 137 can be formed. The first contact plug 137 can penetrate the dummy stacked structure 110D, the first insulating layer 131, and the second insulating layer 136. The first contact plug 137 can contact the sacrificial substrate 101. The first contact plug 137 can be formed of various conductive materials.

[0127] Reference Figure 10CA bit line contact plug 141 can be formed. The bit line contact plug 141 can penetrate the first insulating layer 131 and the second insulating layer 136. The bit line contact plug 141 can overlap with the channel structure 120 of the memory cell array 110C. The bit line contact plug 141 can be formed of various conductive materials.

[0128] Subsequently, a third insulating layer 143 may be formed on the second insulating layer 136. The third insulating layer 143 may extend to cover the bit line contact plug 141 and the first contact plug 137. Subsequently, bit line 145A and bit line horizontal pad 145B may be formed to penetrate the third insulating layer 143. Bit line 145A and bit line horizontal pad 145B may be formed of the same conductive material and formed using a single mask process.

[0129] Bit line 145A can be connected to bit line contact plug 141 and connected to the second end EG2 of channel structure 120 via bit line contact plug 141. Bit line horizontal pad 145B can be connected to first contact plug 137.

[0130] Reference Figure 10D A first insulating structure 151 covering bit line 145A and bit line-level pads 145B can be formed, along with a first interconnect structure 153 and a first bonding metal 155 buried within the first insulating structure 151. The first insulating structure 151 may include multiple layers of insulating layers. The first interconnect structure 153 may include conductors and conductive pads extending in various directions, and conductive vias connecting the conductors and conductive pads. Some of the first interconnect structures 153 may be connected to the bit line-level pads 145B. The first bonding metal 155 may be connected to the first interconnect structure 153.

[0131] Figure 11A and Figure 11B It is shown Figure 9 Cross-sectional view of the implementation of steps ST11 and ST13 shown.

[0132] Reference Figure 11A Before performing step ST11, it can be done through Figure 9 The step ST3 shown provides a semiconductor chip 160. The semiconductor chip 160 may include a substrate 161, which includes a circuit group, a second interconnect structure 165, and a second bonding metal 169.

[0133] The circuit assembly may include a plurality of transistors 163 insulated from each other by an isolation layer 162. A second interconnect structure 165 and a second bonding metal 169 may be buried within a second insulating structure 167 on a cover substrate 161. The second insulating structure 167 may include multiple layers of insulating layers. The second interconnect structure 165 may include conductors and conductive pads extending in various directions, and conductive vias connecting the conductors and conductive patterns. The second interconnect structure 165 may be connected to the transistors 163. The second bonding metal 169 may be connected to the second interconnect structure 165.

[0134] The first bonding metal 155 and the second bonding metal 169 may be bonded to each other via step ST11. The first bonding metal 155 and the second bonding metal 169 may comprise metals to which the first bonding metal 155 and the second bonding metal 169 may be joined together via an in-metal bonding process. In an embodiment, the first bonding metal 155 and the second bonding metal 169 may comprise copper.

[0135] Subsequently, it can be removed via step ST13. Figure 10D The sacrificial substrate 101 is shown. Therefore, the memory layer 121 and the first contact plug 137 are exposed.

[0136] Reference Figure 11B It can remove Figure 11A The exposed area of ​​the memory layer 121 shown exposes the first end EG of the channel structure 120. Hereinafter, the remaining area of ​​the memory layer may be designated as memory pattern 121P.

[0137] Before the exposed areas of the memory layer are removed, impurity regions 123A can be formed by injecting impurities into a portion of the channel layer 123 that is included in the first end EG1 of the channel structure 120. In an embodiment, impurity regions 123A may include n-type impurities.

[0138] Figure 12A and Figure 12B It is shown Figure 9 A cross-sectional view of an embodiment of step ST15 shown.

[0139] Reference Figure 12A Step ST15 can be performed at a temperature lower than the temperature at which electromigration (EM) occurs in the first bonding metal 155 and the second bonding metal 169. In an embodiment, step ST15 can be performed at a temperature of 450°C or lower. Through step ST15, a first conductive layer 171 can be formed. The first conductive layer 171 may include a conductive material with a resistivity lower than that of silicon. Additionally, the first conductive layer 171 may include a conductive material that directly contacts the first end EG1 of the channel structure 120 to provide an ohmic contact. In an embodiment, the first conductive layer 171 may include tungsten silicide or nickel silicide.

[0140] The first conductive layer 171 may be in direct contact with the first end EG1 of the channel structure 120. More specifically, the first conductive layer 171 may be in direct contact with the impurity region 123A of the channel layer 123 exposed at the first end EG1 of the channel structure 120.

[0141] The first conductive layer 171 may be connected to the first contact plug 137. In one embodiment, the first conductive layer 171 may be in contact with the barrier metal of the first contact plug 137.

[0142] Reference Figure 12B It can be achieved through etching Figure 12A The first conductive layer 171 shown defines a first pattern group including a common source line 171A and a pad 171B at the level of the common source line.

[0143] The common source line 171A may surround the first end EG1 of the channel structure 120 and be in direct contact with the channel layer 123. The common source line 171A may overlap with the memory cell array 110C.

[0144] The pad 171B at the level of the common source line can be connected to the first contact plug 137 and can overlap with the dummy stack structure 110D.

[0145] Figure 13 It is shown Figure 9 Cross-sectional view of the implementation of steps ST17 and ST19 shown.

[0146] Reference Figure 13 Step ST17 can be used to form an upper contact group including source contact plug 175A and second contact plug 175B. Source contact plug 175A and second contact plug 175B can penetrate a fourth insulating layer 173. The fourth insulating layer 173 can insulate between the common source line 171A and the common source line horizontal pad 171B, and extends to cover the common source line 171A and the common source line horizontal pad 171B.

[0147] Source contact plug 175A can be connected to common source line 171A. Second contact plug 175B can be connected to pad 171B at the same level as common source line.

[0148] Subsequently, a second pattern set including a metal source pattern 181A and a transmission line 181B can be formed via step ST19. The metal source pattern 181A and the transmission line 181B may include components with resistivity lower than... Figure 12AThe resistivity of the first conductive layer 171 shown is that of a conductive material. The metal source pattern 181A and transmission line 181B can be formed at a temperature lower than the temperature that causes electromigration (EM) phenomena in the first bonding metal 155 and the second bonding metal 169 (e.g., 450°C or lower). In an embodiment, the metal source pattern 181A and transmission line 181B may comprise aluminum.

[0149] The metal source pattern 181A and transmission line 181B may be spaced apart from each other on a plane parallel to the common source line 171A. The metal source pattern 181A and transmission line 181B may be formed to have a reference... Figure 5 The first metal source pattern 71A and the transmission line 71C described have the same layout.

[0150] The metal source pattern 181A can be formed in a mesh shape and is connected to the common source line 171A via the source contact plug 175A. The transmission line 181B can be connected to the second contact plug 175B.

[0151] According to embodiments of this disclosure, the common source line in direct contact with the channel structure is formed of a conductive material that provides an ohmic contact, thereby simplifying the connection structure between the channel structure and the common source line compared to when the common source line is formed as a doped semiconductor layer. For example, when the common source line includes a doped silicon layer in direct contact with the channel structure, a silicide layer can be added to provide an ohmic contact layer on the doped silicon layer. The cell current of the channel structure can flow through the doped silicon layer of the common source line and the silicide layer provided as an ohmic contact layer. In embodiments of this disclosure, providing an ohmic contact without the need for a conductive material with an intercalated doped silicon layer in direct contact with the channel structure simplifies the flow path of the cell current.

[0152] In addition, in this disclosure, the common source line is formed of a conductive material with low resistivity, so that the resistance of the common source line can be reduced.

[0153] To compensate for the voltage drop caused by the common source line, a metal source pattern can be connected to the common source line. According to embodiments of this disclosure, since the resistance of the common source line is reduced, the metal source pattern connected to the common source line can be omitted or the area of ​​the metal source pattern can be reduced.

[0154] According to embodiments of this disclosure, since the area of ​​the metal source patterns is reduced, the metal source patterns overlapping with the memory cell array can be spaced apart from each other. Therefore, in this disclosure, space can be provided between the metal source patterns for providing transmission lines for transmitting signals from the circuit group. Thus, in this disclosure, the degree of freedom in line arrangement can be increased within a limited area.

[0155] According to embodiments of this disclosure, a common source line in direct contact with the channel structure is formed at a temperature of 450°C or lower to address defects that occur during the process of forming the common source line in bonding metals bonded prior to its formation. Therefore, the operational reliability of the semiconductor memory device can be improved in this disclosure.

[0156] Figure 14 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0157] Reference Figure 14 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0158] The memory device 1120 may include transmission lines that overlap with a first memory cell array adjacent to input / output pads and transmit signals from a circuit group. The transmission lines may be disposed between first metal source patterns overlapping the first memory cell array. The memory device 1120 may include second metal source patterns that overlap with a second memory cell array further apart from the first memory cell array from the input / output pads and are formed to be wider than each of the first metal source patterns.

[0159] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0160] The storage controller 1110 controls the storage device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the storage system 1100. The error correction block 1114 detects and corrects errors included in data read from the storage device 1120. The memory interface 1115 interfaces with the storage device 1120. The storage controller 1110 may also include a read-only memory (ROM) for storing code data, etc., used for interfacing with the host.

[0161] Figure 15 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0162] Reference Figure 15The computing system 1200 according to embodiments of the present disclosure may include a CPU 1220, random access memory (RAM) 1230, user interface 1240, modem 1250, and memory system 1210 electrically connected to a system bus 1260. For example, the computing system 1200 may be a mobile device.

[0163] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include transmission lines that overlap with a first memory cell array adjacent to input / output pads and transmit signals from a circuit group. The transmission lines may be disposed between first metal source patterns overlapping the first memory cell array. The memory device 1212 may include second metal source patterns that overlap with a second memory cell array further apart from the first memory cell array from the input / output pads and are formed to be wider than each of the first metal source patterns.

[0164] According to this disclosure, the arrangement freedom of the upper wire layer can be improved by using a conductive material formed at a low temperature of 450°C or lower and having a resistivity lower than that of silicon.

[0165] Cross-references to related applications

[0166] This application claims priority to Korean Patent Application No. 10-2020-0097011, filed with the Korean Intellectual Property Office on August 3, 2020, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A substrate extending in a first direction and in a second direction intersecting the first direction; Multiple input / output pads are disposed on one side of the substrate; A first circuit, which is adjacent to the input / output pads in the first direction; A second circuit is configured to be spaced further away from the input / output pads in the first direction than the first circuit; A first memory cell array, which overlaps with the first circuit; A second memory cell array, which overlaps with the second circuit; A plurality of first metal source patterns, the plurality of first metal source patterns overlapping with the first memory cell array, wherein the plurality of first metal source patterns are spaced apart from each other in the second direction; and A second metal source pattern overlaps with the second memory cell array, wherein, in the second direction, the width of the second metal source pattern is wider than the width of each of the first metal source patterns.

2. The semiconductor memory device of claim 1, further comprising transmission lines overlapping the first memory cell array between the plurality of first metal source patterns. in, The transmission line is configured to transmit internal power supply voltage or internal ground voltage.

3. The semiconductor memory device according to claim 2, wherein, The first metal source pattern, the second metal source pattern, and the transmission line are spaced apart from each other on a plane parallel to the substrate.

4. The semiconductor memory device according to claim 2, wherein, The first metal source pattern, the second metal source pattern, and the transmission line comprise aluminum.

5. The semiconductor memory device according to claim 1, further comprising: A bit line is disposed between the first memory cell array and the first circuit, wherein the bit line is connected to the first memory cell array; and A common source line is disposed between the first memory cell array and the first metal source pattern, wherein the common source line is connected to the first memory cell array.

6. The semiconductor memory device according to claim 5, wherein, The common source line is connected to the plurality of first metal source patterns.

7. The semiconductor memory device according to claim 5, wherein, The first memory cell array includes: A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked between the bit line and the common source line; A channel structure that penetrates the gate stack structure, wherein the channel structure extends to directly contact the common source line; and A memory pattern disposed between the channel structure and the gate stack structure.

8. The semiconductor memory device according to claim 7, wherein, The common source line includes a silicide layer that is in direct contact with the channel structure.

9. The semiconductor memory device according to claim 7, wherein, The common source line includes tungsten silicide or nickel silicide in direct contact with the channel structure.

10. The semiconductor memory device according to claim 7, wherein, The channel structure includes an end that extends into the common source line.

11. The semiconductor memory device of claim 7, further comprising: A transmission line including an end adjacent to the input / output pads, wherein the transmission line extends from the end in the first direction to overlap with the first memory cell array; A common source line horizontal pad is disposed between the transmission line and the substrate; The bit-line level pads are disposed between the common source line level pads and the substrate; A first contact plug is disposed between the first memory cell array and the second memory cell array, wherein the first contact plug extends from the pad at the bit line level toward the pad at the common source line level; and A second contact plug extends from the pad at the level of the common source line toward the transmission line.

12. The semiconductor memory device of claim 11, further comprising a plurality of first dummy interlayer insulating layers and a plurality of second dummy interlayer insulating layers alternately stacked between the pads at the bit line level and the pads at the common source line level. in, The first dummy interlayer insulation layer and the second dummy interlayer insulation layer surround the first contact plug.

13. The semiconductor memory device of claim 11, wherein the semiconductor memory device comprises: A first interconnect structure is connected to the pad at the bit line level, and the first interconnect structure is disposed between the pad at the bit line level and the substrate; A second interconnect structure is disposed between the first interconnect structure and the substrate; A junction region defined in a portion of the substrate connected to the second interconnect structure, wherein the junction region includes n-type or p-type impurities; and A plurality of bonding metals are respectively connected to the first interconnect structure and the second interconnect structure, wherein the plurality of bonding metals are bonded to each other.

14. The semiconductor memory device according to claim 13, wherein, The junction region: Included in the portion of the first circuit that is open between the first memory cell array and the second memory cell array; or It is included in the portion of the second circuit that is open between the first memory cell array and the second memory cell array.

Images