Semiconductor device structure and method for preparing the same

Abstract

The present disclosure provides a semiconductor device structure and a method for manufacturing the same, which can avoid the collapse of micropatterns. The semiconductor device structure has a first target structure and a second target structure disposed on a semiconductor substrate. The semiconductor device structure also has a first boron nitride spacer disposed on the first target structure, wherein in a cross-sectional view, a highest point of the first boron nitride spacer is located between a center line of the first target structure and a center line of the second target structure.

Description

Technical Field

[0001] This application claims the priority and benefit of U.S. Provisional Application No. 16 / 942,049, filed Jul. 29, 2020, the content of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to a semiconductor device structure having boron nitride spacer micro-patterns and a method of manufacturing the same. In particular, it relates to a method for preventing collapse of the micro-patterns. Background Art

[0003] As semiconductor device structures have become smaller and more highly integrated, many techniques for manufacturing semiconductor device structures with micro-patterns have been developed. In particular, a photolithography process is typically used to fabricate electronic and optoelectronic devices on a substrate, and the photoresist patterns prepared by the photolithography process are used as masks in etching or ion implantation processes. As the required pitch size and critical dimension (CD) continue to decrease, the fineness of the photoresist patterns becomes a very important factor in the degree of integration. However, the photolithography process for manufacturing semiconductor features has a limit in the continuously improving resolution of exposure apparatuses.

[0004] Although there are semiconductor device structures with micro-patterns and methods of manufacturing the same that have met their intended purposes, not all aspects thereof have been fully satisfied. Therefore, there are still many problems to be overcome in the technology of semiconductor device structures with multiple micro-patterns prepared by the photolithography process.

[0005] The above description of "prior art" is provided only for background information and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of this case. Summary of the Invention

[0006] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure has a first inner-gap sub-element disposed on an upper surface of a semiconductor substrate. The first inner-gap sub-element has a first portion, a second portion, and a third portion, and the third portion is located between the first portion and the second portion. A height of the first portion and a height of the second portion are less than a height of the third portion, and a width of the first portion continuously increases as the first portion extends toward the upper surface of the semiconductor substrate. The semiconductor device structure also has a first outer-gap sub-element of boron nitride disposed on the second portion of the first inner-gap sub-element.

[0007] In some embodiments, the first portion of the first inner-gap sub-element has a first side, a second side, and an outer surface. The first side is adjacent to a lower portion of a first sidewall surface of the third portion. The second side is adjacent to the upper surface of the semiconductor substrate. The outer surface is connected to the first side and the second side. The outer surface has a convex shape. In some embodiments, the first outer-gap sub-element is adjacent to a second sidewall surface of the third portion, and the first outer-gap sub-element and the upper surface of the semiconductor substrate are separated by the second portion. In some embodiments, the first inner-gap sub-element is a stress-compression film. In some embodiments, the first inner-gap sub-element is a stress-compression film, and the first outer-gap sub-element is a stress-extension film. In some embodiments, the semiconductor device structure further has a second inner-gap sub-element and a second outer-gap sub-element of boron nitride. The second inner-gap sub-element is disposed on the upper surface of the semiconductor substrate. The second inner-gap sub-element has a fourth portion, a fifth portion, and a sixth portion, and the sixth portion is located between the fourth portion and the fifth portion. A width of the fourth portion continuously increases as the fourth portion extends toward the upper surface of the semiconductor substrate, and the fourth portion is located between the sixth portion and the first portion of the first inner-gap sub-element. The second outer-gap sub-element is disposed on the fifth portion of the second inner-gap sub-element. In some embodiments, the fourth portion of the second inner-gap sub-element is separated from the first portion of the first inner-gap sub-element.

[0008] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a target layer disposed on a semiconductor substrate; and a first target structure disposed on the target layer. The first target structure has a first portion, a second portion, and a third portion, and the third portion is connected to the first portion and the second portion. A height of the first portion and a height of the second portion are greater than a height of the third portion. The semiconductor device structure also has a first boron nitride spacer disposed on the first portion of the first target structure; and a second boron nitride spacer disposed on the second portion of the first target structure.

[0009] In some embodiments, the first target structure and the target layer are made of the same material, and the first boron nitride spacer and the second boron nitride spacer are made of the same material. In some embodiments, in a cross-sectional view, a highest point of the first boron nitride spacer is located between a center line of the first portion and a center line of the second portion. In some embodiments, in a cross-sectional view, a highest point of the second boron nitride spacer is located between the center line of the first portion and the center line of the second portion. In some embodiments, the semiconductor device structure further includes a second target structure, a third boron nitride spacer, and a fourth boron nitride spacer. The second target structure is disposed on the target layer. The second target structure has a fourth portion, a fifth portion, and a sixth portion, and the sixth portion is connected to the fourth portion and the fifth portion, and the fourth portion, the fifth portion, and the sixth portion form a U-shaped structure. The third boron nitride spacer is disposed on the fourth portion of the second target structure, and the fourth boron nitride spacer is disposed on the fifth portion of the second target structure. In some embodiments, in a cross-sectional view, the third boron nitride spacer is located between the second boron nitride spacer and the fourth boron nitride spacer, and a highest point of the third boron nitride spacer is located between a center line of the fourth portion and a center line of the fifth portion. In some embodiments, a first opening located between the second boron nitride spacer and the third boron nitride spacer is deeper than a second opening located between the first boron nitride spacer and the second boron nitride spacer. In some embodiments, the semiconductor device structure further includes a hard mask structure formed between the first boron nitride spacer and the first portion of the first target structure, and the hard mask has a high etch selectivity relative to the first boron nitride spacer.

[0010] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first target structure and a second target structure disposed on a semiconductor substrate. The semiconductor device structure also has a first boron nitride spacer disposed on the first target structure, wherein in a cross-sectional view, a highest point of the first boron nitride spacer is between a center line of the first target structure and a center line of the second target structure.

[0011] In some embodiments, the semiconductor device structure further includes a second boron nitride spacer disposed on the second target structure, wherein in a cross-sectional view, a highest point of the second boron nitride spacer is between the center line of the first target structure and the center line of the second target structure. In some embodiments, the first target structure has a high etch selectivity relative to the first boron nitride spacer. In some embodiments, the first target structure and the second target structure are made of a thermally decomposable material, a photo-decomposable material, or an electron beam decomposable material. In some embodiments, an upper surface of the semiconductor substrate is exposed between the first target structure and the second target structure.

[0012] Some embodiments of a semiconductor device structure and a method for manufacturing the same are provided. The method for manufacturing the semiconductor device may include undercutting a photoresist pattern on a semiconductor substrate and forming an inner spacer element on a sidewall surface of the photoresist pattern. The inner spacer element has a portion extending into a recess (e.g., the undercut region) of the photoresist pattern to form a footing, and a width of the portion of the inner spacer element continuously increases as the portion extends toward the semiconductor substrate. Thus, the inner spacer element can avoid collapse after removal of the photoresist pattern.

[0013] Alternatively, the method for manufacturing the semiconductor device structure may include forming a hard mask pillar on a target material; forming a spacer on a sidewall surface of the hard mask pillar; and etching the target material and the hard mask pillar, and using the spacer as a mask for etching to form a spacer element on a target structure. The spacer element can avoid collapse of the spacer element due to support from the target structure.

[0014] Alternatively, the method for manufacturing the semiconductor device structure may include forming an energy-removable pattern on a target material; forming a spacer on a sidewall surface of the energy-removable pattern; forming a dielectric layer to surround the energy-removable pattern and the spacer; and etching the energy-removable pattern, the dielectric layer, and the target material, and using the spacer as a mask for etching to form a spacer element on a target structure. The spacer element can avoid collapse of the spacer element due to high etch selectivity during the etching process for forming the spacer element.

[0015] The technical features and advantages of the present disclosure have been outlined quite extensively above, enabling a better understanding of the following detailed description of the present disclosure. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those having ordinary knowledge in the technical field to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same objectives as the present disclosure. Those having ordinary knowledge in the technical field to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Referring to the embodiments in combination with the drawings considered in conjunction with the claims, a more comprehensive understanding of the disclosure of the present application can be obtained. Identical reference numerals in the drawings refer to identical elements.

[0017] Figure 1 FIG. is a cross-sectional schematic view of a semiconductor element structure according to some embodiments of the present disclosure.

[0018] Figure 2 FIG. is a cross-sectional schematic view of a semiconductor element structure according to some embodiments of the present disclosure.

[0019] Figure 3 FIG. is a cross-sectional schematic view of a semiconductor element structure according to some embodiments of the present disclosure.

[0020] Figure 4 FIG. is a cross-sectional schematic view of a semiconductor element structure according to some embodiments of the present disclosure.

[0021] Figure 5 FIG. is a flow schematic view of a method for manufacturing a semiconductor element structure according to some embodiments of the present disclosure.

[0022] Figure 6 FIG. is a flow schematic view of a method for manufacturing a semiconductor element structure according to some embodiments of the present disclosure.

[0023] Figure 7 FIG. is a flow schematic view of a method for manufacturing a semiconductor element structure according to some embodiments of the present disclosure.

[0024] Figure 8 FIG. is a cross-sectional schematic view of an intermediate stage in forming a plurality of photoresist patterns of a semiconductor element structure according to some embodiments of the present disclosure.

[0025] Figure 9 FIG. is a cross-sectional schematic view of an intermediate stage in undercutting the photoresist pattern according to some embodiments of the present disclosure.

[0026] Figure 10A cross-sectional schematic view of an intermediate stage in forming a plurality of inner spacer sub-elements and a plurality of outer spacer sub-elements according to some embodiments of the present disclosure.

[0027] Figure 11 A cross-sectional schematic view of an intermediate stage in forming a plurality of hard mask pillars and a plurality of photoresist patterns on a semiconductor device structure according to some embodiments of the present disclosure.

[0028] Figure 12 A cross-sectional schematic view of an intermediate stage in forming a conformal spacer material on the semiconductor device structure according to some embodiments of the present disclosure.

[0029] Figure 13 A cross-sectional schematic view of an intermediate stage in forming a spacer element on the semiconductor device structure according to some embodiments of the present disclosure.

[0030] Figure 14 A cross-sectional schematic view of an intermediate stage in forming a plurality of hard mask pillars and a plurality of photoresist patterns on a semiconductor device structure according to some embodiments of the present disclosure.

[0031] Figure 15 A cross-sectional schematic view of an intermediate stage in forming a conformal spacer material on the semiconductor device structure according to some embodiments of the present disclosure.

[0032] Figure 16 A cross-sectional schematic view of an intermediate stage in forming a spacer element on the semiconductor device structure according to some embodiments of the present disclosure.

[0033] Figure 17 A cross-sectional schematic view of an intermediate stage in forming an energy-removable pattern on a semiconductor device structure according to some embodiments of the present disclosure.

[0034] Figure 18 A cross-sectional schematic view of an intermediate stage in forming a conformal spacer material on the energy-removable pattern according to some embodiments of the present disclosure.

[0035] Figure 19 A cross-sectional schematic view of an intermediate stage in forming a spacer element on the semiconductor device structure according to some embodiments of the present disclosure.

[0036] Figure 20 A cross-sectional schematic view of an intermediate stage in forming a dielectric layer to surround the energy-removable pattern and the spacer on the semiconductor device structure according to some embodiments of the present disclosure.

[0037] Figure 21A cross-sectional schematic view of a semiconductor device structure formed after etching the energy-removable pattern, the dielectric layer, and the target material by using the spacer as an etching mask according to some embodiments of the present disclosure.

[0038] Wherein, the reference numerals are described as follows:

[0039] 10: Preparation method

[0040] 20: Preparation method

[0041] 30: Preparation method

[0042] 100: Semiconductor device structure

[0043] 101: Semiconductor substrate

[0044] 101T: Upper surface

[0045] 103: Photoresist pattern

[0046] 103’: Photoresist pattern

[0047] 103a: Lower part

[0048] 103b: Upper part

[0049] 110: Undercut

[0050] 115a: Inner spacer element

[0051] 115a1: First part

[0052] 115a2: Second part

[0053] 115a3: Third part

[0054] 115b: Inner spacer element

[0055] 115b1: Fourth part

[0056] 115b2: Fifth part

[0057] 115b3: Sixth part

[0058] 115c: Inner spacer element

[0059] 115d: Inner spacer element

[0060] 117a: Outer spacer element

[0061] 117b: Outer spacer element

[0062] 117c: Outer spacer element

[0063] 117d: Outer spacer element

[0064] 150: Opening

[0065] 200a: Semiconductor element structure

[0066] 200b: Semiconductor element structure

[0067] 201: Semiconductor substrate

[0068] 203: Target material

[0069] 203’: Target layer

[0070] 203a: Target structure

[0071] 203a1: First part

[0072] 203a2: Second part

[0073] 203a3: Third part

[0074] 203b: Target structure

[0075] 203b1: Fourth part

[0076] 203b2: Fifth part

[0077] 203b3: Sixth part

[0078] 205: Hard mask layer

[0079] 205a: Hard mask part

[0080] 205a1: Hard mask structure

[0081] 205a2: Hard mask structure

[0082] 205b: Hard mask part

[0083] 205b1: Hard mask structure

[0084] 205b2: Hard mask structure

[0085] 207a: Hard mask pillar

[0086] 207b: Hard mask pillar

[0087] 209a: Photoresist pattern

[0088] 209b: Photoresist pattern

[0089] 210: Opening

[0090] 213: Spacer material

[0091] 220: Opening

[0092] 223a: Interstitial

[0093] 223a’: Boron nitride interstitial

[0094] 223b: Interstitial

[0095] 223b’: Boron nitride interstitial

[0096] 223c: Interstitial

[0097] 223c’: Boron nitride interstitial

[0098] 223d: Interstitial

[0099] 223d’: Boron nitride interstitial

[0100] 230: Opening

[0101] 240: Opening

[0102] 270: Opening

[0103] 300: Semiconductor device structure

[0104] 301: Semiconductor substrate

[0105] 301T: Upper surface

[0106] 303: Target material

[0107] 303a: Target structure

[0108] 303b: Target structure

[0109] 303c: Target structure

[0110] 303d: Target structure

[0111] 304a: Upper surface

[0112] 304b: Upper surface

[0113] 305: Energy removable pattern

[0114] 307: Interstitial material

[0115] 307a: Interstitial

[0116] 307a’: Boron nitride interstitial

[0117] 307b: Interstitial

[0118] 307b’: Boron nitride interstitial

[0119] 307c: Interstitial

[0120] 307c’: Boron nitride interstitial

[0121] 307d: Interstitial

[0122] 307d’: Boron nitride interstitial

[0123] 308B1: Lower surface

[0124] 308B2: Lower surface

[0125] 308I: Inner surface

[0126] 308O: Outer surface

[0127] 309: Dielectric layer

[0128] 310: Opening

[0129] CL1: Center line

[0130] CL2: Center line

[0131] CL3: Center line

[0132] CL4: Center line

[0133] ES: Outer surface

[0134] H1: Height

[0135] H2: Height

[0136] H3: Height

[0137] ML: Middle line

[0138] S1: First side

[0139] S2: Second side

[0140] SW1: First sidewall surface

[0141] SW2: Second sidewall surface

[0142] TP1: Highest point

[0143] TP2: Highest point

[0144] TP3: Highest point

[0145] TP4: Highest point

[0146] W1: Width

[0147] W2: Width

[0148] X: Direction

[0149] Y: Direction

[0150] S11: Step

[0151] S13: Step

[0152] S15: Step

[0153] S17: Step

[0154] S19: Step

[0155] S21: Step

[0156] S23: Step

[0157] S25: Step

[0158] S27: Step

[0159] S29: Step

[0160] S31: Step

[0161] S33: Step

[0162] S35: Step

[0163] S37: Step

[0164] S39: Step Detailed Implementation Manner

[0165] The following description of the present disclosure is accompanied by the drawings incorporated herein and forming a part of the specification, which illustrate embodiments of the present disclosure. However, the present disclosure is not limited to these embodiments. In addition, the following embodiments may be appropriately integrated to complete another embodiment.

[0166] "An embodiment", "embodiment", "exemplary embodiment", "other embodiments", "another embodiment", etc. mean that the embodiments described in the present disclosure may include specific features, structures, or characteristics, but not every embodiment must include such specific features, structures, or characteristics. Furthermore, the repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment.

[0167] To make the present disclosure fully understood, the following description provides detailed steps and structures. Obviously, the implementation of the present disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail to avoid unnecessarily limiting the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.

[0168] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and / or the desired properties of the device. In addition, in the following description, the formation of a first feature "on" or "above" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. For simplicity and clarity, various features may be drawn at arbitrary scales. In the drawings, some layers / features may be omitted for simplicity.

[0169] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0170] Figure 1 A cross-sectional schematic view of a semiconductor element structure 100 according to some embodiments of the present disclosure. As Figure 1 shown, according to some embodiments, the semiconductor element structure 100 has a plurality of inner gap sub-elements 115a, 115b, 115c, 115d and a plurality of outer gap sub-elements 117a, 117b, 117c, 117d, and the inner gap sub-elements 115a, 115b, 115c, 115d and the plurality of outer gap sub-elements 117a, 117b, 117c, 117d are located on an upper surface 101T of a semiconductor substrate 101.

[0171] More particularly, the inner gap sub-element 115a has a first portion 115a1, a second portion 115a2, and a third portion 115a3, and the third portion 115a3 is located between the first portion 115a1 and the second portion 115a2. Similarly, the inner gap sub-element 115b has a fourth portion 115b1, a fifth portion 115b2, and a sixth portion 115b3, and the sixth portion 115b3 is located between the fourth portion 115b1 and the fifth portion 115b2.

[0172] There is no distinct interface between the second part 115a2 and the third part 115a3, nor between the third part 115a3 and the first part 115a1. Similarly, there is no distinct interface between the fourth part 115b1 and the sixth part 115b3, nor between the sixth part 115b3 and the fifth part 115b2. Figure 1 The dashed lines in Figure 1 are for illustrating the present disclosure. Additionally, for simplicity and clarity, each sub - part of the inner - gap sub - elements 115a, 115b, 115c, 115d is only specified in the left - half portion of the semiconductor element structure 100. It should be understood that the right - half portion of the semiconductor element structure 100 may have features similar to those of the left - half portion of the semiconductor element structure 100.

[0173] In the inner - gap sub - element 115a, the first part 115a1 has a height H1 in the Y - direction, the second part 115a2 has a height H2 in the Y - direction, and the third part 115a3 has a height H3 in the Y - direction. In some embodiments, the height H3 is greater than the height H1 and the height H2. Furthermore, the first part 115a1 has a width in the X - direction, and this width continuously increases as the first part 115a1 extends towards the upper surface 101T of the semiconductor substrate 101.

[0174] It should be understood that in the inner - gap sub - element 115a, the first part 115a1 has a first side S1, a second side S2, and an outer surface ES, and the outer surface ES is connected to the first side S1 and the second side S2. In some embodiments, the first side S1 of the first part 115a1 abuts a lower portion of a first side - wall surface SW1 of the third part 115a3, the second side S2 of the first part 115a1 abuts the upper surface 101T of the semiconductor substrate 101, and the outer surface ES of the first part 115a1 has a convex shape.

[0175] The features of the inner - gap sub - elements 115b, 115c, 115d may be similar to those of the inner - gap sub - element 115a described above, and their descriptions will not be repeated herein. For example, according to some embodiments, a width of the fourth part 115b1 in the X - direction continuously increases as the fourth part 115b1 extends towards the upper surface 101T of the semiconductor substrate 101.

[0176] In addition, as Figure 1As shown, according to some embodiments, the outer gap sub-element 117a is disposed on the second portion 115a2 of the inner gap sub-element 115a, and the outer gap sub-element 117b is disposed on the fifth portion 115b2 of the inner gap sub-element 115b. More particularly, according to some embodiments, the outer gap sub-element 117a is adjacent to a second sidewall surface SW2 of the third portion 115a3 of the inner gap sub-element 115a, and the outer gap sub-element 117a is separated from the upper surface 101T of the semiconductor element 101 by the second portion 115a2.

[0177] The first sidewall surface SW1 and the second sidewall surface SW2 form two opposite sidewall surfaces of the third portion 115a3. Each feature of the outer gap sub-elements 117b, 117c, 117d may be similar to each feature of the outer gap sub-element 117a described above, and its description will not be repeated herein. Furthermore, the inner gap sub-elements 115a, 115b, 115c, 115d are separated from each other.

[0178] In some embodiments, the inner gap sub-element 115a and the inner gap sub-element 115b are disposed symmetrically with respect to a middle line ML, and the middle line ML is located between the inner gap sub-element 115a and the inner gap sub-element 115b. In some embodiments, the outer gap sub-element 117a and the outer gap sub-element 117b are disposed symmetrically with respect to a middle line ML. In some embodiments, the first portion 115a1 and the second portion 115a2 are disposed symmetrically with respect to a middle line, and the middle line is located between the first portion and the second portion.

[0179] Figure 2 It is a cross-sectional schematic view of a semiconductor element structure 200a according to some embodiments of the present disclosure. As Figure 2 shown, according to some embodiments, the semiconductor element structure 200a has a target layer 203' and target structures 203a, 203b. The target layer 203' is disposed on a semiconductor substrate 201, and the target structures 203a, 203b are disposed on the target layer 203'.

[0180] There is no obvious interface between the target structure 203a and the target layer 203', and between the target structure 203b and the target layer 203'. Figure 2 The dashed lines in are for illustrating the present disclosure. It should be understood that, according to some embodiments, the target structures 203a, 203b and the target layer 203' are made of the same material and are formed from the same material layer simultaneously.

[0181] More particularly, the target structure 203a has a first part 203a1, a second part 203a2, and a third part 203a3, and the third part 203a3 is located between the first part 203a1 and the second part 203a2. Similarly, the target structure 203b has a fourth part 203b1, a fifth part 203b2, and a sixth part 203b3, and the sixth part 203b3 is located between the fourth part 203b1 and the fifth part 203b2.

[0182] There is no obvious interface between the first part 203a1 and the third part 203a3 and between the third part 203a3 and the second part 203a2. Similarly, there is no obvious interface between the fourth part 203b1 and the sixth part 203b3 and between the sixth part 203b3 and the fifth part 203b2. Figure 2 The dashed lines in are for the purpose of illustrating the present disclosure.

[0183] In the target structure 203a, the first part 203a1 has a height H1 in the Y direction, the second part 203a2 has a height H2 in the Y direction, and the third part 203a3 has a height H3 in the Y direction. In some embodiments, the height H1 is substantially the same as the height H2, and the height H3 is greater than both the heights H1 and H2. In the context of the present disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. In some embodiments, the first part 203a1, the second part 203a2, and the third part 203a3 form a U-shaped structure.

[0184] Each feature of the target structure 203b can be similar to each feature of the above-described target structure 203a, and its description will not be repeated herein. For example, according to some embodiments, the fourth part 203b1, the fifth part 203b2, and the sixth part 203b3 form another U-shaped structure.

[0185] In some embodiments, the semiconductor element structure 200a also has a hard mask structure 205a1, a hard mask structure 205a2, a hard mask structure 205b1, and a hard mask structure 205b2. The hard mask structure 205a1 is disposed on the first part 203a1 of the target structure 203a, the hard mask structure 205a2 is disposed on the second part 203a2 of the target structure 203a, the hard mask structure 205b1 is disposed on the fourth part 203b1 of the target structure 203b, and the hard mask structure 205b2 is disposed on the fifth part 203b2 of the target structure 203b. According to some embodiments, the hard mask structures 205a1, 205a2, 205b1, 205b2 are made of the same material and are formed from the same material layer simultaneously.

[0186] In some embodiments, the semiconductor element structure 200a further includes a boron nitride spacer 223a', a boron nitride spacer 223b', a boron nitride spacer 223c', and a boron nitride spacer 223d'. The boron nitride spacer 223a' is disposed on the hard mask structure 205a1, the boron nitride spacer 223b' is disposed on the hard mask layer 225a2, the boron nitride spacer 223c' is disposed on the hard mask structure 205b1, and the boron nitride spacer 223d' is disposed on the hard mask structure 205b2. According to some embodiments, the boron nitride spacers 223a', 223b', 223c', 223d' are made of the same material and are formed simultaneously from the same material layer.

[0187] As Figure 2 shown in the cross-sectional view of, a first portion 203a1 of the target structure 203a has a center line CL1, a second portion 203a2 of the target structure 203a has a center line CL2, a fourth portion 203b1 of the target structure 203b has a center line CL3, and a fifth portion 203b2 of the target structure 203b has a center line CL4. Furthermore, the boron nitride spacer 223a' has a highest point TP1, the boron nitride spacer 223b' has a highest point TP2, the boron nitride spacer 223c' has a highest point TP3, and the boron nitride spacer 223d' has a highest point TP4.

[0188] In particular, according to some embodiments, in Figure 2 the cross-sectional view of, the highest point TP1 of the boron nitride spacer 223a' and the highest point TP2 of the boron nitride spacer 223b' are located between the center line CL1 and the center line CL2; and the highest point TP3 of the boron nitride spacer 223c' and the highest point TP4 of the boron nitride spacer 223d' are located between the center line CL3 and the center line CL4.

[0189] In addition, in some embodiments, a plurality of openings 270 are disposed on the target structures 203a and 203b, and a plurality of openings 240 are formed between adjacent target structures (e.g., between the target structures 203a and 203b). In some embodiments, the boron nitride spacers 223a' and 223b' are separately disposed by means of one of the openings 270, the boron nitride spacers 223c' and 223d' are separately disposed by means of other openings 270, and the boron nitride spacers 223b' and 223c' are separately disposed by means of one of the openings 240. It should be understood that, according to some embodiments, the opening 240 is deeper than the opening 270 (e.g., extends to a lower plane in the Y direction).

[0190] Figure 3A cross-sectional schematic view of a semiconductor device structure 200b according to some embodiments of the present disclosure, which is another embodiment of the semiconductor device structure 200a. For consistency and clarity, similar elements appearing in Figure 2 and Figure 3 are given the same reference numerals. As in Figure 2 shown, one difference between the embodiment shown in Figure 3 and the embodiment shown in Figure 3 is that the hard mask structures 205a1, 205a2, 205b1, 205b2 are not formed in the embodiment shown in

[0191] Figure 4 A cross-sectional schematic view of a semiconductor device structure 300 according to some embodiments of the present disclosure. As in Figure 4 shown, according to some embodiments, the semiconductor device structure 300 has target structures 303a, 303b, 303c, 303d and boron nitride spacers 307a', 307b', 307c', 307d'. The target structures 303a, 303b, 303c, 303d are disposed on a semiconductor substrate 301, and the boron nitride spacers 307a', 307b', 307c', 307d' are disposed on the target structures 303a, 303b, 303c, 303d.

[0192] In some embodiments, the boron nitride spacer 307a' is disposed on the target structure 303a, the boron nitride spacer 307b' is disposed on the target structure 303b, the boron nitride spacer 307c' is disposed on the target structure 303c, and the boron nitride spacer 307d' is disposed on the target structure 303d. Furthermore, in some embodiments, each adjacent pair of boron nitride spacers 307a', 307b', 307c', 307d' is separately disposed by an opening 310. In some embodiments, each adjacent pair of target structures 303a, 303b, 303c, 303d is separately disposed by one of the openings 310 such that an upper surface 301T of the semiconductor substrate 301 is exposed in the opening 310.

[0193] As in Figure 4 shown, the target structure 303a has a center line CL1, the target structure 303b has a center line CL2, the target structure 303c has a center line CL3, and the target structure 303d has a center line CL4. Furthermore, the boron nitride spacer 307a' has a highest point TP1, the boron nitride spacer 307b' has a highest point TP2, the boron nitride spacer 307c' has a highest point TP3, and the boron nitride spacer 307d' has a highest point TP4.

[0194] In some embodiments, as in Figure 4As shown, according to some embodiments, the highest point TP1 of the boron nitride spacer 307a' and the highest point TP2 of the boron nitride spacer 307b' are located between the center line CL1 and the center line CL2; and the highest point TP3 of the boron nitride spacer 307c' and the highest point TP4 of the boron nitride spacer 307d' are located between the center line CL3 and the center line CL4.

[0195] Figure 5 FIG. 4 is a schematic flow chart of a method 10 for fabricating a semiconductor device structure 100 according to some embodiments of the present disclosure, wherein the method 10 includes steps S11, S13, S15, S17, and S19. According to some embodiments, Figure 5 Steps S11 to S19 of Figure 8 、 Figure 9 、 Figure 10 and Figure 1 will be described in detail, which are cross-sectional schematic views of the respective intermediate stages in forming the semiconductor device structure 100 in sequence.

[0196] As Figure 8 shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 can be a part of an integrated circuit (IC) wafer, which includes various different passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (pFETs), n-type field effect transistors (nFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal oxide semiconductor (LDMOS) transistors, high voltage transistors, high frequency transistors, fin field effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0197] According to the manufacturing stage of the IC, the semiconductor substrate 101 can include various different material layers (such as dielectric layers, semiconductor layers, and / or conductive layers), which are configured to form IC features (such as doped regions, insulating features, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, the semiconductor substrate 101 has been simplified. It should be understood that additional features can be added to the semiconductor substrate 101, and some of the features described below can be replaced, improved, or excluded in other embodiments.

[0198] In some embodiments, a plurality of photoresist patterns 103 are disposed on the upper surface 101T of the semiconductor substrate 101. The individual steps are illustrated in step S11 of the manufacturing method 10 as shown in Figure 5 FIG. 5. In some embodiments, the photoresist pattern 103 can be formed by a deposition process and a patterning process.

[0199] The deposition process for forming the photoresist pattern 103 may include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin coating process, or other applicable processes. The patterning process for forming the photoresist pattern 103 may include a photolithography process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking).

[0200] Next, as Figure 9 shown, according to some embodiments, a wet etching process is performed on the photoresist pattern 103. It should be understood that, according to some embodiments, the wet etching process undercuts each upper portion 103b of the etched photoresist pattern 103', and forms a plurality of undercut portions 110 within each lower portion 103a of the etched photoresist pattern 103'. The individual steps are illustrated in step S13 of the manufacturing method 10 as Figure 5 shown.

[0201] As Figure 10 shown, according to some embodiments, after the wet etching process, a plurality of inner gap sub-elements 115a, 115b, 115c, 115d are disposed on each sidewall surface of the etched photoresist pattern 103', and a plurality of outer gap sub-elements 117a, 117b, 117c, 117d are disposed on the inner gap sub-elements 115a, 115b, 115c, 115d. The individual steps are illustrated in step S15 of the manufacturing method 10 as Figure 5 shown.

[0202] In some embodiments, the inner gap sub-elements 115a, 115b, 115c, 115d and the outer gap sub-elements 117a, 117b, 117c, 117d are made of a dielectric material, such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more suitable dielectric materials, or a combination thereof. In some embodiments, the inner gap sub-elements 115a, 115b, 115c, 115d are stress-extension films, while the outer gap sub-elements 117a, 117b, 117c, 117d are stress-compression films. In some other embodiments, the inner gap sub-elements 115a, 115b, 115c, 115d are stress-compression films, while the outer gap sub-elements 117a, 117b, 117c, 117d are stress-extension films.

[0203] In some embodiments, the inner gap sub-elements 115a, 115b, 115c, 115d are formed by a deposition process and an etching process. For example, an inner gap sub-material (not shown) can be conformally deposited on each upper surface and each sidewall surface of the etched photoresist pattern 103', as well as on the upper surface 101T of the semiconductor substrate 101; and a portion of the inner gap sub-material can be deposited into the undercut portion 110 (please refer to Figure 9 ). Then, as Figure 10 shown, according to some embodiments, the inner gap sub-material can be partially removed by an etching process, leaving the inner gap sub-elements 115a, 115b, 115c, 115d. In some embodiments, the etching process includes a dry etching process.

[0204] Next, the outer gap sub-elements 117a, 117b, 117c, 117d are formed by a deposition process and an etching process. For example, an outer gap sub-material (not shown) can be conformally deposited on each upper surface of the etched photoresist pattern 103', on each upper surface and each sidewall surface of the inner gap sub-elements 115a, 115b, 115c, 115d, and on the upper surface 101T of the semiconductor substrate 101. Then, as Figure 10 shown, according to some embodiments, the outer gap sub-material is partially removed by an etching process, leaving the outer gap sub-elements 117a, 117b, 117c, 117d. In some embodiments, the etching process includes a dry etching process.

[0205] In some embodiments, in the manufacture of the outer interstitial elements 117a, 117b, 117c, 117d made of boron nitride, the elements are placed in a reaction chamber, preferably, they are heated to a temperature between 100°C and 500°C, and a chamber pressure between 0.5 Torr and 10 Torr. More preferably, the temperature is between 300°C and 400°C, and the chamber pressure is between 0.5 Torr and 3 Torr.

[0206] In some embodiments, a boron precursor gas or a precursor gas diluted with an inert gas is pulsed into the chamber, the boron precursor gas being, for example, one or more of the following: boron trichloride (BCl 3 ), trimethylboron (B(CH 3 ) 3 ), diborane (B 2 H 6 ), boron tribromide (BBr 3 ), and the inert gas is, for example, helium (He) or argon (Ar), which allows the formation of a monolayer or less than a monolayer on each exposed surface of the device (i.e., each surface of the gate stack, hard mask, semiconductor body, and, if present, the liner layer). In some embodiments, the boron precursor is pulsed for a period of time ranging from 2 seconds to 30 seconds, and a flow rate thereof is from 50 standard cubic centimeters (sccm) per minute to 1000 sccm per minute. In some embodiments, the boron precursor is pulsed into the chamber at a flow rate ranging from 100 sccm per minute to 500 sccm per minute.

[0207] In some embodiments, after the boron precursor is pulsed into the chamber, the chamber is purged with an inert gas, such as nitrogen (N 2 ), argon (Ar) or helium (He), and a certain amount of time (e.g., 30 seconds) is required to remove by-products and all unreacted substances from the chamber.

[0208] In some embodiments, a nitrogen-containing reactant gas is then pulsed into the deposition chamber to react with the first layer and form a monolayer of boron nitride, and the nitrogen-containing reactant gas is, for example, nitrogen, ammonia (NH 3 ), or nitrogen and hydrogen (H 2) a mixture. In some embodiments, the nitrogen-containing gas is pulsed into the chamber for a period of time between 1 second and 10 seconds, and at a flow rate between 50 sccm and 1000 sccm per minute. In some embodiments, the flow rate of the pulsed nitrogen-containing gas is between 100 sccm and 300 sccm per minute.

[0209] In some embodiments, when providing a nitrogen-containing reactive gas to the chamber, the PEALD technique can also be used to assist the reaction of forming boron-nitrogen bonds by using plasma to dissociate the reactive gas. In some embodiments, in the case of using PEALD, it is under a plasma condition where the power is between 50 W and 500 W, and more preferably, the power is between 100 W and 200 W.

[0210] In some embodiments, after pulsing the nitrogen-containing reactive gas, the chamber is purged again for an appropriate period of time, and the cycle is repeated until the deposition of the boron nitride layer has occurred to the desired thickness.

[0211] As described above, the inner gap sub-element 115a has a first part 115a1, a second part 115a2, and a third part 115a3, and the inner gap sub-element 115b has a fourth part 115b1, a fifth part 115b2, and a sixth part 115b3. In some embodiments, the first part 115a1 and the fourth part 115b1 are covered by the upper part 103b of the etched photoresist pattern 103’, and the second part 115a2 and the fifth part 115b2 are covered by the outer gap sub-elements 117a and 117b respectively.

[0212] In some embodiments, the interface between the first part 115a1 and the etched photoresist pattern 103’ has a convex profile facing the etched photoresist pattern 103’, and the first part 115a1 is surrounded by the third part 115a3, the etched photoresist pattern 103’, and the semiconductor substrate 101. Similarly, in some embodiments, the interface between the fourth part 115b1 and the etched photoresist pattern 103’ has a convex profile facing the etched photoresist pattern 103’, and the fourth part 115b1 is surrounded by the sixth part 115b3, the etched photoresist pattern 103’, and the semiconductor substrate 101. It should be understood that the right half of this structure can have features similar to those of the left half of this structure.

[0213] As Figure 1 shown, according to some embodiments, after the outer gap sub-elements 117a, 117b, 117c, 117d are formed, the etched photoresist pattern 103’ is removed. The individual steps are illustrated in as Figure 5Step S19 in the preparation method 10 shown. The etched photoresist pattern 103' is removed by an etching process, such as a dry etching process, a wet etching process, or a combination thereof. After the etched photoresist pattern 103' is removed, a plurality of openings 150 are obtained, and the first portion 115a1 and the fourth portion 115b1 are exposed through one of the openings 150. In some embodiments, the semiconductor element structure 100 has a film structure (not shown in each figure) on the semiconductor substrate 101. In some embodiments, the inner spacer elements 115a, 115b, 115c, 115d are formed on the film structure to be used as hard masks for a plurality of micro-patterns, which can be used in the subsequent manufacturing process to pattern the corresponding micro-patterns in the film structure.

[0214] Since the inner spacer elements 115a, 115b, 115c, 115d have portions that extend into the undercut portion 110 (please refer to Figure 9 ), a plurality of footings are formed, so the base width (along the X direction) of each of the inner spacer elements 115a, 115b, 115c, 115d is increased. Therefore, the inner spacer elements 115a, 115b, 115c, 115d can avoid collapse during the subsequent manufacturing process and be used as hard masks for patterning the film structure, even when removing the etched photoresist pattern 103'. Furthermore, the formation of the outer spacer elements 117a, 117b, 117c, 117d can help the semiconductor element structure 100 better resist the harmful effects of the subsequent etching process, and the etching process is, for example, a dry etching process.

[0215] Figure 6 FIG. is a schematic flow chart of a preparation method 20 of a semiconductor element structure (such as the semiconductor element structure 200a or 200b) according to some embodiments of the present disclosure, wherein the preparation method 20 has steps S21, S23, S25, S27, and S29.

[0216] According to some embodiments, Figure 6 Steps S21 to S29 of Figure 11 are combined with Figure 12 , Figure 13 and Figure 2 for detailed description, which are cross-sectional schematic views of each intermediate stage in sequence during the formation of the semiconductor element structure 200a. According to some other embodiments, Figure 6 Steps S21 to S29 of Figure 14 are combined with Figure 15 , Figure 16 and Figure 3For a detailed description, it is a cross-sectional schematic diagram of each intermediate stage in sequence during the formation of the semiconductor element structure 200b.

[0217] As Figure 11 shown, a semiconductor substrate 201 is provided, and a target material 203 is disposed on the semiconductor substrate 201. Its individual steps are illustrated in the step S21 in the manufacturing method 20 as Figure 6 shown. The details of the semiconductor substrate 201 may be similar to or the same as those of the semiconductor substrate 101, and will not be described repeatedly herein.

[0218] In some embodiments, the target material 203 is a dielectric layer. For example, the target material 203 is made of the following materials: silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof. In some embodiments, the target material 203 includes an interconnect structure having one or more metallization layers (such as copper layers) in the target material 203, and the interconnect structure is used to connect various different electronic components to form functional circuitry. In some embodiments, the target material 203 is formed by any suitable process, such as deposition, damascene, and / or dual damascene.

[0219] Still referring to Figure 11 , according to some embodiments, a hard mask layer 205 is disposed on the target material 203, and the hard mask pillars 207a, 207b are disposed on the hard mask layer 205 by an etching process using a plurality of photoresist patterns 209a, 209b as a mask. In some embodiments, the hard mask layer 205 and the hard mask pillars 207a, 207b are made of a dielectric material, such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more suitable materials, or a combination thereof.

[0220] In particular, according to some embodiments, the hard mask layer 205 and the hard mask pillars 207a, 207b are formed by a deposition process and an etching process. For example, a hard mask material (not shown in the figure) can be conformally deposited on the upper surface of the target layer 203, and the photoresist patterns 209a, 209b are disposed on the hard mask material. Some of the processes used to form the photoresist patterns 209a, 209b are similar to or the same as those used to form the photoresist patterns 103, and will not be described repeatedly herein. As Figure 11 shown, after the photoresist patterns 209a, 209b are formed, the portions of the hard mask material exposed by the photoresist patterns 209a, 209b are removed by a dry etching process to form a plurality of openings 210 between adjacent hard mask pillars (such as the hard mask pillars 207a and 207b). Its individual steps are illustrated in asFigure 6 Steps S23 and S25 in the preparation method 20 shown.

[0221] It should be understood that, according to some embodiments, the target material 203 is not exposed through the opening 210. Furthermore, according to some embodiments, the hard mask layer 205 and the hard mask pillars 207a, 207b are made of the same material and are formed simultaneously. After obtaining the opening 210, the photoresist patterns 209a, 209b can be removed.

[0222] As Figure 12 Shown, according to some embodiments, after removing the photoresist patterns 209a, 209b, a spacer material 213 is conformally deposited on each upper surface and each sidewall surface of the hard mask pillars 207a, 207b, and on the upper surface of the hard mask layer 205, so as to obtain the reduced opening 220.

[0223] In some embodiments, the spacer material 213 is made of boron nitride, and the deposition process for forming the spacer material 213 includes a CVD process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable processes; preferably, ALD and / or PEALD techniques are used. In some embodiments, the material of the spacer material 213 is different from the material of the hard mask pillars 207a, 207b. It should be understood that the material of the hard mask pillars 207a, 207b has a high etch selectivity relative to the material of the spacer material 213.

[0224] Next, as Figure 13 Shown, according to some embodiments, the spacer material 2213 is etched to form spacers 223a, 223b, 223c, 223d on each sidewall surface of the hard mask pillars 207a, 207b. The individual steps are illustrated in step S27 in the preparation method 20 shown in Figure 6 Shown. In some embodiments, the etching process is an anisotropic etching process, which vertically removes the same amount of spacer material 213 at all positions and leaves the spacers 223a, 223b, 223c, 223d on each sidewall surface of the hard mask pillars 207a, 207b. In some embodiments, the etching process is a dry etching process.

[0225] In some embodiments, the component is placed in a reaction chamber, preferably, which is heated to a temperature between 100°C and 500°C, and a chamber pressure is between 0.5 Torr and 10 Torr. More preferably, the temperature is between 300°C and 400°C, and the chamber pressure is between 0.5 Torr and 3 Torr.

[0226] In some embodiments, a boron precursor gas or a precursor gas diluted with an inert gas is pulsed into the chamber. The boron precursor gas is, for example, one or more of the following: boron trichloride (BCl 3 ), trimethylboron (B(CH 3 ) 3 ), diborane (B 2 H 6 ), boron tribromide (BBr 3 ), and the inert gas is, for example, helium (He) or argon (Ar), which allows for the formation of a monolayer or less than a monolayer on each exposed surface of the device (i.e., each surface of the gate stack, hard mask, semiconductor body, and, if present, including the liner layer). In some embodiments, the boron precursor is pulsed for a period of time between 2 seconds and 30 seconds, and its flow rate ranges from 50 standard cubic centimeters per minute (sccm) to 1000 sccm per minute. In some embodiments, the flow rate of the boron precursor pulsed into the chamber ranges from 100 sccm to 500 sccm per minute.

[0227] In some embodiments, after the boron precursor is pulsed into the chamber, the chamber is purged with an inert gas, such as nitrogen (N 2 ), argon (Ar), or helium (He), which takes a certain amount of time (e.g., 30 seconds) to remove by-products and all unreacted substances from the chamber.

[0228] In some embodiments, then, a nitrogen-containing reaction gas is pulsed into the deposition chamber to react with the first layer and form a monolayer of boron nitride. The nitrogen-containing reaction gas is, for example, nitrogen, ammonia (NH 3 ), or a mixture of nitrogen and hydrogen (H 2 ). In some embodiments, the nitrogen-containing gas is pulsed into the chamber for a period of time between 1 second and 10 seconds, and at a flow rate between 50 sccm and 1000 sccm per minute. In some embodiments, the flow rate of the nitrogen-containing gas pulse ranges from 100 sccm to 300 sccm per minute.

[0229] In some embodiments, when a nitrogen-containing reactive gas is provided to the chamber, the PEALD technique can also be used to assist the reaction of forming boron-nitrogen bonds by dissociating the reactive gas using plasma. In some embodiments, in the case of using PEALD, it is under a plasma condition where the power is between 50 W and 500 W, and more preferably, the power is between 100 W and 200 W.

[0230] In some embodiments, after pulsing the nitrogen-containing reactive gas, the chamber is purged again for an appropriate period of time, and the cycle is repeated until the deposition of the boron nitride layer has occurred to the desired thickness.

[0231] Furthermore, as Figure 13 shown, according to some embodiments, some portions of the hard mask layer 205 between the hard mask pillars 207a and 207b are removed to form hard mask portions 205a and 205b, and a plurality of openings 230 are obtained between adjacent hard mask portions (such as hard mask portions 205a and 205b). In some embodiments, the target material 203 is exposed through the openings 230. In some embodiments, the spacers 223a, 223b, 223c, and 223d are separately disposed from the target material 203 by the hard mask portions 205a and 205b.

[0232] Next, as Figure 2 shown, according to some embodiments, the hard mask pillars 207a and 207b, the hard mask portions 205a and 205b, and the target material 203 are etched using the spacers 223a, 223b, 223c, and 223d as a mask. The individual steps are illustrated in step S29 of the manufacturing method 20 as shown in Figure 6 shown. In some embodiments, the etching process is a dry etching process.

[0233] More particularly, in some embodiments, the hard mask pillars 207a and 207b are completely removed, the hard mask portions 205a and 205b are etched to form hard mask structures 205a1, 205a2, 205b1, and 205b2, and according to some embodiments, the target structures 203a and 203b are disposed on the target layer 203' by etching the target material 203. In addition, the spacers 223a, 223b, 223c, and 223d are slightly etched to form boron nitride spacers 223a', 223b', 223c', and 223d'. It should be understood that during the etching process, the material of the hard mask pillars 207a and 207b has a high etching selectivity relative to the material of the spacers 223a, 223b, 223c, and 223d (such as the material of the boron nitride spacers 223a', 223b', 223c', and 223d').

[0234] The hard mask pillars 207a and 207b have a first etch selectivity relative to the material of the spacers 223a, 223b, 223c and 223d; the material of the hard mask portions 205a and 205b has a second etch selectivity relative to the material of the spacers 223a, 223b, 223c and 223d; and the material of the target material 203 has a third etch selectivity relative to the material of the spacers 223a, 223b, 223c and 223d. In some embodiments, the first etch selectivity, the second etch selectivity and the third etch selectivity are similar to each other.

[0235] According to some embodiments, since the upper surfaces of the hard mask pillars 207a, 207b are higher than the upper surface of the target material 203 before the etching process, the opening 240 is deeper than the opening 270 after the etching process. Therefore, the boron nitride spacers 223a', 223b', 223c', 223d' can be prevented from collapsing due to the support provided by the underlying target structures 203a, 203b, which are U-shaped structures protruding from the target layer 203'.

[0236] Furthermore, since the hard mask pillars 207a and 207b, the hard mask portions 205a and 205b, and the target material 203 have a high etch selectivity compared to the spacers 223a, 223b, 223c, 223d in the etching process used to form the boron nitride spacers 223a', 223b', 223c', 223d', the boron nitride spacers 223a', 223b', 223c', 223d' can avoid collapse.

[0237] Figure 14 , Figure 15 , Figure 16 and Figure 3 2 is a schematic cross-sectional view of various intermediate stages in forming a semiconductor device structure 200b. The semiconductor device structure 200b is similar to or identical to the semiconductor device structure 200a, except that the hard mask pillars 205a1, 205a2, 205b1, 205b2 are not formed between the boron nitride spacers 223a', 223b', 223c', 223d' and the target structures 203a, 203b.

[0238] like Figure 14 As shown, according to some embodiments, the target material 203 is disposed on the semiconductor substrate 201, and the hard mask pillars 207a, 207b are disposed on the target material 203 by an etching process using the photoresist patterns 209a, 209b as a mask. The respective steps are shown in FIG. Figure 6Steps S21, S23, and S25 in the preparation method 20 shown. In some embodiments, compared with Figure 11 's structure, Figure 14 the target material 203 is not covered by the hard mask layer 205. More specifically, according to some embodiments, the hard mask layer 205 is not formed in the Figure 14 structure, and the target material 203 is exposed through the opening 210.

[0239] Next, as Figure 15 shown, according to some embodiments, the photoresist patterns 209a, 209b are removed, and the spacer material 213 is conformally deposited on the upper surfaces and sidewall surfaces of each of the hard mask pillars 207a, 207b, and on the upper surface of the target material 203 to obtain the reduced opening 220.

[0240] As Figure 16 shown, according to some embodiments, the spacer material 213 is removed to form spacers 223a, 223b, 223c, 223d on the sidewall surfaces of each of the hard mask pillars 207a, 207b. The individual steps are illustrated in step S27 in the preparation method 20 as Figure 6 shown. In some embodiments, compared with the Figure 13 structure, Figure 16 the spacers 223a, 223b, 223c, 223d are in direct contact with the target material 203.

[0241] Next, as Figure 3 shown, according to some embodiments, the spacers 223a, 223b, 223c, 223d are used as a mask to etch the hard mask pillars 207a, 207b and the target material 203, and the spacers 223a, 223b, 223c, 223d are slightly etched to form boron nitride spacers 223a', 223b', 223c', 223d'. The individual steps are illustrated in step S29 in the preparation method 20 as Figure 6 shown.

[0242] More specifically, according to some embodiments, in some embodiments, the hard mask pillars 207a, 207b are completely removed, and the target layer 203' and the target structures 203a, 203b located on the target layer 203' are formed by etching the target material 203. As described above, according to some embodiments, compared with the semiconductor element structure 200a, the boron nitride spacers 223a', 223b', 223c', 223d' of the semiconductor element structure 200a are in direct contact with the target structures 203a, 203b.

[0243] Figure 7FIG. 0 is a schematic flow chart of a method 30 for fabricating a semiconductor device structure 300 in accordance with some embodiments of the present disclosure, wherein the method 30 includes steps S31, S33, S35, S37, and S39. Figure 7 Steps S31 through S39 are described in detail in conjunction with Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 4 which are cross-sectional schematic views of respective intermediate stages in sequence in forming the semiconductor device structure 300.

[0244] As Figure 17 shown, a semiconductor substrate 301 is provided and a target material 303 is disposed on the semiconductor substrate 301. Details of the semiconductor substrate 301 and the target material 303 are similar to or the same as those of the semiconductor substrate 201 and the target material 203, and their descriptions are not repeated herein. Their individual steps are illustrated in step S31 of the fabrication method 30 as shown in Figure 7 .

[0245] Still referring to Figure 17 , in accordance with some embodiments, a plurality of energy-removable patterns 305 are disposed on the target material 303. Their individual steps are illustrated in step S33 of the fabrication method 30 as shown in Figure 7 . In some embodiments, the energy-removable pattern 305 has a thermally decomposable material. In some other embodiments, the energy-removable pattern 305 has a photo-decomposable material, an electron-beam decomposable material, or other applicable energy-decomposable materials. In particular, in some embodiments, the energy-removable pattern 305 has a base material and a decomposable porogen material, and the decomposable porogen material is substantially removed when exposed to an energy source (i.e., a heat source).

[0246] In some embodiments, the base material includes hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous SiO2, and the decomposable porogen material includes a porogen organic compound that can provide porosity to the space originally occupied by the energy-removable pattern 305 in the subsequent process.

[0247] In some embodiments, the energy-removable pattern 305 is formed by a deposition process and a patterning process. The deposition process includes CVD, PVD, ALD, spin coating, or other suitable processes, and the patterning process for forming the energy-removable pattern 305 may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process.

[0248] In some embodiments, the target material 203 includes a thermally decomposable material, a photo-decomposable material, an electron beam decomposable material, or other applicable energy-decomposable materials. It should be understood that, according to some embodiments, the target material 203 and the energy-removable pattern 305 include the same material or similar materials.

[0249] As Figure 18 shown, according to some embodiments, after the energy-removable pattern 305 is formed, a spacer material 307 is conformally deposited on each upper surface and each sidewall surface of the energy-removable pattern 305 and on the upper surface of the target material 303.

[0250] In some embodiments, the spacer material 307 is made of boron nitride, and the deposition process for forming the spacer material 307 includes CVD, PVD, ALD, spin coating, or other suitable processes; preferably, ALD and / or PEALD techniques are used. In some embodiments, the material of the spacer material 307 is different from the material of the energy-removable pattern 305. It should be understood that the material of the energy-removable pattern 305 has a high etching selectivity relative to the material of the spacer material 307.

[0251] Next, as Figure 19 shown, according to some embodiments, the spacer material 307 is etched to form spacers 307a, 307b, 307c, 307d on each sidewall surface of the energy-removable pattern 305. The individual steps are illustrated in step S35 of the preparation method 30 as Figure 7 shown. In some embodiments, the etching process is an anisotropic etching process, which vertically removes the same amount of the spacer material 307 at all positions and leaves the spacers 307a, 307b, 307c, 307d on each sidewall surface of the energy-removable pattern 305. In some embodiments, the etching process is a dry etching process.

[0252] In some embodiments, the element is placed in a reaction chamber. Preferably, it is heated to a temperature between 100 °C and 500 °C, and a chamber pressure is between 0.5 Torr and 10 Torr. More preferably, the temperature is between 300 °C and 400 °C, and the chamber pressure is between 0.5 Torr and 3 Torr.

[0253] In some embodiments, a boron precursor gas or a precursor gas diluted with an inert gas is pulsed into the chamber. The boron precursor gas is, for example, one or more of the following: boron trichloride (BCl 3 ), trimethylboron (B(CH 3 3 ), diborane (B 2 H 6 ), boron tribromide (BBr 3 ), and the inert gas is, for example, helium (He) or argon (Ar), which allows the formation of a monolayer or less than a monolayer on each exposed surface of the element (i.e., each surface of the gate stack, hard mask, semiconductor body, and, if present, including the liner layer). In some embodiments, the boron precursor is pulsed for a period of time between 2 seconds and 30 seconds, and a flow rate thereof is from 50 standard cubic centimeters per minute (sccm) to 1000 sccm. In some embodiments, the flow rate of the boron precursor pulsed into the chamber is between 100 sccm and 500 sccm.

[0254] In some embodiments, after the boron precursor is pulsed into the chamber, the chamber is purged with an inert gas, such as nitrogen (N 2 ), argon (Ar), or helium (He), which takes a certain amount of time (e.g., 30 seconds) to remove by-products and all unreacted substances from the chamber.

[0255] In some embodiments, then, a nitrogen-containing reaction gas is pulsed into the deposition chamber to react with the first layer and form a monolayer of boron nitride. The nitrogen-containing reaction gas is, for example, nitrogen, ammonia (NH 3 ), or nitrogen and hydrogen (H 2 ​) a mixture. In some embodiments, the nitrogen-containing gas is pulsed into the chamber for a period of time between 1 second and 10 seconds, and at a flow rate between 50 sccm and 1000 sccm per minute. In some embodiments, the flow rate of the pulsed nitrogen-containing gas is between 100 sccm and 300 sccm per minute.

[0256] In some embodiments, when providing a nitrogen-containing reactive gas to the chamber, the PEALD technique can also be used to assist the reaction of forming boron-nitrogen bonds by using plasma dissociation of the reactive gas. In some embodiments, in the case of using PEALD, a plasma is generated at a power (plasma condition), and the power is between 50 W and 500 W, and more preferably, the power is between 100 W and 200 W.

[0257] In some embodiments, after pulsing the nitrogen-containing reactive gas, the chamber is purged again for an appropriate period of time, and the cycle is repeated until the deposition of the boron nitride layer has occurred to the desired thickness.

[0258] As Figure 20 shown, according to some embodiments, after the spacers 307a, 307b, 307c, 307d are formed, a dielectric layer 309 is formed to surround the energy-removable pattern 305 and the spacers 307a, 307b, 307c, 307d. The individual steps are illustrated in step S37 of the manufacturing method 30 as shown in Figure 7 shown.

[0259] In some embodiments, the dielectric layer 309 includes the following materials: silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more suitable dielectric materials, or a combination thereof. In some embodiments, the material of the dielectric layer 309 is different from the material of the spacers 307a, 307b, 307c, 307d. It should be understood that the material of the dielectric layer 309 has a high etch selectivity with respect to the material of the spacers 307a, 307b, 307c, 307d.

[0260] In some embodiments, the dielectric layer 309 contains a thermally decomposable material, a photo-decomposable material, an electron beam decomposable material, or other applicable energy-decomposable materials. It should be understood that according to some embodiments, the dielectric layer 309 and the energy-removable pattern 305 contain the same material or similar materials.

[0261] In some embodiments, the dielectric layer 309 is formed by a deposition process and a subsequent planarization process. The deposition process can be CVD, PVD, ALD, spin coating, or other applicable processes, and the planarization process can be a chemical mechanical polishing (CMP) process.

[0262] Next, asFigure 21 As shown, according to some embodiments, the energy-removable pattern 305, the dielectric layer 309, and the target material 303 are etched using boron nitride spacers 307a, 307b, 307c, 307d as a mask. The individual steps are illustrated in step S39 of the preparation method 30 as shown in Figure 7 As shown. In some embodiments, the etching process is a dry etching process. In some embodiments, please refer to Figure 21 , the boron nitride spacers 307a' and the boron nitride spacer 307b' are symmetrically arranged substantially with respect to the middle line ML located between the boron nitride spacer 307a' and the boron nitride spacer 307b'.

[0263] In some embodiments, please refer to Figure 21 , in a cross-sectional view, the boron nitride spacers 307a' and the boron nitride spacer 307b' each have a rounding upper surface at the highest points TP1 and TP2 respectively. In some embodiments, please refer to Figure 21 , the boron nitride spacer 307a' has an inner surface 308I and an outer surface 308O. In a cross-sectional view, the inner surface 308I faces the middle line ML, the outer surface 308O faces the opposite side, the inner surface 308I is substantially a non-curved surface, the outer surface 308O is substantially a curved surface, and the curvature of the inner surface 308I is less than that of the outer surface 308O.

[0264] In some embodiments, please refer to Figure 21 , the target structure 303a has an upper surface 304a which has a first upper width, the boron nitride spacer 307a' has a lower surface 308B1 which has a first lower width, the upper surface 304a contacts the lower surface 308B1, and the first upper width is substantially the same as the first lower width. In some embodiments, please refer to Figure 21 , the target structure 303b has an upper surface 304b which has a second upper width, the boron nitride spacer 307b' has a lower surface 308B2 which has a second lower width, the upper surface 304b contacts the lower surface 308B2, and the second upper width is substantially the same as the second lower width.

[0265] In some embodiments, please refer to Figure 21, the opening 310 has the same width W1, and the target structures 303a, 303b, 303c, 303d have the same width W2. In some embodiments, the width W1 is designed to be the same as the width W2, such as the same space and pattern. In some embodiments, the semiconductor element structure 300 has a film structure (not shown in the figure), located on the semiconductor substrate 301. In some embodiments, the target structures 303a, 303b, 303c, 303d are formed on the film structure and regarded as multiple micro-patterns, which can be used as a hard mask in the subsequent manufacturing process, and the subsequent manufacturing process is used to pattern the corresponding micro-patterns in the film structure.

[0266] In some embodiments, according to some embodiments, the energy-removable pattern 305 is completely removed, and the target structures 303a, 303b, 303c, 303d can be formed by etching through the target material 303. In addition, the spacers 307a, 307b, 307c, 307d are slightly etched to form boron nitride spacers 307a', 307b', 307c', 307d'. It should be understood that during the etching process, the material of the energy-removable pattern 305 has a high etching selectivity relative to the material of the spacers 307a, 307b, 307c, 307d (such as the material of the spacer elements 307a', 307b', 307c', 307d').

[0267] The material of the energy-removable pattern 305 has a first etching selectivity relative to the material of the spacers 307a, 307b, 307c, 307d; the material of the dielectric layer 309 has a second etching selectivity relative to the material of the spacers 307a, 307b, 307c, 307d; and the material of the target material 303 has a third etching selectivity relative to the material of the spacers 307a, 307b, 307c, 307d. In some embodiments, the first etching selectivity, the second etching selectivity, and the third etching selectivity are similar to each other.

[0268] Since the energy-removable pattern 305, the dielectric layer 309, and the target material 303 have a high etching selectivity in the etching process for forming the boron nitride spacers 307a', 307b', 307c', 307d' relative to the spacers 307a, 307b, 307c, 307d, the etching process can be carried out until the upper surface 301T of the semiconductor substrate 301 while avoiding the collapse of the boron nitride spacers 307a', 307b', 307c', 307d'.

[0269] An embodiment of the present disclosure provides a semiconductor element structure. The semiconductor element structure has a first inner-gap sub-element disposed on an upper surface of a semiconductor substrate. The first inner-gap sub-element has a first portion, a second portion, and a third portion, and the third portion is located between the first portion and the second portion. A height of the first portion and a height of the second portion are less than a height of the third portion, and a width of the first portion continuously increases as the first portion extends toward the upper surface of the semiconductor substrate. The semiconductor element structure also has a first outer-gap sub-element of boron nitride disposed on the second portion of the first inner-gap sub-element.

[0270] In some embodiments, the first portion of the first inner-gap sub-element has a first side, a second side, and an outer surface. The first side is adjacent to a lower portion of a first sidewall surface of the third portion. The second side is adjacent to the upper surface of the semiconductor substrate. The outer surface is connected to the first side and the second side. The outer surface has a convex shape. In some embodiments, the first outer-gap sub-element is adjacent to a second sidewall surface of the third portion, and the first outer-gap sub-element and the upper surface of the semiconductor substrate are separated by the second portion. In some embodiments, the first inner-gap sub-element is a stress-compression film. In some embodiments, the first inner-gap sub-element is a stress-compression film, and the first outer-gap sub-element is a stress-extension film. In some embodiments, the semiconductor element structure further has a second inner-gap sub-element and a second outer-gap sub-element of boron nitride. The second inner-gap sub-element is disposed on the upper surface of the semiconductor substrate. The second inner-gap sub-element has a fourth portion, a fifth portion, and a sixth portion, and the sixth portion is located between the fourth portion and the fifth portion. A width of the fourth portion continuously increases as the fourth portion extends toward the upper surface of the semiconductor substrate, and the fourth portion is located between the sixth portion and the first portion of the first inner-gap sub-element. The second outer-gap sub-element is disposed on the fifth portion of the second inner-gap sub-element. In some embodiments, the fourth portion of the second inner-gap sub-element is separated from the first portion of the first inner-gap sub-element.

[0271] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a target layer disposed on a semiconductor substrate; and a first target structure disposed on the target layer. The first target structure has a first portion, a second portion, and a third portion, and the third portion is connected to the first portion and the second portion. A height of the first portion and a height of the second portion are greater than a height of the third portion. The semiconductor device structure also has a first boron nitride spacer disposed on the first portion of the first target structure; and a second boron nitride spacer disposed on the second portion of the first target structure.

[0272] In some embodiments, the first target structure and the target layer are made of the same material, and the first boron nitride spacer and the second boron nitride spacer are made of the same material. In some embodiments, in a cross-sectional view, a highest point of the first boron nitride spacer is located between a center line of the first portion and a center line of the second portion. In some embodiments, in a cross-sectional view, a highest point of the second boron nitride spacer is located between the center line of the first portion and the center line of the second portion. In some embodiments, the semiconductor device structure further includes a second target structure, a third boron nitride spacer, and a fourth boron nitride spacer. The second target structure is disposed on the target layer. The second target structure has a fourth portion, a fifth portion, and a sixth portion, and the sixth portion is connected to the fourth portion and the fifth portion, and the fourth portion, the fifth portion, and the sixth portion form a U-shaped structure. The third boron nitride spacer is disposed on the fourth portion of the second target structure, and the fourth boron nitride spacer is disposed on the fifth portion of the second target structure. In some embodiments, in a cross-sectional view, the third boron nitride spacer is located between the second boron nitride spacer and the fourth boron nitride spacer, and a highest point of the third boron nitride spacer is located between a center line of the fourth portion and a center line of the fifth portion. In some embodiments, a first opening located between the second boron nitride spacer and the third boron nitride spacer is deeper than a second opening located between the first boron nitride spacer and the second boron nitride spacer. In some embodiments, the semiconductor device structure further includes a hard mask structure formed between the first boron nitride spacer and the first portion of the first target structure, and the hard mask has a high etch selectivity with respect to the first boron nitride spacer.

[0273] An embodiment of the present disclosure provides a semiconductor element structure. The semiconductor element structure includes a first target structure and a second target structure disposed on a semiconductor substrate. The semiconductor element structure also has a first boron nitride spacer disposed on the first target structure, wherein in a cross-sectional view, a highest point of the first boron nitride spacer is between a center line of the first target structure and a center line of the second target structure.

[0274] In some embodiments, the semiconductor element structure further includes a second boron nitride spacer disposed on the second target structure, wherein in a cross-sectional view, a highest point of the second boron nitride spacer is between the center line of the first target structure and the center line of the second target structure. In some embodiments, the first target structure has a high etch selectivity relative to the first boron nitride spacer. In some embodiments, the first target structure and the second target structure are made of a thermally decomposable material, a photo-decomposable material, or an electron beam decomposable material. In some embodiments, an upper surface of the semiconductor substrate is exposed between the first target structure and the second target structure.

[0275] Some embodiments of a semiconductor element structure and a method for manufacturing the same are provided. The method for manufacturing the semiconductor element may include undercutting a photoresist pattern on a semiconductor substrate and forming an inner spacer element on a sidewall surface of the photoresist pattern. The inner spacer element has a portion extending into a recess (e.g., the undercut region) of the photoresist pattern to form a footing, and a width of the portion of the inner spacer element continuously increases as the portion extends toward the semiconductor substrate. Accordingly, the inner spacer element can avoid collapse after removal of the photoresist pattern.

[0276] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be substituted with other processes or combinations thereof.

[0277] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: a first target structure and a second target structure disposed on a semiconductor substrate; and a first boron nitride spacer disposed on the first target structure, wherein in a cross-sectional view, a highest point of the first boron nitride spacer is between a center line of the first target structure and a center line of the second target structure, wherein, in a cross-sectional view, the first boron nitride spacer has a convex upper surface, the convex upper surface includes a curved portion facing the center line of the second target structure in the cross-sectional view, and the highest point of the first boron nitride spacer is located at a top of the curved portion of the convex upper surface.

2. The semiconductor device structure according to claim 1, further comprising a second boron nitride spacer disposed on the second target structure, wherein in a cross-sectional view, a highest point of the second boron nitride spacer is between the center line of the first target structure and the center line of the second target structure.

3. The semiconductor device structure according to claim 1, wherein, the first target structure has a high etch selectivity relative to the first boron nitride spacer.

4. The semiconductor device structure according to claim 1, wherein, the first target structure and the second target structure are made of a thermally decomposable material, a photo-decomposable material or an electron beam decomposable material.

5. The semiconductor device structure according to claim 1, wherein, an upper surface of the semiconductor substrate is exposed between the first target structure and the second target structure.

6. The semiconductor device structure according to claim 2, wherein, in a cross-sectional view, the second boron nitride spacer has a convex upper surface.

7. The semiconductor device structure according to claim 2, wherein, the first boron nitride spacer and the second boron nitride spacer are disposed symmetrically about a middle line, and the middle line is between the first boron nitride spacer and the second boron nitride spacer.

8. The semiconductor device structure according to claim 1, wherein, the first target structure has a first upper width, the first boron nitride spacer has a first lower width, and the first upper width is substantially the same as the first lower width.

9. The semiconductor device structure according to claim 2, wherein, the second target structure has a second upper width, the second boron nitride spacer has a second lower width, and the second upper width is substantially the same as the second lower width.

10. The semiconductor device structure according to claim 1, wherein, the first boron nitride spacer has an inner surface and an outer surface, in a cross-sectional view, the inner surface faces the center line of the second target structure, the inner surface is substantially a non-curved surface, and the outer surface is substantially a curved surface.

11. The semiconductor device structure according to claim 10, wherein, the first boron nitride spacer has an inner surface and an outer surface, in a cross-sectional view, the inner surface faces the center line of the second target structure, and a curvature of the inner surface is less than a curvature of the outer surface.

12. A method for manufacturing a semiconductor device structure, comprising: forming a target material on a semiconductor substrate; Form a plurality of energy-removable patterns on the target material; Form a plurality of boron nitride spacers on sidewall surfaces of respective ones of the energy-removable patterns; Form a dielectric layer to surround the plurality of energy-removable patterns and the plurality of boron nitride spacers; And Etch the plurality of energy-removable patterns, the dielectric layer, and the target material by using the plurality of boron nitride spacers as an etch mask for etching; After etching the target material, form a plurality of target structures from the target material, wherein the plurality of boron nitride spacers are respectively disposed above the plurality of target structures; Each of the plurality of boron nitride spacers disposed above the plurality of target structures is configured to have a convex upper surface in a cross-sectional view; The convex upper surface of each of the plurality of boron nitride spacers disposed above the plurality of target structures is configured to have a curved portion facing a center line of an adjacent target structure in a cross-sectional view, and a highest point of each of the plurality of boron nitride spacers is located at a top of the curved portion of the convex upper surface; and Each of the plurality of boron nitride spacers disposed above the plurality of target structures is configured to have an inner surface and an outer surface, wherein the inner surface is a non-curved surface and the outer surface is a curved surface, and the convex upper surface extends between the inner surface and the outer surface.

13. The method for manufacturing a semiconductor device structure according to claim 12, wherein, Forming a plurality of boron nitride spacers on sidewall surfaces of respective ones of the energy-removable patterns includes: Conformally forming a boron nitride spacer material on upper surfaces and sidewalls of the plurality of energy-removable patterns, and on an upper surface of the target material; and Performing an anisotropic etching process to remove a portion of the boron nitride spacer material so that the plurality of boron nitride spacers are formed on sidewalls of the plurality of energy-removable patterns.

14. The method for manufacturing a semiconductor device structure according to claim 13, wherein, The energy-removable pattern has a first etching selectivity with respect to the plurality of boron nitride spacers; and the dielectric layer has a second etching selectivity with respect to the plurality of boron nitride spacers; and the first etching selectivity and the second etching selectivity are similar to each other.

15. The method for manufacturing a semiconductor device structure according to claim 13, wherein, The energy-removable pattern has a first etching selectivity with respect to the plurality of boron nitride spacers; and the target material has a third etching selectivity with respect to the plurality of boron nitride spacers; and the first etching selectivity and the third etching selectivity are similar to each other.

16. The method for manufacturing a semiconductor device structure according to claim 13, wherein, The dielectric layer has a second etching selectivity with respect to the plurality of boron nitride spacers; and the target material has a third etching selectivity with respect to the plurality of boron nitride spacers; and the second etching selectivity and the third etching selectivity are similar to each other.

17. The method for manufacturing a semiconductor device structure according to claim 12, wherein, The dielectric layer and the plurality of energy-removable patterns include a thermally decomposable material.

18. The method for manufacturing a semiconductor device structure as claimed in claim 12, wherein, the dielectric layer and the plurality of energy-removable patterns comprise a photo-decomposable material or an electron beam-decomposable material.

19. The method for manufacturing a semiconductor device structure as claimed in claim 12, wherein, the dielectric layer and the plurality of energy-removable patterns comprise a base material and a decomposable pore-forming agent material, and the decomposable pore-forming agent material is removed when exposed to an energy source, the base material comprises hydrogen silsesquioxane, methyl silicate, porous polyarylether, porous SiLK or porous silicon oxide, and the decomposable pore-forming agent material comprises a pore-forming organic compound.

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