Method for preparing recessed gate enhanced HEMT device based on CMP etching technology

Abstract

The application discloses a method for preparing a recessed gate enhanced HEMT device based on a CMP etching technology, which comprises the following steps: arranging a mask on an epitaxial wafer for manufacturing the HEMT device, and exposing a gate region of a barrier layer from the mask; and performing a polishing treatment on a side surface of the epitaxial wafer provided with the mask, wherein a polishing liquid also can selectively corrode the barrier layer until a recess structure matched with the gate is formed in the barrier layer. By adopting the chemical polishing mode, the barrier layer in the epitaxial structure of the HEMT device can be selectively etched without damage to form the recess structure matched with the gate, so that the process is simple, the cost is low, the controllability and repeatability are high, the etching damage of the device structure can be effectively reduced, the gate under surface roughness is smaller, the reliability of the device is remarkably improved, and the device has the advantages of large saturation current, small on-resistance, good uniformity and the like, and is beneficial to industrial scale production.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and relates to a manufacturing method of an enhanced HEMT device, in particular to a method for manufacturing a recess gate enhanced HEMT device based on a CMP (chemical mechanical polishing) etching technology and the recess gate enhanced HEMT device. BACKGROUND

[0002] As an important third-generation semiconductor material, GaN material has excellent characteristics such as large band gap, high breakdown field strength and large electron saturation velocity, which makes the performance of GaN-based power electronic devices superior to that of traditional Si-based devices in many aspects. For example, GaN HEMT devices can meet the requirements of high frequency, large power and high efficiency.

[0003] GaN HEMT devices can be divided into two types, i.e., an enhancement type (V th > 0) and a depletion type (V th < 0), according to whether the threshold voltage is greater than zero. The conventional HEMT device is a depletion type device, which needs to introduce a negative voltage source to turn off the device in application, and has a safety hazard, and increases the complexity and cost of the circuit, so the enhancement type device is more preferred in actual application. At present, the schemes for realizing the enhancement type device include a Cascode structure, F ion treatment, a recess gate structure, a P-type gate structure and the like. For the recess gate enhanced GaN HEMT, the recess gate is usually realized by etching to reduce the distance from the gate to the channel, so as to improve the control of the gate on the channel, and thus effectively improve the threshold voltage of the device. Meanwhile, the recess gate etching can improve the transconductance of the device, improve the high-frequency performance of AlGaN / GaN, and reduce the short channel effect caused by the reduction of the gate length.

[0004] At present, the recess gate enhanced GaN HEMT is mainly realized by the following three methods. The first scheme is to use ICP (inductively coupled plasma) technology to etch GaN material by Cl-based gas, to realize slow and low-damage etching recess by adjusting the radio frequency power, flow, pressure and the like. However, the etching selectivity of dry etching for GaN and AlGaN is small, the etching process is difficult to control, the repeatability is poor, and the damage and high concentration interface state caused by dry etching will lead to serious current collapse phenomenon, which greatly reduces the performance of the device. The second scheme is to use hard mask thermal oxidation AlGaN, and then produce recess by means of alkaline solution etching, for example, refer to CN104167362A and CN103258739A. However, the repeatability of this scheme is poor, the uniformity is not ideal for large-size products, and it is not conducive to industrial production. The third scheme is to first use oxygen plasma treatment and then etching, which is repeated for dozens of times, so as to obtain the GaN interface of recess and self-stopping layer. However, this scheme needs a long time and has a complex process. Summary of the Invention

[0005] The main purpose of the present invention is to provide a method for preparing a recessed gate enhancement mode HEMT device based on CMP etching technology, so as to overcome the shortcomings of the prior art.

[0006] Another object of the present invention is to provide a recessed gate enhancement mode HEMT device.

[0007] To achieve the aforementioned object of the invention, the technical solutions adopted by the present invention include:

[0008] One aspect of the present invention provides a method for fabricating a recessed gate enhancement mode HEMT device based on CMP etching technology, comprising:

[0009] Disposing a mask on an epitaxial wafer for fabricating a HEMT device, and exposing a gate region of the barrier layer from the mask;

[0010] The gate region of the barrier layer is polished, wherein the polishing liquid used can also selectively erode the barrier layer until a groove structure cooperating with the gate is formed in the barrier layer.

[0011] Another aspect of the present invention provides a recessed gate enhancement mode HEMT device prepared by the aforementioned method.

[0012] Compared with existing technologies, the present invention utilizes chemical polishing to selectively etch the barrier layer in the HEMT device epitaxial structure without damage, forming a recessed structure that matches the gate. This process is not only simple, cost-effective, and highly controllable and repeatable, but also effectively reduces etching damage to the device structure, resulting in a smaller surface roughness under the gate, significantly improving device reliability, and enabling the device to have high saturation current, low on-resistance, and good uniformity, facilitating industrial-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 This is a process flow chart for preparing a recessed gate enhancement mode HEMT device based on CMP etching technology in a typical embodiment of the present invention;

[0015] Figure 2 1 is a schematic structural diagram of a recessed gate enhancement mode HEMT device in a typical embodiment of the present invention;

[0016] Figure 3 1 is a top view of a groove in an enhanced HEMT device product according to Example 1 of the present invention;

[0017] Figure 4 This is the surface roughness test result of the etched surface in an enhanced HEMT device product in Example 1 of the present invention. DETAILED DESCRIPTION

[0018] In view of the shortcomings of the prior art, the inventors of this case, after long-term research and extensive practice, have proposed the technical solution of the present invention. A clearer and more complete description of the technical solution of the present invention is provided below.

[0019] Some embodiments of the present invention provide a method for fabricating a recessed gate enhancement mode HEMT device based on CMP etching technology, comprising:

[0020] Disposing a mask on an epitaxial wafer for fabricating a HEMT device, and exposing a gate region of the barrier layer from the mask;

[0021] The gate region of the barrier layer is polished, wherein the polishing liquid used can also selectively erode the barrier layer until a groove structure cooperating with the gate is formed in the barrier layer.

[0022] In some embodiments, the polishing liquid is an alkaline polishing liquid.

[0023] In some embodiments, the polishing liquid further comprises polishing particles, and the polishing particles are made of, but not limited to, silicon dioxide.

[0024] In some embodiments, the epitaxial wafer further includes a capping layer.

[0025] In some embodiments, the multiple semiconductor material layers in the epitaxial wafer may be formed from III-V compounds. For example, the channel layer may be made of GaN, the barrier layer may be made of AlGaN, and the cap layer may be made of GaN, but are not limited thereto. Furthermore, the multiple semiconductor material layers in the epitaxial wafer may be made of other semiconductor materials, such as Si, GaAs, etc.

[0026] In some embodiments, the material of the mask includes any one or more combinations of inorganic non-metallic materials, metals, and organic materials. For example, the material of the mask can be selected from any one or more combinations of silicon nitride, silicon oxide, polyimide (PI), Al, Cr, and photoresist. Furthermore, the raw material used to form the mask can be selected from porous glass film (SPG), tetraethyl orthosilicate (TEOS), etc., but is not limited thereto.

[0027] In some embodiments, the method further includes: growing a dielectric layer on the epitaxial wafer, and removing a gate region of the dielectric layer to form the mask.

[0028] Furthermore, the method may include:

[0029] Growing a channel layer and a barrier layer in sequence on a substrate to obtain the epitaxial wafer;

[0030] Performing mesa isolation on the epitaxial wafer;

[0031] A dielectric layer is grown on the epitaxial wafer, and the gate region of the dielectric layer is removed to form the mask.

[0032] Furthermore, the method may specifically include: forming a photoresist layer on the dielectric layer, and exposing and developing the gate region of the photoresist layer to expose the gate region of the dielectric layer, and then removing the gate region of the dielectric layer by dry etching or wet etching, and then removing the remaining photoresist layer.

[0033] In some embodiments, the polishing process includes:

[0034] Fixing the epitaxial wafer with the mask on its surface on a chemical polishing device, and making the gate region of the barrier layer contact with the polishing layer of the polishing tool;

[0035] Pressure is applied between the epitaxial wafer and the polishing tool, and polishing liquid is allowed to enter the contact interface between the gate region of the barrier layer and the polishing layer of the polishing tool, while the epitaxial wafer and the polishing tool are rotated relative to each other.

[0036] Furthermore, the pH value of the polishing liquid is 10-12, and the content of the polishing particles is 5-30 wt%.

[0037] Furthermore, the pressure is preferably 2kg-5kg, but is not limited thereto.

[0038] Furthermore, the relative rotation speed between the epitaxial wafer and the polishing tool is preferably 2000-4000 rpm.

[0039] Furthermore, during the polishing process, the polishing tool also rotates at a speed of 40-80 rpm.

[0040] Furthermore, the polishing tool may be a polishing pad commonly used in the art.

[0041] Furthermore, the method further includes the steps of fabricating a source electrode, a drain electrode, and a gate electrode, wherein the source electrode, the drain electrode, and the gate electrode can be fabricated and formed in various ways known in the art, and thus will not be described in detail here.

[0042] Furthermore, the chemical polishing process in the method described above may be supplemented by light irradiation (eg, ultraviolet irradiation), laser polishing (eg, deep ultraviolet laser polishing), and other operations to further improve processing efficiency and processing accuracy.

[0043] In the present invention, a mask is provided on an epitaxial wafer used to fabricate a HEMT device, and the gate region of the barrier layer is exposed through the mask. An alkaline polishing solution containing nanoparticles is then selected to polish the masked side of the epitaxial wafer. High-speed relative rotation between the polishing tool and the epitaxial wafer is utilized to promote chemical corrosion of the barrier layer by the alkaline substances in the alkaline polishing solution. Simultaneously, the polishing particles are caused to strike the etched area at a high frequency due to the vigorous oscillation of the alkaline polishing solution, slowing the deposition of chemical corrosion products in the etched area. This ensures that the etching rate of the alkaline polishing solution on all regions of the etched surface is consistent, effectively reducing the roughness of the etched surface, thereby achieving a smaller surface roughness under the gate, thereby significantly improving device reliability. In the present invention, by adjusting the concentration of alkaline substances in the alkaline polishing solution, the particle size and content of the polishing particles, and the relative rotation speed of the polishing tool and the epitaxial wafer, the etching speed and etching depth can be accurately controlled to meet different practical application requirements. The operation is simple and the controllability is high. Compared with processes such as dry etching, no complex equipment is required, the cost is significantly reduced, the efficiency is higher, and the obtained product has better performance, including but not limited to a larger saturation current and a smaller on-resistance.

[0044] See also Figure 1 As shown, in a more specific embodiment of the present invention, a method for preparing a recessed gate enhancement mode HEMT device based on CMP etching technology includes the following steps:

[0045] S1. First, an epitaxial wafer for making an enhanced HEMT device is provided. The epitaxial wafer can be formed by sequentially growing a nucleation layer, a buffer layer, a channel layer, and a barrier layer on a cleaned substrate. In some cases, a cap layer (not shown in the figure) can also be grown on the barrier layer. The nucleation layer, buffer layer, channel layer, barrier layer, and cap layer can all be formed from III-V compounds. For example, the cap layer can be formed from intrinsic GaN and can have a thickness of 20-100 nm. In this step S1, the active area of ​​the epitaxial wafer can also be isolated in a manner known in the art. For example, a photoresist can be spin-coated on the epitaxial wafer, and an isolation pattern can be photoetched out, and then ion implantation or etching technology can be used to achieve isolation of the active area.

[0046] S2. Grow a dense dielectric layer on the epitaxial wafer, the material of which may be silicon nitride, etc. Then, set a photoresist layer (photoresist layer) on the dielectric layer, and expose the gate region of the dielectric layer through exposure and development processes.

[0047] S3. Using the photoresist layer as a mask, the gate region of the dielectric layer is removed by dry etching or other methods to expose the gate region of the barrier layer, and then the remaining photoresist layer is completely peeled off.

[0048] S4. The gate region of the barrier layer is polished and etched by CMP, wherein the polishing liquid used also serves as a wet etching liquid, thereby forming a shallow groove in the barrier layer by physical polishing and chemical selective etching, that is, a groove structure matching the gate, thereby blocking the formation of two-dimensional electron gas (2DEG).

[0049] S5. Remove the source and drain regions of the dielectric layer through processes such as photolithography and dry etching to expose the source and drain regions of the barrier layer. Then, use metal deposition techniques such as electron beam evaporation or sputtering to deposit metal in the source and drain regions of the barrier layer. After annealing, achieve ohmic contact to form the source and drain. In the case where the epitaxial wafer includes a cap layer, this step may also include etching away the source and drain regions of the cap layer using photolithography, dry etching or wet etching techniques. These operations can also be completed by those skilled in the art in accordance with known methods. Furthermore, in step S5, after the source and drain are made, a gate may be made again through metal deposition techniques such as photolithography, electron beam evaporation or sputtering to complete the preparation of the groove gate enhanced HEMT device. The device structure can be referred to in Figure 2 shown.

[0050] The methods provided in the above embodiments of the present invention can quickly and efficiently form a gate-matching groove structure in the barrier layer of the HEMT device epitaxial structure, significantly reducing or even avoiding etching damage. The methods feature a simple process, high controllability, good repeatability, excellent uniformity, and low cost, facilitating industrial-scale production.

[0051] Some embodiments of the present invention also provide a recessed gate enhancement-mode HEMT device fabricated using the aforementioned method. This recessed gate enhancement-mode HEMT device exhibits advantages such as minimal etching damage and surface roughness under the gate, high reliability, high saturation current, low on-resistance, and good uniformity, and has broad application prospects.

[0052] The technical solution of the present invention is further described in detail below in conjunction with the embodiments and drawings. This embodiment is implemented on the premise of the technical solution of the invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0053] Example 1 A recessed gate enhancement-mode HEMT device provided in this embodiment includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer, wherein a source and a drain are provided on the barrier layer, and a recess is formed in the region of the barrier layer between the source and the drain. The recess cooperates with the gate to form a recessed gate, which can deplete the two-dimensional electron gas under the gate and can generate two-dimensional electron gas by induction when the device is operating, thereby realizing an enhancement-mode device.

[0054] A method for manufacturing the recessed gate enhancement mode HEMT device provided in this embodiment includes the following steps:

[0055] (1) MOCVD growth of HEMT epitaxial layer

[0056] After obtaining the Si substrate, it was ultrasonically cleaned with acetone, isopropyl alcohol, and deionized water. Subsequently, a 100nm-thick nucleation layer, a 2μm-thick AlGaN stress control layer, a 300nm-thick high-resistance GaN layer, a 300nm-thick GaN channel layer, a 20nm-thick AlGaN barrier layer, and a 3nm-thick intrinsic cap layer were grown using MOCVD, yielding an epitaxial wafer (hereinafter referred to as a wafer).

[0057] (2) Countertop isolation

[0058] First, the wafer was spin-coated with a photoresist at 3000 rpm for 30 seconds. This was followed by a soft bake on a hot plate set to 90°C for 100 seconds. After the soft bake, the wafer was exposed for active area isolation. Finally, the exposed sample was developed in a developer, rinsed repeatedly with ultrapure water, and then dried with nitrogen.

[0059] (3) Groove grid production

[0060] A 500nm thick silicon nitride dielectric layer is grown on the wafer surface after the mesa is isolated. The wafer is then spin-coated using a spin coater at a speed of 3000rpm for 30 seconds. This is followed by a soft bake, with the hot plate set to 90°C for 100 seconds. After the soft bake, the wafer is exposed for the groove gate. The exposed wafer is then placed in a developer, repeatedly rinsed with pure water, and dried with nitrogen. The gate region of the silicon nitride dielectric layer is then dry-etched to remove the photoresist. The remaining silicon nitride dielectric layer then doubles as a mask after cleaning with acetone and isopropyl alcohol. The wafer is then fixed on the stage using low-temperature wax or vacuum, and the stage is mounted on the carrier assembly to complete the fixation of the wafer, and then the surface of the wafer on which the silicon nitride dielectric layer is grown is brought into contact with the polishing layer of the polishing tool in the CMP device; the carrier assembly can provide a controllable pressure between the wafer and the polishing tool (e.g., a polishing pad) (e.g., a pressure of 2-5 kg ​​can be applied between the two), and at the same time, a polishing liquid (e.g., an alkaline polishing liquid containing NaOH and polishing particles, the pH value of the polishing liquid is preferably 11-12, the content of the polishing particles is 5-30 wt%, preferably 10-15 wt%, and the polishing particles are 500 nm in diameter) is added. Below, for example, silicon oxide particles with a particle size of about 300-500nm can be used) can be distributed onto the polishing tool and enter the gap between the wafer and the polishing tool, the polishing tool and the wafer rotate relative to each other (relative rotation speed is about 2000-4000rpm, for example 2500rpm) and rotate at a low speed (rotation speed is 40-80rpm, for example 60rpm), the polishing time is set to about 3-5min, and finally a groove structure is formed in the gate area of ​​the barrier layer, the polishing etching is terminated at the surface of the channel layer, and the surface roughness of the etched surface finally formed can be controlled within the range of 0.1nm-10nm, especially around 0.2nm.

[0061] (4) Source and drain fabrication

[0062] Before making the source and drain, the surface of the wafer is cleaned first, and the dielectric layer can be removed or retained (for example, the aforementioned dense silicon nitride dielectric layer can be retained, while the dielectric layer and passivation layer of other materials can be removed by wet etching and other processes). Then, the wafer is spin-coated with glue using a glue spreader at a speed of 3000 rpm for 30 seconds. Soft baking is then performed, with the hot plate set to a temperature of 90°C for 100 seconds. After soft baking, the sample is exposed to the source and drain areas. Finally, the exposed wafer is placed in a developer for development, repeatedly rinsed with ultrapure water, and blown dry with nitrogen.

[0063] The source and drain areas of the cap layer are etched away using ICP etching equipment. The etched wafer is placed in an electron beam evaporation table, and four layers of metal, Ti / Al / Ni / Au, are sequentially deposited on the source and drain areas not covered by the photoresist. After the metal is evaporated, the wafer is peeled off and placed in a rapid annealing furnace for rapid annealing at 850°C for 30 seconds in a nitrogen atmosphere to form an ohmic contact.

[0064] (5) Gate fabrication

[0065] The wafer is spin-coated with photoresist using a spin coater at 3000 rpm for 30 seconds. A soft bake is then performed on a hot plate at 90°C for 100 seconds. The gate region of the wafer after the soft bake is then exposed. Finally, the exposed wafer is placed in a developer, rinsed repeatedly with ultrapure water, and dried with nitrogen. The photolithographic wafer is then placed in an electron beam evaporation station, where two layers of Ni / Au are sequentially deposited on the gate region uncovered by the photoresist. This is followed by a lift-off process to form the gate contact, ultimately resulting in a recessed-gate enhancement-mode HEMT device.

[0066] The macroscopic morphology of the groove in the enhanced HEMT device product prepared in this embodiment is as follows: Figure 3 As shown, the surface roughness of the etched surface can be controlled at about 0.2nm (the surface micromorphology of the etched surface is shown in Figure 4 As shown), the device saturation current density can reach 50mA / mm 2 about.

[0067] Comparative Example 1 The method for producing a recessed gate enhanced HEMT device provided in this comparative example is substantially the same as that in Example 1, except that:

[0068] Step (3) includes: growing a 500nm thick silicon nitride dielectric layer on the surface of the wafer after the table is isolated, and then using a spin coater to spin coat the wafer at a speed of 3000rpm for 30s. Then soft baking is performed, with the hot plate set to 90°C for 100s. The wafer after soft baking is exposed to groove gates, and then the exposed wafer is placed in a developer for development, repeatedly rinsed with pure water, and then blown dry with nitrogen. The gate area of ​​the silicon nitride dielectric layer is then dry-etched to remove the photoresist, and then the remaining silicon nitride dielectric layer is cleaned with acetone and isopropyl alcohol to remove the photoresist, so that the remaining silicon nitride dielectric layer can be used as a mask. The surface of the wafer with the silicon nitride dielectric layer was placed in contact with a NaOH solution with a pH value of about 10-11. After 5 minutes, 25 minutes, and 60 minutes, the wafer was separated from the NaOH solution and thoroughly cleaned with ultrapure water. The etched grooves were then inspected. The results showed that the etching was incomplete after 5 minutes, over-etching occurred after 60 minutes, and the etching depth after 25 minutes was more appropriate. However, the roughness of the etched surface obtained by the three etching times was greater than 100nm. The wafer with the more appropriate etching depth was selected to continue the operation of steps (4)-(5). Among the multiple batches of enhanced HEMT device products finally obtained, the best performing product had a saturation current density of 10mA / mm 2 about.

[0069] It should be understood that the technical solution of the present invention is not limited to the above-mentioned specific implementation cases. Any technical variations made according to the technical solution of the present invention without departing from the scope of protection of the purpose of the present invention and the claims shall fall within the scope of protection of the present invention.

Claims

1. A method for preparing a recessed gate enhancement mode HEMT device based on CMP etching technology, characterized in that: include: First, a mask is set on an epitaxial wafer for manufacturing a HEMT device, and the gate region of the barrier layer is exposed from the mask, wherein the epitaxial wafer includes a GaN channel layer and an AlGaN barrier layer; Then, the epitaxial wafer is fixed on a chemical polishing device, and the gate region of the barrier layer is brought into contact with the polishing layer of a polishing tool; Then, a pressure of 2-5 kg ​​is applied between the epitaxial wafer and the polishing tool, and a polishing liquid is allowed to enter the contact interface between the gate region of the barrier layer and the polishing layer of the polishing tool. Simultaneously, the epitaxial wafer and the polishing tool are rotated relative to each other at a relative rotation speed of 2000-4000 rpm, and the polishing tool is rotated at a speed of 40-80 rpm to polish the surface of the epitaxial wafer on the side provided with the mask until a groove structure that matches the gate is formed in the barrier layer; The polishing liquid has a pH value of 10-12 and contains 5-30 wt % polishing particles, and can selectively erode the barrier layer. The particle size of the polishing particles is greater than 0 and less than 500 nm.

2. The method according to claim 1, wherein: The epitaxial wafer further includes a capping layer, and the material of the capping layer includes GaN.

3. The method according to claim 1, wherein: The material of the mask includes any one or more combinations of inorganic non-metallic materials, metals, and organic materials.

4. The method according to claim 3, wherein: The material of the mask includes any one or more combinations of silicon nitride, silicon oxide, polyimide, Al, Cr, and photoresist.

5. The method according to claim 1, wherein Also includes: A dielectric layer is grown on the epitaxial wafer, and the gate region of the dielectric layer is removed to form the mask.

6. The method according to claim 5, characterized in that Also includes: Growing a channel layer and a barrier layer in sequence on a substrate to obtain the epitaxial wafer; Performing mesa isolation on the epitaxial wafer; A dielectric layer is grown on the epitaxial wafer, and the gate region of the dielectric layer is removed to form the mask.

7. The method according to claim 5, characterized in that Specifically include: A photoresist layer is formed on the dielectric layer, and the gate region of the photoresist layer is exposed and developed to expose the gate region of the dielectric layer. The gate region of the dielectric layer is then removed by dry etching or wet etching, and then the remaining photoresist layer is removed.

8. The method according to claim 1, wherein: The pH value of the polishing liquid is 11-12, and it contains 10-15 wt % of polishing particles. The polishing particles are silicon oxide particles with a particle size of 300-500 nm.

9. The method according to claim 1, wherein: The polishing tool includes a polishing pad.

10. The method according to claim 1, characterized in that It also includes steps of making a source, a drain and a gate.

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