A semiconductor structure and a method for forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate; forming a gate layer on a portion of the substrate; modifying the sidewalls of the gate layer; forming modified regions on the sidewalls of the gate layer, wherein the bottom dimension of the modified regions is larger than its top dimension; and etching the modified regions. This method makes the sidewalls of the gate layer more nearly perpendicular to the substrate, improving the reliability of the semiconductor device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the existing semiconductor field, the fin field effect transistor (FinFET) is an emerging multi-gate device. Compared with the planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has stronger short channel suppression capability and stronger operating current, and is now widely used in various semiconductor devices.

[0003] With the continuous development of semiconductor technology, integrated circuits continue to "scale down". When the size of semiconductor devices is reduced to the nanometer level, especially for fin field effect transistors, the control ability of the gate is closely related to its physical size. The small geometric size and three-dimensional structure of fin field effect transistors make the device impact caused by process changes more and more serious, and new methods are urgently needed for optimization. The formation method of fin field effect tube structure in the existing technology needs to be improved. Summary of the invention

[0004] The invention provides a semiconductor structure and a forming method thereof to improve the performance of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, forming a gate layer on a portion of the substrate, modifying the side wall of the gate layer, forming a modified area on the side wall of the gate layer, the bottom size of the modified area is larger than the top size, and etching the modified area.

[0006] Optionally, in a direction perpendicular to the extension direction of the gate layer, a bottom dimension of a cross-sectional graph of the gate layer is larger than a top dimension.

[0007] Optionally, the modification method includes an amorphization treatment.

[0008] Optionally, the modification method includes: performing ion implantation on the side wall of the gate layer.

[0009] Optionally, the modification method further includes: performing annealing after the ion implantation.

[0010] Optionally, the parameters of the ion implantation process include: the implanted ions include N ions, B ions, BF 2+One or more combinations of ions and C ions, the injection energy is 5KeV to 15KeV, the angle between the injection direction and the substrate normal direction is 0 degree to 15 degrees, the injection dose is 5E15 to 5E16 / sccm, and the injection direction is perpendicular to the gate extension direction.

[0011] Optionally, the ion implantation includes: a first ion implantation and a second ion implantation, wherein the first ion implantation direction is perpendicular to the substrate, the angle between the second ion implantation direction and the substrate normal direction is 0 to 15 degrees, and the implantation direction is perpendicular to the gate extension direction.

[0012] Optionally, the process of etching the modified area includes a first dry etching and a second dry etching, and a rate of the second dry etching is lower than a rate of the first dry etching.

[0013] Optionally, the method for forming the semiconductor structure further comprises: etching the modified region so that the angle between the gate sidewall and the substrate is in the range of 85 degrees to 95 degrees, thereby forming a second modified region.

[0014] Optionally, the second modified zone is subjected to nitridation treatment.

[0015] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, comprising: a substrate; a gate layer covering a portion of the substrate; the sidewall of the gate layer has a modified region, and the bottom size of the modified region is larger than the top size.

[0016] Optionally, the material of the modified zone is an amorphous material.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0018] In the method for forming a semiconductor structure in the technical solution of the present invention, the side wall of the gate layer is modified, a modified area is formed on the side wall of the gate layer, the bottom size of the modified area is larger than the top size, and the modified area is etched. Through the modification treatment, the bottom of the modified area is in a loose state, and the loose area is easily removed in subsequent etching. After the modified area is removed or partially removed, the side wall of the gate layer is close to perpendicular to the substrate surface. In the fin field effect transistor process, the gate layer is a pseudo gate, which will eventually be replaced by a metal material, and the morphology of the gate layer determines the morphology of the final device gate structure. Through the technical solution of the present invention, the side wall of the gate layer is closer to perpendicular to the substrate surface. In the subsequent transistor process, the pseudo gate material with different electrical properties will not remain in the formed gate structure, and the side wall of the gate structure is close to perpendicular to the substrate, thereby improving the reliability of the performance of the semiconductor device.

[0019] Furthermore, ion implantation is performed on the sidewall of the gate layer. The implantation angle of the ion implantation is 0 to 15 degrees, the implantation angle is the angle between the implantation direction and the substrate normal direction, and the implantation direction is perpendicular to the gate extension direction. The small-angle ion implantation makes the modified area mainly concentrated at the bottom of the gate sidewall, while having little effect on the gate sidewall, while improving the perpendicularity between the gate sidewall and the substrate without affecting the performance of the semiconductor device.

[0020] Furthermore, the modified area is etched to make the gate sidewall nearly perpendicular to the substrate, and a second modified area is formed, and the second modified area is nitrided. The nitridation treatment forms a very thin dielectric layer on the surface of the gate sidewall, and the dielectric layer acts as a gate dielectric layer after the subsequent metal gate is formed, effectively improving the gate leakage current and the power consumption caused by it, so that the reliability of the semiconductor device is improved.

[0021] In the semiconductor structure of the technical solution of the present invention, the side wall of the gate layer has a second modified region, and the second modified region can effectively improve the gate leakage current and the power consumption caused by it, and improve the reliability of the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 to Figure 2 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0023] Figures 3 to 13 It is a cross-sectional schematic diagram of the semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] As described in the background art, the method for forming a FinFET structure in the prior art needs to be improved.

[0025] Figure 1 to Figure 2 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0026] Please refer to Figure 1 , a gate material layer 101 is formed on a substrate 100 , a hard mask layer 102 is deposited on the gate material layer, and a photoresist layer 103 is deposited on the hard mask layer.

[0027] Please refer to Figure 2 , the hard mask layer 102 is etched using the photoresist layer 103 as a mask to form a mask pattern; and the gate material layer 101 is etched using the hard mask pattern as a mask to form a gate layer 104 on the substrate 100 .

[0028] In the above method, the shape of the gate layer is determined by various factors, such as the control of the etching endpoint, the flatness of the substrate surface, the flatness of the sidewall of the mask pattern, etc. Usually, the gate layer 104 will form Figure 2The morphology shown in FIG. 1 is that the bottom of the gate 104 is larger than the top, and after etching, the material of the gate material layer 101 is likely to remain on the substrate surface, and a layer as shown in FIG. Figure 2 The footing A shown in the figure makes the dimension of the bottom of the gate in the extending direction perpendicular to the gate layer larger than the designed length value, resulting in the device operating slowly, and even failing to operate in severe cases.

[0029] The gate layer 104 is used as a dummy gate of the FinFET, and the gate layer 104 will eventually be replaced by a metal material to form a metal gate, and the morphology of the dummy gate ultimately determines the morphology of the metal gate. Since the corresponding area of ​​the foot A is not easily filled with metal material in the subsequent process, or the material of the foot A remains, it is easy to cause the reliability of the formed FinFET device to be poor.

[0030] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, forming a gate structure on the substrate, modifying the sidewall of the gate structure, forming a modified area on the sidewall of the gate structure, wherein the bottom size of the modified area is larger than the top size, and etching the modified area. The foot of the bottom of the pseudo gate of the fin field effect transistor is removed by the method, so that the sidewall of the pseudo gate is close to vertical to the substrate surface, and in the subsequent fin field effect transistor production process, it is easy to fill the metal material, thereby improving the reliability of the semiconductor device.

[0031] In order to make the above-mentioned objects, characteristics and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 3 to 13 It is a cross-sectional schematic diagram of the semiconductor structure forming process according to an embodiment of the present invention.

[0033] Please refer to Figure 3 , providing a substrate 200.

[0034] In this embodiment, the substrate 200 includes: a base 201, and a fin 202 located on the surface of the base. The substrate 200 also has an isolation structure (not shown) covering the fin 202, the top surface of the isolation structure is lower than the top surface of the fin 202, and covers part of the sidewall of the fin 202. The isolation structure is used to achieve electrical insulation between different semiconductor devices. In other embodiments, the substrate is a planar substrate.

[0035] The substrate 201 and the fin 202 are made of single crystal silicon. The isolation structure is made of silicon oxide.

[0036] In this embodiment, a gate layer is subsequently formed, and the gate layer covers a portion of the top surface and sidewall of the fin 202, and spans the fin 202, and is located on a portion of the top surface and a portion of the sidewall surface of the fin 202. Figures 4 to 5 .

[0037] Please refer to Figure 4 , forming a gate material layer 203 on the substrate 200; and forming a patterned layer 204 on a portion of the surface of the gate material layer.

[0038] The material of the gate material layer 203 includes polysilicon. In other embodiments, the initial gate material layer includes silicon nitride, silicon carbide, amorphous silicon, polysilicon or single crystal silicon.

[0039] The method for forming the patterned layer 204 includes: forming a hard mask layer on the surface of the gate material layer 203, forming a photoresist layer on a portion of the surface of the hard mask layer; etching the hard mask layer using the photoresist layer as a mask to form a patterned layer. The material of the patterned layer includes silicon oxide.

[0040] Please refer to Figure 5 , with the patterned layer 204 (such as Figure 4 ) is used as a mask, and the gate material layer 203 is etched until the surface of the substrate 200 is exposed, thereby forming the gate layer 205.

[0041] In other embodiments, the gate material layer can be formed not only on the top surface and sidewalls of the fin, but also on the planar substrate surface.

[0042] In this embodiment, the gate layer 205 is used as a dummy gate and is used to occupy a space position for a gate structure to be formed subsequently.

[0043] The material of the gate layer 205 is polysilicon. In other embodiments, the material of the gate layer includes silicon nitride or silicon carbide.

[0044] The width of the gate layer 205 is in the range of 7 nanometers to 14.5 nanometers. The width of the gate layer 205 refers to the dimension of the gate layer 205 along the length direction of the device channel.

[0045] The etching process includes a first dry etching and a second dry etching, wherein the rate of the second dry etching is lower than the rate of the first dry etching.

[0046] The parameters of the etching process include: the etching gas includes hydrogen bromide (HBr) and chlorine (Cl2), the power of the etcher is 100 W to 1000 W, the gas pressure in the etching chamber is 2 mTorr to 20 mTorr, the flow rate of hydrogen bromide is 10 sccm to 500 sccm, and the flow rate of chlorine is 10 sccm to 500 sccm; the power of the etcher and the flow rate of the hydrogen bromide or the chlorine are adjusted to reduce the etching speed of the second dry etching to half of the first dry etching.

[0047] The morphology of the gate layer 205 is limited by the photolithography process and the etching process. The side wall of the gate layer 205 is difficult to be perpendicular to the substrate surface, so that the bottom size of the gate layer is larger than the top size, and a foot B is formed at the bottom of the side wall of the gate layer 205. The foot B protrudes relative to the top of the side wall of the gate layer 205.

[0048] In this embodiment, the sidewall of the gate layer 205 is subsequently modified to form a modified area. After removing part of the modified area located at the foot B, the remaining modified area is further modified and retained, but does not affect the device performance.

[0049] Please refer to Figure 6 , the side wall of the gate layer 205 is modified to form a modified area 206 on the side wall of the gate layer 205, and the bottom size of the modified area 206 is larger than the top size.

[0050] In this embodiment, the modification treatment includes an amorphization treatment. The amorphous material lattice is disordered, so it is looser than the crystalline material, and is therefore easier to remove in the subsequent etching process. In other embodiments, the modification treatment is not limited to the amorphous treatment, and also includes making the material of the modified area form a material with a larger etching selectivity relative to the material of the gate layer 205. The modification method includes changing the physical properties of the modified area, such as forming a porous material; the modification method also includes changing the chemical properties of the material of the modified area, such as forming an oxide, a nitride or a carbide.

[0051] In this embodiment, the material of the modified area 206 is amorphous silicon.

[0052] The modified region 206 is located on the sidewall and bottom of the gate layer 205 . The top of the modified region 206 is lower than the sidewall of the gate layer 205 . The bottom size of the modified region depends on the size of the foot portion B of the sidewall of the gate layer 205 .

[0053] The modification method includes: performing ion implantation on the sidewall of the gate layer 205 .

[0054] In this embodiment, the parameters of the ion implantation process include: implantation energy of 5KeV to 15KeV, implantation angle of 0 to 15 degrees, implantation dose of 5E15 to 5E16 / sccm, the implantation angle is the angle between the implantation direction and the substrate normal direction, and the implantation direction is parallel to the gate extension direction. The gate extension direction refers to the length direction perpendicular to the device channel. Openings will be formed on both sides of the gate layer 205, and source and drain regions will be formed in the openings. The area between the source and drain regions is the device channel.

[0055] Since the ion implantation process inevitably implants the gate layer 205 side wall surface and the substrate 200 surface, during the N ion implantation process, a small amount of N ions are implanted into the gate layer 205 side wall surface and the substrate 200 surface, forming a stable Si-N bond interface between the gate layer 205 side wall surface and the substrate 200 surface, without causing significant interface damage, and forming a stable interface state between the gate side wall surface and the substrate silicon surface, thereby improving the reliability of the semiconductor device. In other embodiments, the ion materials include: N ions, B ions, BF 2+ One or more combinations of ions and C ions. The defects generated when the ion material collides with the silicon crystal lattice atoms are relatively small, so the impact on the device performance is relatively small.

[0056] In the ion implantation process, the energy of the ions is 5 KeV to 15 KeV. Since the energy of the ion implantation is very high, the crystal material is severely damaged and an amorphous structure is formed.

[0057] Since ion implantation has a great influence on material damage, a small angle ion implantation of 0 to 15 degrees is adopted. The small angle ion implantation makes most ion implantation range limited to the foot of the bottom of the gate side wall, and has little influence on other areas.

[0058] In this embodiment, the implanted ions include a first implanted ion 207 and a second implanted ion 208, the first implanted ion 207 is implanted at an angle of 0 degrees, and the second implanted ion 208 is implanted at an angle of 0 to 15 degrees. The implantation angle is the angle between the implantation direction and the substrate normal direction, and the implantation direction is parallel to the gate extension direction. In other embodiments, the second implanted ions are implanted at an angle of 3 degrees, 4 degrees, 5 degrees, or 6 degrees. In other embodiments, the implantation direction of the implanted ions can be one or more, and the angle of the implantation direction is 0 to 15 degrees. The angle refers to the angle between the implantation direction and the substrate normal direction, and the implantation direction is parallel to the gate extension direction. Ion implantation in multiple directions makes the modified area more amorphous.

[0059] The first implanted ions 207 are implanted at an angle of 0 degrees because the ions are vertically implanted into the foot B region and are prevented from being implanted into the sidewall surface of the gate layer 205 .

[0060] The second implanted ions 208 are implanted at an angle of 0 to 15 degrees because: the foot B has a certain thickness in a direction perpendicular to the substrate, and the angle of 0 to 15 degrees has a very small inclination, which makes the material of the foot B more fully amorphous in the vertical direction.

[0061] In other embodiments, the modification process further includes: performing annealing on the device after ion implantation on the sidewall of the gate layer 205. The annealing process is mainly used to repair the damage to the sidewall of the gate layer 205 and the surface of the substrate 200 caused by ion implantation.

[0062] The annealing process includes: a post nitridation annealing process (Post Nitridation Anneal, PNA) and an in-situ steam generation process (In-Situ Steam Generation, ISSG). The post nitridation annealing process is used to repair the lattice damage caused by ion implantation and form a stable Si-N bond interface between the gate layer sidewall and the substrate surface. The in-situ steam generation process is used to oxidize the gate layer and the substrate to repair the damage caused to the gate layer and the substrate during ion implantation.

[0063] Please refer to Figure 7 , etching the modified area 206 to form a second modified area 209; and performing nitridation treatment on the second modified area 209.

[0064] The process of etching the modified area 206 is a dry etching process. Dry etching can achieve anisotropic etching, so that the foot B (such as Figure 6 As shown in the figure, the gate sidewall is etched away with little impact.

[0065] In this embodiment, the method for etching the modified area 206 includes: detecting the foot B to obtain foot information (such as position and size information); etching the foot B according to the foot information until the foot is completely etched and removed.

[0066] In another embodiment, the foot B is etched away by controlling the etching time and etching rate of the foot B.

[0067] The second modified region 209 is located on the sidewall of the gate layer 205 , and a surface thereof is perpendicular to the substrate 200 .

[0068] The nitridation process includes an in-situ steam generation process (ISSG). The nitridation process further modifies the second modified region 209 into a dielectric material. After the subsequent device metal gate is formed, the second modified region 209 effectively improves the gate leakage current and the power consumption caused by it, thereby improving the reliability of the semiconductor device performance.

[0069] In this embodiment, the modified region 206 is etched to form a second modified region 207, that is, part of the modified region is retained. In other embodiments, the modified region 206 is completely etched away.

[0070] Please refer to Figure 8 , forming a sidewall spacer 210 on the sidewall surface of the gate layer 205 .

[0071] The sidewall spacer 210 is used to define the position of the subsequent source and drain regions. In this embodiment, the material of the sidewall spacer 210 is silicon oxide and silicon nitride. In other embodiments, the sidewall spacer includes one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0072] The method for forming the sidewall 210 includes: depositing a sidewall material on the substrate 200 , the sidewall of the gate layer 205 and the surface of the gate layer 205 , etching to expose the surface of the gate 203 layer and the surface of the substrate 200 , and forming the sidewall 210 on the sidewall of the gate layer 205 .

[0073] Please refer to Fig. 9 , openings 211 are formed in the substrate on both sides of the gate layer 205 and the spacer 210 .

[0074] The process of forming the opening 211 includes: using the sidewall 210 as a mask, etching the substrate 200 to form the opening 211 .

[0075] The etching process is one or both of a dry etching process and a wet etching process.

[0076] Please refer to Fig.10 , at the opening 211 (such as Fig. 9 As shown in the figure, source and drain regions 212 are formed therein.

[0077] The source and drain regions 212 are formed by an epitaxial growth process.

[0078] The source and drain regions 212 have doping ions therein, and the type of the doping ions and the material of the source and drain regions 212 are related to the transistor type. In this embodiment, the material of the source and drain regions 212 includes silicon carbide or silicon phosphide, and the doping ions are N-type ions. In other embodiments, the material of the source and drain regions includes silicon germanium, and the source and drain regions have doping ions therein, and the doping ions are P-type ions.

[0079] Please refer to Fig.11 An interlayer dielectric layer 213 is formed on the surfaces of the substrate 200 , the source and drain regions 212 , and the sidewalls 210 .

[0080] The interlayer dielectric layer 213 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce parasitic capacitance between metal and substrate, and improve the formation of parasitic field effect transistors when metal crosses different regions.

[0081] The material of the interlayer dielectric layer 213 includes silicon oxide.

[0082] The method for forming the interlayer dielectric layer 213 includes: using a chemical vapor deposition process to form a dielectric material layer on the surface of the substrate 200, the surface of the source and drain regions 212, and the surface of the gate layer 205; and using a chemical mechanical polishing process to flatten the dielectric material layer until the top surface of the gate layer 205 is exposed.

[0083] In this embodiment, before forming the interlayer dielectric layer 213, a contact etch stop layer 214 is further formed on the surface of the source / drain region 212 and the sidewall, and the contact etch stop layer 214 is located between the source / drain region 212 and the sidewall, and the interlayer dielectric layer 213. The material of the contact etch stop layer is silicon oxide. The formation process of the contact etch stop layer is a deposition process. In other embodiments, the material of the contact etch stop layer includes silicon nitride.

[0084] Please refer to Fig.12 , remove the gate layer 205 and form a trench 215 in the interlayer dielectric layer 213.

[0085] In this embodiment, the silicon substrate 200 is exposed at the bottom of the trench 215, and the second modified region 209 is exposed at the sidewall. The trench 215 will be filled with metal material later to form a real gate of the device.

[0086] The process of removing the gate layer 205 includes: dry etching and wet etching or a combination of the two.

[0087] In this embodiment, the process of removing the gate layer 205 is a wet etching process.

[0088] The solution used in the wet etching process includes tetramethylammonium hydroxide or potassium hydroxide solution, so that during the etching process of removing the gate layer 205 , the gate layer 205 can have a larger etching selectivity ratio relative to the second modified region 209 and the substrate 200 .

[0089] Please refer to Fig.13 In the groove 215 (such as Fig.12 A gate structure 214 is formed therein.

[0090] Since the gate layer 205 (such as Figure 6 The foot B of the groove 215 is removed, and the angle between the sidewall of the groove 215 and the bottom of the groove 215 is in the range of 85 degrees to 95 degrees, which is significantly larger than the angle before the foot B is removed, so it is easier to fill the groove 215 with material to form the gate structure 214. The gate structure 214 is the real gate of the device.

[0091] The gate structure 214 includes a gate dielectric layer 216 located on the surface of the trench 215 and a gate electrode layer 217 located on the gate dielectric layer 216 .

[0092] The gate dielectric layer 216 is formed by an atomic layer deposition process.

[0093] The material of the gate dielectric layer 216 includes a high-K dielectric material. The high-K (i.e., dielectric constant K≧3.9) dielectric layer can significantly reduce the quantum tunneling effect of the gate dielectric layer, thereby effectively improving the gate leakage current and the power consumption caused by it. In this embodiment, the high-K dielectric material is hafnium oxide. In other embodiments, the material of the gate dielectric layer also includes a silicon nitride layer, and the silicon nitride layer formation process includes an in-situ water vapor generation process. The silicon nitride layer is between the high-K dielectric layer and the groove surface, and the purpose is to improve the interface state between the high-K dielectric material and the substrate silicon.

[0094] The gate electrode layer 217 is made of metal.

[0095] The gate electrode layer 217 is formed by an atomic layer deposition process, which has a good step coverage, so that the trench 215 is well filled.

[0096] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Figure 6 , comprising: a substrate 200; a gate layer 205 located on a portion of the substrate, wherein the sidewall surface of the gate layer 205 has a modified area 206, and the bottom size of the modified area is larger than the top size.

[0097] In this embodiment, the material of the gate layer 205 is polysilicon; the material of the modified region 206 is an amorphous material, such as amorphous silicon.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a base; forming a gate layer on a portion of the substrate; The side wall of the gate layer is modified to form a modified area on the side wall of the gate layer, wherein the bottom size of the modified area is larger than the top size, and the modification method comprises: ion implantation of the side wall of the gate layer, wherein in the ion implantation process, the implanted ions comprise first implanted ions and second implanted ions, wherein the first implanted ions comprise N ions, the implantation direction of the first implanted ions is perpendicular to the substrate, the angle between the implantation direction of the second implanted ions and the normal direction of the substrate is 0 to 15 degrees, and the implantation direction is perpendicular to the extension direction of the gate; The modified area is etched.

2. The method for forming a semiconductor structure according to claim 1, wherein: In a direction perpendicular to the extension of the gate layer, a bottom dimension of a cross-sectional graph of the gate layer is larger than a top dimension.

3. The method for forming a semiconductor structure according to claim 1, wherein: The modification method includes an amorphization treatment.

4. The method for forming a semiconductor structure according to claim 1, wherein: The modification method further comprises: performing annealing after the ion implantation.

5. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the ion implantation process include: the second implanted ions include N ions, B ions, BF 2+ One or more combinations of ions and C ions, the implantation energy is 5KeV to 15KeV, the implantation dose is 5E15 to 5E16 / sccm, and the implantation direction is perpendicular to the gate extension direction.

6. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the modified area includes a first dry etching and a second dry etching, wherein the rate of the second dry etching is lower than the rate of the first dry etching.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: The modified area is etched so that the angle between the gate sidewall and the substrate is in the range of 85 degrees to 95 degrees, thereby forming a second modified area.

8. The method for forming a semiconductor structure according to claim 7, wherein: The second modified area is subjected to nitriding treatment.

9. A semiconductor structure, characterized in that: include: substrate; A gate layer covering a portion of the substrate; The sidewall of the gate layer has a modified area, the bottom size of the modified area is larger than the top size, the modified area has a bottom adjacent to the substrate and a side adjacent to the gate layer, and the modification degree of the bottom is greater than that of the side.

10. The semiconductor structure according to claim 9, wherein: The material of the modified zone is an amorphous material.

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