Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The structure includes: a substrate having a first dielectric layer formed thereon; a metal connection structure extending through the first dielectric layer, with the top surface of the metal connection structure being higher than the top surface of the first dielectric layer, and the width of the top of the metal connection structure being greater than the width of the bottom of the metal connection structure; a barrier layer located on the surface of the first dielectric layer, with the top surface of the barrier layer being coplanar with the top surface of the metal connection structure; a second dielectric layer located on the surface of the barrier layer and the surface of the metal connection structure; and an interlayer connection structure extending through the second dielectric layer and electrically connecting the metal connection structure. This structure can prevent excessive etching during the formation of the interlayer connection structure, which could affect subsequent formation of the interlayer connection structure; and can also increase the core size of the interlayer connection structure, improving its filling quality.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Metal interconnects and vias are the primary structures in semiconductor structures that enable electrical connections within a chip and between chips. Vias are primarily used for vertical conduction within a chip and between chips.

[0003] However, as semiconductor core sizes shrink, the size of metal interconnects and vias has also shrunk significantly, posing significant challenges to the via manufacturing process. Current via manufacturing processes still have drawbacks, leading to the need for more reliable and efficient technical solutions. Summary of the Invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can improve the filling quality of an interlayer connection structure.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate having a first dielectric layer formed thereon; forming a metal connection structure in the first dielectric layer that penetrates the first dielectric layer, wherein the width of the top of the metal connection structure is greater than the width of the bottom of the metal connection structure; etching back the first dielectric layer so that the top surface of the first dielectric layer is lower than the top surface of the metal connection structure; forming a barrier layer on the surface of the first dielectric layer, wherein the top surface of the barrier layer is coplanar with the top surface of the metal connection structure; forming a second dielectric layer on the surface of the barrier layer and the surface of the metal connection structure; and forming an interlayer connection structure in the second dielectric layer that penetrates the second dielectric layer and is electrically connected to the metal connection structure.

[0006] In some embodiments of the present application, the method for forming the metal connection structure includes: forming a first trench penetrating the first dielectric layer in the first dielectric layer; etching back the first trench so that the width of the top of the first trench is greater than the width of the bottom of the first trench; and forming the metal connection structure in the first trench.

[0007] In some embodiments of the present application, the method for forming the barrier layer includes: forming a barrier material layer on the surface of the first dielectric layer and the surface of the metal connection structure; and using a chemical mechanical polishing process to polish the barrier material layer until the metal connection structure is exposed to form the barrier layer.

[0008] In some embodiments of the present application, the thickness of the barrier layer is 50 angstroms to 300 angstroms.

[0009] In some embodiments of the present application, the material of the barrier layer includes silicon nitride.

[0010] In some embodiments of the present application, the second dielectric layer includes a buffer layer located on the surface of the first dielectric layer and the surface of the metal connection structure, and a dielectric layer located on the surface of the buffer layer.

[0011] Another aspect of the present application also provides a semiconductor structure, comprising: a substrate, on which a first dielectric layer is formed; a metal connection structure, which penetrates the first dielectric layer and the top surface of the metal connection structure is higher than the top surface of the first dielectric layer, and the width of the top of the metal connection structure is greater than the width of the bottom of the metal connection structure; a barrier layer, which is located on the surface of the first dielectric layer, and the top surface of the barrier layer is coplanar with the top surface of the metal connection structure; a second dielectric layer, which is located on the surface of the barrier layer and the surface of the metal connection structure; and an interlayer connection structure, which penetrates the second dielectric layer and is electrically connected to the metal connection structure.

[0012] In some embodiments of the present application, the thickness of the barrier layer is 50 angstroms to 300 angstroms.

[0013] In some embodiments of the present application, the material of the barrier layer includes silicon nitride.

[0014] In some embodiments of the present application, the second dielectric layer includes a buffer layer located on a surface of the first dielectric layer and a surface of the first connection structure, and a dielectric layer located on a surface of the buffer layer.

[0015] The semiconductor structure and its formation method described in the present application are characterized in that the width of the top of the metal connection structure is greater than the width of the bottom of the metal connection structure. On the one hand, this can avoid excessive etching when forming the interlayer connection structure, affecting the subsequent formation of the interlayer connection structure; on the other hand, it can increase the core size of the interlayer connection structure and improve its filling quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following figures describe in detail exemplary embodiments disclosed in this application. Identical reference numerals denote similar structures in several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the same inventive intent as described in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0017] Figure 1 Schematic diagrams of some defective semiconductor structures;

[0018] Figure 2 Schematic diagrams of other defective semiconductor structures;

[0019] Figures 3 to 12Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0021] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0022] Current through-hole processes still have flaws, resulting in low fill quality in interlayer connection structures. The main issues include the following two.

[0023] Figure 1 Schematic diagrams of some defective semiconductor structures. Figure 1 The semiconductor structure includes: a substrate 100, a first dielectric layer 110 is formed on the surface of the substrate 100; a metal connection structure 120, which penetrates the first dielectric layer 110; a second dielectric layer 130, which is located on the surface of the first dielectric layer 110; and an interlayer connection structure 140, which penetrates the second dielectric layer 130.

[0024] refer to Figure 1 As the core size of the semiconductor structure decreases, the core size (horizontal size) of the interlayer connection structure 140 also decreases. This may result in the interlayer connection structure 140 not being properly filled, leaving gaps 150 unfilled. This can affect the function of the interlayer connection structure 140 and reduce the yield of the semiconductor structure.

[0025] Figure 2 Schematic diagrams of other defective semiconductor structures. Figure 2 The semiconductor structure includes: a substrate 200, a first dielectric layer 210 is formed on the surface of the substrate 200; a metal connection structure 220, which penetrates the first dielectric layer 210; a second dielectric layer 230, which is located on the surface of the first dielectric layer 210; and an interlayer connection structure 240, which penetrates the second dielectric layer 230.

[0026] refer to Figure 2 In some semiconductor structures, in order to solve Figure 1To solve the problem shown, the core size of the interlayer connection structure 240 is appropriately increased. However, this results in the formation of sharp-angled gaps 250 along the sidewalls of the top of the metal connection structure 220 when the second dielectric layer 230 is etched before forming the interlayer connection structure 240. The sharp-angled gaps 250 are small in size and have a unique shape. Residual organic matter such as etching solution remaining in the sharp-angled gaps 250 is difficult to completely remove. Such residual organic matter affects the subsequent deposition process for forming the interlayer connection structure 240, resulting in poor filling quality of the interlayer connection structure 250.

[0027] Currently, whether simply increasing or decreasing the size of the interlayer connection structure, one of the above-mentioned two problems may occur, and there is no solution that can address both problems. To address the above-mentioned problems, the present application provides a semiconductor structure and a method for forming the same. When forming a metal connection structure, the width of the top of the metal connection structure is made greater than the width of the bottom of the metal connection structure. On the one hand, this can avoid excessive etching during the formation of the interlayer connection structure to form sharp corners and gaps, which would affect the subsequent formation of the interlayer connection structure; on the other hand, it can increase the core size of the interlayer connection structure and improve its filling quality.

[0028] Figures 3 to 12 The following is a structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0029] The embodiment of the present application provides a method for forming a semiconductor structure, comprising: referring to Figure 3 , providing a substrate 300, on which a first dielectric layer 310 is formed; referring to Figures 4 to 6 , a metal connection structure 320 is formed in the first dielectric layer 310 and penetrates the first dielectric layer 310, and the width of the top of the metal connection structure 320 is greater than the width of the bottom of the metal connection structure 320; Figure 7 , etching back the first dielectric layer 310 so that the top surface of the first dielectric layer 310 is lower than the top surface of the metal connection structure 320; Figure 8 , forming a barrier layer 330 on the surface of the first dielectric layer 310, wherein the top surface of the barrier layer 330 is coplanar with the top surface of the metal connection structure 320; Figure 9 , forming a second dielectric layer 340 on the surface of the barrier layer 330 and the surface of the metal connection structure 320; Figures 10 to 12 An interlayer connection structure 350 is formed in the second dielectric layer 340 , penetrating the second dielectric layer 340 and electrically connecting the metal connection structure 320 .

[0030] In the method for forming a semiconductor structure described in an embodiment of the present application, the width of the top of the metal connection structure 320 is greater than the width of the bottom of the metal connection structure 320. On the one hand, this can avoid excessive etching when forming the interlayer connection structure 350, which affects the subsequent formation of the interlayer connection structure 350; on the other hand, it can increase the core size of the interlayer connection structure 350 and improve its filling quality.

[0031] refer to Figure 3 , providing a substrate 300 , on which a first dielectric layer 310 is formed.

[0032] In some embodiments of the present application, the substrate 300 may be a semiconductor substrate, and the material of the semiconductor substrate may include (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0033] In some other embodiments of the present application, the substrate 300 may include but is not limited to a semiconductor substrate and corresponding active devices formed on the semiconductor substrate (such as a source and a drain located in the substrate).

[0034] In some embodiments of the present application, the material of the first dielectric layer 310 includes silicon oxide, etc. The first dielectric layer 310 is formed by a chemical vapor deposition process or a physical vapor deposition process, etc.

[0035] refer to Figures 4 to 6 A metal connection structure 320 is formed in the first dielectric layer 310 and penetrates the first dielectric layer 310. The width of the top of the metal connection structure 320 is greater than the width of the bottom of the metal connection structure 320. The width of the top of the metal connection structure 320 is greater than the width of the bottom of the metal connection structure 320. This can prevent excessive etching during the formation of the interlayer connection structure, which would affect the subsequent formation of the interlayer connection structure. It can also increase the core size of the interlayer connection structure and improve its filling quality.

[0036] refer to Figure 4 , a first trench 311 penetrating the first dielectric layer 310 is formed in the first dielectric layer 310 .

[0037] In some embodiments of the present application, the method for forming the first groove 311 includes: forming a patterned photoresist on the surface of the first dielectric layer 310, wherein the patterned photoresist defines the position of the first groove 311; etching the first dielectric layer 310 using the patterned photoresist as a mask to form the first groove 311; and removing the patterned photoresist.

[0038] refer to Figure 5 , the first trench 311 is etched back so that the width of the top of the first trench 311 is greater than the width of the bottom of the first trench 311 .

[0039] In some embodiments of the present application, etching back the first trench 311 does not increase the core size of the first trench 311 , but only increases the width of the top of the first trench 311 .

[0040] In some embodiments of the present application, the etching solution for etching back the first trench 311 includes SiCoNi.

[0041] In some embodiments of the present application, the top of the first groove 311 is as follows Figure 5 In other embodiments of the present application, the first groove 311 may also be in any other suitable shape (eg, a T-shape, etc.), as long as the width of the top of the first groove 311 is greater than the width of the bottom of the first groove 311 .

[0042] refer to Figure 6 The metal connection structure 320 is formed in the first trench 311. The metal connection structure 320 can electrically connect active devices (not shown in the figure) such as source and drain in the substrate 300.

[0043] In some embodiments of the present application, the method for forming the metal connection structure 320 includes: forming a metal layer on the surface of the first groove 311 and the first dielectric layer 310; using a chemical mechanical polishing process to polish the metal layer so that the top surface of the metal layer is coplanar with the top surface of the first dielectric layer to form the metal connection structure 320 located in the first groove 311.

[0044] In some embodiments of the present application, the material of the metal connection structure 320 includes copper or aluminum.

[0045] refer to Figure 7 The first dielectric layer 310 is etched back so that the top surface of the first dielectric layer 310 is lower than the top surface of the metal connection structure 320. A portion of the sidewalls of the metal connection structure 320 is exposed, and a barrier layer is formed on the sidewalls and the first dielectric layer 310. The barrier layer and the top of the metal connection structure 320 can better protect the first dielectric layer 310 from excessive etching.

[0046] refer to Figure 8A barrier layer 330 is formed on the surface of the first dielectric layer 310. The top surface of the barrier layer 330 is coplanar with the top surface of the metal connection structure 320. The barrier layer 330 and the top of the metal connection structure 320 can jointly protect the first dielectric layer 310 from being excessively etched in subsequent processes, thereby preventing the formation of Figure 2 The sharp-angled gap shown improves the filling quality of the subsequently formed interlayer connection structure.

[0047] Since the first dielectric layer 310 is etched back first and then the barrier layer 330 is formed, the barrier layer 330 fills the position of the etched back first dielectric layer, and the overall size of the semiconductor structure does not change, and does not affect other subsequent process steps.

[0048] In some embodiments of the present application, the method for forming the barrier layer 330 includes: forming a barrier material layer on the surface of the first dielectric layer 310 and the surface of the metal connection structure 320; and using a chemical mechanical polishing process to polish the barrier material layer until the metal connection structure 320 is exposed to form the barrier layer 330.

[0049] In some embodiments of the present application, the barrier layer 330 has a thickness of 50 angstroms to 300 angstroms. The barrier layer 330 should not be too thin, otherwise it will not fully protect the first dielectric layer 310 from being etched; nor should it be too thick, otherwise it will increase material waste in the relevant process.

[0050] In some embodiments of the present application, the material of the barrier layer 330 includes silicon nitride. The barrier layer 220 can serve as an etch barrier during the subsequent etching of the second dielectric layer, preventing the first dielectric layer 310 from being etched. Therefore, the barrier layer 330 can also be made of other suitable insulating materials, as long as the barrier layer 330 can protect the first dielectric layer 310.

[0051] refer to Figure 9 A second dielectric layer 340 is formed on the surface of the barrier layer 330 and the surface of the metal connection structure 320 .

[0052] In some embodiments of the present application, the second dielectric layer 340 includes a buffer layer 341 located on the surface of the first dielectric layer 310 and the surface of the metal connection structure 320, and a dielectric layer 342 located on the surface of the buffer layer 341. The buffer layer 341 can prevent excessive etching and damage to the metal connection structure 320 when etching the second dielectric layer 340, and further protect the first dielectric layer 310 from being etched.

[0053] In some embodiments of the present application, the material of the buffer layer 341 includes NDC, etc. In some embodiments of the present application, the material of the dielectric layer 342 includes silicon oxide, etc.

[0054] In some embodiments of the present application, a method for forming the second dielectric layer 340 includes a chemical vapor deposition process or a physical vapor deposition process.

[0055] refer to Figures 10 to 12 An interlayer connection structure 350 is formed in the second dielectric layer 340, penetrating the second dielectric layer 340 and electrically connecting the metal connection structure 320. Since the top width of the metal connection structure 320 is relatively large, the contact area between the interlayer connection structure 350 and the metal connection structure 320 is increased, and the width of the interlayer connection structure 350 can also be increased, thereby improving the filling quality of the interlayer connection structure 350.

[0056] refer to Figure 10 , a second trench 351 is formed in the dielectric layer 342, penetrating the dielectric layer 342. The buffer layer 341 can serve as a stop layer for etching the dielectric layer 342, preventing excessive etching from damaging the metal connection structure 320. Without the buffer layer 341, the dielectric layer 342 is thick, and the etching amount is large, which can easily cause excessive etching and damage to the metal connection structure 320.

[0057] refer to Figure 11 , continue etching the second trench 351 until the metal connection structure 320 is exposed. Since the thickness of the buffer layer 341 is relatively small, the etching amount is also small, so the etching amount is easy to control and the metal connection structure 320 will not be damaged by excessive etching. In addition, due to the blocking effect of the barrier layer 330 and the top of the metal connection structure 320, the first dielectric layer 310 will not be etched. Figure 2 The sharp-angled gaps shown affect the filling quality of the subsequent interlayer connection structure 350 .

[0058] refer to Figure 12 , an interlayer connection structure 350 is formed in the second trench 351 .

[0059] In some embodiments of the present application, a method for forming the interlayer connection structure 350 includes a chemical vapor deposition process or a physical vapor deposition process.

[0060] In some embodiments of the present application, the material of the interlayer connection structure 350 includes copper or aluminum.

[0061] In the method for forming a semiconductor structure described in the present application, the width of the top 320 of the metal connection structure is greater than the width of the bottom of the metal connection structure 320. On the one hand, this can avoid excessive etching when forming the interlayer connection structure 350, which affects the subsequent formation of the interlayer connection structure 350; on the other hand, it can increase the core size of the interlayer connection structure 350 and improve its filling quality.

[0062] The embodiment of the present application further provides a semiconductor structure, referring to Figure 12 The semiconductor structure includes: a substrate 300, on which a first dielectric layer 310 is formed; a metal connection structure 320, which penetrates the first dielectric layer 310 and has a top surface higher than the top surface of the first dielectric layer 310, and a width of the top of the metal connection structure 320 is greater than a width of the bottom of the metal connection structure 320; a barrier layer 330, which is located on the surface of the first dielectric layer 310, and the top surface of the barrier layer 330 is coplanar with the top surface of the metal connection structure 320; a second dielectric layer 340, which is located on the surfaces of the barrier layer 330 and the metal connection structure 320; and an interlayer connection structure 350, which penetrates the second dielectric layer 340 and is electrically connected to the metal connection structure 320.

[0063] In some embodiments of the present application, the substrate 300 may be a semiconductor substrate, and the material of the semiconductor substrate may include (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0064] In some other embodiments of the present application, the substrate 300 may include but is not limited to a semiconductor substrate and corresponding active devices formed on the semiconductor substrate (such as a source and a drain located in the substrate).

[0065] In some embodiments of the present application, the material of the first dielectric layer 310 includes silicon oxide or the like.

[0066] refer to Figure 12 The width of the top of the metal connection structure 320 is greater than the width of the bottom of the metal connection structure 320. On the one hand, it can avoid excessive etching when forming the interlayer connection structure 350, affecting the subsequent formation of the interlayer connection structure 350; on the other hand, it can increase the core size of the interlayer connection structure 350 and improve its filling quality.

[0067] In some embodiments of the present application, the metal connection structure 320 can electrically connect active devices such as a source and a drain in the substrate 300 (not shown in the figure).

[0068] In some embodiments of the present application, the top of the metal connection structure 320 is as follows: Figure 12 In other embodiments of the present application, the metal connection structure 320 may also be in any other suitable shape (such as a T-shape), as long as the width of the top of the metal connection structure 320 is greater than the width of the bottom of the first trench 311 .

[0069] In some embodiments of the present application, the material of the metal connection structure 320 includes copper or aluminum.

[0070] Continue to refer Figure 12 A barrier layer 330 is formed on the surface of the first dielectric layer 310. The top surface of the barrier layer 330 is coplanar with the top surface of the metal connection structure 320. The barrier layer 330 and the top of the metal connection structure 320 can jointly protect the first dielectric layer 310 from being excessively etched in subsequent processes, thereby preventing the formation of Figure 2 The sharp-angled gap shown improves the filling quality of the subsequently formed interlayer connection structure.

[0071] In some embodiments of the present application, the barrier layer 330 has a thickness of 50 angstroms to 300 angstroms. The barrier layer 330 should not be too thin, otherwise it will not fully protect the first dielectric layer 310 from being etched; nor should it be too thick, otherwise it will increase material waste in the relevant process.

[0072] In some embodiments of the present application, the material of the barrier layer 330 includes silicon nitride. The barrier layer 220 can serve as an etch barrier during the subsequent etching of the second dielectric layer, preventing the first dielectric layer 310 from being etched. Therefore, the barrier layer 330 can also be made of other suitable insulating materials, as long as the barrier layer 330 can protect the first dielectric layer 310.

[0073] Continue to refer Figure 12 A second dielectric layer 340 is formed on the surface of the barrier layer 330 and the surface of the metal connection structure 320 .

[0074] In some embodiments of the present application, the second dielectric layer 340 includes a buffer layer 341 located on the surface of the first dielectric layer 310 and the surface of the metal connection structure 320, and a dielectric layer 342 located on the surface of the buffer layer 341. The buffer layer 341 can prevent excessive etching and damage to the metal connection structure 320 when etching the second dielectric layer 340, and further protect the first dielectric layer 310 from being etched.

[0075] In some embodiments of the present application, the material of the buffer layer 341 includes NDC, etc. In some embodiments of the present application, the material of the dielectric layer 342 includes silicon oxide, etc.

[0076] Continue to refer Figure 12 An interlayer connection structure 350 is formed in the second dielectric layer 340, penetrating the second dielectric layer 340 and electrically connecting the metal connection structure 320. Since the top width of the metal connection structure 320 is relatively large, the width of the interlayer connection structure 350 can also be increased, thereby improving the filling quality of the interlayer connection structure 350.

[0077] In some embodiments of the present application, the material of the interlayer connection structure 350 includes copper or aluminum.

[0078] In the semiconductor structure described in the present application, the width of the top 320 of the metal connection structure is greater than the width of the bottom of the metal connection structure 320. On the one hand, this can avoid excessive etching when forming the interlayer connection structure 350, affecting the subsequent formation of the interlayer connection structure 350; on the other hand, it can increase the core size of the interlayer connection structure 350 and improve its filling quality.

[0079] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0080] It should be understood that the term "and / or" used in this embodiment includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present.

[0081] Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means there are no intervening elements.

[0082] It should also be understood that the terms “comprise,” “comprising,” “include,” or “including,” when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0083] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0084] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a first dielectric layer is formed; A metal connection structure is formed in the first dielectric layer and penetrates the first dielectric layer, wherein the width of the top of the metal connection structure is greater than the width of the bottom of the metal connection structure. The method for forming the metal connection structure comprises: forming a first trench in the first dielectric layer and penetrates the first dielectric layer; etching back the first trench so that the width of the top of the first trench is greater than the width of the bottom of the first trench; and forming the metal connection structure in the first trench; Etching back the first dielectric layer so that a top surface of the first dielectric layer is lower than a top surface of the metal connection structure; A barrier layer is formed on the surface of the first dielectric layer, wherein the top surface of the barrier layer is coplanar with the top surface of the metal connection structure. The method for forming the barrier layer comprises: forming a barrier material layer on the surface of the first dielectric layer and the surface of the metal connection structure; polishing the barrier material layer using a chemical mechanical polishing process until the metal connection structure is exposed to form the barrier layer; forming a second dielectric layer on the surface of the barrier layer and the surface of the metal connection structure; An interlayer connection structure is formed in the second dielectric layer, penetrating the second dielectric layer and electrically connected to the metal connection structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The barrier layer has a thickness of 50 angstroms to 300 angstroms.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer includes silicon nitride.

4. The method for forming a semiconductor structure according to claim 1, wherein: The second dielectric layer includes a buffer layer located on the surface of the first dielectric layer and the surface of the metal connection structure, and a dielectric layer located on the surface of the buffer layer.

5. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 4, characterized in that: include: a substrate having a first dielectric layer formed thereon; a metal connection structure, penetrating the first dielectric layer, with a top surface of the metal connection structure higher than a top surface of the first dielectric layer, and a width of a top of the metal connection structure greater than a width of a bottom of the metal connection structure; a barrier layer, located on a surface of the first dielectric layer, wherein a top surface of the barrier layer is coplanar with a top surface of the metal connection structure; a second dielectric layer, located on the surface of the barrier layer and the surface of the metal connection structure; An interlayer connection structure penetrates the second dielectric layer and is electrically connected to the metal connection structure.

6. The semiconductor structure according to claim 5, wherein: The barrier layer has a thickness of 50 angstroms to 300 angstroms.

7. The semiconductor structure according to claim 5, wherein: The material of the barrier layer includes silicon nitride.

8. The semiconductor structure according to claim 5, wherein: The second dielectric layer includes a buffer layer located on the surface of the first dielectric layer and the surface of the metal connection structure, and a dielectric layer located on the surface of the buffer layer.

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