Metal hard mask for reducing line bending

Abstract

The present disclosure relates to metal hard masks for reducing line bending. One method includes forming a hard mask layer comprising a metal over a dielectric layer, where the hard mask layer comprising a metal has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa; patterning the hard mask layer comprising a metal to form an opening in the hard mask layer comprising a metal; and etching the dielectric layer using the hard mask layer comprising a metal as an etch mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The hard mask layer comprising a metal is then removed.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a hard metal mask for reducing line bending. Background Technology

[0002] Metal lines and vias are used to interconnect integrated circuits such as transistors to form functional circuits. As device dimensions shrink, metal lines and vias also become smaller. The formation of a metal line may include: forming a hard mask layer on top of a dielectric layer in which the metal line is formed; using the hard mask layer as an etching mask to pattern the dielectric layer to form trenches; and filling the trenches with metal to form the metal line.

[0003] As linewidth and spacing between metal lines decrease, some sections of the dielectric layer between trenches become narrower and may deform. This deformation causes problems in the gap-filling process of filling trenches with metal. Line breaking may occur when some sections of the trench are not filled with metal. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa; patterning the metal-containing hard mask layer to form a first opening in the metal-containing hard mask layer; using the metal-containing hard mask layer as an etch mask to etch the dielectric layer, wherein the first opening extends into the dielectric layer; filling the first opening with a conductive material to form a conductive feature; and removing the metal-containing hard mask layer.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: depositing a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a tensile stress greater than about 600 MPa; forming a plurality of mandrels over the metal-containing hard mask layer; forming a plurality of spacers on the sidewalls of the plurality of mandrels; etching the metal-containing hard mask layer to form a first trench in the metal-containing hard mask layer, wherein the first trench overlaps with a first space between two of the plurality of spacers; etching one of the mandrels of the plurality of mandrels to leave a second space; etching the metal-containing hard mask layer to form a second trench in the metal-containing hard mask layer, wherein the second trench overlaps with the second space; and etching the dielectric layer to extend the first trench and the second trench into the dielectric layer.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: depositing a low-k dielectric layer; depositing a first mask layer over the low-k dielectric layer; depositing a tungsten-containing hard mask layer over the first mask layer; depositing a second mask layer over the tungsten-containing hard mask layer; forming a patterned photoresist over the second mask layer; using the patterned photoresist to etch the second mask layer and the tungsten-containing hard mask layer such that a trench is formed in the tungsten-containing hard mask layer, wherein a top surface of the first mask layer is located below the trench and exposed to the trench; and transferring the trench in the tungsten-containing hard mask layer into the low-k dielectric layer. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1 to 2 , Figure 3A , Figure 3B , Figures 4 to 5 , Figure 6A , Figure 6B , Figures 7 to 8 , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figures 13 to 14 , Figure 15A , Figure 15B , Figure 16 Cross-sectional and top views are shown at intermediate stages in the formation of an interconnect structure including metal wires and vias according to some embodiments.

[0009] Figure 17 The figure illustrates a graph showing the tensile stress in a metal hard mask layer as a function of plasma power according to some embodiments.

[0010] Figure 18 A process flow for forming an interconnect structure according to some embodiments is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used in this document to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). Besides the orientation shown in the figure, spatially related terms are also intended to cover different orientations of the device being used or operated. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially related descriptors used herein may be interpreted accordingly.

[0013] An interconnect structure including metal lines and vias and a method for forming the same are provided. According to some embodiments of this disclosure, a hard metal mask layer is formed over a dielectric layer. The hard metal mask layer is formed from a selected material using selected process conditions, such that the hard metal mask layer has a high Young's modulus and high tensile stress. When used to form trenches, the hard metal mask layer can reduce deformation of the remaining dielectric layer between trenches, thereby improving gap-filling metal in the trenches, which reduces linewidth roughness. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplation of the various embodiments. Similar reference numerals are used to denote similar elements in the various views and illustrative embodiments. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1 to 2 , Figure 3A , Figure 3B , Figures 4 to 5 , Figure 6A , Figure 6B , Figures 7 to 8 , Figure 9A , Figure 9B Figure 10 Figure 11A , Figure 11B Figure 12 to Figure 14 , Figure 15A , Figure 15B and Figure 16 A cross-sectional view is shown of an intermediate stage in forming an interconnect structure according to some embodiments of the present disclosure. Figure 18 The corresponding process is also schematically reflected in the process flow 200 shown in the figure.

[0015] Figure 1 A cross-sectional view of wafer 10 is shown, where the portion shown is a part of a device die within wafer 10. According to some embodiments of this disclosure, wafer 10 is a device wafer that includes active devices (e.g., transistors and / or diodes) and may include passive devices (e.g., capacitors, inductors, and / or resistors, etc.). According to alternative embodiments, wafer 10 may be an insert wafer that does not include active devices, and may or may not include passive devices.

[0016] According to some embodiments of this disclosure, wafer 10 includes a semiconductor substrate 12 and features formed on the upper surface of the semiconductor substrate 12. The semiconductor substrate 12 may be formed of a crystalline semiconductor material (e.g., silicon, germanium, silicon-germanium) and / or of a III-V compound semiconductor (e.g., GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP, etc.). The semiconductor substrate 12 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 12 to isolate active regions in the semiconductor substrate 12. Although not shown, through-vias may be formed to extend into the semiconductor substrate 12, wherein the through-vias are used to electrically couple features on opposite sides of the semiconductor substrate 12 to each other. Active devices 14, possibly including transistors, are formed on the top surface of the semiconductor substrate 12.

[0017] Figure 1 The diagram also shows a dielectric layer 16. According to some embodiments of this disclosure, the dielectric layer 16 is formed of a low-k dielectric material with a dielectric constant (k value) below about 3.5, below about 3.0, or even lower. The dielectric layer 16 can be formed from materials such as Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), and / or methyl silsesquioxane (MSQ). According to some embodiments of this disclosure, the formation of the dielectric layer 16 includes depositing a dielectric material containing a pore-forming agent, followed by a curing process to remove the pore-forming agent, such that the remaining IMD layer 16 is porous.

[0018] Conductive features 22A and 22B are formed in IMD 16. According to some embodiments, each of conductive features 22A and 22B includes a diffusion barrier layer and a copper-containing material situated above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, or tantalum nitride, and has the function of preventing copper from diffusing into the IMD 16 from the copper-containing material. Alternatively, conductive features 22A and 22B may be barrier-less and may be formed of cobalt or tungsten, etc. Conductive features 22A and 22B may have a single damask structure or a double damask structure.

[0019] According to some embodiments, dielectric layer 16 is an intermetallic dielectric (IMD) layer, and conductive features 22A and 22B are metal lines and / or vias. According to alternative embodiments, dielectric layer 16 is an interlayer dielectric layer, and conductive features 22A and 22B are contact plugs. Additional features may or may not be present between dielectric layer 16 and device 14, and these additional features are represented as structure 15, which may include dielectric layers such as one or more contact etch stop layers, interlayer dielectric layers, one or more etch stop layers, and one or more IMDs. Structure 15 may also include contact plugs, vias, metal lines, etc.

[0020] Dielectric layer 24 is deposited over dielectric layer 16 and conductive lines 22A and 22B. Dielectric layer 24 can be used as an etch stop layer (ESL), therefore, dielectric layer 24 is referred to as an etch stop layer or ESL 24 throughout this embodiment. Etch stop layer 24 may include nitrides, silicon-carbon based materials, carbon-doped oxides, or metal-containing dielectrics (e.g., SiCN, SiOCN, SiOC, AlO). x (e.g., AlN or AlCN), or combinations thereof. The etch stop layer 24 can be a single layer formed of a homogeneous material or a composite layer comprising multiple dielectric sublayers. According to some embodiments of this disclosure, the etch stop layer 24 includes an aluminum nitride (AlN) layer, a SiOC layer above the AlN layer, and aluminum oxide (AlO) above the SiOC layer. x )layer.

[0021] Dielectric layer 26 is deposited on ESL 24. According to some exemplary embodiments of this disclosure, dielectric layer 26 is formed of a silicon-containing dielectric material (e.g., silicon oxide). Dielectric layer 26 may also be formed of a low-k dielectric material and is therefore referred to hereinafter as low-k dielectric layer 26. Low-k dielectric layer 26 may be formed using a material selected from the same (or different) group of candidate materials used to form dielectric layer 16. When selected from the same group of candidate materials, the materials of dielectric layers 16 and 26 may be the same or different from each other.

[0022] According to some embodiments of this disclosure, mask layers 28A, 28B, and 28C are formed on dielectric layer 26. It should be understood that the mask layers 28A, 28B, and 28C shown are examples, and different layer schemes may be used. Hereinafter, mask layers 28A, 28B, and 28C are individually referred to and collectively referred to as mask layer 28. According to some embodiments, mask layers 28A and 28C are formed of or comprise a non-metallic dielectric (e.g., silicon oxide), which may be formed, for example, using tetraethyl orthosilicate (TEOS) as a precursor. Formation methods may include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or subatmospheric chemical vapor deposition (SACVD), etc.

[0023] Mask layer 28B is deposited after mask layer 28A and before mask layer 28C. In such... Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 202. Mask layer 28B can be a hard metal mask layer comprising a metal, which can be tungsten (W), ruthenium (Ru), or combinations thereof. Therefore, mask layer 28B is alternatively referred to as hard metal mask layer 28B below. The metal in hard metal mask layer 28B can be an element (not a compound) or in the form of a metal compound. For example, hard metal mask layer 28B can be an elemental tungsten layer, an elemental ruthenium layer, a tungsten alloy layer, or a ruthenium alloy layer. Hard metal mask layer 28B can also be a compound layer of a metal and other elements (e.g., carbon, nitrogen, or combinations thereof). For example, when the metal is tungsten, the compound can be W. x N y C z W x N y or W x C z And so on, where x, y, and z are relative atomic numbers. Similarly, when the metal comprises more than one metal (e.g., W and Ru), the metal hard mask layer may comprise a metal carbide, a metal nitride, or a metal carbonitride. Mask layer 28B may be a single layer formed of a homogeneous material selected from the above materials. Alternatively, mask layer 28B may have a composite structure comprising multiple sublayers selected from the above materials. For example, mask layer 28B may comprise two W... x N y Layer or two W x C z W between layers x N y C z Layers. Forming a composite structure can result in, for example, improved etch resistance and improved etch selectivity against some etch chemicals relative to the underlying mask layer 28A (in Figure 4 and Figure 7(As shown in the steps). The structure and material of the metallic hard mask layer 28B can also be selected to suit the underlying dielectric layer 26, thereby reducing line distortion and linewidth roughness. The mask layer 28 can be formed using PECVD, atomic layer deposition (ALD), CVD, or physical vapor deposition (PVD), etc. The thickness of the mask layer 28 can be approximately... To about between.

[0024] According to some embodiments, such as when using PECVD or other chemical vapor deposition methods, a process gas including a precursor is used as the first gas to perform the formation of the metal hard mask layer 28B. If the metal hard mask layer contains tungsten, the precursor may include WF6, WCl6, etc., or combinations thereof. If the metal hard mask layer contains ruthenium, the precursor may include RuF3, RuCl3, etc., or combinations thereof. The process gas may further include a second gas, which may be a gas containing carbon, containing nitrogen, or containing carbon and nitrogen, such as N2, NH3, alkynes, alkanes, alkenes, etc., or combinations thereof. In embodiments using PVD, a tungsten target, a tungsten carbide target, a ruthenium target, a ruthenium carbide target, etc., may be used depending on the material of the metal hard mask layer 28B. In PECVD, CVD, and / or PVD, process gases (e.g., Ar, He, N2, H2, etc., or combinations thereof) may be added.

[0025] To reduce bending in some portions of the metal line (formed in subsequent processes) and the dielectric layer between the metal lines, the metal hard mask layer 28B is deposited to have a high Young's modulus, for example, greater than about 400 MPa, and can be in the range of about 400 MPa to about 1000 MPa and / or in the range of about 500 MPa to about 1000 MPa. The formation process of the metal hard mask layer 28B is adjusted to increase the Young's modulus of the metal hard mask layer 28B to a very large value, close to or above about 1000 MPa. For example, the deposition rate can be reduced to form a denser metal hard mask layer 28B, and thus have a higher Young's modulus.

[0026] Furthermore, to reduce bending in some portions of the dielectric layer between the metal lines, the metal hard mask layer 28B is deposited with high tensile stress. According to some embodiments, the tensile stress is greater than about 600 MPa or greater than about 1000 MPa, and can be between about 600 MPa and about 2000 MPa, between about 1000 MPa and about 2000 MPa, or between about 1300 MPa and about 2000 MPa. The formation process of the metal hard mask layer 28B is adjusted to increase the tensile stress of the metal hard mask layer 28B to a very large value, for example, close to or above about 1000 MPa. According to some embodiments using PECVD, the plasma power can be in the range of about 100 watts to about 3000 watts, and can be adjusted to a selected range to increase the tensile stress. The frequency of the RF power can include frequencies of 27 MHz, 13 MHz, 430 kHz, 400 kHz, or combinations thereof.

[0027] As described above, the process conditions used for depositing the metallic hard mask layer 28B can be adjusted to increase the tensile stress of the metallic hard mask layer 28B. For example, Figure 17 An example correlation is shown between the normalized plasma power used for depositing the metallic hard mask layer 28B and the normalized tensile stress generated in the metallic hard mask layer 28B. It should be understood that the figure shown is illustrative, and this correlation can be affected by other factors such as the material of the metallic hard mask layer 28B, the bias power, the deposition temperature, and the presence of ion bombardment via a carrier gas such as He or Ar. However, this trend may still exist. Figure 17 As can be seen, at low plasma power, the tensile stress may be low, and the tensile stress gradually increases with increasing plasma power. When the tensile stress reaches its maximum point, it decreases again with further increases in plasma power. Therefore, the plasma power will be selected as an intermediate value that is neither too high nor too low to achieve high tensile stress.

[0028] Since the Young's modulus and tensile stress of the metallic hard mask layer 28B can be affected by various factors, such as the material and its composition (elements and atomic percentages of elements), and process conditions such as plasma power, deposition rate, or temperature, multiple samples can be fabricated to deposit sample metallic hard mask layers 28B. These multiple samples can be formed using different combinations of materials and process conditions, as described above. Optimal materials (and optimal material composition) and optimal process conditions that result in high Young's modulus and high tensile stress can be determined and used in the manufacturing process.

[0029] Next, multiple mandrels 30 are formed on top of the mask layer 28. For example... Figure 18As shown, in process flow 200, the corresponding process is shown as process 204. According to some embodiments, the mandrel 30 is formed as a plurality of parallel strips, for example, as... Figure 3B As shown in the top view. The mandrel 30 may be formed of or include amorphous silicon, amorphous carbon, or tin oxide, etc. According to some embodiments, the mandrel 30 ( Figure 1 The width W1 of the mandrel 30 can be less than about 20 nm, and can be in the range of about 5 nm to about 20 nm. The spacing S1 between adjacent mandrels 30 can be 2.5 to 4 times the width W1. According to some embodiments, the height H1 of the mandrel 30 can be in the range of about 10 nm to about 40 nm, and can be in the range of about 25 nm to about 40 nm. The formation of the mandrel 30 may include depositing a blanket layer (which may be a planar layer with uniform thickness), and then performing an etching process to pattern the blanket layer and form the mandrel 30.

[0030] refer to Figure 2 This forms spacer 32. In such a case... Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 206. According to some embodiments, the spacer 32 is formed of or includes a metal-containing material, such as a metal oxide or metal nitride (e.g., titanium oxide or titanium nitride). The width W2 of the spacer 32 can range from about 5 nm to about 20 nm. The height H2 of the spacer 32 is equal to or slightly less than the height H1 of the mandrel 30 (e.g., between about 62% and 100%). The height H2 can range from about 20 nm to about 40 nm, and can be between about 25 nm and about 40 nm. The height H2 is further greater than the width W2 of the spacer 32, and can be greater than about 1.5 times or 2 times the width W2. The process of forming the spacer layer 32 may include performing a conformal deposition process to form a conformal spacer layer including vertical portions on the sidewalls of the mandrel 30, a top horizontal portion on the top of the mandrel 30, and a bottom horizontal portion between the vertical portions. An anisotropic etching process is then performed to remove the top and bottom horizontal portions, leaving the vertical portions as spacers 32. According to some embodiments, an etching gas such as Cl2, HBr, or CH4, or a combination thereof, is used to perform the anisotropic etching process. A carrier gas such as N2 or argon may also be added to the etching gas. Spaces 34 are formed between the spacers 32 on adjacent mandrels 30, and these spaces 34 may have a spacing S2 ranging from about 0.5W1 to about 1.5W2.

[0031] Figure 3A , Figure 3B , Figure 4 and Figure 5The formation of a first trench pattern in a metal hard mask layer 28B according to some embodiments is shown. The corresponding process can also be referred to as the first patterning process in a dual patterning process. (Refer to...) Figure 3A This forms an etching mask 38, which can be three-layered. In such cases... Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 208. The etching mask 38 may include a bottom layer (sometimes also called the lower layer) 38BL, an intermediate layer 38ML above the bottom layer 38BL, and a top layer 38TL (sometimes also called the upper layer) above the intermediate layer 38ML. According to some embodiments, the bottom layer 38BL and the top layer 38TL are formed of photoresist, wherein the bottom layer 38BL is cross-linked. The intermediate layer 38ML may be formed of an inorganic material, such as a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), or an oxide (e.g., silicon oxide). The intermediate layer 38ML has high etch selectivity relative to the top layer 38TL and the bottom layer 38BL; therefore, the top layer 38TL can be used as an etching mask for patterning the intermediate layer 38ML, and the intermediate layer 38ML can be used as an etching mask for patterning the bottom layer 38BL. The top layer 38TL is patterned to form an opening 40, which defines a trench in the low-k dielectric layer 26. The photolithography process in this patterning can be performed using, for example, extreme ultraviolet (EUV) light with a wavelength of 193 nm.

[0032] Figure 3B yes Figure 3A Top view of the structure shown. Figure 3A The cross-sectional view shown is from Figure 3B The reference cross-section AA was obtained. Etching mask 38 is formed over the entire illustrated area of ​​wafer 10, and opening 40 is formed in etching mask 38. Figure 3B An opening 40 passes through a space 34, and each space 34 is located between two adjacent spacers 32.

[0033] Next, the patterned top layer 38TL was used as an etching mask to etch the intermediate layer 38ML. Figure 3A This allows the opening 40 to extend into the intermediate layer 38ML. After etching through the intermediate layer 38ML, the bottom layer 38BL is further patterned by etching, with the intermediate layer 38ML serving as an etching mask during the patterning of the bottom layer 38BL. During the patterning of the bottom layer 38BL, the top layer 38TL is consumed. The intermediate layer 38ML may be partially or completely consumed during the patterning of the bottom layer 38BL. During the patterning of the bottom layer 38BL, the opening 40 extends downward, thereby exposing the mandrel 30 and the spacer 32. The resulting structure is as follows: Figure 4 As shown.

[0034] Etching continues to etch through the hard mask layer 28C and the metal hard mask layer 28B, forming a trench 42A in the hard mask 28C and penetrating the metal hard mask layer 28B. In... Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 210. Trench 42A may stop on hard mask layer 28A, and hard mask layer 28A is used as an etch stop layer. Different etching chemicals can be used to etch hard mask layer 28C and metal hard mask layer 28B, and each of hard mask layer 28C and metal hard mask layer 28B can be etched using an anisotropic etching process (dry etching process) or an isotropic etching process. For example, a mixture of NF3 and NH3 gases or a mixture of HF and NH3 gases (when using dry etching) or an HF solution (when using wet etching) can be used to etch hard mask layer 28C. Gases including BCl3, Cl2, CF4, CHF3, NF3, O2, Ar, etc., or combinations thereof (when using dry etching) or a phosphoric acid solution (when using wet etching) can be used to etch metal hard mask layer 28B. Next, the remaining portion of etch mask 38 is removed, resulting in the structure shown below. Figure 5 As shown. In the example Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 212. A top view of the example trench 42A can be found... Figure 6B Found it.

[0035] Figure 6A , Figure 6B and Figure 7 The formation of a second trench pattern in a metallic hard mask layer 28B according to some embodiments is illustrated. The corresponding process can also be referred to as a second patterning process in a dual patterning process. (Refer to...) Figure 6A An etching mask 46 is formed, which may be three-layered. The three layers include a bottom layer 46BL, an intermediate layer 46ML above the bottom layer 46BL, and a top layer 46TL above the intermediate layer 46ML. Figure 18 In the illustrated process flow 200, the corresponding process is shown as process 214. The materials of the bottom layer 46BL, the intermediate layer 46ML, and the top layer 46TL can be similar to the materials of the bottom layer 38BL, the intermediate layer 38ML, and the top layer 38TL, respectively. The top layer 46TL is patterned to form an opening 48, which is used to define a trench in the low-k dielectric layer 26. The photolithography process in the patterning of the top layer 46TL can be performed using, for example, EUV light with a wavelength of 193 nm.

[0036] Figure 6B It shows Figure 6A A top view of the structure shown. The previously formed groove 42A is also shown as an example. Figure 6AThe cross-sectional view shown is from Figure 6B The reference cross section AA was obtained. An etch mask 46 is formed over the entire illustrated area of ​​wafer 10, and an opening 48 is formed in the etch mask 46. The opening 48 overlaps with some portions of the mandrel 30.

[0037] Next, the patterned top layer 46TL was used as an etching mask to etch the intermediate layer 46ML. Figure 6A This allows the opening 48 to extend into the intermediate layer 46ML. After the intermediate layer 46ML is etched through, the bottom layer 46BL is patterned, with the intermediate layer 46ML serving as an etching mask during the patterning of the bottom layer 46BL. During the patterning of the bottom layer 46BL, the top layer 46TL is consumed. The intermediate layer 46ML may be partially or completely consumed during the patterning of the bottom layer 46BL. During the patterning of the bottom layer 46BL, the opening 48 extends downward, thereby exposing the mandrel 30 and the spacer 32.

[0038] Next, an etching process is performed to remove the exposed mandrel 30 without removing the spacer 32. This forms trench 42B. Figure 7 Trench 42B is also shown. Etching is performed using a process gas that attacks the mandrel 30 but not the spacer 32. A hard mask layer 28C serves as an etch stop layer and is exposed to trench 42B. Subsequently, the hard mask layer 28C and the metal hard mask layer 28B are etched, such that trench 42B extends into the hard mask layer 28C and the metal hard mask layer 28B. (As shown in...) Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 216. The etching process can be performed using chemicals selected from the candidate etching chemicals used to form trench 42A, and details are not repeated here. After the metal hard mask layer 28B is etched through, the hard mask layer 28A is exposed, and the hard mask layer 28A acts as an etch stop layer to stop the etching of the metal hard mask layer 28B. Next, the remainder of the etch mask 46 is removed, resulting in the structure shown below. Figure 8 As shown. In the example Figure 18 In the process flow 200 shown, the corresponding process is illustrated as process 218. (It can be...) Figure 9C Find the top view of example trench 42B.

[0039] In subsequent processes, such as wet etching, the mandrel 30 and spacer 32 are removed. The resulting structure is as follows: Figure 9B (as well as Figure 9A and Figure 9C As shown in the image. Figure 18As shown, in process flow 200, the corresponding process is shown as process 220. According to an alternative embodiment, the mandrel 30 and spacer 32 are not removed at this stage, and the mandrel 30 and spacer 32 can be removed after the via opening is subsequently formed. For example, not in Figure 9A and Figure 9B Instead of removing the mandrel 30 and spacer 32 in the steps shown, it can be done... Figure 13 and Figure 14 The mandrel 30 and spacer 32 are removed between the steps shown, and this removal occurs in the formation of grooves and through-hole openings. Figure 13 After, and before depositing conductive material into the trenches and via openings. According to yet another alternative embodiment, conductive material 60 (e.g., Figure 14 After removing the mandrel 30 and spacer 32 (as shown), the same planarization process used to remove excess conductive material 60 can be performed (e.g., ...). Figure 14 and Figure 15A Remove the mandrel 30 and spacer 32 from the part shown.

[0040] Refer again Figure 9A and Figure 9B After removing the mandrel 30 and spacer 32, the hard mask layer 28C is exposed. Figure 9B It shows the relationship with Figure 8 The corresponding structure. Figure 9C It shows Figure 9A and Figure 9B A top view of the structure shown, and Figure 9A and Figure 9B They are shown respectively Figure 9A Reference sections 9A-9A and 9B-9B are shown. Grooves 42A and 42B are formed as elongated strips that are parallel to each other and close to each other.

[0041] Figure 10A , Figure 10B and Figure 10C A cross-sectional view and a top view of the through-hole opening 56 are shown. Figure 10C It shows Figure 10A and Figure 10B Top view of the structure shown. Figure 10A and Figure 10B They are shown respectively Figure 10A Reference sections 10A-10A and 10B-10B are shown in the figure.

[0042] refer to Figure 10A and Figure 10B This forms an etching mask 52, which can be three-layered. In such cases... Figure 18In the process flow 200 shown, the corresponding process is illustrated as process 224. The three layers include a bottom layer 52BL, an intermediate layer 52ML above the bottom layer 52BL, and a top layer 52TL above the intermediate layer 52ML. The materials of the bottom layer 52BL, intermediate layer 52ML, and top layer 52TL may be similar to the materials of the bottom layer 38BL, intermediate layer 38ML, and top layer 38TL, respectively. The top layer 52TL is patterned to form one or more openings 54 (see also...). Figure 10C These openings 54 are used to define via openings in the low-k dielectric layer 26. Therefore, the openings 54 may overlap with portions of trenches 42A and 42B, such as... Figure 10C As shown.

[0043] When forming the opening 54, the patterned top layer 52TL is first used as an etching mask to etch the intermediate layer 52ML. Figure 10A and Figure 10B This allows the opening 54 to extend into the intermediate layer 52ML. After the intermediate layer 52ML is etched through, the bottom layer 52BL is patterned, with the intermediate layer 52ML serving as an etching mask during the patterning of the bottom layer 52BL. During the patterning of the bottom layer 52BL, the top layer 52TL is consumed. During the patterning of the bottom layer 52BL, the intermediate layer 52ML may be partially or completely consumed. During the patterning of the bottom layer 52BL, the opening 54 extends downward, thereby exposing the underlying hard mask layer 28A.

[0044] Etching continues to etch the hard mask layer 28A. Next, the dielectric layer 26 is etched to form via openings 56 within it. Figure 18 In the illustrated process flow 200, the corresponding process is shown as process 226. According to some embodiments, etching of the dielectric layer 26 is performed using an etching gas selected from the following: C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. The etching stops at an intermediate level between the top and bottom surfaces of the dielectric layer 26.

[0045] In the example via formation process discussed above, a single patterning process is used. According to an alternative embodiment, a dual patterning process can also be used to form the via opening 56.

[0046] Figure 10C It shows Figure 10A and Figure 10B A top view of the structure shown. (See attached image.) Figure 10C As shown, opening 54 passes through previously formed grooves 42A and 42B. Figure 10C Via 56 is also shown. The etch mask 52 is then removed, resulting in the structure shown below. Figure 11Aand Figure 11B As shown. In the example Figure 18 In the process flow 200 shown, the corresponding process is shown as process 228.

[0047] In subsequent processes, such as Figure 12A and Figure 12B As shown, the hard mask layer 28A is etched through, exposing the underlying dielectric layer 26. Next, the dielectric layer 26 is etched, causing trenches 42A and 42B to extend into the low-k dielectric layer 26. Simultaneously, via openings 56 extend downwards to the bottom of the dielectric layer 26. Figure 18 In the illustrated process flow 200, the corresponding process is shown as process 230. According to some embodiments, etching of the dielectric layer 26 is performed using an etching gas selected from the following: C4F6, C4F8, C5F8, CF4, CHF3, CH2F2, NF3, N2, O2, Ar, He, and combinations thereof. According to some embodiments, trenches 42A and 42B extend to an intermediate level between the top and bottom surfaces of the dielectric layer 26, and this intermediate level may be located between the top and bottom surfaces of the dielectric layer 26. According to some embodiments, the hard mask layer 28C is consumed during etching of the hard mask layer 28A and during subsequent etching processes.

[0048] The metallic hard mask layer 28B has advantageous characteristics due to its high modulus and high tensile stress, which improve the profile of the underlying trenches 42A and 42B. For example, the roughness of the exposed sidewalls of the dielectric layer 26 in the trench 42 is reduced. Furthermore, when viewed from the top ( Figure 10C When the trenches 42A and 42B are straighter, the sidewalls of the dielectric layer 26 facing the trenches 42A and 42B are smoother. Therefore, in the top view, the trench width roughness is reduced. Experimental results show that, for example, when the spacing of the trenches 42 is less than 20 nm, the linewidth roughness of the trenches 42A and 42B (see...) Figure 10C It is less than approximately 2.0.

[0049] Next, one or more etching processes are performed to etch through the etch stop layer 24 and expose conductive features 22A and 22B. Figure 13 The structure obtained from this is shown in the figure.

[0050] Figure 14 The deposition of conductive material 60 is shown to fill trenches 42A and 42B and via opening 56. In such a way... Figure 18In the illustrated process flow 200, the corresponding process is shown as process 232. According to some embodiments, the filler metal material (e.g., cobalt, tungsten, or combinations thereof) can be deposited using a barrier-free process, in which no barrier layer is formed, and the metal material is in solid contact with the conductive feature 22A and the dielectric layer 26. According to an alternative embodiment, the conductive material may include a barrier layer and a metal material situated on the diffusion barrier layer. The barrier layer may be formed of titanium, titanium nitride, tantalum, or tantalum nitride, etc. The metal material may be formed of copper or include copper.

[0051] In subsequent processes, such as Figure 15A and Figure 15B As shown, a planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, is performed to remove excess portions of the conductive material 60. In such cases... Figure 18 In the illustrated process flow 200, the corresponding process is shown as process 234. According to some embodiments, dielectric layer 26 serves as a CMP stop layer. According to alternative embodiments, hard mask layer 28A or 28B serves as a CMP stop layer, and in subsequent processes, metal hard mask layer 28B (and optionally, hard mask layer 28A) is etched. Vias 62A and 62B (individually referred to as via 62 and collectively as via 62) and metal lines 64A and 64B (individually referred to as metal lines 64 and collectively as metal lines 64) are formed. Figure 15A It shows Figure 15B Reference section 15A-15A.

[0052] It should be understood that although the double damask process is shown as an example of forming both metal wire 64 and via 62 in the discussed embodiments, the process in this disclosure can also be used to form a single damask structure.

[0053] Figure 16 The formation of the upper layer is shown, which includes an etch stop layer 66, a dielectric layer 68, a via 70, and a metal line 72. This formation process may be similar to the formation of the via 62 and the metal line 64, except that the formation of the hard metal mask layer 28B used to form the via 62 and the metal line 64 may differ from the formation of the hard metal mask layer (corresponding to hard metal mask layer 28B) used to form the via 70 and the metal line 72. The remaining materials and formation processes used to form the etch stop layer 66, the dielectric layer 68, the via 70, and the metal line 72 may be similar to those for the corresponding etch stop layer 24, the dielectric layer 26, the via 62, and the metal line 64, respectively.

[0054] According to some embodiments, when the linewidth and spacing of the metal lines are small, for example, when the linewidth is less than a threshold (e.g., a value in the range of about 20 nm to about 30 nm), the corresponding metal hard mask layer is formed to have a high Young's modulus and high tensile stress (as described above), thereby reducing the linewidth roughness of the corresponding metal lines / vias. On the other hand, when the linewidth and spacing of the metal lines are large, for example, when the linewidth is greater than a threshold, the metal hard mask layer can be formed to have a low Young's modulus and / or low tensile stress, regardless of whether the linewidth roughness exceeds the specifications. According to some embodiments, with the help of a metal hard mask layer having a high Young's modulus and high tensile stress, a lower metal layer (e.g., metal feature layers 22A / 22B and 64A / 64B / 56A / 56B) with denser metal lines, smaller linewidth W3, and smaller spacing P1 is formed, as discussed in the previous embodiments. The upper layer (e.g., the metal layer for metal lines 72 and vias 70) with looser metal lines, a larger linewidth W4, and a larger spacing P2 is formed using a corresponding hard metal mask layer made of another material (e.g., TiN) having a low Young's modulus and / or low tensile stress. The process and structure involved in forming the upper metal layer are essentially the same as those shown in the foregoing embodiments, except that the corresponding hard metal mask layer 28B can be replaced with a hard metal mask layer having a lower Young's modulus and / or lower tensile stress. For example, TiN can be used to form the hard metal mask layer for forming the upper metal layer, and TiN has a Young's modulus of about 306 MPa and a tensile stress of about 750 MPa. According to some embodiments, the ratio P2 / P1 is greater than 1.0, and can be greater than about 1.5 or greater than about 2.0. The ratio W4 / W3 can also be greater than 1.0, and can be greater than about 1.5 or greater than about 2.0. Furthermore, in the wafer / device, there may be a partition metal layer, which and all metal layers located below (including) the partition metal layer can be formed using a metal hard mask layer with high Young's modulus and high tensile stress, while all metal layers above the partition metal layer (which have a large spacing and a large width) can be formed using a metal hard mask layer with low Young's modulus and / or low tensile stress.

[0055] The tensile stress of the 28B metal hard mask layer and its effect on metal wire bending were investigated by forming sample wafers. Figure 15A and Figure 15BThe structures in the samples were formed using the process shown. In the first group of samples, the tensile stress values ​​in the corresponding metal hard mask layers were relatively low and ranged from approximately 500 MPa to 1000 MPa. In the second group of samples, the tensile stress values ​​in the corresponding metal hard mask layers were moderate and ranged from approximately 1000 MPa to approximately 1300 MPa. In the third group of samples, the tensile stress values ​​in the corresponding metal hard mask layers were relatively high and ranged from approximately 1300 MPa to approximately 2000 MPa. Transmission electron microscopy (TEM) results showed that the normalized bending of the metal wires in the low-stress samples was 1.17, and the normalized bending of the metal wires in the medium-stress samples was 1.20. This means that the low-stress and medium-stress samples were not significantly affected by the tensile stress. However, the normalized bending of the metal wires in the high-stress samples decreased significantly to 0.67. This means that increasing the tensile stress to a certain value can significantly reduce the bending of the metal wires. It should also be recognized that the low-stress, medium-stress, and high-stress ranges are related to various factors and may shift when the structure and materials change. For example, in some embodiments, tensile stress greater than about 600 MPa can be considered high stress.

[0056] The embodiments of this disclosure have several advantageous features. By forming high-stress and high-modulus hard metal mask layers (which are used to pattern the underlying dielectric layer to form trenches and via openings), the resulting metal lines and vias have lower linewidth roughness and line edge roughness. Therefore, line interruptions are reduced. Gap filling processes are also easier to perform once the trenches and via openings are filled.

[0057] According to some embodiments of this disclosure, a method includes: forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa; patterning the metal-containing hard mask layer to form a first opening in the metal-containing hard mask layer; using the metal-containing hard mask layer as an etch mask to etch the dielectric layer, wherein the first opening extends into the dielectric layer; filling the first opening with a conductive material to form a conductive feature; and removing the metal-containing hard mask layer. In one embodiment, forming the metal-containing hard mask layer includes: depositing a tungsten-containing compound layer, the tungsten-containing compound layer comprising a metal and elements selected from the group consisting essentially of carbon, nitrogen, and combinations thereof. In one embodiment, forming the metal-containing hard mask layer includes: depositing a tungsten carbide layer. In one embodiment, forming the metal-containing hard mask layer includes: depositing a tungsten carbonitride layer. In one embodiment, forming the metal-containing hard mask layer includes depositing a tungsten layer. In one embodiment, the method includes: forming a plurality of mandrels over a hard mask layer containing metal; forming a plurality of spacers on the sidewalls of the plurality of mandrels; and removing one mandrel between two of the spacers, leaving a space between the mandrels, wherein a first opening is located directly below the space. In another embodiment, the method includes: forming a plurality of mandrels over a hard mask layer containing metal; and forming a plurality of spacers on the sidewalls of the plurality of mandrels, with a space between two of the spacers, wherein a first opening is located directly below the space. In another embodiment, the first opening extending into a dielectric layer forms a trench, and the method further includes: forming a patterned photoresist over the hard mask layer containing metal; and forming a via opening in the dielectric layer, the via opening being located below the first opening, wherein, when forming the via opening, the patterned photoresist and the hard mask layer containing metal are combined as an additional etch mask. In one embodiment, the method includes: patterning a metal-containing hard mask layer to form a second opening in the metal-containing hard mask layer, wherein the first opening and the second opening are formed in separate etching processes, and the first opening and the second opening extend simultaneously into a dielectric layer.

[0058] According to some embodiments of this disclosure, a method includes: depositing a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a tensile stress greater than about 600 MPa; forming a plurality of mandrels over the metal-containing hard mask layer; forming a plurality of spacers on the sidewalls of the plurality of mandrels; etching the metal-containing hard mask layer to form a first trench in the metal-containing hard mask layer, wherein the first trench overlaps with a first space between two of the plurality of spacers; etching one of the mandrels to leave a second space; etching the metal-containing hard mask layer to form a second trench in the metal-containing hard mask layer, wherein the second trench overlaps with a second space; and etching the dielectric layer to extend the first trench and the second trench into the dielectric layer. In one embodiment, the method includes: depositing a first mask layer over a dielectric layer, wherein a metal-containing hard mask layer is deposited over the first mask layer; and depositing a second mask layer over the metal-containing hard mask layer, wherein a plurality of mandrels and a plurality of spacers are formed over the second mask layer, and wherein a first trench and a second trench terminate on the first mask layer. In one embodiment, depositing the metal-containing hard mask layer includes: depositing a tungsten layer. In one embodiment, depositing the metal-containing hard mask layer includes: depositing a tungsten carbide layer. In one embodiment, depositing the metal-containing hard mask layer includes: depositing a ruthenium-containing layer. In one embodiment, depositing the metal-containing hard mask layer is performed using a plasma-enhanced chemical vapor deposition process. In one embodiment, depositing the metal-containing hard mask layer is performed using a physical vapor deposition process.

[0059] According to some embodiments of this disclosure, a method includes: depositing a low-k dielectric layer; depositing a first mask layer over the low-k dielectric layer; depositing a tungsten-containing hard mask layer over the first mask layer; depositing a second mask layer over the tungsten-containing hard mask layer; forming a patterned photoresist over the second mask layer; etching the second mask layer and the tungsten-containing hard mask layer using the patterned photoresist, such that a trench is formed in the tungsten-containing hard mask layer, wherein a top surface of the first mask layer is located below the trench and exposed to the trench; and transferring the trench in the tungsten-containing hard mask layer into the low-k dielectric layer. In one embodiment, depositing the tungsten-containing hard mask layer includes: depositing a tungsten carbide layer. In one embodiment, depositing the tungsten-containing hard mask layer includes: depositing a tungsten layer. In one embodiment, depositing the tungsten-containing hard mask layer is performed using plasma-enhanced chemical vapor deposition, and the plasma power is adjusted such that the tensile stress in the tungsten-containing hard mask layer is greater than about 1000 MPa.

[0060] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0061] Example 1 is a method for forming a semiconductor structure, comprising: forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa; patterning the metal-containing hard mask layer to form a first opening in the metal-containing hard mask layer; using the metal-containing hard mask layer as an etch mask to etch the dielectric layer, wherein the first opening extends into the dielectric layer; filling the first opening with a conductive material to form a conductive feature; and removing the metal-containing hard mask layer.

[0062] Example 2 is the method of Example 1, wherein forming the metal-containing hard mask layer includes: depositing a tungsten-containing compound layer, the tungsten-containing compound layer comprising a metal and elements selected from the group consisting primarily of carbon, nitrogen, and combinations thereof.

[0063] Example 3 is the method described in Example 2, wherein forming the metal-containing hard mask layer includes: depositing a tungsten carbide layer.

[0064] Example 4 is the method described in Example 2, wherein forming the metal-containing hard mask layer includes: depositing a tungsten carbonitride layer.

[0065] Example 5 is the method described in Example 1, wherein forming the metal-containing hard mask layer includes: depositing a tungsten layer.

[0066] Example 6 is the method of Example 1, further comprising: forming a plurality of mandrels on the hard mask layer containing metal; forming a plurality of spacers on the sidewalls of the plurality of mandrels; and removing one of the plurality of mandrels between two of the plurality of spacers, thereby leaving space occupied by the one of the plurality of mandrels, wherein the first opening is located directly below the space.

[0067] Example 7 is the method of Example 1, further comprising: forming a plurality of mandrels on the hard mask layer containing metal; and forming a plurality of spacers on the sidewalls of the plurality of mandrels, wherein there is a space between two of the plurality of spacers, wherein the first opening is located directly below the space.

[0068] Example 8 is the method of Example 1, wherein the first opening extending into the dielectric layer forms a trench, and the method further includes: forming a patterned photoresist over the metal-containing hard mask layer; and forming a via opening in the dielectric layer, wherein the via opening is located below the first opening, wherein, when forming the via opening, the patterned photoresist and the metal-containing hard mask layer are combined as an additional etch mask.

[0069] Example 9 is the method of Example 1, further comprising: patterning the metal-containing hard mask layer to form a second opening in the metal-containing hard mask layer, wherein the first opening and the second opening are formed in separate etching processes, and the first opening and the second opening extend simultaneously into the dielectric layer.

[0070] Example 10 is a method of forming a semiconductor structure, comprising: depositing a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a tensile stress greater than about 600 MPa; forming a plurality of mandrels over the metal-containing hard mask layer; forming a plurality of spacers on the sidewalls of the plurality of mandrels; etching the metal-containing hard mask layer to form a first trench in the metal-containing hard mask layer, wherein the first trench overlaps with a first space between two of the plurality of spacers; etching one of the mandrels of the plurality of mandrels to leave a second space; etching the metal-containing hard mask layer to form a second trench in the metal-containing hard mask layer, wherein the second trench overlaps with the second space; and etching the dielectric layer such that the first trench and the second trench extend into the dielectric layer.

[0071] Example 11 is the method of Example 10, further comprising: depositing a first mask layer over the dielectric layer, wherein the metal-containing hard mask layer is deposited over the first mask layer; and depositing a second mask layer over the metal-containing hard mask layer, wherein the plurality of mandrels and the plurality of spacers are formed over the second mask layer, and wherein the first trench and the second trench terminate on the first mask layer.

[0072] Example 12 is the method of Example 10, wherein depositing the metal-containing hard mask layer includes: depositing a tungsten layer.

[0073] Example 13 is the method of Example 10, wherein depositing the metal-containing hard mask layer includes: depositing a tungsten carbide layer.

[0074] Example 14 is the method of Example 10, wherein depositing the metal-containing hard mask layer includes: depositing a layer containing ruthenium.

[0075] Example 15 is the method of Example 10, wherein the deposition of the metal-containing hard mask layer is performed by a plasma-enhanced chemical vapor deposition process.

[0076] Example 16 is the method described in Example 10, wherein the deposition of the metal-containing hard mask layer is performed by a physical vapor deposition process.

[0077] Example 17 is a method of forming a semiconductor structure, comprising: depositing a low-k dielectric layer; depositing a first mask layer over the low-k dielectric layer; depositing a tungsten-containing hard mask layer over the first mask layer; depositing a second mask layer over the tungsten-containing hard mask layer; forming a patterned photoresist over the second mask layer; using the patterned photoresist to etch the second mask layer and the tungsten-containing hard mask layer such that a trench is formed in the tungsten-containing hard mask layer, wherein a top surface of the first mask layer is located below and exposed to the trench; and transferring the trench in the tungsten-containing hard mask layer into the low-k dielectric layer.

[0078] Example 18 is the method of Example 17, wherein depositing the tungsten-containing hard mask layer includes: depositing a tungsten carbide layer.

[0079] Example 19 is the method of Example 17, wherein depositing the tungsten-containing hard mask layer includes: depositing a tungsten layer.

[0080] Example 20 is the method described in Example 17, wherein the deposition of the tungsten-containing hard mask layer is performed using plasma-enhanced chemical vapor deposition, and the power of the plasma is adjusted such that the tensile stress in the tungsten-containing hard mask layer is greater than about 1000 MPa.

Claims

1. A method of forming a semiconductor structure, comprising: forming a metal-containing hardmask layer over a dielectric layer; forming a plurality of mandrels over the metal-containing hardmask layer; forming a plurality of spacers on sidewalls of the plurality of mandrels; patterning the metal-containing hardmask layer in a first patterning process to form a first opening in the metal-containing hardmask layer, wherein the first opening is directly below a space between two spacers of the plurality of spacers, and wherein the first opening extends from a top surface of the plurality of spacers to a second top surface of a first non-metal-containing layer that is below the metal-containing hardmask layer, and the first opening terminates on the second top surface of the first non-metal-containing layer; removing one of the plurality of mandrels in a second patterning process to form a second opening that extends into the metal-containing hardmask layer, wherein the second opening terminates on the second top surface; after forming the first opening and the second opening that terminate on the second top surface, removing remaining portions of the plurality of mandrels and the plurality of spacers; etching the dielectric layer using the metal-containing hardmask layer as an etch mask, wherein both the first opening and the second opening extend into the dielectric layer; filling the first opening with a conductive material to form a conductive feature; and removing the metal-containing hardmask layer.

2. The method of claim 1, further comprising: depositing the first non-metal-containing layer and a second non-metal-containing layer, wherein the second non-metal-containing layer is over the metal-containing hardmask layer.

3. The method of claim 2, wherein, forming the metal-containing hardmask layer includes depositing elemental ruthenium.

4. The method of claim 2, wherein, both the first opening and the second opening are in physical contact with the metal-containing hardmask layer.

5. The method of claim 1, wherein, the metal-containing hardmask layer has a Young’s modulus that is higher than 1000 MPa.

6. The method of claim 1, further comprising: depositing a spacer layer on the plurality of mandrels, wherein forming the plurality of mandrels includes performing an anisotropic etch process on the spacer layer, wherein portions of the spacer layer on sidewalls of the plurality of mandrels form the plurality of spacers.

7. The method of claim 1, wherein, the first opening that extends into the dielectric layer forms a trench, and the method further comprises: forming a patterned photoresist over the metal-containing hardmask layer; and forming a via opening in the dielectric layer, and the via opening is below the first opening, wherein the patterned photoresist and the metal-containing hardmask layer are used in combination as an additional etch mask when forming the via opening.

8. The method of claim 1, wherein, the first patterning process and the second patterning process are performed using first and second photoresists, respectively, and wherein etching the dielectric layer is performed using a third photoresist.

9. A method of forming a semiconductor structure, comprising: depositing a metal-containing hardmask layer over a dielectric layer; forming a plurality of mandrels over the metal-containing hardmask layer; forming a plurality of spacers on sidewalls of the plurality of mandrels; etching the metal-containing hard mask layer to form a first trench in the metal-containing hard mask layer, wherein the first trench overlaps a first space between two spacers of the plurality of spacers; etching a first mandrel of the plurality of mandrels using a second photoresist in a second etching process separate from the first etching process to leave a second space, wherein a second mandrel of the plurality of mandrels remains after etching the first mandrel; etching the metal-containing hard mask layer to form a second trench in the metal-containing hard mask layer, wherein the second trench overlaps the second space and the second mandrel serves as part of an etch mask for the etching; after both the first etching process and the second etching process are performed, removing remaining portions of the plurality of mandrels and the plurality of spacers; and after removing the remaining portions of the plurality of mandrels and the plurality of spacers, etching the dielectric layer to extend the first trench and the second trench into the dielectric layer, wherein etching the dielectric layer includes using a third photoresist.

10. The method of claim 9, further comprising: depositing a first mask layer over the dielectric layer, wherein the metal- containing hard mask layer is deposited over the first mask layer; and depositing a second mask layer over the metal-containing hard mask layer, wherein the plurality of mandrels and the plurality of spacers are formed over the second mask layer, and wherein the first trench and the second trench stop on the first mask layer.

11. The method of claim 10, further comprising: depositing a spacer layer over the plurality of mandrels; and performing an anisotropic etching process to pattern the spacer layer and form the plurality of spacers when all top surfaces of the spacer layer are exposed, wherein the second mask layer is uncovered by the anisotropic etching process.

12. The method of claim 9, wherein, depositing the metal-containing hard mask layer includes depositing a layer containing tungsten.

13. The method of claim 9, wherein, depositing the metal-containing hard mask layer includes depositing a layer containing ruthenium.

14. The method of claim 9, wherein, depositing the metal-containing hard mask layer is performed by a plasma- enhanced chemical vapor deposition process.

15. The method of claim 9, wherein, depositing the metal-containing hard mask layer is performed by a physical vapor deposition process.

16. A method of forming a semiconductor structure, comprising: depositing a low-k dielectric layer; depositing a first mask layer over the low-k dielectric layer; depositing a tungsten-containing hard mask layer over the first mask layer; depositing a second mask layer over the tungsten-containing hard mask layer; forming a plurality of mandrels over the second mask layer; forming a plurality of spacers on sidewalls of the plurality of mandrels; forming a first patterned photoresist over the second mask layer; etching the second mask layer and the tungsten-containing hard mask layer using the first patterned photoresist such that a first trench is formed in the tungsten-containing hard mask layer and between two adjacent spacers of the plurality of spacers, and the first trench terminates at a top surface of the first mask layer; forming a second patterned photoresist over the second mask layer; etching one of the plurality of mandrels using the second patterned photoresist such that a second trench is formed extending into the tungsten-containing hard mask layer, wherein the top surface of the first mask layer is located below and exposed to the first trench and the second trench, and the second trench terminates at the top surface of the first mask layer; etching the low-k dielectric layer using a third layer of photoresist to form a via opening, wherein the via opening is formed in the first trench and extends from the top surface of the first mask layer to an intermediate level of the low-k dielectric layer; and transferring the trench in the tungsten-containing hard mask layer into the low-k dielectric layer, wherein during the transferring, the via opening extends to a bottom of the low-k dielectric layer.

17. The method of claim 16, wherein, depositing the tungsten-containing hard mask layer includes depositing a tungsten carbide layer.

18. The method of claim 16, wherein, depositing the tungsten-containing hard mask layer includes depositing a tungsten layer.

19. The method of claim 16, further comprising: after forming the first trench and the second trench and before forming the via opening, removing remaining portions of the plurality of mandrels and the plurality of spacers. after forming the first trench and the second trench and before forming the via opening, removing remaining portions of the plurality of mandrels and the plurality of spacers.

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