Semiconductor memory device and method of manufacturing the same

Abstract

The application discloses a semiconductor storage device and a preparation method thereof, which can meet the resolution requirement or the manufacturing process requirement of a micro line width pattern. The preparation method of the semiconductor storage device comprises the following steps: providing a substrate, an upper surface of the substrate being provided with a conductive structure layer; patterning the conductive structure layer, so as to form a first conductive structure comprising a first pattern structure, the first pattern structure extending along a first direction and having a first width in a second direction perpendicular to the first direction, and the first pattern structure further comprising a terminal conductive structure, the terminal conductive structure comprising an inner widening part and an outer widening part arranged in sequence along the first direction, and being respectively used for extending the first pattern structure along a third direction and extending the first pattern structure along a fourth direction, and the third direction and the fourth direction are both non-parallel to the first direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, and in particular, to a semiconductor memory device and a method for fabricating the same. BACKGROUND

[0002] In semiconductor fabrication processes, some microstructures are manufactured by forming micro-patterns with precise dimensions in a semiconductor substrate / film layer, a dielectric material layer, or a metal material layer, etc. To achieve this, in conventional semiconductor technology, a mask layer is formed on a target material layer, so as to form / define the micro-patterns in the mask layer first, and then transfer the patterns to the target film layer. Generally, the mask layer is a patterned photoresist layer formed by a photolithography process, and / or a patterned mask layer formed using the patterned photoresist layer.

[0003] With the increasing complexity of integrated circuits, the dimensions of these micro-patterns are continuously reduced, and the structures are also continuously changed, so the equipment used to generate the feature patterns must meet the stringent requirements of fabrication process resolution and overlay accuracy. Single patterning methods cannot meet the resolution requirements or fabrication process requirements for manufacturing micro-line width patterns. Therefore, it is an important task in the field to improve the existing fabrication process of the microstructures. SUMMARY

[0004] In view of this, the present application provides a semiconductor memory device and a method for fabricating the same, which can meet the resolution requirements or fabrication process requirements for manufacturing micro-line width patterns.

[0005] The present application provides a method for fabricating a semiconductor memory device, which includes the following steps: providing a substrate, wherein an upper surface of the substrate is formed with a conductive structure layer; patterning the conductive structure layer, thereby forming a first conductive structure, wherein the first conductive structure includes a first pattern structure, the first pattern structure extends along a first direction and has a first width in a second direction, the second direction is perpendicular to the first direction, the first pattern structure further includes a terminal conductive structure arranged in the first direction, the terminal conductive structure includes an inner widening portion and an outer widening portion arranged in sequence along the first direction, the outer widening portion is used to extend the first pattern structure along a third direction, the inner widening portion is used to extend the first pattern structure along a fourth direction, and the third direction and the fourth direction are both non-parallel to the first direction.

[0006] Optionally, the maximum width of the outer widening portion is different from the maximum width of the inner widening portion, and both are greater than the first width, and the maximum width of the inner widening portion is 1.5 to 2 times wider than the first width.

[0007] Optionally, before patterning the conductive structure layer to form the first conductive structure, the following steps are also included: etching the first side surface of the conductive structure layer downward in a direction perpendicular to the upper surface of the substrate so that the first side surface of the conductive structure layer forms a comb-like structure, and each tooth of the comb-like structure extends along the first direction, and the substrate is exposed to the comb-like structure; forming a dielectric layer on the upper surface of the substrate, the dielectric layer is located at least between two adjacent teeth of the comb-like structure, and the upper surface of the dielectric layer is flush with the upper surface of the conductive structure layer.

[0008] Optionally, when patterning the conductive structure layer to form a first conductive structure, the following steps are included: forming a mask layer on the upper surface of the comb-like structure, and patterning the mask layer to expose the comb-like structure and the dielectric layer in part; etching the comb-like structure downward in a direction perpendicular to the upper surface of the substrate, thereby forming a first conductive structure on the surface of the substrate.

[0009] Optionally, forming a mask layer on the upper surface of the comb-like structure includes at least the following steps: using a self-aligned double imaging etching method to form a first graphic mask on the upper surface of the comb-like structure and the dielectric layer; stacking to form a second graphic mask on the upper surface of the first graphic mask, and the second graphic mask is also partially located on the upper surface of the dielectric layer and the comb-like structure, thereby constituting the mask layer.

[0010] Optionally, using a self-aligned double imaging etching method, forming a first graphic mask on the upper surface of the comb-like structure includes at least the following steps: forming a linear sacrificial layer on the upper surface of the comb-like structure, the linear sacrificial layer extending along the first direction, and the linear sacrificial layer is at least partially located on the upper surface of a single tooth of the comb-like structure of the conductive structure layer, and at least partially located on the upper surface of the dielectric layer, and the linear sacrificial layer is provided with an extension portion at the first end along the first direction, and the extension direction of the extension portion is the fourth direction; forming an isolation layer on the upper surface and side wall surface of the linear sacrificial layer, and the isolation layers provided on the side wall surfaces of two adjacent sacrificial layers intersect in the area of ​​the extension portion; removing the isolation layer on the upper surface of the linear sacrificial layer and the linear sacrificial layer to form the first graphic mask.

[0011] Optionally, when the second pattern mask is stacked on the upper surface of the first pattern mask to form the second pattern mask, the second pattern mask at least partially covers the first end of the comb-shaped structure in the first direction.

[0012] Optionally, the width of the comb structure exposed by the first patterned mask is less than half of the width of the teeth.

[0013] The semiconductor storage device provided by the present application comprises: a substrate, and a first pattern structure disposed on the substrate and extending along a first direction and having a first width in a second direction perpendicular to the first direction; a first end pattern disposed at a first end of the first pattern structure in the first direction, comprising an inner widening portion and an outer widening portion disposed in sequence along the first direction, the outer widening portion being used for extending the first pattern structure along a third direction, the inner widening portion being used for extending the first pattern structure along a fourth direction, and the third direction and the fourth direction are both non-parallel to the first direction; and a plurality of second pattern structures disposed on the upper surface of the substrate and each extending along the first direction, wherein the plurality of second pattern structures and the plurality of first pattern structures are alternately arranged along the second direction.

[0014] The semiconductor storage device provided by the present application comprises: a substrate, and a first conductive structure disposed on the upper surface of the substrate and comprising a first pattern structure extending along a first direction and having a first width in a second direction perpendicular to the first direction, and the first pattern structure further comprising an end conductive structure disposed at a first end in the first direction, the end conductive structure comprising an inner widening portion and an outer widening portion disposed in sequence along the first direction, the outer widening portion being used for extending the first pattern structure along a third direction, the inner widening portion being used for extending the first pattern structure along a fourth direction, and the third direction and the fourth direction are both non-parallel to the first direction; and the first conductive structure comprising at least three conductive layers of different materials.

[0015] Optionally, the maximum width of the outer widening portion is different from the maximum width of the inner widening portion, and both are greater than the first width, and the maximum width of the inner widening portion is 1.5 to 2 times the first width.

[0016] Optionally, the maximum width of the outer widening portion is greater than 2.0 times the first width.

[0017] Optionally, the first pattern structure extends along the first direction to have two oppositely disposed side edges, and the inner widening portion is tangent to one of the side edges.

[0018] Optionally, the first pattern structure extends along the first direction to have two oppositely disposed side edges, and the outer widening portion extends to both of the side edges.

[0019] Optionally, it further includes: a plurality of second pattern structures, each extending along the first direction, wherein the plurality of second pattern structures and the plurality of first pattern structures are alternately arranged along the second direction, and each second pattern structure includes an end located on the first side, and the end coincides with the second end of the first pattern structure.

[0020] Optionally, the outer contour surfaces of the outer widening portion and the inner widening portion include curved surfaces.

[0021] Optionally, the top-view area of ​​the outer widened portion is larger than the top-view area of ​​the inner widened portion.

[0022] The critical dimension of the end of the first graphic structure of the semiconductor memory device and the preparation method of the present application is large, which can prevent the bit line (Bit Line) prepared based on the first graphic structure from being open (Line Open). In addition, when a window is opened at the end position to form a contact window, the area of ​​the contact window can be large enough to reduce the impedance of the contact point at the contact window. In addition, since the critical dimension of the end is large, the size of the mask used in the process of preparing the end is also large. The large mask size also leads to a reduced preparation difficulty in the process of patterning the conductive structure layer, so that the patterning process of preparing the semiconductor memory device has a certain fault tolerance, even for semiconductor memory devices with large ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 The flowchart of the steps of the method for manufacturing a semiconductor memory device in one embodiment of the present application is a schematic diagram.

[0025] Figure 2 1 is a schematic flow chart of the steps before patterning the conductive structure layer to form a first conductive structure in one embodiment of the present application.

[0026] Figure 3 1 is a schematic flow chart of the steps of patterning the conductive structure layer to form a first conductive structure in one embodiment of the present application.

[0027] Figure 4 1 is a schematic flow chart of the steps of forming a mask layer on the upper surface of the comb-shaped structure in one embodiment of the present application.

[0028] Figure 51 is a flow chart of the steps of forming a first pattern mask on the upper surface of the comb-shaped structure using a self-aligned double imaging etching method according to one embodiment of the present application.

[0029] Figure 6 FIG1 is a side view of a semiconductor memory device during fabrication of the semiconductor memory device according to an embodiment of the present application.

[0030] Figure 7 FIG1 is a side view of a semiconductor memory device during fabrication of the semiconductor memory device according to an embodiment of the present application.

[0031] Figure 8 Schematic diagram of the structure after a dielectric layer is formed on the upper surface of the substrate when preparing a semiconductor memory device in one embodiment of the present application.

[0032] Figure 9 Schematic diagram of the structure after a mask layer is formed on the upper surface of the comb-shaped structure when preparing a semiconductor memory device in one embodiment of the present application.

[0033] Figure 10 This is a structural schematic diagram of a semiconductor memory device manufactured in one embodiment of the present application after the mask layer is patterned to partially expose the comb-like structure and the dielectric layer.

[0034] Figure 11 This is a structural schematic diagram of forming a first conductive structure on the surface of the substrate by etching the comb-shaped structure downward in a direction perpendicular to the upper surface of the substrate when preparing a semiconductor memory device in one embodiment of the present application.

[0035] Figure 12 Schematic diagram of a structure in which a first pattern mask is formed on the comb structure and the upper surface of the dielectric layer using a self-aligned double imaging etching method in one embodiment of the present application.

[0036] Figure 13 This is a structural schematic diagram of forming a first pattern mask on the comb-shaped structure and the upper surface of the dielectric layer when preparing a semiconductor memory device in one embodiment of the present application.

[0037] Figure 14 Schematic diagram of the structure of a semiconductor memory device according to an embodiment of the present application.

[0038] Figure 15 Schematic diagram of the structure of a semiconductor memory device according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The semiconductor memory device and the manufacturing method thereof are further described below with reference to the accompanying drawings and embodiments.

[0040] See also Figure 1, is a schematic diagram of the steps of a method for preparing a semiconductor memory device in one embodiment of the present application.

[0041] In this embodiment, the present application provides a method for preparing a semiconductor memory device, comprising the following steps:

[0042] Step S101: Provide a substrate 101, wherein a conductive structure layer is formed on the upper surface of the substrate 101. Figure 6 As shown, Figure 6 FIG1 is a side view of a semiconductor memory device during fabrication of the semiconductor memory device according to an embodiment of the present application.

[0043] The substrate 101 includes a semiconductor base and a plurality of film layers formed on a surface of the semiconductor base.

[0044] The material of the semiconductor substrate may include silicon (Si), such as crystalline Si, polycrystalline silicon, or amorphous Si. In some embodiments, the semiconductor substrate may include a semiconductor material such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0045] In some embodiments, a conductive region may be formed in the semiconductor substrate, such as a well doped with impurities, or other structures doped with impurities.

[0046] An isolation structure is formed within the semiconductor substrate, dividing the semiconductor substrate into multiple active regions, each of which can be arranged at equal intervals. The isolation structure can be a shallow trench isolation (STI) structure, formed by etching the semiconductor substrate to form a trench, which is then filled with an insulating material. The insulating material used in the isolation structure can be at least one of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0047] The active region may have a regular shape, such as a strip, and be arranged in a regular pattern. A gate structure is formed in the active region. In some other embodiments, word lines are further formed in the semiconductor substrate, intersecting the active region.

[0048] In this embodiment, the conductive structural layer can be made of conductive metal and may include a combination of multiple metal layers.

[0049] Step S102: patterning the conductive structure layer to form a first conductive structure.

[0050] In one embodiment, the first conductive structure includes three conductive layers made of different materials, including a doped polysilicon layer, a metal layer, and a metal compound layer.

[0051] When patterning the conductive structure layer, at least one of dry etching and wet etching can be used. In this embodiment, the first conductive structure finally formed is as follows Figure 14 shown.

[0052] exist Figure 14 In the illustrated embodiment, the first conductive structure includes a first pattern structure 102C. The first pattern structure 102C extends along a first direction and has a first width in a second direction perpendicular to the first direction. The first pattern structure 102C also includes an end conductive structure arranged in the first direction. The end conductive structure includes an inner widening portion 1021 and an outer widening portion 1022 arranged sequentially along the first direction. The outer widening portion 1022 is used to extend the first pattern structure 102C along a third direction, and the inner widening portion 1021 is used to extend the first pattern structure 102C along a fourth direction. Both the third direction and the fourth direction are non-parallel to the first direction.

[0053] The maximum width of the outer widening portion 1022 is different from the maximum width of the inner widening portion 1021 and both are greater than the first width, and the maximum width of the inner widening portion 1021 is 1.5 to 2 times wider than the first width.

[0054] exist Figure 14 In the embodiment shown, the third direction and the fourth direction are parallel to the second direction. In other embodiments, the third direction and the fourth direction may also form a certain angle with the second direction, as long as they are not parallel to the first direction.

[0055] In this embodiment, the manufacturing method used can produce a semiconductor memory device having a first pattern structure with a larger critical dimension at the end portion of the conductive structure layer, thereby simplifying the manufacturing difficulty, overcoming manufacturing errors, and preventing the bit line (Bit Line) prepared based on the first pattern structure from being open. In addition, the end portion of the bit line structure (Bit Line) prepared based on the first pattern has a larger dimension. When a contact window is formed at the end portion, the area of ​​the contact window can be sufficiently large, thereby reducing the impedance of the contact point at the contact window. In addition, due to the larger critical dimension of the end portion, the size of the mask used in the process of preparing the end portion is also larger. The larger mask size also reduces the manufacturing difficulty in the process of patterning the conductive structure layer, thereby providing a certain degree of fault tolerance in the patterning process of preparing the semiconductor memory device.

[0056] See also Figure 2 , is a schematic flow chart of the steps before patterning the conductive structure layer to form a first conductive structure in one embodiment.

[0057] In this embodiment, before patterning the conductive structure layer to form the first conductive structure, the following steps are further included:

[0058] Step S201: Etch the first side surface 102a of the conductive structure layer downward in a direction perpendicular to the upper surface of the substrate 101, so that the first side surface 102a of the conductive structure layer forms a comb-like structure, and each tooth of the comb-like structure extends along a first direction, and the substrate 101 is exposed in the comb-like structure.

[0059] The corresponding structure here is Figure 7 shown. Figure 7 FIG1 is a side view of a semiconductor memory device during fabrication of the semiconductor memory device according to an embodiment of the present application.

[0060] exist Figure 7 In the embodiment shown, the first side surface 102a of the conductive structure layer refers to Figure 7 After the first side surface 102a of the conductive structure layer forms a comb-like structure, a first conductive structure of a desired pattern can be formed in combination with subsequent processes.

[0061] The size and number of teeth of the comb-like structure can be set as needed. Generally speaking, the number of teeth of the comb-like structure is related to the number of bit lines, and the size of the teeth is related to the size of the wafer.

[0062] Step S202: forming a dielectric layer 103 on the upper surface of the substrate 101, wherein the dielectric layer 103 is at least located between two adjacent teeth of the comb-like structure, and the upper surface of the dielectric layer 103 is flush with the upper surface of the conductive structure layer. Figure 8 shown.

[0063] The etching process used here includes but is not limited to at least one of dry etching and wet etching. The dielectric layer 103 includes silicon, polysilicon, phosphorus-doped silicon, amorphous silicon, etc. The dielectric layer 103 is used to separate two adjacent teeth to prevent them from intersecting.

[0064] See also Figure 3 , is a schematic flow chart of the steps of patterning the conductive structure layer to form a first conductive structure in one embodiment.

[0065] In this embodiment, patterning the conductive structure layer to form a first conductive structure includes the following steps:

[0066] Step S301: forming a mask layer 107 on the upper surface of the comb-like structure; and patterning the mask layer 107 so that the comb-like structure and the dielectric layer 103 are partially exposed. The corresponding structure here is as follows Figure 13 shown.

[0067] Step S302: etching the comb structure downward along a direction perpendicular to the upper surface of the substrate 101, so as to form a first conductive structure on the surface of the substrate 101. The corresponding structure is shown in FIG. 3B. Figure 11

[0068] FIG. 4 is a schematic diagram of a step flow for forming a mask layer on the upper surface of the comb structure in an embodiment. Figure 4

[0069] In this embodiment, when forming the mask layer 107 on the upper surface of the comb structure, at least the following steps are included:

[0070] Step S401: using a self-aligned double imaging etching method to form a first pattern mask 105b on the upper surface of the comb structure and the dielectric layer 103. The corresponding structure is shown in FIG. 5B. Figure 12

[0071] Step S402: stacking a second pattern mask 106 on the upper surface of the first pattern mask 105b, so as to form the mask layer 107. The second pattern mask also partially covers the upper surface of the dielectric layer 103 and the comb structure.

[0072] FIG. 6 is a schematic diagram of a structure of a semiconductor memory device in an embodiment. Figure 13 In this embodiment, after the step flow described in the embodiment of FIG. 4, the second pattern mask 106 at least partially covers the first end of the comb structure in the first direction. In other embodiments, the second pattern mask 106 can also completely cover the first end of the comb structure in the first direction.

[0073] Figure 4 In this embodiment, the width of the comb structure exposed to the first pattern mask 105b is less than one half of the width of the teeth. In other embodiments, the second pattern mask can also completely cover the first end of the comb structure in the first direction.

[0074] FIG. 7 is a schematic diagram of a step flow for forming a first pattern mask 105b on the upper surface of the comb structure using a self-aligned double imaging etching method in an embodiment.

[0075] In this embodiment, when forming the first pattern mask 105b on the upper surface of the comb structure using a self-aligned double imaging etching method, at least the following steps are included: Figure 5

[0076] In this embodiment, when forming the first pattern mask 105b on the upper surface of the comb structure using a self-aligned double imaging etching method, at least the following steps are included:

[0077] ​​​​​Step S501: forming a linear sacrificial layer 104a on the upper surface of the comb-like structure, wherein the linear sacrificial layer 104a extends along the first direction, and the linear sacrificial layer 104a is at least partially located on the upper surface of a single tooth of the comb-like structure of the conductive structure layer, and at least partially located on the upper surface of the dielectric layer 103, and an extension portion 104b is provided at the first end of the linear sacrificial layer 104a along the first direction, and the extension direction of the extension portion 104b is the fourth direction. The corresponding structure here is as follows Figure 10 shown.

[0078] Step S502: forming a partition layer 105 on the upper surface and sidewall surface of the linear sacrificial layer 104a, and the partition layers 105 provided on the sidewall surfaces of two adjacent sacrificial layers intersect in the region of the extension portion. Figure 11 shown.

[0079] Step S503: remove the isolation layer 105 and the linear sacrificial layer 104a on the upper surface of the linear sacrificial layer to form the first pattern mask 105b. The corresponding structure here is as follows: Figure 12 shown.

[0080] When removing the isolation layer 105 and the linear sacrificial layer 104a, wet etching can be selected to directly remove them. During the removal of these materials, due to the geometric effect of the sidewalls of the linear sacrificial layer 104a, the materials deposited on both sides of the linear sacrificial layer 104a will remain, forming the isolation layer 105.

[0081] The linear sacrificial layer 104a comprises a polysilicon layer. The barrier layer 105 comprises a silicon dioxide layer. The period of the barrier layer 105 pattern is half that of the desired photolithographic pattern. The pattern obtained using the self-aligned double imaging etching method can double the spatial pattern density and reduce pattern deviation problems caused by excessively small line widths.

[0082] In this embodiment, the semiconductor structure finally prepared is Figure 14 As shown, it includes a first pattern structure 102C and a second pattern structure 102D, and the two pattern structures are alternately arranged in sequence along the second direction, and can be used to form a bit line structure of a semiconductor memory device.

[0083] A semiconductor storage device is also provided in an embodiment of the present application.

[0084] See also Figure 14 , is a schematic structural diagram of a semiconductor storage device according to an embodiment.

[0085] In this embodiment, the semiconductor memory device includes: a substrate 101; and a first pattern structure 102C, which is arranged on the substrate 101 and extends along a first direction and has a first width in a second direction, wherein the second direction is perpendicular to the first direction; a first end pattern, which is arranged at a first end of the first pattern structure 102C in the first direction, and includes an inner widening portion 1021 and an outer widening portion 1022 arranged in sequence along the first direction, wherein the outer widening portion 1022 is used to extend the first pattern structure 102C along a third direction, and the inner widening portion 1021 is used to extend the first pattern structure 102C along a fourth direction, wherein neither the third direction nor the fourth direction is parallel to the first direction; and further includes: a plurality of second pattern structures 102D, each extending along the first direction, wherein the plurality of second pattern structures 102D and the plurality of first pattern structures 102C are alternately arranged along the second direction, and each of the second pattern structures 102D includes an end located on a first side, wherein the end is located at the same end as the second end of the first pattern structure 102C.

[0086] The maximum width of the outer widening portion 1022 is different from the maximum width of the inner widening portion 1021 and both are greater than the first width, and the maximum width of the inner widening portion 1021 is 1.5 to 2 times wider than the first width.

[0087] The maximum width of the outer widened portion 1022 is greater than 2.0 times the first width, ensuring that the end of the first pattern has sufficient width. This significantly reduces the likelihood of the first pattern breaking during fabrication. Furthermore, because the critical dimension of the end of the first pattern is sufficiently large, the size of the contact window fabricated therein can be increased accordingly, thereby reducing the impedance of the contact window. Furthermore, the mask used to fabricate the end of the first pattern is larger in size. This reduces the likelihood of the mask being etched by the etching solution or gas and breaking during etching.

[0088] In one embodiment, the first pattern structure 102C extends along the first direction and has two opposite sides, and the inner widened portion 1021 is tangent to one of the sides. In fact, the specific shape and structure of the inner widened portion 1021 can also be set according to needs.

[0089] In one embodiment, the first pattern structure 102C extends along a first direction and has two oppositely disposed side edges, wherein the outer widened portion 1022 extends toward the two side edges, thereby increasing the critical dimension of the end portion of the first pattern structure 102C in two directions.

[0090] In one embodiment, the outer contour surfaces of the outer widened portion 1022 and the inner widened portion 1021 include curved surfaces. Figure 15 , wherein the outer contour surface of the inner widened portion 1021 is a curved surface.

[0091] In one embodiment, the top-view area of ​​the outer widening portion 1022 is larger than the top-view area of ​​the inner widening portion 1021, thereby increasing the critical dimension of the end of the first graphic and reducing the risk of wire breaking due to the small target critical dimension during the preparation of the first graphic. In addition, the size of the contact window prepared on the end of the first graphic can be increased accordingly, thereby reducing the impedance of the contact window.

[0092] A semiconductor storage device is also provided in an embodiment of the present application.

[0093] See also Figure 14 , is a schematic structural diagram of a semiconductor storage device according to an embodiment.

[0094] In this embodiment, the semiconductor storage device includes: a substrate 101; a first conductive structure, arranged on the upper surface of the substrate 101, including a first pattern structure 102C, the first pattern structure 102C extending along a first direction and having a first width in a second direction, and the second direction is perpendicular to the first direction, the first pattern structure 102C also includes an end conductive structure arranged in the first direction, the end conductive structure includes an inner widening portion 1021 and an outer widening portion 1022 arranged in sequence along the first direction, the outer widening portion 1022 is used to extend the first pattern structure 102C along a third direction, the inner widening portion 1021 is used to extend the first pattern structure 102C along a fourth direction, and the third direction and the fourth direction are both non-parallel to the first direction, and the first conductive structure includes at least three conductive layers of different materials.

[0095] The maximum width of the outer widening portion 1022 is different from the maximum width of the inner widening portion 1021 and both are greater than the first width, and the maximum width of the inner widening portion 1021 is 1.5 to 2 times wider than the first width.

[0096] In this embodiment, by providing the inner widening portion 1021 and the outer widening portion 1022 , the critical dimension of the end of the first graphic is increased as much as possible, thereby reducing the risk of line breakage caused by the smaller target critical dimension during the preparation of the first graphic.

[0097] The number of the first conductive structures is multiple, and the structure of the semiconductor memory device further includes multiple second conductive structures, and the patterns of the multiple second conductive structures are as follows: Figure 14As shown in the second pattern structure 102D, each of the second conductive structures extends along the first direction, wherein the multiple second conductive structures and the first conductive structure are alternately arranged along the second direction, and each of the second conductive structures includes an end located on the first side, and the end is located at the same end as the second end of the first pattern structure 102C.

[0098] The first conductive structure and the second conductive structure are made of the same type of metal material layers.

[0099] In practice, the first conductive structure includes three conductive layers made of different materials. These three conductive layers include a doped polysilicon layer, a metal layer, and a metal compound layer. The second conductive structure can also be formed using other conductive layers. The first and second conductive structures can be used to form bit lines in a semiconductor memory device.

[0100] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a semiconductor memory device, characterized in that: The following steps are involved: Providing a substrate, wherein a conductive structure layer is formed on the upper surface of the substrate; Etching downwardly the first side surface of the conductive structure layer in a direction perpendicular to the upper surface of the substrate, so that the first side surface of the conductive structure layer forms a comb-like structure, wherein each tooth of the comb-like structure extends along a first direction, and the substrate is exposed between two adjacent teeth of the comb-like structure; forming a dielectric layer on the upper surface of the substrate, wherein the dielectric layer is located at least between two adjacent teeth of the comb-shaped structure, and the upper surface of the dielectric layer is flush with the upper surface of the conductive structure layer; forming a linear sacrificial layer on the upper surface of the comb-like structure, the linear sacrificial layer extending along the first direction, and the linear sacrificial layer being at least partially located on the upper surface of a single tooth of the comb-like structure of the conductive structure layer, and at least partially located on the upper surface of the dielectric layer, and an extension portion being provided at a first end of the linear sacrificial layer along the first direction, the extension portion extending in a fourth direction; forming a partition layer on the upper surface and sidewall surface of the linear sacrificial layer, wherein the partition layers provided on the sidewall surfaces of two adjacent sacrificial layers intersect in the region of the extension portion; removing the isolation layer on the upper surface of the linear sacrificial layer and the linear sacrificial layer to form a first pattern mask; On the upper surface of the first pattern mask, a second pattern mask is stacked to form the second pattern mask, wherein the second pattern mask is also partially located on the upper surface of the dielectric layer and the comb-shaped structure, thereby forming a mask layer; patterning the mask layer so that the comb-like structure and the dielectric layer are partially exposed; Etching the comb-shaped structure downward in a direction perpendicular to the upper surface of the substrate, thereby forming a first conductive structure on the surface of the substrate; The first conductive structure includes a first pattern structure, which extends along a first direction and has a first width in a second direction, and the second direction is perpendicular to the first direction. The first pattern structure also includes an end conductive structure arranged in the first direction, and the end conductive structure includes an inner widening portion and an outer widening portion arranged in sequence along the first direction. The outer widening portion is used to extend the first pattern structure along a third direction, and the inner widening portion is used to extend the first pattern structure along a fourth direction, and both the third direction and the fourth direction are not parallel to the first direction.

2. The preparation method according to claim 1, characterized in that The maximum width of the outer widening portion is different from the maximum width of the inner widening portion and both are greater than the first width, and the maximum width of the inner widening portion is 1.5 to 2 times wider than the first width.

3. The preparation method according to claim 1, characterized in that When the second pattern mask is stacked on the upper surface of the first pattern mask to form the second pattern mask, the second pattern mask at least partially covers the first end of the comb-shaped structure in the first direction.

4. The preparation method according to claim 1, characterized in that The width of the comb-shaped structure exposed from the first pattern mask is less than half of the width of the teeth.

Images