Semiconductor package including dam pattern and method of manufacturing the same

Abstract

The present application relates to a semiconductor package including a dam pattern and a method of manufacturing the same. A semiconductor package and a method of manufacturing the same are disclosed. A semiconductor chip can be disposed on a package substrate having a vent hole formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion can be formed. The package substrate can include a substrate body having a plurality of cell regions, a spherical bump disposed in the cell region, and a first dam pattern and a second dam pattern spanning the cell region and extending into an edge region located outside of the cell region.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to a packaging technology, and more particularly, to a semiconductor package including a dam pattern and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor package can include a semiconductor chip and a molding layer disposed on a package substrate. The molding layer can be molded as a layer to protect the semiconductor chip from external stress. During a molding process, a mold flash phenomenon in which a molding material leaks out of a mold cavity can occur. The leaked molding material can contaminate elements of the package substrate. SUMMARY

[0003] An aspect of the disclosure can provide a semiconductor package including a package substrate having a vent hole formed therethrough, a semiconductor chip disposed on the package substrate, and a molding layer including an upper molding portion encapsulating the semiconductor chip and a lower molding portion connected to the upper molding portion through the vent hole. The package substrate can include a substrate body including a plurality of unit areas having the vent hole disposed therethrough, a ball bump disposed in each unit area of the substrate body, and a first dam pattern and a second dam pattern spaced apart from the ball bump of the substrate body, extending across the unit areas, and further extending into an edge area of the substrate body outside the unit areas.

[0004] An aspect of the disclosure can provide a semiconductor package including a package substrate having a vent hole formed therethrough, a semiconductor chip disposed on the package substrate, and a molding layer including an upper molding portion encapsulating the semiconductor chip and a lower molding portion connected to the upper molding portion through the vent hole, wherein the package substrate can include a substrate body including a first edge and a second edge on opposite sides of each other and a surface between the first edge and the second edge, a ball bump disposed on the surface of the substrate body, and a first dam pattern and a second dam pattern spaced apart from the ball bump, extending across the surface to the first edge and the second edge.

[0005] One aspect of the present disclosure can provide a method of manufacturing a semiconductor package, the method including the steps of: disposing a semiconductor chip on a package substrate having a vent hole therethrough, the package substrate including: a substrate body having a plurality of cell regions, a ball bump disposed in a cell region of the substrate body, a first dam pattern and a second dam pattern spaced apart from the ball bump of the substrate body and extending across the cell region, and further extending into an edge region of the substrate body outside the cell region, and a dielectric layer extending to cover the substrate to cover the first and second dam patterns and leave some portions of the ball bump open; loading the package substrate in a mold chase including an upper mold and a lower mold, the upper mold providing an upper cavity in which the semiconductor chip is to be located, and the lower mold providing a lower cavity connected with the vent hole; and molding a molding layer into an upper molding portion by filling the upper cavity and into a lower molding portion by filling the lower cavity while connected to the upper molding portion through the vent hole, wherein the lower mold includes a side surface of the lower mold having an upper end portion overlapping the first and second dam patterns of the package substrate and in contact with a surface of the dielectric layer to close the lower cavity. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 and Figure 2 is a schematic cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 3 is a schematic plan view illustrating a planar arrangement shape of a dam pattern of the semiconductor package of Figure 1 .

[0008] Figure 4 is a schematic plan view illustrating an enlarged portion of the dam pattern of the semiconductor package of Figure 3 .

[0009] Figure 5 is a schematic plan view illustrating a planar arrangement shape of an extended portion of a lower molding portion of the semiconductor package of Figure 1 .

[0010] Figure 6 is a schematic plan view illustrating an enlarged portion of the extended portion of the lower molding portion of the semiconductor package of Figure 5 .

[0011] Figure 7 is a schematic flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0012] Figure 8 and Figure 9 is a schematic flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.Figure 7 FIG. 1 is a schematic cross-sectional view illustrating a step of loading a semiconductor chip onto a package substrate in a method of manufacturing a semiconductor package according to a comparative embodiment.

[0013] Figure 10 Figure 11 FIG. 2 is a schematic cross-sectional view illustrating a step of loading a package substrate into a mold recess device of Figure 7

[0014] Figure 12 Figure 13 FIG. 3 is a schematic cross-sectional view illustrating a step of molding a molding layer in a method of manufacturing a semiconductor package of Figure 7

[0015] Figure 14 FIG. 4 is a schematic cross-sectional view illustrating a mold flash according to the comparative embodiment.

[0016] Figure 15 FIG. 5 is a schematic cross-sectional view illustrating an enlarged lower molding portion of the semiconductor package of Figure 12

[0017] Figure 16 FIG. 6 is a schematic plan view illustrating a planar arrangement shape of a dam pattern of a semiconductor package according to an embodiment of the present disclosure.

[0018] Figure 17 Figure 18 FIG. 7 is a schematic cross-sectional view illustrating a semiconductor package according to an embodiment of the present disclosure.

[0019] Figure 19 FIG. 8 is a schematic plan view illustrating a planar arrangement shape of a dam pattern and an extended portion of a lower molding portion of a semiconductor package of Figure 17

[0020] FIG. 9 is a block diagram illustrating an electronic system employing a memory card including a package according to an embodiment of the present disclosure. Figure 20

[0021] FIG. 10 is a block diagram illustrating an electronic system including a package according to an embodiment of the present disclosure. Figure 21 DETAILED DESCRIPTION

[0022] The terms used herein can correspond to words selected with consideration of their functions in the presented embodiments, and the meanings of the terms can be interpreted differently according to the ordinary skill in the art to which the embodiments pertain. If defined in detail, the terms can be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meanings as commonly understood by one of ordinary skill in the art to which the embodiments pertain.

[0023] ​​​​​​​In the description of the embodiments of the disclosure, descriptions such as "first" and "second", "upper" and "lower", and "left" and "right" are used to distinguish components, and are not used to limit the components themselves or to mean a particular order.

[0024] Furthermore, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0025] The semiconductor device can include a semiconductor substrate or a structure in which a plurality of semiconductor substrates are stacked. The semiconductor device can indicate a semiconductor package structure in which a structure in which semiconductor substrates are stacked is packaged. The semiconductor substrate can indicate a semiconductor chip in which electronic components and devices are integrated, a semiconductor wafer, or a semiconductor die. The semiconductor chip can indicate a memory chip in which a memory integrated circuit such as a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a magnetic random access memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PCRAM) is integrated, a logic die in which a logic circuit is integrated in a semiconductor substrate, or an ASIC chip, or a processor such as an application processor (Ap), a graphics processing unit (GPU), a central processing unit (CPU), or a system on chip (SoC). The semiconductor device can be used in an information communication system such as a mobile phone, an electronic system associated with biotechnology or health care, or a wearable electronic system. The semiconductor package can be applied to the Internet of Things (IoT).

[0026] Throughout the specification, the same reference numerals refer to the same devices. Even if a reference numeral is not mentioned or described with reference to a drawing, it can be mentioned or described with reference to another drawing. In addition, even if a reference numeral is not shown in a drawing, it can be shown in another drawing.

[0027] Figure 1 and Figure 2 is a schematic cross-sectional view showing a semiconductor package 10 according to an embodiment of the disclosure. Figure 1 shows a schematic cross-sectional shape of the semiconductor package 10 along the X-axis, and Figure 2 shows a schematic cross-sectional shape of the semiconductor package 10 along the Y-axis. In the X-Y plane, the X-axis direction can be a direction in which the extension portion 352 of the lower molded portion 350 of the semiconductor package 10 extends long, and the Y-axis direction can be a direction orthogonal to the X-axis direction.

[0028] Referring toFigure 1 and Figure 2 The semiconductor package 10 can include a package substrate 100S, semiconductor chips 200, and a molding layer 300. Each of the semiconductor chips 200 can be a semiconductor chip integrated with an integrated circuit. The semiconductor chips 200 can be disposed on the package substrate 100S in a flip-chip method. The semiconductor chips 200 can be electrically and physically connected to the package substrate 100S by internal connectors 210. The internal connectors 210 can include conductive bumps.

[0029] The molding layer 300 can include a molding material that encapsulates the semiconductor chips 200. The molding layer 300 can include an epoxy molding compound (EMC). The molding layer 300 can be molded by a molding process using a mold recess. The molding layer 300 can extend to fill a gap G between each of the semiconductor chips 200 and the package substrate 100S while covering and protecting the semiconductor chips 200. The molding layer 300 can be disposed in the form of a mold underfill (MUF).

[0030] The package substrate 100S can be an interconnection element for electrically connecting the semiconductor chips 200 to an external device. The package substrate 100S can be a member having circuit traces for electrical connection. The package substrate 100S can include a structure of a printed circuit board (PCB).

[0031] The package substrate 100S can include a vent hole 100H therethrough. The vent hole 100H can be disposed at a position overlapping the semiconductor chips 200. The vent hole 100H can be introduced to substantially reduce, inhibit, or prevent occurrence of a filling defect in which the gap G between each of the semiconductor chips 200 and the package substrate 100S is not filled with a molding material in a mold underfill (MUF) molding process for forming the molding layer 300. The MUF molding process can be performed such that the molding material is introduced into the vent hole 100H. The molding material can pass through the gap G between each of the semiconductor chips 200 and the package substrate 100S and flow into the vent hole 100H. The flow of the molding material can substantially reduce or inhibit an undesirable stagnation of the molding material in the gap G between each of the semiconductor chips 200 and the package substrate 100S. Accordingly, a phenomenon in which a void is trapped in the gap G between each of the semiconductor chips 200 and the package substrate 100S can be substantially reduced, inhibited, or prevented.

[0032] By such a mold underfill molding process, the molding layer 300 can be formed to have a structure of an upper molding portion 310 and a lower molding portion 350. The lower molding portion 350 can be connected to the upper molding portion 310 of the molding layer 300 through the vent holes 100H. The upper molding portion 310 can be formed to be a portion of the molding layer 300 located on the package substrate 100S, and encapsulate the semiconductor chip 200. The lower molding portion 350 can include a filled portion 351 and an extended portion 352. The extended portion 352 of the lower molding portion 350 can include a portion of the molding layer 300 located below the package substrate 100S. The filled portion 351 of the lower molding portion 350 can include a portion of the molding layer 300 filling the vent holes 100H.

[0033] The package substrate 100S can include a substrate body 100, a first dielectric layer 160, and a second dielectric layer 170 disposed on the substrate body 100. The substrate body 100 can have a first surface 101 and a second surface 102 on opposite sides of each other. The semiconductor chip 200 can be disposed over the first surface 101 of the substrate body 100.

[0034] The bond fingers 120 can be disposed on the first surface 101 of the substrate body 100. The bond fingers 120 can be a portion of a circuit wiring structure connected with the internal connections 210. The bond fingers 120 can be a metal pattern or a conductive pattern formed of or including a metal material such as copper (Cu). The first dielectric layer 160 can be disposed to cover the first surface 101 of the substrate body 100 on which the bond fingers 120 are disposed. The first dielectric layer 160 can be made of or include a solder resist (SR) material.

[0035] The ball bumps 130 and the dam patterns 150 can be disposed below the second surface 102 of the substrate body 100. Each of the dam patterns 150 can include a first dam pattern 151 and a second dam pattern 153 facing each other. As shown, the first dam pattern 151 and the second dam pattern 153 can be disposed on both sides of each of the vent holes 100H interposed therebetween. Figure 1 As shown, each of the dam patterns 150 can further include a third dam pattern 155 disposed in an edge region 100E of the substrate body 100. Figure 2

[0036] The ball bumps 130 can be connection terminals to electrically connect the semiconductor package 10 to an external device. The ball bumps 130 can be connection terminals connected with external connections (not shown). The external connections can include solder balls. The ball bumps 130 can be a portion of a circuit wiring structure configured in the package substrate 100S.

[0037] ​The ball bump 130, the first dam pattern 151, the second dam pattern 153, and the third dam pattern 155 can be made of or include substantially the same metal material. The ball bump 130, the first dam pattern 151, the second dam pattern 153, and the third dam pattern 155 can be made of or include a metal material such as copper (Cu). The ball bump 130, the first dam pattern 151, the second dam pattern 153, and the third dam pattern 155 can be metal or conductive patterns formed together in the same process. The first dam pattern 151, the second dam pattern 153, and the third dam pattern 155, and the ball bump 130 can be formed to have substantially the same thickness below the second surface 102 of the substrate body 100.

[0038] The second dielectric layer 170 can be disposed to leave some portions of the ball bump 130 open while covering the first dam pattern 155, the second dam pattern 153, and the third dam pattern 155. The second dielectric layer 170 can be disposed to extend to cover the layer of the second surface 102 of the substrate body 100. The second dielectric layer 170 can be formed of or include a solder resist (SR) material.

[0039] Figure 3 is a schematic plan view illustrating a planar shape of the dam pattern 150 of the semiconductor package 10 of Figure 1 . Figure 4 is a schematic plan view illustrating an enlarged portion of the dam pattern 150 of the semiconductor package 10 of Figure 3 .

[0040] Referring to Figure 3 and Figure 4 , the ball bump 130 can be disposed on the second surface 102 of the substrate body 100 of the package substrate 100S. The dam pattern 150 having the first dam pattern 151 and the second dam pattern 153 can be disposed to be spaced apart from the ball bump 130. The first dam pattern 151 and the second dam pattern 153 can be disposed to be electrically isolated from the ball bump 130 without being electrically connected to the ball bump 130. Since the first dam pattern 151 and the second dam pattern 153 can be made of the same metal material as the ball bump 130, the first dam pattern 151 and the second dam pattern 153 can be disposed to be spaced apart from the ball bump 130 so as to be electrically isolated from the ball bump 130.

[0041] The substrate body 100 can include a plurality of unit regions 11R. The plurality of unit regions 11R can be configured as regions located on the second surface 102 of the substrate body 100. The plurality of unit regions 11R can be disposed on the second surface 102 of the substrate body 100 to form a matrix-like structure with each other. The plurality of unit regions 11R can be disposed on the second surface 102 to form rows in the X-axis direction and columns in the Y-axis direction.

[0042] The spherical bumps 130 can be disposed as a group in the unit regions 11R. All of the spherical bumps 130 disposed as a group in one unit region 11R can be electrically connected to one semiconductor chip 200. As shown in FIG. 1, one semiconductor chip 200 can overlap one unit region 11R of the substrate body 100. The conductive connection patterns 131 and the conductive vias 132 can be further disposed in the unit regions 11R of the substrate body 100. The connection patterns 131 can be conductive patterns electrically connecting the spherical bumps 130 to the conductive vias 132. The conductive vias 132 can substantially extend through the substrate body 100 to be electrically connected to the bonding fingers 120 on the first surface 101 of the substrate body 100. The spherical bumps 130 can be electrically connected to the bonding fingers 120 through the conductive vias 132 and the connection patterns 131. Figure 1 Figure 1 As shown, one semiconductor chip 200 can overlap one unit region 11R of the substrate body 100. The conductive connection patterns 131 and the conductive vias 132 can be further disposed in the unit regions 11R of the substrate body 100. The connection patterns 131 can be conductive patterns electrically connecting the spherical bumps 130 to the conductive vias 132. The conductive vias 132 can substantially extend through the substrate body 100 to be electrically connected to the bonding fingers 120 on the first surface 101 of the substrate body 100. The spherical bumps 130 can be electrically connected to the bonding fingers 120 through the conductive vias 132 and the connection patterns 131. Figure 1

[0043] Each of the vent holes 100H can be disposed in each of the unit regions 11R of the substrate body 100. In an embodiment, a plurality of vent holes 100H can be disposed in one unit region 11R, but one vent hole 100H can be more effectively arranged for each unit region 11R to achieve flow of the molding material into the vent hole 100H.

[0044] The first dam pattern 151 and the second dam pattern 153 can be linear patterns extending while facing each other. Each of the vent holes 100H can be disposed between the first dam pattern 151 and the second dam pattern 153.

[0045] The first dam pattern 151 and the second dam pattern 153 can be linear patterns extending to span the plurality of unit regions 11R on the second surface 102 of the substrate body 100. The first dam pattern 151 and the second dam pattern 153 can extend to span some of the unit regions 11R arranged in columns among the unit regions 11R. The first dam pattern 151 and the second dam pattern 153 can extend to span the intermediate regions 11B between two unit regions 11R adjacent to each other in the Y-axis direction.

[0046] ​​The first dam pattern 151 and the second dam pattern 153 can extend across the cell region 11R and further extend into the edge region 100E of the substrate body 100 located outside the cell region 11R. The edge region 100E of the substrate body 100 can be a region including an intermediate region between the outermost cell region 11R-1 located at the outermost of the cell region 11R and the edge 109 of the substrate body 100.

[0047] Each of the dam patterns 150 can further include a third dam pattern 155. The third dam pattern 155 can connect the end portions of the first dam pattern 151 and the second dam pattern 153 to each other. The third dam pattern 155 can be disposed in the edge region 100E of the substrate body 100. Thus, the third dam pattern 155 can be located outside the cell region 11R. As shown, the third dam pattern 155 can connect the first dam pattern and the second dam pattern to each other such that the dam pattern 150 can be disposed in a ring-shaped planar shape. Figure 3

[0048] The first dam pattern 151, the second dam pattern 153, and the third dam pattern 155 can extend the extension region 352R located therein along the extension portion (352 of 350) of the lower molding portion (350 of 350). Thus, the extension region 352R located in the extension portion (352 of 350) of the lower molding portion (350 of 350) can be disposed inside the first dam pattern 151, the second dam pattern 153, and the third dam pattern 155. The extension region 352R can be disposed as a region extending long in the Y-axis direction along the first dam pattern 151 and the second dam pattern 153. The extension region 352R can extend across the cell region 11R and can further extend into the edge region 100E. Figure 2 Figure 2 Figure 2 is a schematic plan view showing a planar arrangement shape of the extension portion 352 of the lower molding portion of the semiconductor package 10 of Figure 2

[0049] Figure 5 is a schematic plan view showing a planar arrangement shape of the extension portion 352 of the lower molding portion of the semiconductor package 10 of Figure 1 Figure 6 is a schematic plan view showing an enlarged portion of the extension portion 352 of the lower molding portion of the semiconductor package 10 of Figure 5

[0050] Referring to Figure 5 and Figure 6 ​​​​​​The extended portions 352 of the lower molding portion 350 can be disposed in the extended regions 352R. Each of the extended portions 352 of the lower molding portion 350 can be located in the inner regions of the first dam pattern 151, the second dam pattern 153, and the third dam pattern 155. The extended portions 352 of the lower molding portion 350 can overlap with the portion of the substrate body 100 between the first dam pattern 151 and the second dam pattern 153. The extended portions 352 of the lower molding portion 350 can extend across the cell region 11R and further extend into the edge region 100E of the substrate body 100 located outside the cell region 11R. In an embodiment, the extended portions 352 of the lower molding portion 350 can further extend to partially overlap with the first dam pattern 151 and the second dam pattern 153.

[0051] Figure 7 is a schematic flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the disclosure. Figure 8 and Figure 9 is a schematic cross-sectional view illustrating a step S2 of arranging a semiconductor chip 200 on a package substrate 100S in a method of manufacturing a semiconductor package. Figure 7 Figure 8 illustrates a schematic cross-sectional shape of the package substrate 100S and the semiconductor chip 200 along the X-axis direction, and Figure 9 illustrates a schematic cross-sectional shape of the package substrate 100S and the semiconductor chip 200 along the Y-axis direction.

[0052] Referring to Figure 7 and Figure 8 and Figure 9 illustrates a package substrate 100S having a first dam pattern 151 and a second dam pattern 153 and a vent hole 100H. The package substrate 100S can further include a third dam pattern 155. A semiconductor chip 200 can be disposed on the package substrate 100S (S2). The structure on which the semiconductor chip 200 can be disposed on the package substrate 100S can be a structure to be molded to which a Mold Under Fill (MUF) molding process is to be applied.

[0053] Figure 10 and Figure 11 is a schematic cross-sectional view illustrating a step S3 of loading the package substrate 100S of Figure 7 into a mold recess 40.

[0054] Referring to Figure 7 and Figure 10 and Figure 11 ​The package substrate 100S provided with the semiconductor chip 200 is loaded into a mold recess 40. The mold recess 40 can be a process apparatus that performs a mold underfill (MUF) molding process. The mold recess 40 can include an upper mold 450 and a lower mold 410.

[0055] The upper mold 450 can be a mold part that provides an upper cavity 455 into which the semiconductor chip 200 is inserted. The lower mold 410 can be a different mold part corresponding to the upper mold 450. The lower mold 410 can be another mold part that provides a lower cavity 415. The lower mold 410 can include side surfaces of a lower mold 411. The side surfaces of the lower mold 411 can each have a tubular shape that provides the lower cavity 415 as an inner space. The vent hole 100H can be connected to the lower cavity 415.

[0056] The package substrate 100S can be loaded in the cavities 415 and 455 of the mold recess 40. By closing the upper mold 450 and the lower mold 410, the cavities 415 and 455 therein can be sealed and isolated from the outside. The upper end portions 411T of each of the side surfaces of the lower mold 411 can be in close contact with the surface of the second dielectric layer 170 of the package substrate 100S. In this way, the lower cavity 415 can be isolated from the outside by closing the package substrate 100S and the upper end portions 411T of each of the side surfaces of the lower mold 411. The upper end portions 411T of each of the side surfaces of the lower mold 411 can overlap the first dam pattern 151 and the second dam pattern 153 and be in contact with the surface of the second dielectric layer 170. The upper end portions 411T of each of the side surfaces of the lower mold 411 can further extend to be in contact with the surface of the second dielectric layer 170 while overlapping the third dam pattern 155.

[0057] Figure 12 and Figure 13 is a schematic cross-sectional view illustrating a step S4 of molding a mold layer 300 in a method of manufacturing a semiconductor package. Figure 7

[0058] Referring to Figure 7 and Figure 12 and Figure 13 ​The molding step S4 for forming the molding layer 300 can be performed. Molding material can be introduced into the upper cavity 455 of the upper mold 450. The molding material can be introduced to fill the upper cavity 455 and fill the gap G between each of the semiconductor chips 200 and the package substrate 100S. Molding material can be introduced into the lower cavity 415 through the vent hole 100H. The molding material can fill the upper cavity 455 to mold the upper mold 310. The molding material can fill the vent hole 100H to form the filling portion 351 of the lower molding portion 350, and the molding material can fill the lower cavity 415 to form the extension portion 352 of the lower molding portion 350. After molding the molding layer 300, the package substrate 100S can be separated from the mold recess 40.

[0059] Figure 14 This is a schematic cross-sectional view showing the mold overflow 53F according to a comparative embodiment. Figure 15 It is shown Figure 12 A schematic cross-sectional view of the enlarged portion of the lower mold 410. (Refer to...) Figure 14 Without introducing dam patterns ( Figure 12 In the comparative example (150) of the lower mold 41, the lower cavity 45 can be closed by the dielectric layer 57 and the side of the lower mold 41, and a molding process can be performed. As the molding material 53 flows into the lower cavity 45, the stress caused by the molding pressure can be concentrated at the interface between the dielectric layer 57 and the side of the lower mold 41. Compared with metal materials, the dielectric material forming the dielectric layer 57 is more susceptible to stress, and therefore, compared with metal layers, the dielectric material forming the dielectric layer 57 may be more easily deformed due to the applied stress.

[0060] The dielectric layer 57 can be compressed according to the stress of the molding pressure, and the surface of the dielectric layer 57 can retract from the initial height 57-1 to the pressing height 57-2. Therefore, an undesirable gap clearance 46 may be caused between the dielectric layer 57 and the side of the lower mold 41. The molding material 53 may flow out of the gap 46, resulting in a defect of mold overflow 53FIS.

[0061] Reference Figure 15 In this embodiment, the lower cavity 415 is closed and encapsulated by the side of the lower mold 411, the overlapping portion 170A of the second dielectric layer 170 with the side of the lower mold 411, and the dam pattern 150. As molding material flows into the lower cavity 415 and the lower cavity 415 is encapsulated, stress caused by molding pressure can be applied to the component. The overlapping portion 170A of the second dielectric layer 170 and the upper end portion 411T of the side of the lower mold 411 are in contact with each other, and stress can be concentrated at the interface between the overlapping portion 170A of the second dielectric layer 170 and the upper end portion 411T of the side of the lower mold 411.

[0062] Because the overlap portions 170A of the second dielectric layer 170 are supported by the dam pattern 150, the overlap portions 170A can resist concentrated stress without substantially deforming. In addition, because the overlap portions 170A of the second dielectric layer 170 overlap the dam pattern 150, the thickness T1 of each of the overlap portions 170A can be thinner than the thickness T2 of another portion of the second dielectric layer 170 that is not supported by the dam pattern 150. In addition, a metal material such as copper (Cu) that constitutes the dam pattern 150 can be a relatively harder material than a solder resist material that constitutes the second dielectric layer 170. Thus, the dam pattern 150 can be more resistant than the second dielectric layer 170 without deforming due to stress.

[0063] The overlapping structure of the overlap portions 170A of the second dielectric layer 170 and the dam pattern 150 makes it possible to resist stress caused by molding pressure without deforming. The overlapping structure of the overlap portions 170A of the second dielectric layer 170 and the dam pattern 150 can not substantially deform due to stress. In a process of filling the lower cavity 415 with a molding material to perform molding, the lower cavity 415 can be maintained in a closed and encapsulated state by the overlapping structure of the overlap portions 170A of the second dielectric layer 170 and the dam pattern 150. Thus, occurrence of a mold flash failure can be substantially suppressed, reduced, or prevented.

[0064] Figure 16 is a schematic plan view illustrating a planar arrangement shape of a dam pattern 1150 of a semiconductor package 19 according to an embodiment of the disclosure.

[0065] Referring to Figure 16 , the package substrate 1100S of the semiconductor package 19 can include a first dam pattern 1151 and a second dam pattern 1153 on the substrate body 1100. The first dam pattern 1151 and the second dam pattern 1153 can be linear patterns extending across the cell region 1011R. The first dam pattern 1151 and the second dam pattern 1153 can extend to the edge region 1100E of the substrate body 1100. Each of the dam patterns 1150 can include the first dam pattern 1151 and the second dam pattern 1153, and the third dam pattern (155) in Figure 3 may be omitted. The first dam pattern 1151 and the second dam pattern 1153 can extend facing each other, and an extension region 1352R in which an extended portion of a lower molding portion is located can be disposed between the first dam pattern 1151 and the second dam pattern 1153. A vent hole 1100H can be arranged between the first dam pattern 1151 and the second dam pattern 1153. The first dam pattern 1151 and the second dam pattern 1153 can substantially reduce, prevent, or suppress contamination of the ball bump 1130 due to mold flash.

[0066] Figure 17 and Figure 18 is a schematic cross-sectional view illustrating a semiconductor package 20 according to an embodiment of the disclosure, and Figure 19 is a schematic plan view illustrating an extended portion 2352 of a lower molding portion of the semiconductor package 20 of Figure 17 and a planar arrangement shape of a dam pattern 2150.

[0067] Referring to Figure 17 and Figure 18 , the semiconductor package 20 can include a package substrate 2100S, a semiconductor chip 2200, and a molding layer 2300. The semiconductor chip 2200 can be electrically and physically connected to the package substrate 2100S by internal connectors 2210. The package substrate 2100S can include a vent hole 2100H passing therethrough. The molding layer 2300 can be disposed in a structure having an upper molding portion 2310 and a lower molding portion 2350. The lower molding portion 2350 can be connected to the upper molding portion 2310 by the vent hole 2100H. The upper molding portion 2310 can encapsulate the semiconductor chip 2200. The lower molding portion 2350 can include a filled portion 2351 filling the vent hole 2100H and an extended portion 2352 located below the package substrate 2100S.

[0068] The package substrate 2100S can include a substrate body 2100, a first dielectric layer 2160, and a second dielectric layer 2170 disposed on the substrate body 2100. The substrate body 2100 can have a first surface 2101 and a second surface 2102 on opposite sides of each other. Spherical bosses 2130 and a dam pattern 2150 can be disposed below the second surface 2102 of the substrate body 2100. Each of the dam patterns 2150 can include a first dam pattern 2151 and a second dam pattern 2153 facing each other.

[0069] Referring to Figure 19 , the spherical bosses 2130 can be disposed on the second surface 2102 of the substrate body 2100 of the package substrate 2100S, and the first dam pattern 2151 and the second dam pattern 2153 can be disposed to be spaced apart from the spherical bosses 2130.

[0070] The substrate body 2100 can include a first edge 2107 and a second edge 2108 each facing each other. The second surface 2102 can be disposed to connect the first edge 2107 and the second edge 2108 of the substrate body 2100. The first dam pattern 2151 and the second dam pattern 2153 can be linear patterns extending across the second surface 2102 to the first edge 2107 and the second edge 2108. The extended portion 2352 of the lower molding portion can extend to partially overlap with a portion between the first dam pattern 2151 and the second dam pattern 2153 of the substrate body 2100. The extended portion 2352 of the lower molding portion can have a shape extending across the second surface 2102 of the substrate body 2100 to the first edge 2107 and the second edge 2108.

[0071] The extended portion 2352 of the lower molding portion and the first dam pattern 2151 and the second dam pattern 2153 can be additionally used to reinforce the semiconductor package 20. Because the extended portion 2352 of the lower molding portion and the first dam pattern 2151 and the second dam pattern 2153 extend across the second surface 2102 of the substrate body 2100 to the first edge 2107 and the second edge 2108, the extended portion 2352 of the lower molding portion and the first dam pattern 2151 and the second dam pattern 2153 can be used to reinforce the semiconductor package 20 in the Y-axis direction. Accordingly, when an undesirable external force is applied to the semiconductor package 20, a bending phenomenon of the semiconductor package 20 can be substantially reduced, suppressed, or prevented.

[0072] The upper molding portion 2310 and the package substrate 2100S can have different coefficients of thermal expansion from each other. Due to the difference in the coefficients of thermal expansion of the upper molding portion 2310 and the package substrate 2100S, a stress that warps the semiconductor package 20 according to a temperature change can be generated. The extended portion 2352 of the lower molding portion and the first dam pattern 2151 and the second dam pattern 2153 can be used to alleviate or compensate for such a stress, or to reinforce the semiconductor package 20 so that the semiconductor package 20 resists such a stress.

[0073] According to embodiments of the disclosure, as described above, a dam pattern can be introduced into a package substrate and used as an element to improve mold leakage. The dam pattern can improve a contact state of a mold and a package substrate, thereby improving a phenomenon of leakage of a molding material from a mold cavity or a phenomenon causing mold overflow.

[0074] Figure 20is a block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to embodiments. The memory card 7800 can include a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 can include at least one of the semiconductor packages according to embodiments.

[0075] The memory 7810 can include a nonvolatile memory device to which a technology of embodiments of the present disclosure is applied. The memory controller 7820 can control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from a host 7830.

[0076] Figure 21 is a block diagram illustrating an electronic system 8710 including at least one of semiconductor packages according to embodiments. The electronic system 8710 can include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 can be coupled to each other through a bus 8715 that provides a path of data movement.

[0077] In embodiments, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 can include at least one of the semiconductor packages according to embodiments of the present disclosure. The input / output device 8712 can include at least one selected from among a keypad, a keyboard, a display device, a touchscreen, etc. The memory 8713 can be a device for storing data. The memory 8713 can store data and / or commands to be executed by the controller 8711, etc.

[0078] The memory 8713 can include a volatile memory device such as a DRAM and / or a nonvolatile memory device such as a flash memory. For example, a flash memory can be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory can constitute a solid state disk (SSD). In this case, the electronic system 8710 is capable of stably storing a large amount of data in the flash memory system.

[0079] The electronic system 8710 can further include an interface 8714 configured to transmit and receive data to and from a communication network. The interface 8714 can be of a wired or wireless type. For example, the interface 8714 can include an antenna or a wired or wireless transceiver.

[0080] The electronic system 8710 can be implemented as a logic system, a mobile system, a personal computer, or an industrial computer that performs various functions. For example, the mobile system can be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0081] If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can be used in a communication system using a technology of CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0082] The inventive concept has been disclosed in connection with some embodiments as described above. Those skilled in the art will understand that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed in the specification should be considered as illustrative and not restrictive, and the scope of the inventive concept is not limited to the above description as defined by the appended claims, and all unique features in the equivalent range should be interpreted as included in the inventive concept.

[0083] Cross Reference to Related Applications

[0084] This application claims priority to Korean Application No. 10-2020-0095470, filed on July 30, 2020, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package comprising: A packaging substrate having a vent hole formed through the packaging substrate; A semiconductor chip, wherein the semiconductor chip is disposed on the packaging substrate; as well as A molding layer, the molding layer including an upper molding portion for encapsulating the semiconductor chip and a lower molding portion connected to the upper molding portion through the vent hole. The packaging substrate includes: A substrate body, the substrate body comprising a plurality of unit regions, the plurality of unit regions having the vent holes disposed therethrough; A spherical boss, wherein the spherical boss is disposed in each of the unit regions of the substrate body; and A first dam pattern and a second dam pattern, the first dam pattern and the second dam pattern being spaced apart from the spherical boss of the substrate body, extending across the unit region, and further extending into the edge region of the substrate body located outside the unit region. The packaging substrate further includes a dielectric layer that extends to cover the substrate body, the first dam pattern and the second dam pattern are covered and some portions of the spherical boss are exposed through the dielectric layer.

2. The semiconductor package according to claim 1, wherein, The lower molded portion extends across the unit region to partially overlap with the space between the first dam pattern and the second dam pattern, and further extends into the edge region of the substrate body located outside the unit region.

3. The semiconductor package according to claim 1, wherein, The vent is disposed between the first dam pattern and the second dam pattern on the packaging substrate.

4. The semiconductor package according to claim 1, wherein, The first dam pattern and the second dam pattern comprise linear patterns that extend while facing each other.

5. The semiconductor package of claim 1, further comprising a third dam pattern connecting the edge portions of the first dam pattern and the second dam pattern.

6. The semiconductor package according to claim 5, wherein, The third dam pattern is set in the edge region of the substrate body.

7. The semiconductor package according to claim 1, wherein, The dielectric layer includes a solder resist material.

8. The semiconductor package according to claim 1, wherein, The first dam pattern, the second dam pattern, and the spherical boss all consist of the same metallic material.

9. The semiconductor package according to claim 8, wherein, The first dam pattern, the second dam pattern, and the spherical boss all comprise copper (Cu).

10. The semiconductor package according to claim 1, in, The substrate body includes a first surface and a second surface on opposite sides of each other. The semiconductor chip is disposed on the first surface, and The spherical boss, the first dam pattern, and the second dam pattern are disposed below the second surface.

11. The semiconductor package according to claim 1, wherein, The edge region of the substrate body includes the portion between the outermost unit region among the plurality of unit regions and the edge of the substrate body.

12. The semiconductor package according to claim 1, wherein, The vent overlaps with the semiconductor chip.

13. A semiconductor package comprising: A packaging substrate having a vent hole formed through the packaging substrate; A semiconductor chip, wherein the semiconductor chip is disposed on the packaging substrate; as well as A molding layer, the molding layer including an upper molding portion for encapsulating the semiconductor chip and a lower molding portion connected to the upper molding portion through the vent hole. The packaging substrate includes: A substrate body, the substrate body including a first edge and a second edge on opposite sides of each other and a surface between the first edge and the second edge; A spherical boss, the spherical boss being disposed on the surface of the substrate body; and A first dam pattern and a second dam pattern, spaced apart from the spherical boss, extend across the surface to the first edge and the second edge, respectively. The packaging substrate further includes a dielectric layer that extends to cover the surface of the substrate body, wherein the first dam pattern and the second dam pattern are covered and some portions of the spherical boss are exposed through the dielectric layer.

14. The semiconductor package of claim 13, wherein, The lower molded portion extends across the surface of the substrate body to the first edge and the second edge, and crosses the cell region to partially overlap with the space between the first dam pattern and the second dam pattern.

15. The semiconductor package of claim 14, wherein, The vent is disposed between the first dam pattern and the second dam pattern on the packaging substrate.

16. The semiconductor package of claim 14, wherein, The first dam pattern and the second dam pattern comprise linear patterns extending to face each other.

17. The semiconductor package of claim 14, wherein, The first dam pattern, the second dam pattern, and the spherical boss all consist of the same metallic material.

18. The semiconductor package of claim 14, wherein, The vent overlaps with the semiconductor chip.

19. A method for manufacturing a semiconductor package, the method comprising the following steps: A semiconductor chip is disposed on a packaging substrate having vents passing through the packaging substrate. The packaging substrate includes: a substrate body having a plurality of cell regions; a spherical boss disposed in the cell regions of the substrate body; a first dam pattern and a second dam pattern spaced apart from the spherical boss of the substrate body and extending across the cell regions, and further extending into an edge region of the substrate body located outside the cell regions; and a dielectric layer extending to cover the substrate body to cover the first dam pattern and the second dam pattern and leave some portions of the spherical bosses open. The packaging substrate is loaded into a mold recess, the mold recess including an upper mold and a lower mold, the upper mold providing an upper cavity in which the semiconductor chip will be located, and the lower mold providing a lower cavity connected to the vent hole; and The molding layer is molded into the upper molding portion by filling the upper cavity, and the molding layer is molded into the lower molding portion by filling the lower cavity while connecting it to the upper molding portion through the vent hole. The lower mold includes a side with an upper end, the upper end overlapping the first dam pattern and the second dam pattern of the packaging substrate and contacting the surface of the dielectric layer to close the lower cavity.

20. The method according to claim 19, wherein, The lower molded portion fills the lower cavity to be molded into a shape that partially overlaps with the space between the first dam pattern and the second dam pattern of the substrate body. The lower molded portion extends across the cell region and further extends into the edge region of the substrate body located outside the cell region.

21. The method according to claim 19, wherein, The vent is located between the first dam pattern and the second dam pattern.

22. The method according to claim 19, wherein, The first dam pattern and the second dam pattern comprise linear patterns extending to face each other.

23. The method according to claim 19, The semiconductor package further includes a third dam pattern that connects the edge portions of the first dam pattern and the second dam pattern to each other, and in, The upper end of the side of the lower mold extends further to overlap with the third dam pattern.

24. The method according to claim 23, wherein, The third dam pattern is set in the edge portion of the substrate body.

25. The method according to claim 19, wherein, The dielectric layer includes a solder resist material.

26. The method according to claim 19, wherein, The first dam pattern, the second dam pattern, and the spherical boss all consist of the same metallic material.

27. The method according to claim 26, wherein, The first dam pattern, the second dam pattern, and the spherical boss all comprise copper (Cu).

28. The method according to claim 19, in, The substrate body includes a first surface and a second surface on opposite sides of each other. The semiconductor chip is disposed on the first surface, and The spherical boss, the first dam pattern, and the second dam pattern are disposed below the second surface.

29. The method according to claim 19, wherein, The edge region of the substrate body includes the portion between the outermost unit region among the plurality of unit regions and the edge of the substrate body.

30. The method according to claim 19, wherein, The vent overlaps with the semiconductor chip.

31. A semiconductor package comprising: A packaging substrate having a vent hole formed through the packaging substrate; A semiconductor chip, wherein the semiconductor chip is disposed on the packaging substrate; The packaging substrate includes: A substrate body, the substrate body comprising a plurality of unit regions, the plurality of unit regions having the vent holes disposed therethrough; A first dam pattern and a second dam pattern extend across the unit region and further into the edge region of the substrate body located outside the unit region; A dielectric layer covering the first dam pattern and the second dam pattern; and A lower mold, formed on the dielectric layer to align with the first dam pattern and the second dam pattern, The first dam pattern and the second dam pattern are formed of a material that is harder than the dielectric layer.

Images