Field effect transistor, method for manufacturing same, and layout in the process of forming same

Abstract

The present invention relates to a field effect transistor structure and semiconductor integrated circuit technology. The connection hole for leading out the gate structure is arranged on the formation region of one of multiple fin bodies or semiconductor wire bodies, and the connection holes for leading out the source and drain are located on the formation regions of different fin bodies or semiconductor wire bodies from the connection hole for leading out the gate structure. A gate capping layer is formed on the top of the gate structure formed on the same fin body or semiconductor wire body adjacent to the connection holes for leading out the source and drain. The gate capping layer protects the corresponding gate structure. Buried holes are formed on the source and drain on both sides of the connection hole for leading out the gate structure, and buried hole capping layers are formed on the buried holes. The buried hole capping layers protect the buried holes connecting the source and drain, increasing the semiconductor product density, avoiding short circuits, and improving the reliability of the field effect transistor.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuit technology, and particularly to a field effect transistor. Background Art

[0002] With the continuous development of semiconductor technology, the critical dimension is continuously reduced, and the device density is getting larger and larger. Three-dimensional devices have emerged as the times require. FinFET (Fin Field-Effect Transistor) is a three-dimensional device. Compared with planar transistors, the fin field effect transistor (FinFET) has a three-dimensional channel structure, so it has better on-current and off-current characteristics, and can also improve the short channel effect (SCE). The fin transistor generally includes a fin body, and the fin body is composed of nanorods or nanosheets formed on a semiconductor substrate. The gate structure covers the top surface and side surfaces of a part of the length of the fin body, and the surface of the fin body covered by the gate structure is used to form a channel, that is, channels are present on the top surface and two side surfaces of the fin body. The source region and the drain region are formed in the fin body on both sides of the gate structure.

[0003] Furthermore, at the 5nm process node and below, the fin field effect transistor application adopts a Gate-All-Around (GAA) structure of nanowire or nanosheet, which can further improve the short channel effect (SCE). The gate-all-around structure includes a wire body formed on a semiconductor substrate, and the channel region of the semiconductor device is formed in the wire body. A metal gate (MG) completely wraps the wire body to form a gate structure, and the source region and the drain region are formed in the wire body on both sides of the gate structure. The GAA structure can effectively improve the short channel effect (SCE) of the device.

[0004] Please refer to Figure 1 , Figure 1 which is a layout schematic diagram of a fin field effect transistor or a gate-all-around structure field effect transistor in the prior art. As Figure 1 shown, multiple fin bodies or wire bodies 110 are arranged in parallel, multiple polysilicon gate rows 120 are arranged in parallel and intersect with multiple fin bodies or wire bodies 110. The overlapping area between the polysilicon gate rows 120 and the fin bodies or wire bodies 110, that is, the area shown by the dotted box 140, is the area of the gate structure of the field effect transistor. The gate structure is a polysilicon gate structure or a metal gate structure. The source region and the drain region are formed on the fin body or wire body 110 and are located on both sides of the gate structure. Then, the source region, the drain region, and the gate structure are respectively led out through the first connection hole 131, the second connection hole 132, and the third connection hole 133. As Figure 1As shown, the source region is led out to the first metal line 151 through the first connection hole 131, the drain region is led out to the second metal line 152 through the second connection hole 132, and the gate structure is led out through the third connection hole 133. In the prior art, the third connection hole 133 for leading out the gate structure is located on the polysilicon gate row 120 outside the diffusion region, thus increasing the area of the field effect transistor, such as the area shown by the dashed box 160 in Figure 1 , which is contrary to the demand for high-integration semiconductor devices and reduces the device density. SUMMARY OF THE INVENTION

[0005] The present invention provides a field effect transistor, including: a semiconductor substrate, on which a plurality of fin bodies or semiconductor wire bodies are formed, and the plurality of fin bodies or semiconductor wire bodies are arranged in parallel; a plurality of polysilicon gate rows, the plurality of polysilicon gate rows are arranged in parallel, and the plurality of polysilicon gate rows intersect with the plurality of fin bodies or semiconductor wire bodies, and gate structures of the field effect transistor are formed in the overlapping regions between the plurality of fin bodies or semiconductor wire bodies and the plurality of polysilicon gate rows; a source electrode and a drain electrode, the source electrode and the drain electrode are formed on the plurality of fin bodies or semiconductor wire bodies and are located on both sides of the gate structure; and an interlayer dielectric layer, the interlayer dielectric layer fills the gaps between the plurality of polysilicon gate rows and the plurality of fin bodies or semiconductor wire bodies on the semiconductor substrate and covers the gate structure, and a first connection hole, a second connection hole, a third connection hole, a first buried hole and a second buried hole are formed in the interlayer dielectric layer, wherein the first connection hole and the second connection hole are located in the formation region of the first fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies to respectively lead out the source electrode and the drain electrode formed on the first fin body or semiconductor wire body, and a gate capping layer is formed on the top of the gate structure formed on the first fin body or semiconductor wire body adjacent to the first connection hole and the second connection hole, the third connection hole is located in the formation region of the second fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies and is connected to the gate structure formed on the second fin body or semiconductor wire body to lead out the gate structure, and the first buried hole is formed on the source electrode on one side of the gate structure, the second buried hole is formed on the drain electrode on the other side of the gate structure, and a buried hole capping layer is formed on the first buried hole and the second buried hole.

[0006] Furthermore, the third connection hole is arranged on the diffusion region.

[0007] Furthermore, the first connection hole and the second connection hole for leading out the source electrode and the drain electrode are spatially misaligned with the third connection hole for leading out the gate structure.

[0008] Furthermore, the semiconductor substrate and the plurality of fin bodies or semiconductor wire bodies are made of the same material.

[0009] Further, the gate structure is a metal gate structure, including a stacked structure of a gate dielectric layer and a metal gate, and the gate capping layer is formed on the stacked structure.

[0010] Further, the material of the gate capping layer is silicon nitride.

[0011] Further, the third connection hole contacts the metal gate of the gate structure to lead out the gate structure to form the gate of the field effect transistor.

[0012] Further, the multiple fin bodies or semiconductor line bodies are semiconductor line bodies, and the gate dielectric layer and the metal gate cover the peripheral sides of the semiconductor line bodies to form a gate structure with gate wrap-around. The gate structure with gate wrap-around and the source and drain together form a gate-all-around field effect transistor.

[0013] Further, the multiple fin bodies or semiconductor line bodies are fin bodies, and the gate dielectric layer and the metal gate form a fin-type gate structure with the fin bodies. The fin-type gate structure and the source and drain together form a fin field effect transistor.

[0014] Further, the material of the buried hole capping layer is silicon oxide.

[0015] Further, the third connection hole is formed in the region where the second fin body or semiconductor line body intersects with the polysilicon gate row intersecting therewith, and is located on the gate structure formed in this overlapping region, so that the third connection hole contacts the gate structure formed in this overlapping region to lead out the gate structure.

[0016] Further, the field effect transistor is a device with a process node below 7nm.

[0017] The present invention further provides a layout of a field effect transistor, including: a plurality of fin bodies or semiconductor wire bodies, the plurality of fin bodies or semiconductor wire bodies being arranged in parallel; a plurality of polysilicon gate rows, the plurality of polysilicon gate rows being arranged in parallel, and the plurality of polysilicon gate rows intersecting with the plurality of fin bodies or semiconductor wire bodies, and the overlapping regions between the plurality of fin bodies or semiconductor wire bodies and the plurality of polysilicon gate rows are used to form a gate structure of the field effect transistor; a source electrode and a drain electrode, the source electrode and the drain electrode being formed on the plurality of fin bodies or semiconductor wire bodies and located on both sides of the gate structure; a first connection hole and a second connection hole are located on the formation region of the first fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies to respectively lead out the source electrode and the drain electrode formed on the first fin body or semiconductor wire body; and a third connection hole is located on the formation region of the second fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies and is connected to the gate structure formed on the second fin body or semiconductor wire body to lead out the gate structure.

[0018] Furthermore, the third connection hole is disposed on the diffusion region.

[0019] Furthermore, the first connection hole and the second connection hole for leading out the source electrode and the drain electrode are spatially misaligned with the third connection hole for leading out the gate structure.

[0020] Furthermore, the third connection hole is formed in the overlapping region between the second fin body or semiconductor wire body and the polysilicon gate row intersecting therewith and is located on the gate structure formed in the overlapping region, so that the third connection hole is in contact with the gate structure formed in the overlapping region to lead out the gate structure.

[0021] The present invention also lies in providing a manufacturing method of the above-mentioned field-effect transistor, comprising: S1: providing a semiconductor substrate, and forming a plurality of fin bodies or semiconductor wire bodies on the semiconductor substrate, wherein the plurality of fin bodies or semiconductor wire bodies are arranged in parallel; S2: forming a plurality of polysilicon gate rows, wherein the plurality of polysilicon gate rows are arranged in parallel, and the plurality of polysilicon gate rows intersect with the plurality of fin bodies or semiconductor wire bodies, and a gate structure of the field-effect transistor is formed in an overlapping area between the plurality of fin bodies or semiconductor wire bodies and the plurality of polysilicon gate rows; S3: forming a source electrode and a drain electrode on the plurality of fin bodies or semiconductor wire bodies, and the source electrode and the drain electrode are located on both sides of the gate structure; S4: forming a first interlayer dielectric layer and performing planarization, wherein the first interlayer dielectric layer fills a gap between the plurality of polysilicon gate rows and the plurality of fin bodies or semiconductor wire bodies on the semiconductor substrate and covers the gate structure; S5: performing a photolithography etching process to etch off the top of the gate structure to form a groove at the top of the gate structure; S6: forming a first material layer and performing planarization to make the first material layer fill the groove located at the top of the gate structure, thereby forming a gate capping layer located at the top of the gate structure; S7: performing a photolithography etching process on the first interlayer dielectric layer to form vias on the source electrode and the drain electrode, filling a conductive material in the vias, and performing planarization; S8: performing a photolithography etching process to etch off the top of the vias located on the source electrode and the drain electrode to form grooves at the tops of the vias; S9: forming a second material layer and performing planarization to make the second material layer fill the grooves located at the tops of the vias, so that the via formed on the source electrode forms a first buried via, the via formed on the drain electrode forms a second buried via, and the second material layer filled in the grooves located at the tops of the first buried via and the second buried via constitutes a buried via capping layer;and S10: Form a second interlayer dielectric layer and perform planarization so that the second interlayer dielectric layer and the first interlayer dielectric layer together form an interlayer dielectric layer. Perform a photolithography and etching process until the buried via capping layer on the formation region of the first fin or semiconductor line among the multiple fins or semiconductor lines is etched away, and the gate capping layer on a gate structure on the formation region of the second fin or semiconductor line among the multiple fins or semiconductor lines is etched away. Form a conductive material layer and perform planarization to form a first connection hole and the second connection hole on the formation region of the first fin or semiconductor line among the multiple fins or semiconductor lines, so as to respectively lead out the source and drain formed on the first fin or semiconductor line, and a gate capping layer is formed on the top of the gate structure formed on the first fin or semiconductor line adjacent to the first connection hole and the second connection hole. And form a third connection hole on the formation region of the second fin or semiconductor line among the multiple fins or semiconductor lines to connect a gate structure formed on the second fin or semiconductor line, so as to lead out the gate structure. A first buried via is formed on the source on one side of the gate structure, a second buried via is formed on the drain on the other side of the gate structure, and a buried via capping layer is formed on the first buried via and the second buried via.

[0022] In this way, the third connection hole for leading out the gate structure is arranged on the formation region of one fin or semiconductor line among the multiple fins or semiconductor lines, that is, the third connection hole for leading out the gate structure is arranged on the diffusion region, rather than on the polysilicon gate row outside the diffusion region as in the prior art, thereby increasing the device density and improving the integration degree of the semiconductor device. And the first connection hole and the second connection hole for leading out the source and drain are located on the formation region of the first fin or semiconductor line, and the third connection hole for leading out the gate structure is located on the formation region of the second fin or semiconductor line, that is, the first connection hole and the second connection hole for leading out the source and drain are spatially misaligned with the third connection hole for leading out the gate structure, avoiding short circuit between them, improving the reliability of the field effect transistor. And a gate capping layer is formed on the top of the gate structure formed on the same fin or semiconductor line adjacent to the first connection hole and the second connection hole for leading out the source and drain, and the gate capping layer protects the corresponding gate structure, avoiding short circuit between the gate structure and the first connection hole and the second connection hole for leading out the source and drain. At the same time, buried vias are formed on the source and drain on both sides of the third connection hole for leading out the gate structure, and a buried via capping layer is formed on the buried vias, and the buried via capping layer protects the buried vias connecting the source and drain, avoiding short circuit between the third connection hole and the adjacent source and drain, and further improving the reliability of the field effect transistor. Description of the Drawings

[0023] Figure 1 It is a layout schematic diagram of a fin field-effect transistor or a gate-all-around structure field-effect transistor of the prior art.

[0024] Figure 2 It is a layout schematic diagram of a fin field-effect transistor or a gate-all-around structure field-effect transistor according to an embodiment of the present invention.

[0025] Figure 3 It is along the Figure 2 in the AA line of a field-effect transistor according to an embodiment of the present invention.

[0026] Figure 4 It is along the Figure 2 in the BB line of a field-effect transistor according to an embodiment of the present invention.

[0027] Figures 5 to 10 It is a cross-sectional schematic diagram along the AA line or the BB line during the formation process of a field-effect transistor according to an embodiment of the present invention. Figure 2 in the AA line or the BB line.

[0028] The description of the main component reference numerals in the figure is as follows:

[0029] 210, fin body or semiconductor wire body; 220, polysilicon gate row; 240, overlapping area; 231, first connection hole; 232, second connection hole; 233, third connection hole; 251, first metal wire; 252, second metal wire. Detailed implementation manners

[0030] Next, the technical solutions in the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] It should be understood that the terms "first", "second", etc. in the claims and the description of the present application are used to distinguish different objects, rather than to describe a specific order. The terms "including" and "comprising" used in the description and claims of the present application indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0032] In an embodiment of the present invention, it is to provide a field-effect transistor. Specifically, please refer to Figure 2 , Figure 2 which is a layout schematic diagram of a fin field-effect transistor or a gate-all-around structure field-effect transistor according to an embodiment of the present invention, and refer to Figure 3 andFigure 4 , Figure 3 is a schematic cross-sectional view of the AA line in a field-effect transistor according to an embodiment of the present invention, Figure 2 and Figure 4 is a schematic cross-sectional view of the BB line in a field-effect transistor according to an embodiment of the present invention. A field-effect transistor according to an embodiment of the present invention includes: Figure 2

[0033] a semiconductor substrate, on which a plurality of fin bodies or semiconductor wire bodies 210 are formed, and the plurality of fin bodies or semiconductor wire bodies 210 are arranged in parallel;

[0034] a plurality of polysilicon gate rows 220, the plurality of polysilicon gate rows 220 are arranged in parallel, and the plurality of polysilicon gate rows 220 intersect with the plurality of fin bodies or semiconductor wire bodies 210, and a gate structure 270 of the field-effect transistor is formed in the overlapping region 240 between the plurality of fin bodies or semiconductor wire bodies 210 and the plurality of polysilicon gate rows 220;

[0035] a source electrode 261 and a drain electrode 262, the source electrode 261 and the drain electrode 262 are formed on the plurality of fin bodies or semiconductor wire bodies 210 and are located on both sides of the gate structure 270;

[0036] an interlayer dielectric layer 310, the interlayer dielectric layer 310 fills the gaps between the plurality of polysilicon gate rows 220 and the plurality of fin bodies or semiconductor wire bodies 210 on the semiconductor substrate and covers the gate structure 270. A first connection hole 231, a second connection hole 232, a third connection hole 233, a first buried hole 234 and a second buried hole 235 are formed in the interlayer dielectric layer 310. The first connection hole 231 and the second connection hole 232 are located on the formation region of the first fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies to respectively lead out the source electrode 261 and the drain electrode 262 formed on the first fin body or semiconductor wire body, and a gate capping layer 274 is formed on the top of the gate structure 270 adjacent to the first connection hole 231 and the second connection hole 232 and formed on the first fin body or semiconductor wire body. The third connection hole 233 is located on the formation region of the second fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies and is connected to the gate structure 270 formed on the second fin body or semiconductor wire body to lead out the gate structure 270, and a first buried hole 234 is formed on the source electrode 261 on one side of the gate structure 270, and a second buried hole 235 is formed on the drain electrode 262 on the other side of the gate structure 270. A buried hole capping layer 281 is formed on the first buried hole 234 and the second buried hole 235.

[0037] ​Thus, the third connection hole for leading out the gate structure is disposed on the formation region of one of the plurality of fins or semiconductor line bodies, that is, the third connection hole for leading out the gate structure is disposed on the diffusion region, rather than Figure 1 being disposed on the polysilicon gate row outside the diffusion region as in the prior art described, compared with Figure 1 the prior art shown, the present invention saves Figure 1 the area shown by the dashed box in, thereby increasing the device density, improving the integration degree of the semiconductor device, and enabling the first connection hole and the second connection hole for leading out the source and drain to be located on the formation region of the first fin or semiconductor line body, and enabling the third connection hole for leading out the gate structure to be located on the formation region of the second fin or semiconductor line body, that is, the first connection hole and the second connection hole for leading out the source and drain are spatially misaligned with the third connection hole for leading out the gate structure, avoiding short - circuiting between them, improving the reliability of the field - effect transistor, and a gate capping layer is formed on the top of the gate structure adjacent to the first connection hole and the second connection hole for leading out the source and drain and formed on the same fin or semiconductor line body, and the gate capping layer protects the corresponding gate structure, thus avoiding short - circuiting between the gate structure and the first connection hole and the second connection hole for leading out the source and drain. At the same time, buried vias are formed on the source and drain on both sides of the third connection hole for leading out the gate structure, and a buried via capping layer is formed on the buried vias, and the buried via capping layer protects the buried vias connecting the source and drain, thus avoiding short - circuiting between the third connection hole and the adjacent source and drain, further improving the reliability of the field - effect transistor.

[0038] In an embodiment of the present invention, the semiconductor substrate has the same material as the plurality of fins or semiconductor line bodies 210, such as silicon, that is, the plurality of fins or semiconductor line bodies 210 are formed by the substrate or an epitaxial layer formed on the substrate. In an embodiment of the present invention, a plurality of fins are formed by photolithography and etching of the semiconductor substrate, or at least one stacked layer including a germanium - silicon epitaxial layer and a silicon epitaxial layer is first formed on the surface of the semiconductor substrate, a plurality of fins are formed by photolithography and etching, and then a germanium - silicon etching process is performed to remove the germanium - silicon epitaxial layer in the fins, forming semiconductor line bodies formed by the silicon epitaxial layer.

[0039] In an embodiment of the present invention, the parallel arrangement of the plurality of fins or semiconductor line bodies 210 means that the plurality of fins or semiconductor line bodies 210 do not cross each other, but there may be a certain angle between them, or the plurality of fins or semiconductor line bodies 210 may be parallel to each other.

[0040] In an embodiment of the present invention, the parallel arrangement of the plurality of polysilicon gate rows 220 means that the plurality of polysilicon gate rows 220 do not cross each other, but there may be a certain angle between them, or the plurality of polysilicon gate rows 220 may be parallel to each other.

[0041] In one embodiment of the present invention, the gate structure 270 is a metal gate structure, including a stacked structure of a gate dielectric layer 271 and a metal gate 272. Further, a work function layer (not shown in the figure) may also be included between the gate dielectric layer 271 and the metal gate 272. In one embodiment of the present invention, sidewalls 273 are formed on both sides of the stacked structure of the gate dielectric layer 271 and the metal gate 272. In one embodiment of the present invention, an interface layer 275 is further included between the gate structure 270 and multiple fin bodies or semiconductor line bodies 210.

[0042] In one embodiment of the present invention, a gate capping layer 274 is formed on the stacked structure of the gate dielectric layer 271 and the metal gate 272. In one embodiment of the present invention, the material of the gate capping layer 274 is silicon nitride (SiN).

[0043] In one embodiment of the present invention, the third via 233 is in contact with the metal gate 272 of the gate structure 270 to lead out the gate structure 270 to form the gate of the field effect transistor.

[0044] In one embodiment of the present invention, the multiple fin bodies or semiconductor line bodies 210 are semiconductor line bodies, and the gate dielectric layer 271 and the metal gate 272 cover the peripheral sides of the semiconductor line bodies to form a gate structure with gate surround. The gate structure with gate surround and the source and drain together form a gate-all-around structure field effect transistor; the multiple fin bodies or semiconductor line bodies 210 are fin bodies, and the gate dielectric layer 271 and the metal gate 272 form a fin-type gate structure with the fin bodies. The fin-type gate structure and the source and drain together form a fin-type field effect transistor.

[0045] In one embodiment of the present invention, the material of the buried via capping layer 281 is silicon oxide, such as silicon dioxide (SiO2).

[0046] In one embodiment of the present invention, the conductive material in the first via 231, the second via 232, the third via 233, the first buried via 234, and the second buried via 235 is tungsten (W), cobalt (Co), or copper (Cu).

[0047] In one embodiment of the present invention, the third via 233 is formed in the overlapping region between the second fin body or semiconductor line body and the polysilicon gate row 220 intersecting therewith, and is located on the gate structure formed in the overlapping region, so that the third via 233 is in contact with the gate structure formed in the overlapping region to lead out the gate structure.

[0048] In one embodiment of the present invention, the first via 231 leads out the source to the first metal line 251, and the second via 232 leads out the drain to the second metal line 252.

[0049] In one embodiment of the present invention, the above-mentioned field effect transistor is a device with a process node of less than 7 nm.

[0050] In an embodiment of the present invention, a layout of a field effect transistor is further provided. As Figure 2 shown, the layout includes:

[0051] Multiple fin bodies or semiconductor wire bodies 210, and the multiple fin bodies or semiconductor wire bodies 210 are arranged in parallel;

[0052] Multiple polysilicon gate rows 220, the multiple polysilicon gate rows 220 are arranged in parallel, and the multiple polysilicon gate rows 220 intersect with the multiple fin bodies or semiconductor wire bodies 210. The overlapping region 240 between the multiple fin bodies or semiconductor wire bodies 210 and the multiple polysilicon gate rows 220 is used to form the gate structure of the field effect transistor;

[0053] A source electrode and a drain electrode, the source electrode and the drain electrode are formed on the multiple fin bodies or semiconductor wire bodies 210 and are located on both sides of the gate structure;

[0054] A first connection hole 231 and a second connection hole 232 are located on the formation region of the first fin body or semiconductor wire body among the multiple fin bodies or semiconductor wire bodies 210 to lead out the source electrode and the drain electrode formed on the first fin body or semiconductor wire body respectively;

[0055] A third connection hole 233 is located on the formation region of the second fin body or semiconductor wire body among the multiple fin bodies or semiconductor wire bodies 210 and is connected to the gate structure formed on the second fin body or semiconductor wire body to lead out the gate structure.

[0056] In this way, the third connection hole for leading out the gate structure is arranged on the formation region of one of the multiple fin bodies or semiconductor wire bodies, that is, the third connection hole for leading out the gate structure is arranged on the diffusion region, rather than Figure 1 being arranged on the polysilicon gate row outside the diffusion region as in the prior art described. Compared with Figure 1 the prior art shown, the present invention saves Figure 1 the region shown by the dashed box in, thereby increasing the device density, improving the integration degree of the semiconductor device, and making the first connection hole and the second connection hole for leading out the source electrode and the drain electrode located on the formation region of the first fin body or semiconductor wire body, and making the third connection hole for leading out the gate structure located on the formation region of the second fin body or semiconductor wire body. That is, the first connection hole and the second connection hole for leading out the source electrode and the drain electrode are spatially misaligned with the third connection hole for leading out the gate structure, avoiding short circuit between them and improving the reliability of the field effect transistor.

[0057] In an embodiment of the present invention, a third connection hole 233 is formed on a region where a second fin or a semiconductor wire intersects and overlaps with a polysilicon gate row 220 intersecting therewith, and is located on a gate structure formed on the overlapping region, so that the third connection hole 233 contacts the gate structure formed on the overlapping region to lead out the gate structure.

[0058] In one embodiment of the present invention, a method for manufacturing a field effect transistor is provided, including: S1: providing a semiconductor substrate, and forming a plurality of fin bodies or semiconductor wire bodies on the semiconductor substrate, wherein the plurality of fin bodies or semiconductor wire bodies are arranged in parallel; S2: forming a plurality of polysilicon gate rows, wherein the plurality of polysilicon gate rows are arranged in parallel, and the plurality of polysilicon gate rows intersect with the plurality of fin bodies or semiconductor wire bodies, and a gate structure of the field effect transistor is formed in an overlapping area between the plurality of fin bodies or semiconductor wire bodies and the plurality of polysilicon gate rows; S3: forming a source electrode and a drain electrode on the plurality of fin bodies or semiconductor wire bodies, and the source electrode and the drain electrode are located on both sides of the gate structure; S4: forming a first interlayer dielectric layer and performing planarization, wherein the first interlayer dielectric layer fills a gap between the plurality of polysilicon gate rows and the plurality of fin bodies or semiconductor wire bodies on the semiconductor substrate and covers the gate structure; S5: performing a photolithography etching process to etch off the top of the gate structure to form a groove on the top of the gate structure; S6: forming a first material layer and performing planarization to make the first material layer fill the groove located on the top of the gate structure, thereby forming a gate capping layer located on the top of the gate structure; S7: performing a photolithography etching process on the first interlayer dielectric layer to form through holes on the source electrode and the drain electrode, filling a conductive material in the through holes, and performing planarization; S8: performing a photolithography etching process to etch off the top of the through holes located on the source electrode and the drain electrode to form grooves on the top of the through holes; S9: forming a second material layer and performing planarization to make the second material layer fill the grooves located on the top of the through holes, so that a first buried hole is formed by the through hole formed on the source electrode, a second buried hole is formed by the through hole formed on the drain electrode, and the second material layer filled in the grooves located on the tops of the first buried hole and the second buried hole constitutes a buried hole capping layer;S10: Form a second interlayer dielectric layer and perform planarization so that the second interlayer dielectric layer and the first interlayer dielectric layer together constitute an interlayer dielectric layer. Perform a lithography and etching process until the buried via capping layer on the formation region of the first fin or semiconductor wire among the multiple fins or semiconductor wires is etched away, and the gate capping layer on a gate structure on the formation region of the second fin or semiconductor wire among the multiple fins or semiconductor wires is etched away. Form a conductive material layer and perform planarization to form a first connection hole and a second connection hole on the formation region of the first fin or semiconductor wire among the multiple fins or semiconductor wires, so as to respectively lead out the source and drain formed on the first fin or semiconductor wire, and a gate capping layer is formed on the top of the gate structure formed on the first fin or semiconductor wire adjacent to the first connection hole and the second connection hole. And form a third connection hole on the formation region of the second fin or semiconductor wire among the multiple fins or semiconductor wires to connect a gate structure formed on the second fin or semiconductor wire, so as to lead out the gate structure. A first buried via is formed on the source on one side of the gate structure, a second buried via is formed on the drain on the other side of the gate structure, and a buried via capping layer is formed on the first buried via and the second buried via.;

[0059] Specifically, please refer to Figures 5 to 10 , Figures 5 to 10 which is a cross-sectional schematic view along the AA line or BB line during the formation process of a field-effect transistor according to an embodiment of the present invention. And please combine Figure 2 with Figures 2 to 4 The manufacturing method of the field-effect transistor of the present invention includes:

[0060] S1: As Figure 2 shown, provide a semiconductor substrate, and form multiple fins or semiconductor wires 210 on the semiconductor substrate. The multiple fins or semiconductor wires 210 are arranged in parallel;

[0061] In an embodiment of the present invention, the semiconductor substrate and the multiple fins or semiconductor wires 210 are made of the same material, such as silicon, that is, the multiple fins or semiconductor wires 210 are formed by the substrate or an epitaxial layer formed on the substrate. In an embodiment of the present invention, multiple fins are formed by performing lithography and etching on the semiconductor substrate, or at least one stacked layer formed by a germanium-silicon epitaxial layer and a silicon epitaxial layer is first formed on the surface of the semiconductor substrate, multiple fins are formed by lithography and etching, and then a germanium-silicon etching process is performed to remove the germanium-silicon epitaxial layer in the fins to form semiconductor wires formed by the silicon epitaxial layer.

[0062] In one embodiment of the present invention, the parallel arrangement of multiple fin bodies or semiconductor wire bodies 210 means that the multiple fin bodies or semiconductor wire bodies 210 do not cross each other, but there may be a certain angle between them, or they may be parallel to each other.

[0063] S2: As Figure 2 and Figure 5 shown, multiple polysilicon gate rows 220 are formed. The multiple polysilicon gate rows 220 are arranged in parallel, and the multiple polysilicon gate rows 220 cross the multiple fin bodies or semiconductor wire bodies 210. A gate structure 270 of a field effect transistor is formed in the overlapping region 240 between the multiple fin bodies or semiconductor wire bodies 210 and the multiple polysilicon gate rows 220;

[0064] In one embodiment of the present invention, the gate structure 270 is a metal gate structure, including a stacked structure of a gate dielectric layer 271 and a metal gate 272. Further, a work function layer (not shown in the figure) may also be included between the gate dielectric layer 271 and the metal gate 272. In one embodiment of the present invention, sidewalls 273 are formed on both sides of the stacked structure of the gate dielectric layer 271 and the metal gate 272. In one embodiment of the present invention, an interface layer 275 is further included between the gate structure 270 and the multiple fin bodies or semiconductor wire bodies 210.

[0065] In one embodiment of the present invention, the parallel arrangement of multiple polysilicon gate rows 220 means that the multiple polysilicon gate rows 220 do not cross each other, but there may be a certain angle between them, or they may be parallel to each other.

[0066] S3: As Figure 5 shown, a source electrode 261 and a drain electrode 262 are formed on the multiple fin bodies or semiconductor wire bodies 210, and the source electrode 261 and the drain electrode 262 are located on both sides of the gate structure 270;

[0067] In one embodiment of the present invention, the multiple fin bodies or semiconductor wire bodies 210 are semiconductor wire bodies, and the gate dielectric layer 271 and the metal gate 272 cover the peripheral sides of the semiconductor wire bodies to form a gate-all-around gate structure. The gate-all-around gate structure and the source electrode and the drain electrode together constitute a gate-all-around structure field effect transistor; the multiple fin bodies or semiconductor wire bodies 210 are fin bodies, and the gate dielectric layer 271 and the metal gate 272 form a fin-type gate structure with the fin bodies. The fin-type gate structure and the source electrode and the drain electrode together constitute a fin-type field effect transistor.

[0068] S4: As Figure 5 shown, a first interlayer dielectric layer 311 is formed and planarized. The first interlayer dielectric layer 311 fills the gaps between the multiple polysilicon gate rows 220 and the multiple fin bodies or semiconductor wire bodies on the semiconductor substrate and covers the gate structure 270;

[0069] S5: As shown in Figure 6 , perform a photolithography etching process to etch off the top of the gate structure to form a groove 291 on the top of the gate structure;

[0070] S6: As shown in Figure 7 , and refer to Figure 6 , form a first material layer and perform planarization so that the first material layer fills the groove 291 located on the top of the gate structure, thereby forming a gate capping layer 274 on the top of the gate structure;

[0071] In an embodiment of the present invention, the gate capping layer 274 is formed on a stacked structure of a gate dielectric layer 271 and a metal gate 272. In an embodiment of the present invention, the material of the gate capping layer 274 is silicon nitride (SiN), that is, the material of the first material layer is silicon nitride (SiN).

[0072] S7: As shown in Figure 8 , perform a photolithography etching process on the first interlayer dielectric layer 311 to form a via 2311 on the source 261 and the drain 262, fill the via with a conductive material, and perform planarization;

[0073] S8: As shown in Figure 9 , perform a photolithography etching process to etch off the top of the via 2311 located on the source 261 and the drain 262 to form a groove 292 on the top of the via 2311;

[0074] S9: As shown in Figure 10 , form a second material layer and perform planarization so that the second material layer fills the groove 292 located on the top of the via 2311, thereby forming a first buried via 234 from the via 2311 formed on the source 261 and forming a second buried via 235 from the via 2311 formed on the drain 262, and the second material layer filled in the groove on the top of the first buried via 234 and the second buried via 235 constitutes a buried via capping layer 281;

[0075] In an embodiment of the present invention, the material of the buried via capping layer 281 is silicon oxide, such as silicon dioxide (SiO2), that is, the material of the second material layer is silicon oxide.

[0076] S10: As shown in Figure 3 and Figure 4As shown, a second interlayer dielectric layer is formed and planarized so that the second interlayer dielectric layer and the first interlayer dielectric layer together form the interlayer dielectric layer 310. A photolithography and etching process is carried out until the buried via capping layer 281 on the formation region of the first fin or semiconductor wire 210 among the multiple fins or semiconductor wires is etched away, and the gate capping layer 274 on a gate structure on the formation region of the second fin or semiconductor wire 210 among the multiple fins or semiconductor wires is etched away. A conductive material layer is formed and planarized to form a first via 231 and a second via 232 on the formation region of the first fin or semiconductor wire 210 among the multiple fins or semiconductor wires, so as to lead out the source 261 and the drain 262 formed on the first fin or semiconductor wire respectively, and a gate capping layer 274 is formed on the top of the gate structure formed on the first fin or semiconductor wire adjacent to the first via 231 and the second via 232. A third via 233 is formed on the formation region of the second fin or semiconductor wire 210 among the multiple fins or semiconductor wires to connect a gate structure formed thereon, so as to lead out the gate structure. A first buried via 234 is formed on the source 261 on one side of the gate structure, a second buried via 235 is formed on the drain 262 on the other side of the gate structure, and a buried via capping layer 281 is formed on the first buried via 234 and the second buried via 235.

[0077] In an embodiment of the present invention, the material of the conductive material layer is tungsten (W), cobalt (Co), or copper (Cu).

[0078] In an embodiment of the present invention, the third via 233 is formed in the overlapping region between the second fin or semiconductor wire and the polysilicon gate row 220 intersecting therewith, and is located on the gate structure formed in the overlapping region, so that the third via 233 contacts the gate structure formed in the overlapping region to lead out the gate structure. In an embodiment of the present invention, the third via 233 contacts the metal gate 272 of the gate structure 270 to lead out the gate structure 270 to form the gate of the field effect transistor.

[0079] In an embodiment of the present invention, the first via 231 leads out the source to the first metal wire 251, and the second via 232 leads out the drain to the second metal wire 252.

[0080] In an embodiment of the present invention, the above-mentioned field effect transistor is a device with a process node below 7nm.

[0081] As described above, the third connection hole for leading out the gate structure is disposed on the formation region of one of the plurality of fins or semiconductor line bodies, that is, the third connection hole for leading out the gate structure is disposed on the diffusion region, rather than Figure 1 being disposed on the polysilicon gate row outside the diffusion region as in the prior art described, compared with Figure 1 the prior art shown, the present invention saves the Figure 1 region shown by the dashed box in, thereby increasing the device density, improving the integration degree of the semiconductor device, and enabling the first connection hole and the second connection hole for leading out the source and drain to be located on the formation region of the first fin or semiconductor line body, and enabling the third connection hole for leading out the gate structure to be located on the formation region of the second fin or semiconductor line body, that is, the first connection hole and the second connection hole for leading out the source and drain are spatially misaligned with the third connection hole for leading out the gate structure, avoiding short-circuiting between them, improving the reliability of the field effect transistor, and a gate capping layer is formed on the top of the gate structure adjacent to the first connection hole and the second connection hole for leading out the source and drain and formed on the same fin or semiconductor line body, and the gate capping layer protects the corresponding gate structure, thus avoiding short-circuiting between the gate structure and the first connection hole and the second connection hole for leading out the source and drain. At the same time, buried vias are formed on the source and drain on both sides of the third connection hole for leading out the gate structure, and a buried via capping layer is formed on the buried vias, and the buried via capping layer protects the buried vias connecting the source and drain, thus avoiding short-circuiting between the third connection hole and the adjacent source and drain, and further improving the reliability of the field effect transistor.

[0082] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A field effect transistor, characterized in that, comprising: a semiconductor substrate, on which a plurality of fin bodies or semiconductor wire bodies are formed, and the plurality of fin bodies or semiconductor wire bodies are arranged in parallel; a plurality of polysilicon gate rows, the plurality of polysilicon gate rows are arranged in parallel, and the plurality of polysilicon gate rows intersect with the plurality of fin bodies or semiconductor wire bodies, and a gate structure of the field effect transistor is formed in an overlapping region between the plurality of fin bodies or semiconductor wire bodies and the plurality of polysilicon gate rows; a source electrode and a drain electrode, the source electrode and the drain electrode are formed on the plurality of fin bodies or semiconductor wire bodies and are located on both sides of the gate structure; and an interlayer dielectric layer, the interlayer dielectric layer fills a gap between the plurality of polysilicon gate rows and the plurality of fin bodies or semiconductor wire bodies on the semiconductor substrate and covers the gate structure, a first connection hole, a second connection hole, a third connection hole, a first buried hole and a second buried hole are formed in the interlayer dielectric layer, wherein the first connection hole and the second connection hole are located on a formation region of a first fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies to respectively lead out the source electrode and the drain electrode formed on the first fin body or semiconductor wire body, and a gate capping layer is formed on a top of the gate structure formed on the first fin body or semiconductor wire body adjacent to the first connection hole and the second connection hole, the third connection hole is located on a formation region of a second fin body or semiconductor wire body among the plurality of fin bodies or semiconductor wire bodies and is connected to the gate structure formed on the second fin body or semiconductor wire body to lead out the gate structure, the first buried hole is formed on the source electrode on one side of the gate structure, the second buried hole is formed on the drain electrode on the other side of the gate structure, and a buried hole capping layer is formed on the first buried hole and the second buried hole.

2. The field effect transistor according to claim 1, characterized in that, the third connection hole is arranged on a diffusion region.

3. The field effect transistor according to claim 1, characterized in that, the first connection hole and the second connection hole for leading out the source electrode and the drain electrode are spatially misaligned with the third connection hole for leading out the gate structure.

4. The field effect transistor according to claim 1, characterized in that, the semiconductor substrate has the same material as the plurality of fin bodies or semiconductor wire bodies.

5. The field effect transistor according to claim 1, characterized in that, the gate structure is a metal gate structure, including a stacked structure of a gate dielectric layer and a metal gate, and the gate capping layer is formed on the stacked structure.

6. The field effect transistor according to claim 1, characterized in that, the material of the gate capping layer is silicon nitride.

7. The field effect transistor according to claim 5, characterized in that, the third connection hole is in contact with the metal gate of the gate structure to lead out the gate structure to form a gate of the field effect transistor.

8. The field effect transistor according to claim 5, characterized in that, The multiple fin bodies or semiconductor wire bodies are semiconductor wire bodies. The gate dielectric layer and the metal gate wrap around the circumferential side of the semiconductor wire bodies to form a gate-all-around gate structure. The gate-all-around gate structure and the source and drain electrodes together constitute a gate-all-around field-effect transistor.

9. The field-effect transistor according to claim 5, wherein, the multiple fin bodies or semiconductor wire bodies are fin bodies. The gate dielectric layer and the metal gate form a fin gate structure with the fin bodies. The fin gate structure and the source and drain electrodes together constitute a fin field-effect transistor.

10. The field-effect transistor according to claim 1, wherein, the material of the buried via capping layer is silicon oxide.

11. The field-effect transistor according to claim 1, wherein, the third connection hole is formed in the overlapping region between the second fin body or semiconductor wire body and the polysilicon gate row intersecting therewith, and is located on the gate structure formed in this overlapping region, so that the third connection hole contacts the gate structure formed in this overlapping region to lead out the gate structure.

12. The field-effect transistor according to claim 1, wherein, the field-effect transistor is a device with a process node below 7 nm.

13. A layout of a field-effect transistor, wherein, it includes: multiple fin bodies or semiconductor wire bodies, and the multiple fin bodies or semiconductor wire bodies are arranged in parallel; multiple polysilicon gate rows, and the multiple polysilicon gate rows are arranged in parallel, and the multiple polysilicon gate rows intersect with the multiple fin bodies or semiconductor wire bodies. The overlapping regions between the multiple fin bodies or semiconductor wire bodies and the multiple polysilicon gate rows are used to form the gate structure of the field-effect transistor; a source and a drain, and the source and the drain are formed on the multiple fin bodies or semiconductor wire bodies and are located on both sides of the gate structure; a first connection hole and a second connection hole are located in the formation region of the first fin body or semiconductor wire body among the multiple fin bodies or semiconductor wire bodies to lead out the source and the drain formed on the first fin body or semiconductor wire body respectively; and a third connection hole is located in the formation region of the second fin body or semiconductor wire body among the multiple fin bodies or semiconductor wire bodies and is connected to the gate structure formed on the second fin body or semiconductor wire body to lead out the gate structure; the first connection hole and the second connection hole for leading out the source and the drain are spatially misaligned with the third connection hole for leading out the gate structure.

14. The layout of the field-effect transistor according to claim 13, wherein, the third connection hole is arranged on the diffusion region.

15. The layout of the field-effect transistor according to claim 13, wherein, the third connection hole is formed in the overlapping region between the second fin body or semiconductor wire body and the polysilicon gate row intersecting therewith, and is located on the gate structure formed in this overlapping region, so that the third connection hole contacts the gate structure formed in this overlapping region to lead out the gate structure.

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