Digital line formation for horizontally oriented access devices

Abstract

A system, method, and apparatus for forming a digital line for a horizontally oriented access device are provided. An example method includes forming layers of a first dielectric material, a low-doped semiconductor material, and a second dielectric material in a vertically repeated superposition manner to form a vertical stack; forming a vertical opening in the vertical stack; selectively etching the second dielectric material to form a horizontal opening in the second dielectric material; vapor-doping a dopant on a top surface of the low-doped semiconductor material in the horizontal opening to form a source / drain region; forming a highly doped semiconductor material in the horizontal opening; selectively etching the highly doped semiconductor material formed in the horizontal opening so that a portion of the highly doped semiconductor material remains; and converting the remaining highly doped semiconductor material into a conductive material having properties different from those of the remaining highly doped semiconductor material.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices and methods, and more particularly to digit line formation for horizontally oriented access devices. Background Art

[0002] Memory is often implemented in electronic systems such as computers, cellular phones, handheld devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory may provide persistent data by retaining stored data when power is not supplied, and may include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (such as phase change random access memory), resistive memory (such as resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), or the like.

[0003] As design rules shrink, less semiconductor space can be used to manufacture memories including DRAM arrays. A corresponding memory cell for a DRAM may include an access device, such as a transistor, having a first and a second source / drain region separated by a channel region. The gate may be opposite the channel region and separated from the channel region by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of the DRAM cell. The DRAM cell may include a storage node, such as a capacitor cell, coupled to a digital line through an access device. The access device may be activated (e.g., to select a cell) by an access line coupled to an access transistor. The capacitor may store a charge corresponding to a data value (e.g., a logical "1" or "0") of the corresponding cell. Summary of the invention

[0004] An aspect of the present disclosure provides a method for forming an array (101, 1010) of vertically stacked memory cells (110) having horizontally oriented access devices (230, 901) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840), comprising: forming a first dielectric material (430, 530, 630, 730, 830, 930), a low-doped semiconductor material (432, 532, 632, 732, 832), and a second dielectric material (433, 533, 833) in a vertically repeated iterative manner. 633, 733, 833) to form a vertical stack (401); forming a vertical opening (471) in the vertical stack (401); selectively etching the second dielectric material (433, 533, 633, 733, 833) to form a horizontal opening (473) in the second dielectric material (433, 533, 633, 733, 833); vapor-doping a dopant into the horizontal opening (473) The invention relates to a method for selectively etching the highly doped semiconductor material (482) formed in the horizontal opening (473) so as to retain a portion of the highly doped semiconductor material (482); and converting the remaining highly doped semiconductor material (482) into a conductive material (477) having properties different from those of the remaining highly doped semiconductor material (482).

[0005] Another aspect of the present disclosure provides a method for forming an array (101, 1010) of vertically stacked memory cells (110) having horizontally oriented access devices (230, 901) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840), comprising: forming a first dielectric material (430, 530, 630, 730, 830, 930), a low-doped semiconductor material (432, 532, 632, 732, 832), and a second dielectric material (433, 533, 833) in a vertically repeated iterative manner. The method comprises: selectively etching the second dielectric material (433, 533, 633, 733, 833) to form a vertical stack (401); forming a vertical opening (471) in the vertical stack (401); selectively etching the second dielectric material (433, 533, 633, 733, 833) to form a first horizontal opening (473) in the second dielectric material (433, 533, 633, 733, 833) horizontally back from the vertical opening (471) to a first distance (476); vapor-doping a dopant into a top surface (478) of the low-doped semiconductor material (432, 532, 632, 732, 832) in the first horizontal opening (473) to form a source / drain region (475, 775, 875, 975); and etching the first dielectric material (433, 533, 633, 733, 833) to form a first horizontal opening (473) in the second dielectric material (433, 533, 633, 733, 833) to form a source / drain region (475, 775, 875, 975); 73); selectively etching the first highly doped semiconductor material (482) formed in the first horizontal opening (473) so that a portion of the first highly doped semiconductor material (482) formed in the first horizontal opening (473) remains; converting the remaining first highly doped semiconductor material (482) into a conductive material (477) having properties different from the properties of the remaining highly doped semiconductor material (482), wherein the source / drain region (475, 775, 875, 975) remains intact during the conversion; selectively etching the source / drain region (475, 775, 875, 975) and the low-doped semiconductor material (432, 532, 632, 732, 832) to form a second horizontal opening (472) horizontally back from the vertical opening (471) to a second distance (483); forming a third dielectric material (474, 774, 874) in the second horizontal opening (472); and forming a second highly doped semiconductor material (495, 795, 895, 995) in the vertical opening (471).

[0006] Another aspect of the present disclosure provides a memory cell array (101, 1010), comprising: a plurality of access transistors (230, 901) stacked one above the other, each of the access transistors (230, 901) comprising a first source / drain region (221, 321, 475, 775, 875, 975), a second source / drain region (223, 323, 778) and a channel region (225, 325) and a body region (226, 326, 932) arranged horizontally therebetween; at least one access line (103, 203, 303, a plurality of storage capacitors (227) stacked one above the other, each of the plurality of storage capacitors (227) being horizontally placed and coupled to a corresponding second source / drain region in the second source / drain regions (223, 323, 778) of the plurality of access transistors (230, 901); a plurality of digit lines (107, 207, 977), each of the plurality of digit lines (107, 207, 977) being coupled to the first source / drain regions (221, 321, 475, 775, 875, 978) of the plurality of access transistors (230, 901); 975); and a body contact region (295, 795, 895, 995) vertically elongated and coupled to each of the body regions (226, 326, 932) of the plurality of access transistors (230, 901). BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic illustration of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 2 is a perspective view illustrating a portion of a digit line for a horizontally formed access device according to several embodiments of the present disclosure.

[0009] Figure 3 is a perspective view illustrating a portion of a digit line for a horizontally oriented access device according to several embodiments of the present disclosure.

[0010] Figures 4A-4M is a cross-sectional view of a method for forming an array of vertically stacked memory cells at various stages of a semiconductor fabrication process to form digit lines for horizontally oriented access devices in accordance with several embodiments of the present disclosure.

[0011] Figure 5A-5BAn example method of forming an array of vertically stacked memory cells having digit lines for horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process according to several embodiments of the present disclosure is described.

[0012] Figures 6A-6E An example method of forming an array of vertically stacked memory cells having digit lines for horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process according to several embodiments of the present disclosure is described.

[0013] Figures 7A-7E An example method of forming an array of vertically stacked memory cells having digit lines for horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process according to several embodiments of the present disclosure is described.

[0014] Figures 8A-8E An example method of forming an array of vertically stacked memory cells having digit lines for horizontally oriented access devices and vertically oriented access lines at another stage of a semiconductor fabrication process according to several embodiments of the present disclosure is described.

[0015] Fig. 9 Cross-sectional diagram illustrating an example horizontally-oriented access device coupled to a horizontally-oriented storage node and to a vertically-oriented access line and a horizontally-oriented digit line in accordance with several embodiments of the present disclosure.

[0016] Fig.10 is a block diagram of an apparatus in the form of a computing system including a memory device according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure describe systems, methods, and apparatus for forming digital lines for horizontally oriented access devices. An example method includes forming a first dielectric material layer, a low-doped semiconductor material layer, and a second dielectric material layer, performing vertical iterative repetition to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, vapor-phase doping dopants on a top surface of the low-doped semiconductor material in the horizontal opening to form a source / drain region, forming a highly doped semiconductor material in the horizontal opening, selectively etching the highly doped semiconductor material formed in the horizontal opening so as to retain a portion of the highly doped semiconductor material, and converting the remaining highly doped semiconductor material into a conductive material having properties different from the properties of the remaining highly doped semiconductor material.

[0018] In an embodiment of the present disclosure, a digit line and a body contact region are formed in an array of vertically stacked memory cells together with a horizontal access device. The horizontal access device is integrated with the vertically oriented access line and with the horizontally oriented digit line. The body contact region can be formed to provide better body bias control of the body region of the horizontally oriented access device (e.g., transistor). This additionally provides better access device channel control and device refresh improvements for silicon oxide channel access devices. The vertically oriented body contact line is integrated to form a body contact with the body region of the horizontally oriented access device.

[0019] According to embodiments, the digit line can be better isolated from the body contact line, resulting in lower digit line capacitance and reduced capacitive coupling with the body contact line. The isolation technology further reduces the possibility of dopant diffusion into the source / drain and digit line contact areas and may have more uniform and lower source / drain doping requirements.

[0020] In addition, in embodiments of the present disclosure, digit lines can be formed in a highly conformal manner while reducing the complexity of digit line formation to allow digit lines to be formed in complex three-dimensional isotropic structures. The contact resistance of the digit line to the source / drain can also be reduced.

[0021] The drawings herein follow a numbering convention in which the first one or more digits correspond to the figure number of the drawing and the remaining digits identify the element or component in the drawing. Similar elements or components between different figures can be identified by using similar numerals. For example, reference numeral 104 is shown in FIG. Figure 1 can refer to component "04" in, and similar components can be found in Figure 2 204 in the figure. Multiple similar elements within a figure may be represented by a reference numeral followed by a hyphen and another number or letter. For example, 302-1 may refer to Figure 3 302-1 and 302-2 may refer to element 302-2, which may be similar to element 302-1. Such similar elements may be generally referred to without hyphens and additional numbers or letters. For example, elements 302-1 and 302-2 or other similar elements may be generally represented as 302.

[0022] Figure 1 is a block diagram of a device according to several embodiments of the present disclosure. Figure 1 The description shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1A cell array having a plurality of sub-cell arrays 101-1, 101-2, ..., 101-N is illustrated. The sub-cell arrays 101-1, 101-2, ..., 101-N may be arranged along a second direction (D2) 105. Each of the sub-cell arrays, such as the sub-cell array 101-2, may include a plurality of access lines 103-1, 103-2, ..., 103-Q (which may also be referred to as word lines). In addition, each of the sub-cell arrays (such as the sub-cell array 101-2) may include a plurality of digital lines 107-1, 107-2, ..., 107-P (which may also be referred to as bit lines, data lines, or sense lines). In Figure 1 , digit lines 107-1, 107-2, ..., 107-P are illustrated extending along a first direction (D1) 109, and access lines 103-1, 103-2, ..., 103-Q are illustrated extending along a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 may be considered to be in a horizontal ("XY") plane. The third direction (D3) 111 may be considered to be in a vertical ("Z") plane. Thus, according to embodiments described herein, access lines 103-1, 103-2, ..., 103-Q extend in a vertical direction, such as the third direction (D3) 111.

[0023] Memory cells, such as 110, may include access devices, such as access transistors, and storage nodes located at the intersection of each access line 103-1, 103-2, ..., 103-Q and each digit line 107-1, 107-2, ..., 107-P. Access lines 103-1, 103-2, ..., 103-Q and digit lines 107-1, 107-2, ..., 107-P may be used to write to or read from the memory cells. Digit lines 107-1, 107-2, ..., 107-P may interconnect memory cells in a conductive manner along horizontal columns of each subcell array 101-, 101-2, ..., 101-N, and access lines 103-1, 103-2, ..., 103-Q may interconnect memory cells in a conductive manner along vertical rows of each subcell array 101-, 101-2, ..., 101-N. One memory cell (e.g., 110) can be located between one access line (e.g., 103-2) and one digit line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of access lines 103-1, 103-2, ..., 103-Q and digit lines 107-1, 107-2, ..., 107-P.

[0024] The digit lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. The digit lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. The digit lines 107-1, 107-2, ..., 107-P in one sub-unit array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0025] The access lines 103-1, 103-2, ..., 103-Q may be or include conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., in a third direction (D3) 111) relative to the substrate. The access lines in one sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0026] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 103-2), and a first conductive node (e.g., a first source / drain region) of an access device (e.g., a transistor) of memory cell 110 may be connected to a digit line (e.g., 107-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. A second conductive node (e.g., a second source / drain region) of an access device (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although reference to first and second source / drain regions is used herein to represent two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a unique meaning. It is intended that only one of the source / drain regions is connected to a digit line, such as 107-2, and the other may be connected to a storage node.

[0027] Figure 2 A three-dimensional (3D) semiconductor memory device (eg, Figure 1 1-2 as a perspective view of a portion of a subcell array 101-2 shown in FIG. Figure 3 Description Display Figure 2 The unit cell of the 3D semiconductor memory device shown in Figure 1 A perspective view of a memory cell 110 shown in FIG.

[0028] like Figure 2 As shown in FIG. 1 , a bonding Figure 1 One of the multiple sub-unit arrays described (eg, 101 - 2 ). For example, the substrate 200 may be or include a silicon substrate, a germanium substrate, or a silicon germanium substrate, etc. However, the embodiments are not limited to these examples.

[0029] like Figure 2 As shown in the example embodiment of FIG. 1 , a memory cell (eg, a memory cell extending in a vertical direction such as a third direction (D3) 111) may be fabricated on the substrate 200. Figure 1 According to some embodiments, the vertically oriented stack of memory cells can be manufactured such that each memory cell (e.g. Figure 1 The memory cells 110 in the embodiment are formed on multiple vertical levels, such as a first level (L1), a second level (L2), and a third level (L3). Figure 1 The repeating vertical levels L1, L2, and L3 are arranged (e.g., "stacked") in a third direction (D3) 111 shown in FIG. 1 and may be separated from the substrate by an insulator material 220. Each of the repeating vertical levels L1, L2, and L3 may include a plurality of discrete components (e.g., regions) of laterally oriented access devices 230 (e.g., transistors) and storage nodes (e.g., capacitors), including access lines 103-1, 103-2, ..., 103-Q connections and digit lines 107-1, 107-2, ..., 107-P connections. The plurality of discrete components of the laterally oriented access devices 230 (e.g., transistors) may be formed in multiple iterations of the vertical repeating layers within each level, as described below in conjunction with Figures 4A-4M etc., and can be described in more detail along the lines similar to Figure 1 The second direction (D2) 205 shown in FIG. 1 extends horizontally.

[0030] A plurality of discrete components of a laterally oriented access device 230, such as a transistor, may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally along a second direction (D2) 205 and formed in a body of the access device. In some embodiments, the channel region 225 may include silicon, germanium, silicon germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include n-type dopant regions formed in a p-type doped body of the access device to form an n-type conductivity transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may include p-type dopants formed within an n-type doped body of the access device to form a p-type conductivity transistor. By way of example and not limitation, the n-type dopant may include phosphorus (P) atoms and the p-type dopant may include boron (B) atoms formed in a counter-doped body region of a polysilicon semiconductor material. However, the embodiments are not limited to these examples.

[0031] A storage node 227 (eg, a capacitor) may be connected to a respective end of the access device. Figure 2As shown in FIG. 1 , a storage node 227 (e.g., a capacitor) may be connected to a second source / drain region 223 of an access device. The storage node may be or include a memory element capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistance body including a phase change material, etc. However, the embodiments are not limited to these examples. In some embodiments, the storage node 227 (e.g., a capacitor) may be connected to a second source / drain region 223 of an access device. The storage node may be or include a memory element capable of storing data. Figure 1 Each storage node associated with the access device of the memory unit 110 in Figure 1 The second direction (D2) 205 extends in the second direction (D2) 105 shown in FIG.

[0032] like Figure 2 As shown in FIG. 1 , a plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P are arranged in a manner similar to Figure 1 The plurality of horizontally oriented digital lines 207-1, 207-2, ..., 207-P may extend in a first direction (D1) 209 in the first direction (D1) 109 in the first direction (D1). Figure 1 , 107-P. A plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P may be arranged (e.g., "stacked") along a third direction (D3) 211. A plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P may include a conductive material. For example, the conductive material may include one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, embodiments are not limited to these examples.

[0033] In each of the vertical levels (L1) 213-1, (L2) 213-2, and (L3) 213-P, horizontally oriented memory cells (e.g. Figure 1 The memory cells 110 in the embodiment may be horizontally spaced apart from each other along the first direction (D1) 209. However, as described below in conjunction with Figures 4A-4MAs described in more detail in FIG. 2 , multiple discrete components of the laterally oriented access device 230, such as a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally along a second direction (D2) 205, and a plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P extending laterally along a first direction (D1) 209, can be formed in different vertical layers within each level. For example, the plurality of horizontally oriented digit lines 207-1, 207-2, ..., 207-P extending along the first direction (D1) 209 can be disposed on and in electrical contact with a top surface of the first source / drain region 221, and orthogonal to the laterally oriented access device 230 (e.g., transistor) extending laterally along the second direction (D2) 205. In some embodiments, the plurality of horizontally-oriented digit lines 207-1, 207-2, ..., 207-P extending along the first direction (D1) 209 are formed in a higher vertical layer within a hierarchy (e.g., within the hierarchy (L1)) that is further away from the substrate 200 than the layer in which the discrete components of the laterally-oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed. In some embodiments, the plurality of horizontally-oriented digit lines 207-1, 207-2, ..., 207-P extending along the first direction (D1) 209 may be connected to the top surface of the first source / drain region 221 directly and / or through an additional contact region containing metal silicide.

[0034] like Figure 2 As shown in the example embodiment of , the access lines 203-1, 203-2, ..., 203-Q extend in a vertical direction relative to the substrate 200, for example, along a third direction (D3) 211. Figure 2 As shown in FIG. 1 , a subunit array (e.g. Figure 1 , 203-Q in the sub-cell array 101-2 in the embodiment of the present invention may be spaced apart from each other along the first direction (D1) 209. The access lines 203-1, 203-2, ..., 203-Q may be arranged to extend vertically along a third direction (D3) 211 relative to the substrate 200 between a pair of laterally oriented access devices 230 (e.g., transistors) extending laterally along the second direction (D2) 205, but adjacent to each other at a level such as a first level (L1) along the first direction (D1) 209. Each of the access lines 203-1, 203-2, ..., 203-Q may extend vertically along the third direction (D3) on a sidewall of a corresponding one of a plurality of laterally oriented access devices 230 (e.g., transistors) stacked vertically.

[0035] For example, and if Figure 3As shown in more detail in , a first one of the vertically-extending access lines (e.g., 203-1) may be adjacent to a sidewall of a channel region 225 of a first one of the laterally-oriented access devices 230 (e.g., transistors) in the first level (L1) 213-1, a sidewall of a channel region 225 of a first one of the laterally-oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2, and a sidewall of a channel region 225 of a first one of the laterally-oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Similarly, a second one of the vertically-extending access lines (e.g., 203-2) may be adjacent to a sidewall of a channel region 225 of a second one of the laterally-oriented access devices 230 (e.g., transistors) in the first level (L1) 213-1, spaced apart from a first end of the laterally-oriented access devices 230 (e.g., transistors) in the first level (L1) 213-1 along a first direction (D1) 209. Also, a second one of the vertically extending access lines (e.g., 203-2) may be adjacent to a sidewall of a channel region 225 of a second one of the laterally oriented access devices 230 (e.g., transistors) in the second level (L2) 213-2 and a sidewall of a channel region 225 of a second one of the laterally oriented access devices 230 (e.g., transistors) in the third level (L3) 213-P, etc. Embodiments are not limited to a particular number of levels.

[0036] The vertically extending access lines 203-1, 203-2, ..., 203-Q may include a conductive material, such as one of a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. The access lines 203-1, 203-2, ..., 203-Q may correspond to the bonding Figure 1 Describes the word line (WL).

[0037] like Figure 2 As shown in the example embodiment of FIG. 1 , a conductive body contact region 295 may be formed to extend along a first direction (D1) 209 along an end surface of a laterally oriented access device 230 (e.g., a transistor) in each level (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200. The body contact region 295 may be connected to each memory cell (e.g., Figure 1 The body 226, such as the body region, of a laterally oriented access device 230 (eg, a transistor) in the memory cell 110 in FIG. 290 may include a conductive material, such as one of a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0038] although Figure 2Although not shown in the figure, the insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may include one or more of silicon oxide material, silicon nitride material and / or silicon oxynitride material, etc. However, the embodiments are not limited to these examples.

[0039] Figure 3 A vertically stacked memory cell array (eg, Figure 1 ) unit cell within the sub-unit array 101-2, for example Figure 1 The memory cell 110 in FIG. Figure 3 As shown in FIG. 1 , the first source / drain region 321 and the second source / drain region 323 may be impurity-doped regions of the laterally oriented access device 230 (eg, a transistor). The first source / drain region 321 and the second source / drain region 323 may be similar to Figure 2 2 and 3. The first source / drain region 221 and the second source / drain region 223 are shown in FIG. The first source / drain region and the second source / drain region may be separated by a channel 325 formed in a body (e.g., body region 326) of a semiconductor material of a laterally oriented access device 230 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by n-type or p-type dopants doped in the body region 326. The embodiment is not limited thereto.

[0040] For example, for an n-type conductivity transistor configuration, the body region 326 of the laterally oriented access device 230 (e.g., a transistor) may be formed of a low-doped (p-) p-type semiconductor material. In one embodiment, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may include a low-doped p-type (e.g., low dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant of polysilicon. In this example, the first source / drain region 321 and the second source / drain region 323 may include a high dopant concentration n-type conductivity impurity (e.g., high dopant (n+)) doped in the first source / drain region 321 and the second source / drain region 323. In some embodiments, the high-doped n-type conductivity first drain region 321 and the second drain region 323 may include a high concentration of phosphorus (P) atoms deposited therein. However, the embodiment is not limited to this example. In other embodiments, the laterally-oriented access device 230 (eg, a transistor) may have a p-type conductivity configuration, in which case the conductivity type of the impurities, such as dopants, would be reversed.

[0041] like Figure 3As shown in the example embodiment of , the first source / drain region 321 can occupy an upper portion of the body 326 of the laterally oriented access device 230 (e.g., a transistor). For example, the first source / drain region 321 can have a bottom surface 324 within the body 326 of the laterally oriented access device 230 that is vertically higher along the third direction (D3) 311 than the bottom surface of the body 326 of the laterally oriented access device 230. Thus, the laterally oriented horizontally oriented transistor 230 can have a bottom surface 324 that is lower than the first source / drain region 321 and in contact with the body contact region (e.g., Figure 2 295) electrical contact body portion 326 shown in FIG. Figure 3 As shown in the example embodiment of Figure 2 The digital lines 207-1, 207-2, ..., 207-P and Figure 1 The digit lines 107 - 1 , 107 - 2 , . . . , 107 -P shown in FIG. 3 ( eg 307 - 1 ) may be disposed on and electrically coupled to a top surface 322 of the first source / drain region 321 .

[0042] like Figure 3 As shown in the example embodiment of Figure 2 The access lines 203-1, 203-2, ..., 203-Q and Figure 1 The access lines 103-1, 103-2, ..., 103-Q (e.g., 303-1) of the laterally oriented access device 230 (e.g., transistor) may extend vertically along the third direction (D3) 311 adjacent to the sidewall of the channel region 325 portion of the body 326 of the laterally oriented access device 230 (e.g., transistor), and the channel region is horizontally conductive along the second direction (D2) 305 between the first and second source / drain regions 321 and the second source / drain region 323. The gate dielectric material 304 may be inserted between the access line 303-1 (part of which forms the gate of the laterally oriented access device 230 (e.g., transistor)) and the channel region 325. The gate dielectric material 304 may include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or a combination thereof. The embodiment is not limited thereto. For example, in the high-k dielectric material instance, the gate dielectric material 304 may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0043] Figure 4A According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at a stage such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0044] exist Figure 4A In the example embodiment shown in the example of , alternating layers of first dielectric material 430-1, 430-2, ..., 430-N (collectively referred to as first dielectric material 430), semiconductor material 432-1, 432-2, ..., 432-N (collectively referred to as semiconductor material 432), and second dielectric material 433-1, 433-2, ..., 433-N (collectively referred to as second dielectric 433) are formed (e.g., deposited) in a repeated iterative manner to form a vertical stack 401 on a working surface of a semiconductor substrate 400. The vertical stack 401 may be separated from the substrate 400 by an insulator material (e.g., a film) 420.

[0045] In one embodiment, the substrate 400 may be or include a silicon substrate, a germanium substrate, or a silicon germanium substrate, etc. In one embodiment, the substrate 400 may be or include a low-doped polycrystalline silicon material. In one embodiment, the substrate 400 may be or include a low-doped polycrystalline germanium material. In one embodiment, the substrate 400 may be or include a low-doped polycrystalline silicon germanium material. However, the embodiments are not limited to these examples. In some embodiments, a first dielectric material 430, a semiconductor material 432, and a second dielectric material 433 may be deposited using a chemical vapor deposition (CVD) process. In one embodiment, the first dielectric material 430 may be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, such as a vertical height along a third direction (D3). In one embodiment, the semiconductor material 432 may be deposited to have a thickness in the range of twenty (20) nm to one hundred (100) nm, such as a vertical height. In one embodiment, the second dielectric material 433 may be deposited to have a thickness in the range of ten (10) nm to thirty (30) nm, such as a vertical height. However, the embodiments are not limited to these examples. As Figure 4A As shown in FIG. 4 , the vertical direction 411 is described as similar to Figure 1-3 A third direction (D3) among the first, second and third directions shown in , for example, the z direction in the xyz coordinate system.

[0046] In some embodiments, the first dielectric material 430-1, 430-2, ..., 430-N may be an interlayer dielectric (ILD). By way of example, but not limitation, the first dielectric material 430-1, 430-2, ..., 430-N may include an oxide material, such as SiO2. In another example, the first dielectric material 430-1, 430-2, ..., 430-N may include a silicon nitride (Si3N4) material (also referred to herein as "SiN"). In another example, the first dielectric material 430-1, 430-2, ..., 430-N may include a silicon oxynitride (SiO x Cy In another example, the first dielectric material 430-1, 430-2, ..., 430-N may include silicon oxynitride (SiO x N y ) materials (also referred to herein as "SiON") and / or combinations thereof. Embodiments are not limited to these examples.

[0047] In some embodiments, semiconductor materials 432-1, 432-2, ..., 432-N may include silicon (Si) materials in a polycrystalline and / or amorphous state. Semiconductor materials 432-1, 432-2, ..., 432-N may be low-doped p-type (p-) silicon materials. Semiconductor materials 432-1, 432-2, ..., 432-N may be formed by gas-phase doping with boron atoms (B) as an impurity dopant at a low concentration to form a low-doped p-type (p-) silicon material. In some embodiments, semiconductor materials 432-1, 432-2, ..., 432-N may be formed by in-situ gas-phase doping with boron atoms. The low-doped p-type (p-) silicon material may be a polycrystalline silicon material. However, embodiments are not limited to these examples.

[0048] In some embodiments, the second dielectric material 433-1, 433-2, ..., 433-N may be an interlayer dielectric (ILD). By way of example, but not limitation, the second dielectric material 433-1, 433-2, ..., 433-N may include a nitride material. The nitride material may be a silicon nitride (Si3N4) material (also referred to herein as "SiN"). In another example, the second dielectric material 433-1, 433-2, ..., 433-N may include a silicon oxynitride (SiOC) material. In another example, the second dielectric material 433-1, 433-2, ..., 433-N may include silicon oxynitride (SiON) and / or a combination thereof. Embodiments are not limited to these examples. However, according to an embodiment, the second dielectric material 433-1, 433-2, ..., 433-N is purposefully selected to have a different material or composition from the first dielectric material 430-1, 430-2, ..., 430-N, so that a selective etching process can be performed on one of the first dielectric layer and the second dielectric layer, and is selective to the other of the first dielectric layer and the second dielectric layer, for example, the second SiN dielectric material 433-1, 433-2, ..., 433-N can be selectively etched relative to the semiconductor material 432-1, 432-2, ..., 432-N and the first oxide dielectric material 430-1, 430-2, ..., 430-N.

[0049] The repeated iterative structure of alternating first dielectric material 430-1, 430-2, ..., 430-N layers, semiconductor material 432-1, 432-2, ..., 432-N layers, and second dielectric material 433-1, 433-2, ..., 433-N layers may be deposited in a semiconductor manufacturing device according to a semiconductor manufacturing process, such as chemical vapor deposition (CVD). However, the embodiment is not limited to this example and other suitable semiconductor manufacturing techniques may be used to deposit alternating layers of the first dielectric material, the semiconductor material, and the second dielectric material in a repeated iterative manner to form the vertical stack 401.

[0050] Layers can appear in vertically repeated iterations. Figure 4A In the example of , three levels of repeated iterations numbered 1, 2, and 3 are shown. For example, the stack may include: a first dielectric material 430-1, a semiconductor material 432-1, a second dielectric material 433-1, a third dielectric material 430-2, a second semiconductor material 432-2, a fourth dielectric material 433-2, a fifth dielectric material 430-3, a third semiconductor material 432-3, and a sixth dielectric material 433-3 of further repeated iterations. Thus, the stack may include: a first oxide material 430-1, a first semiconductor material 432-1, a first nitride material 433-1, a second oxide material 430-2, a second semiconductor material 432-2, a second nitride material 433-2, a third oxide material 430-3, a third semiconductor material 432-3, and a third nitride material 433-3. However, embodiments are not limited to this example and may include more or fewer repeated iterations.

[0051] Figure 4B According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0052] According to the embodiment, combined Figure 4B-4M The semiconductor manufacturing process described may be performed in a manner such as Figures 5A-6E The elongated pillars extending in the second direction shown in FIG. 1 and the access lines appear after formation.

[0053] The vertical opening 471 may be formed in the vertical stack through the layers within the vertically stacked memory cells to expose the vertical sidewalls in the vertical stack. The vertical opening 471 may be formed by repeated iterations of the oxide material 430, the semiconductor material 432, and the nitride material 433. Thus, the vertical opening 471 may be formed by the first oxide material 430-1, the first semiconductor material 432-1, the first nitride material 433-1, the second oxide material 430-2, the second semiconductor material 432-2, the second nitride material 433-2, the third oxide material 430-3, the third semiconductor material 432-3, and the third nitride material 433-3. However, the embodiments are not limited to Figure 4B 4. A single vertical opening is shown in FIG. Multiple vertical openings may be formed by the material layer. Vertical opening 471 may be formed to expose a vertical sidewall in a vertical stack.

[0054] Figure 4C According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0055] The etchant may flow into the vertical opening 471 to selectively etch the second dielectric material 433. For example, the etchant may flow into the vertical opening 471 to selectively etch the nitride material 433. The etchant may target all iterations of the second dielectric material 433 within the stack. Thus, the etchant may target the first nitride material 433-1, the second nitride material 433-2, and the third nitride material 433-3 within the stack.

[0056] The selective etching process may include one or more etching chemistries selected from aqueous etching chemistries, semi-aqueous etching chemistries, vapor etching chemistries, or plasma etching chemistries, as well as other possible selective etching chemistries. For example, a dry etching chemistry of oxygen (O2) or O2 and sulfur dioxide (SO2) (O2 / SO2) may be utilized. A dry etching chemistry of O2 or O2 and nitrogen (N2) (O2 / N2) may be used to selectively etch the second dielectric material 433. Alternatively or in addition, the selective etching to remove the second dielectric material 433 may include a selective etching chemistry of phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or use a selective solvent (e.g., NH4OH or HF) as well as other possible etching chemistries or solvents to dissolve the second dielectric material 433. The etching process may cause only the nitride material 433 to oxidize. As Figure 4CAs shown in the example of , the etching process can form a protective oxide coating, such as the second oxide material 434, on the sidewalls of the semiconductor material 430. Therefore, the first dielectric material 430 and the semiconductor material 432 can remain intact during the selective etching process. For example, the selective etching process can etch a portion of the nitride material 433 while not removing the oxide material 430 and the polysilicon material 432.

[0057] As mentioned, the semiconductor material 432 may be protected during the selective etching process by the second oxide material 434 formed on the sidewalls of the semiconductor material 432. The second oxide material 434 may be present on all iterations of the semiconductor material 432. For example, the second oxide material 434 may be present on the sidewalls of the first semiconductor material 432-1, the second semiconductor material 432-2, and the third semiconductor material 432-3, etc., in the vertical opening 471 within the stack.

[0058] Figure 4D According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0059] The selective etching process may etch the nitride material 433 to form a horizontal opening 473 in the nitride material 433. The selective etching process may be performed such that the horizontal opening 473 has a length or depth (D1) 476, i.e., a first distance 476 laterally returned from the vertical opening 471. The distance (D1) 476 may be controlled by controlling the time, composition of the etchant gas, and the etching rate (e.g., rate, concentration, temperature, pressure, and time parameters) of the reactant gas flowing into the vertical opening 471. Thus, the nitride material 433 may be etched the first distance 476 laterally returned from the vertical opening 471. The selective etching may be isotropic, but selective to the second dielectric material 433, substantially stopping on the first dielectric material 430 and the semiconductor material. Thus, in one example embodiment, the selective etching process can remove substantially all of the nitride material 433 from the top surface of the semiconductor material 403 to the bottom surface of the first dielectric material (e.g., oxide material) in the layer above when etching horizontally between the semiconductor material 432 and the oxide material 430 from the vertical opening 471 back laterally by a distance (D1) 476. In this example, the horizontal opening 473 will have a first height (H1) 435 that is substantially equivalent to and controlled by the height of the deposited second dielectric layer 433 (e.g., nitride material). However, embodiments are not limited to this example. As described herein, the selective etching process can etch the nitride material 433 by the first distance (D1) 476 and the first height (H1) 435.

[0060] Figure 4E According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0061] The source / drain region 475 may be formed by gas phase doping dopants into the top surface portion of the semiconductor material 432 in the horizontal opening 473. Gas phase controlled doping may be used to achieve highly isotropic (e.g., non-directional) doping. In another example, thermal annealing with a doping gas (e.g., phosphorus) may be used with high energy plasma assistance to break bonding. The embodiment is not limited thereto, and other suitable semiconductor fabrication techniques may be utilized. The width of the source / drain region 475 doped into the top surface portion of the semiconductor material 432 may be formed substantially all along the first distance (D1) 476 of the horizontal opening 473 from the vertical opening 471. The source / drain region 475 may be formed by gas phase doping with phosphorus (P) atoms as an impurity dopant with high plasma energy (e.g., PECVD) to form a high concentration n-type doped (n+) region in the top surface of the semiconductor material 432.

[0062] Figure 4F According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0063] like Figure 4F As shown in , semiconductor material 482 may be formed (e.g., deposited) in vertical opening 471 and horizontal opening 473. Semiconductor material 482 may include silicon (Si) material in a polycrystalline and / or amorphous state. Semiconductor material 482 may be a highly doped degenerate semiconductor material, such as a highly doped n-type (n+) silicon material. The highly doped n-type (n+) silicon material may be a polycrystalline silicon material.

[0064] As used herein, a degenerate semiconductor material refers to a semiconductor material, such as polysilicon, that contains a high level of doping that exploits significant interactions between dopants such as phosphorus (P), boron (B), etc. In contrast, a non-degenerate semiconductor contains a moderate level of doping where the dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions.

[0065] Semiconductor material 482 may be formed by isotropically depositing semiconductor material 482 in vertical opening 471 and horizontal opening 473. Such deposition may be highly conformal and may fill the isotropic 3D structure of the device (eg, filling openings 471 and 473), such as Figure 4FAs described in .

[0066] Figure 4G According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0067] like Figure 4G As shown in , the semiconductor material 482 formed in the vertical opening 471 can be etched to remove the semiconductor material 482 formed in the vertical opening 471. As a result, the vertical opening 471 can be reformed to re-expose the vertical sidewalls in the vertical stack (e.g., the sidewalls including the semiconductor material 482 formed in the horizontal opening 473), as shown in FIG. Figure 4G As described in .

[0068] The etching of the semiconductor material 482 formed in the vertical opening 471 may be an anisotropic etching that removes the semiconductor material 482 from the vertical opening 471 but does not remove (eg, leave) the semiconductor material 482 formed in the horizontal opening 473, such as Figure 4G For example, etching may be a wet etching process or a dry etching process.

[0069] Figure 4H According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0070] like Figure 4H As shown in FIG. 1 , the semiconductor material 482 formed in the horizontal opening 473 can be selectively etched so that a portion of the semiconductor material 482 remains. For example, the semiconductor material 482 can be etched away from the vertical opening 471 and recessed back into the horizontal opening 473. In some examples, the semiconductor material 482 can be etched back in the horizontal opening 473 to a second distance (D2) 483 that can be less than the first distance (D1) laterally returned from the vertical opening 471, such as Figure 4H Thus, the selective etching may not remove a portion of the semiconductor material 482 formed in the horizontal opening 473 (eg, it may be retained), as shown in FIG. Figure 4H In addition, the selective etching can leave the dielectric material 430, the semiconductor material 432 and the source and drain regions 475 intact, as shown in FIG. Figure 4H As described in .

[0071] The selective etching of the semiconductor material 482 formed in the horizontal opening 473 may be an anisotropic etch, for example, using tetramethylammonium hydroxide (TMAH). As an additional example, the selective etching may be an isotropic dry etching process.

[0072] The semiconductor material 482 may be recessed back into the horizontal opening 473 by a second distance (D2) 483 to maintain direct electrical contact on the top surface of the source / drain region 475 formed in the semiconductor material 432. Thus, the semiconductor material 482 maintains electrical contact with the source / drain region 475 and may be converted into a single-piece horizontally-oriented conductive digit line (e.g., at each of the first and second electrodes 484, 485, 486, 487, 488, 490, 491, 492, 494, 496, 497, 498, 499, 400, 401, 402, 403, 404, 405, 406, 407, 408, 410, 411, 412, 413, 414, 41 Figure 1-3 Conductive material of portions of digital lines 107, 207 and 307) as will be further described herein.

[0073] Fig. 4I According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0074] exist Fig. 4I In the example illustrated in FIG. 4 , the remaining semiconductor material 482 (e.g., the remaining portion thereof) is converted (e.g., replaced) with the conductive material 477. The conductive material 477 may have different properties than the remaining semiconductor material 482. For example, the conductive material 477 may be a tungsten (W) material. For example, the conductive material 477 may be a β-phase tungsten material.

[0075] The remaining semiconductor material (e.g., highly doped polysilicon material) 482 can be converted into a conductive material (e.g., tungsten material) 477 by selectively reacting a tungsten hexafluoride (WF6) material with the remaining semiconductor material 482. For example, the tungsten hexafluoride material can flow into the vertical opening 471 and the horizontal opening 473 to expose the remaining semiconductor material 482 in the horizontal opening 473 to the tungsten hexafluoride material, so that the remaining (e.g., exposed) semiconductor material 482 is soaked with tungsten hexafluoride to cause the tungsten material to grow. This reaction can be chemically expressed as:

[0076] WF6+3 / 2Si→W+3 / 2SiF4

[0077] Wherein the enthalpy change for the reaction is -1908 kilojoules per mole (KJ / mole). Tungsten hexafluoride may target all iterations of the remaining semiconductor material 482 in the stack (eg, react with the remaining semiconductor material in all horizontal openings).

[0078] However, the tungsten hexafluoride material may react only with the remaining semiconductor material 482. For example, the tungsten hexafluoride material may not react with the dielectric material (e.g., SiO2) 430, the source / drain region 475, or the oxide material 434. Therefore, the conversion process may be selective to the semiconductor material (e.g., highly doped polysilicon material) 482. For example, the dielectric material 430, the source / drain region 475, and the oxide material 434 may remain intact during the conversion process, and the source / drain region 475 may remain almost free of contact with the conversion process.

[0079] For example, the conversion process may have a conversion difference with respect to doping levels. Because the semiconductor material 482 may be a highly doped polysilicon material, and the semiconductor material 432 in which the source / drain regions 475 are formed may be a low-doped silicon material, there may be a doping level difference between the semiconductor material 482 and the source / drain regions 475 that may be used (e.g., employed) in performing the conversion of the semiconductor material 482 while keeping the source / drain regions 475 almost untouched.

[0080] Additionally, any additional material (eg, conductive material) formed on the source / drain regions 475 during the conversion process will be significantly greater than Fig. 4I The thickness of the conductive material 477 illustrated in FIG. 4 is thin. Therefore, any such additional material may be removed (eg, cleaned) from the source / drain regions 475.

[0081] The rate at which the semiconductor material (e.g., highly doped polysilicon material) 482 is converted to the conductive (e.g., tungsten) material 477 may be proportional to the concentration of the tungsten hexafluoride material that selectively reacts with the semiconductor material 482, the doping of the semiconductor material 482, and the temperature at which the conversion occurs (e.g., the temperature at which the tungsten hexafluoride material selectively reacts with the semiconductor material 482). For example, the conversion rate may be higher when the WF6 concentration, the doping of the semiconductor material 482, and / or the conversion temperature are higher. However, the rate at which the semiconductor material 482 is converted to the conductive material 477 may be independent of the amount of time that the semiconductor material 482 is exposed to the tungsten hexafluoride material (e.g., the WF6 exposure time may not change the conversion rate).

[0082] As an example, the temperature at which the conversion occurs may be 300 degrees Celsius, the tungsten hexafluoride exposure time may be 6 seconds, the flow rate of tungsten hexafluoride used in the conversion may be 70 standard cubic centimeters per minute, 135 SCCM, or 270 SCCM, and / or the doping of semiconductor material 482 may be 1.3×10 21 or 4.7 × 10 21 However, embodiments of the present disclosure are not limited to these specific examples.

[0083] Figure 4JAccording to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0084] like Figure 4J As shown in FIG. 1 , the oxide material (at the bottom of FIG. 1 ) that protects the sidewalls of the semiconductor material in the vertical opening 471, a portion of the source / drain region 475, and a first portion 478 of the semiconductor material 432 below the source / drain region 475 can be selectively etched away. Figure 4C-4I 434) to allow for the formation of a body contact with the body region of the horizontal access device. In this example, a portion of the source / drain region 475 and a top portion of the semiconductor material 432 below the first source / drain region 475 (e.g., first portion 478) may also be etched back to a second distance (D2) 483 laterally back from the vertical opening 471. The etching may be performed using atomic layer etching (ALE) or other suitable techniques. In some embodiments, the source / drain region 475 may be etched to the same horizontal distance (D2) 483 as the conductive material 477 from the vertical opening 471.

[0085] Thus, a second horizontal opening 472 may be formed by etching a portion of the source / drain region 475 and a top surface (e.g., 478) of the semiconductor material 432 below the first source / drain region 475 to a second horizontal distance (D2) 483 laterally back from the vertical opening 471. Thus, the second horizontal opening 472 may have a second vertical height (H2) 485. The second vertical height (H2) 485 may be greater than (e.g., vertically higher than) a combination of the height (H1) 435 of the first horizontal opening 473 formed in the second dielectric material (e.g., nitride material) and the height of the source / drain region 475 (e.g., the depth of vapor phase doping into the top surface of the semiconductor material 432). For example, the second height (H2) 485 may also include the height of the top portion (e.g., 478) of the etched away semiconductor material 432. Thus, the second distance (D2) 483 may be shorter than the first distance (D1) 476, but the second height 485 may be greater than the first height (H2). Figure 4D-4E In the description, it is H1).

[0086] Figure 4K According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0087] like Figure 4KAs shown in FIG. 4 , for example, a third dielectric material 474 is conformally deposited into the vertical opening 471 and the second horizontal opening 472 using a CVD process, and the third dielectric material 474 can conformally fill the vertical opening 471 and the second horizontal opening 472. The third dielectric material 474 can be connected to the conductive material 477 (for example, along the Figure 1 The third dielectric material 474 is horizontally adjacent to the first dielectric material 430, the horizontal conductive digit line extending in the first direction (D1) 109 in the first direction (D1), the source / drain region 475, and the first portion of the low-doped (e.g., p-type low-doped (p-)) semiconductor material 432. For example, in some embodiments, the third dielectric material 474 may be below the first dielectric material 430 and directly contact the conductive material 477, the source / drain region 475, and the first portion of the low-doped semiconductor material 432. However, the embodiments are not limited to this example.

[0088] The third dielectric material 474 can be the same material or a different material from the second dielectric material 433. For example, the second dielectric material can be Si2N3 and the third dielectric material can also be Si3N4. In another example, the third dielectric material 474 can include a silicon dioxide (SiO2) material. In another example, the third dielectric material 474 can include silicon oxynitride (SiO x C y In another example, the third dielectric material 474 may include silicon oxynitride (SiO x N y ) and / or combinations thereof. The embodiments are not limited to these examples.

[0089] Figure 4L According to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0090] The third dielectric material 474 may be recessed to remove the third dielectric material 474 from the first vertical opening 471 and maintain the first vertical opening 471 to allow deposition of the conductive material ( Figure 4M ), thereby forming a direct electrical contact between such conductive material deposited within the vertical opening 471 and a second portion 479 (e.g., a body region contact region) of the low-doped (e.g., p-type low-doped (p-)) semiconductor material 432 of the horizontally oriented access device within the vertical stack. In some embodiments, the third dielectric material 474 can be etched away from the vertical opening 471 to expose the sidewalls of the first dielectric material 430, the third dielectric material 474, and the second portion 479 of the semiconductor material 432.

[0091] Figure 4MAccording to several embodiments of the present disclosure, a semiconductor manufacturing process is formed at another stage, such as Figure 1-3 A cross-sectional view of a digit line of a semiconductor device having a horizontally oriented access device and a vertically oriented access line is shown in FIG.

[0092] like Figure 4M As shown in , a conductive material 495 is deposited into the vertical opening 471 to form a direct electrical contact with the second portion 479 of the low-doped (e.g., p-type low-doped (p-)) semiconductor material 432. In some embodiments, the conductive material may be a metal, such as tungsten (W). However, the embodiments are not so limited. In some embodiments, the conductive material 495 is a highly doped (e.g., p-type highly doped (p+)) semiconductor material that can be deposited into the vertical opening 471. In this example, the highly doped semiconductor material 495 may be a highly doped (p-type (p+) silicon material. The highly doped p-type (p+) silicon material 495 may be a polycrystalline silicon material. In some examples, the highly doped semiconductor material 495 may be a highly doped p-type (p+) silicon germanium (SiGe) material. The SiGe material can be deposited into the vertical opening 471 at a relatively low temperature. However, the embodiments are not limited to these examples.

[0093] The highly doped p-type (p+) silicon material 495 may form a conductive body contact with the second portion 479 of the semiconductor material 432. The highly doped p-type (p+) silicon material 495 may reduce voids generated by gate induced drain leakage (GIDL) during operation of the laterally oriented access device. The highly doped p-type (p+) silicon material 495 may control the channel potential within the semiconductor material 432 by controlling void formation within the semiconductor material 432. For example, if the first source / drain region 475 is not electrically isolated from the conductive material 495 by the third dielectric material 474, void formation may occur between the first source / drain region 475, the highly doped (p+) polysilicon material, and the body region of the horizontally oriented access device.

[0094] Figure 5A In another stage of the semiconductor manufacturing process, for example, a semiconductor device is formed according to several embodiments of the present disclosure. Figure 1-3 An example method of a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines is described in . Figure 5A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process is illustrated according to one or more embodiments. Figure 5A In the example embodiment shown in the example of , the method includes using an etching process to form a plurality of first vertical openings 515 through the vertical stack to the substrate, which have a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505. In one example, as Figure 5AAs shown in FIG. 5 , the plurality of first vertical openings 515 extend primarily along the second horizontal direction (D2) 505 and may form an elongated vertical columnar column 513 having a sidewall 514 in the vertical stack. Prior to etching the plurality of first vertical openings 515, a photolithography mask 535 may be patterned using a photolithography technique on the vertical stack, for example to form a hard mask (HM) to form the plurality of first vertical openings 515.

[0095] Figure 5B is along Figure 5A A cross-sectional view taken along the cutting line AA′ in FIG. 1 shows another view of the semiconductor structure at a specific time during the semiconductor manufacturing process. Figure 5B The cross-sectional view shown in FIG. 5 shows that alternating layers of first dielectric material 530-1, 530-2, ..., 530-N, semiconductor material 532-1, 532-2, ..., 532-N, and second dielectric material 533-1, 533-2, ..., 533-N on semiconductor substrate 500 are repeated to form a vertical stack, such as Figure 4A 401 shown in , which may be separated from the substrate 500 by an insulator material 520 . Figure 5B It is illustrated that conductive materials 540-1, 540-2, ..., 540-4 may be formed on the gate dielectric material 538 in the plurality of first vertical openings 515. By way of example and not limitation, the gate dielectric material 538 may be conformally deposited in the plurality of first vertical openings 515 using a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD), an atomic layer deposition (ALD), or other suitable deposition process to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 may be deposited to a specific thickness (t1) suitable for a specific design rule, such as a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. By way of example and not limitation, the gate dielectric 538 may include a silicon dioxide (SiO2) material, an aluminum oxide (Al2O3) material, a high dielectric constant (k) (e.g., high-k) dielectric material, and / or combinations thereof, as also described in Figure 3 Described in.

[0096] In addition, if Figure 5BAs shown in , conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited in the plurality of first vertical openings 515 on the surface of the gate dielectric material 538. By way of example and not limitation, the conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited in the plurality of first vertical openings 515 on the surface of the gate dielectric material 538 using chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings above the gate dielectric 538. The conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited to a particular thickness (t2) to form vertically oriented access lines, such as Figure 1 etc., and the specific thickness is suitable for specific design rules. For example, the conductive material 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. By way of example but not limitation, the conductive material 540-1, 540-2, ..., 540-4 can be one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.) and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.) and / or some other combination thereof, and / or Figure 3 Described in.

[0097] like Figure 5B As shown in FIG. 5 , the conductive materials 540 - 1 , 540 - 2 , . . . , 540 - 4 may be recessed to Figure 5B Only the vertical sidewalls along the elongated vertical columnar columns (now shown as 542-1, 542-2 and 542-3) remain in the cross-sectional view of FIG. The plurality of individual vertical access lines formed of the conductive material 540-1, 540-2, ..., 540-4 may be recessed from the first vertical opening (e.g., Figure 5A The conductive materials 540-1, 540-2, ..., 540-4 are removed from the bottom surface of the storage device 515 in the embodiment of the present invention, exposing the gate dielectric 538 on the bottom surface to form separate vertical access lines 540-1, 540-2, ..., 540-4. Figure 5BAs shown in , a dielectric material 539 (e.g., an oxide or other suitable spin-on dielectric (SOD)) can then be deposited in the first vertical opening 515 using a process such as CVD to fill the first vertical opening 515. The dielectric can be planarized to the top surface of the hard mask 535 of the vertical semiconductor stack using chemical mechanical planarization (CMP) or other suitable semiconductor fabrication techniques. A subsequent photolithographic material 536 (e.g., a hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical opening 515 above the individual vertical access lines 540-1, 540-2, ..., 540-4. Similar semiconductor processing techniques can be used at other points in the semiconductor fabrication process described herein.

[0098] Fig. 6A In another stage of the semiconductor manufacturing process, for example, a semiconductor device is formed according to several embodiments of the present disclosure. Figure 1-3 An example method of a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines is described in . Fig. 6A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process is illustrated according to one or more embodiments. Fig. 6A In an example embodiment, the method includes patterning using a photolithography process Figure 5B The photolithography masks 636, 536 in FIG. Fig. 6A The method further illustrates using a selective isotropic etching process to remove portions of the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z to separate and individually form a plurality of separate vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z, for example. Figure 1 103-1, 103-2, ..., 103-Q, etc. Thus, a plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z are shown along the sidewalls of the elongated vertical columnar columns, e.g., along Figure 5B The side walls of the slender vertical columnar columns 542-1, 542-2 and 542-3 in the cross-sectional view of FIG.

[0099] like Fig. 6A As shown in the example of FIG. 1 , an appropriate selective isotropic etching process may be used to remove the exposed conductive materials 640 - 1 , 640 - 2 , ... , 640 -N , 640 -(N+1) , ... , 640 -(Z-1) and 640 -Z to return to the first vertical opening (e.g. Figure 5A The gate dielectric material 638 in 515) is as shown in FIG. Fig. 6A, a subsequent dielectric material 641 (e.g., an oxide or other suitable spin-on dielectric (SOD)) may then be deposited using a process such as CMP or other suitable technique to fill the remaining openings from which the exposed conductive materials 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z were removed using a process such as CVD or other suitable technique. The dielectric material 641 may be planarized to the vertical semiconductor stack (e.g., as shown in FIG. 1 ). Figure 4A In some embodiments, a subsequent photolithography material 537 (eg, a hard mask) may be deposited using CVD and planarized using CMP to cover and seal the top surface of the previous hard mask 635 of 401). Figure 4A , 640-(N+1), ..., 640-(Z-1), and 640-Z above the working surface of the vertical semiconductor stack 401 in the embodiment of the present invention, leaving the plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and 640-Z protected along the sidewalls of the elongated vertical columnar columns. However, the embodiments are not limited to these process examples.

[0100] Figure 6B Description Fig. 6A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6B , 640-(N+1), ..., 640-(Z-1), and shows repeated iterations of alternating layers of a first dielectric material 630-1, 630-2, ..., 630-N, a semiconductor material 632-1, 632-2, ..., 632-N, and a second dielectric material 633-1, 633-2, ..., 633-N on a semiconductor substrate 600 to form a vertical stack (e.g., as shown in FIG. 1 ). Figures 4A-4M 401), the vertical stack may be separated from the substrate 600 by an insulator material 620. Figure 6B As shown in FIG. , the vertical direction 611 is illustrated as a third direction (D3), such as the z direction in the xyz coordinate system, similar to Figure 1-3 The third direction (D3) 111 among the first, second and third directions shown in FIG. The plane of the drawing extends left and right along the first direction (D1) 609. Figure 6B In the example embodiment of FIG. 6 , dielectric material 641 is shown filling the vertical openings above the residual gate dielectric 638 deposit. The hard mask 637 described above covers the illustrated structure.

[0101] Figure 6C Description Fig. 6A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6C The cross-sectional view shown in FIG. 6 is illustrated as extending along a second direction (D2) 605 along an axis of a repeating iterative structure of alternating layers of a first dielectric material 630-1, 630-2, ..., 630-N, a semiconductor material 632-1, 632-2, ..., 632-N, and a second dielectric material 633-1, 633-2, ..., 633-N, and wherein horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of semiconductor material 632-1, 632-2, ..., 632-N along the axis. Figure 6C , adjacent relative vertical access lines 640-3 are illustrated by dashed lines indicating their orientation from the plane of the drawing sheet and the orientation setting therein.

[0102] Fig.6D Description Fig. 6A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.6D 633-2, ..., 633-N, and a second dielectric material 632-1, 632-2, ..., 632-N. The cross-sectional view shown in FIG. 605 is illustrated as extending along an axis of a repeating iterative structure of alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N outside of a region in which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) are to be formed within the semiconductor material layers 632-1, 632-2, ..., 632-N. Figure 6C , for a three-dimensional array of vertically oriented memory cells, dielectric material 641 is shown filling spaces between horizontally oriented access devices and horizontally oriented storage nodes, which may be spaced apart along a first direction (D1) extending into and out of the plane of the drawing. Repeated iterations of alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N are shown at the left end of the drawing, where horizontally oriented digit lines (e.g., Figure 1The digit lines 107-1, 107-2, ..., 107-P, etc.) shown in FIG. 107 may be integrated to form electrical contact with a second source / drain region or digit line conductive contact material, as described in more detail below.

[0103] Fig. 6E Description Fig. 6A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig. 6E , 632-N, semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N, intersecting across a plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1), and intersecting regions of semiconductor material 632-1, 632-2, ..., 632-N, wherein a channel region may be formed through a gate dielectric 638. Spaced apart from a plurality of individual vertical access lines 640-1, 640-2, ..., 640-N, 640-(N+1), ..., 640-(Z-1). Fig. 6E , a first dielectric fill material 639 is shown as spacing spaces between adjacent horizontally-oriented access devices and horizontally-oriented storage nodes, which horizontally-oriented access devices and horizontally-oriented storage nodes can be formed to extend into and out of the plane of the drawing, as described in more detail below, and can be spaced along a first direction (D1) 609 and vertically stacked in an array extending along a third direction (D3) 611 in a three-dimensional (3D) memory.

[0104] Fig. 7A In another stage of the semiconductor manufacturing process, for example, a semiconductor device is formed according to several embodiments of the present disclosure. Figure 1-3 An example method for a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines is described in . Fig. 7A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process is illustrated according to one or more embodiments. Fig. 7A In an example embodiment of the present invention, the method includes using a photolithography process to form a photolithography mask 735, 736 and / or 737 (eg, Figures 6A-6E 635, 636 and / or 637) are patterned. Fig. 7A The method further describes using one or more etching processes to form a storage node region 750 (and Fig. 7A and 7CA vertical opening 751 is formed in the vertical stack 744 and extends primarily along the first horizontal direction (D1) 709. The one or more etching processes form the vertical opening 751 to expose Figure 7B-7E , 730-N, semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N in the vertical stack shown in FIG. Other numbered components may be similar to those in the combination Figures 6A-6E Those components shown and discussed.

[0105] In some embodiments, this process is combined with Figures 4A-4M The semiconductor manufacturing process described above is performed previously. Figure 7B-7E The embodiment shown in the figure illustrates that the combination has been performed Figures 4A-4M The order of storage node fabrication processes (eg, digit line formation first) is described as being performed “after” digit line 777 and first source / drain region formation. Here, digit line 777 may be illustrated as being along a plurality of separate vertical access lines 740 .

[0106] According to example embodiments, Figure 7B-7E As shown in , the method includes vertically stacking ( Figure 4A 401) in the vertical stack (401) to form a second vertical opening 751 and selectively etch the second region 744 of the semiconductor material 732-1, 732-2, ..., 732-N to form a second horizontal opening 779, which is from the vertical stack ( Figure 4A In accordance with an embodiment, selectively etching the second region 744 of the semiconductor material 732-1, 732-2, ..., 732-N may include using an atomic layer etch (ALE) process. Figure 7C To explain more, second source / drain regions 778 may be formed in the semiconductor material 732 - 1 , 732 - 2 , . . . , 732 -N at a distal end of the second horizontal opening 779 from the vertical opening.

[0107] Figure 7B Description Fig. 7A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7BThe cross-sectional view shown in FIG. 1 is away from a plurality of individual vertical access lines 740-1, 740-2, ..., 740-N, 740-(N+1), ..., 740-(Z-1), and shows repeated iterations of alternating layers of dielectric material 730-1, 730-2, ..., 730-(N+1), semiconductor material 732-1, 732-2, ..., 732-N, and second dielectric material 733-1, 733-2, ..., 733-N separated by openings 751 on a semiconductor substrate 700 to form a vertical stack, which may be separated from the substrate 700 by an insulator material 720. Figure 7B As shown in FIG. , the vertical direction 711 is illustrated as a third direction (D3), such as the z direction in the xyz coordinate system, similar to Figure 1-3 The third direction (D3) 111 among the first, second and third directions shown in FIG. The plane of the drawing extends left and right along the first direction (D1) 709. Figure 7B In an example embodiment, materials within the vertical stack (dielectric materials 730-1, 730-2, ..., 730-(N+1), semiconductor materials 732-1, 732-2, ..., 732-N and second dielectric materials 733-1, 733-2, ..., 733-N) extend into and out of the plane of the drawing along a second direction (D2) and along the orientation axes of horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory.

[0108] Figure 7C Description Fig. 7A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 7C The cross-sectional view shown in the figure is illustrated as extending along a second direction (D2) 705, extending left and right along the plane of the drawing, and extending along an axis of a repeating iterative structure of alternating layers of first dielectric material 730-1, 730-2, ..., 730-N, semiconductor material 732-1, 732-2, ..., 732-N and second dielectric material 733-1, 733-2, ..., 733-N, and wherein horizontally-oriented access devices and horizontally-oriented storage nodes (e.g., capacitor cells) may be formed along the axis within the layers of semiconductor material 732-1, 732-2, ..., 732-N.

[0109] exist Figure 7C In the example embodiment of the present invention, the vertical opening 751 and the horizontal opening 779 are shown as being connected by combining Fig. 7A The mask, patterning and etching process described above is formed. Figure 7CAs shown in FIG. 7 , semiconductor materials 732-1, 732-2, ..., 732-N in the second region 744 have been selectively removed to form a horizontal opening 779. In one example, an atomic layer etch (ALE) process is used to selectively etch the semiconductor materials 732-1, 732-2, ..., 732-N and remove them back from the vertical opening 751 by a second distance (D2 opening). Figures 4A-4K The manufacturing process shown in FIG. 1 may be performed later or first in the second horizontal opening 779 to form a Figures 8A-8E A horizontally oriented storage node (e.g., capacitor cell) is shown in FIG.

[0110] Also like Figure 7C As shown in , the first source / drain region 775 may be formed by vapor-phase doping a dopant into a top surface portion of the semiconductor material 732. In some embodiments, the first source / drain region 775 may be adjacent to the vertical access line 740. According to an example embodiment, as shown in FIG. Figure 7C As shown in , a second source / drain region 778 can be formed by flowing a high energy gas phase dopant (e.g., phosphorus (P) for n-type transistors) into the second horizontal opening 779 at a distal end of the second horizontal opening 779 from the vertical opening 751 to dope the dopant into the semiconductor material 732-1, 732-2, ..., 732-N. In one example, gas phase doping can be used to achieve highly isotropic, such as non-directional doping, to form a second source / drain region 778 of a horizontally oriented access device in region 742. In another example, thermal annealing with a doping gas (e.g., phosphorus) can be used with high energy plasma assist to break bonding. However, the embodiments are not limited thereto and other suitable semiconductor fabrication techniques can be utilized.

[0111] A conductive material 777 may be deposited adjacent to the second dielectric material 733. The conductive material 777 may be in electrical contact with a top surface of the first source / drain region 775. Thus, the conductive material 777 is in electrical contact with the source / drain region 775. In some embodiments, a third dielectric material 774 may be below the first dielectric material 730, with a remaining portion in direct contact with the conductive material 777, the first source / drain region 775, and a first portion of the low-doped semiconductor material 732. The third dielectric material 774 may form a direct electrical contact with a highly doped p-type (p+) silicon material 795 (e.g., a body region contact region of a horizontally oriented access device).

[0112] like Figure 7C As further shown in FIG. 1 , the first electrode (eg, 761) of the horizontally oriented storage node will be coupled to the second source / drain region 778 of the horizontal access device. Figure 7CAs shown later in the drawing, such horizontally oriented storage nodes are shown to be formed in a second horizontal opening 779 extending from left to right in the plane of the drawing along a second direction (D2) and along the orientation axis of the horizontal access devices and horizontal storage nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory, the second horizontal opening 779 being 1 / 2 inches from the second horizontal opening 779 formed in the vertical stack (e.g. Figure 4A The vertical opening 751 in 401) reaches a second distance (D2 opening). Figure 7C , adjacent relative vertical access lines 740-3 are illustrated by dashed lines indicating locations set inwardly from the plane of the drawing and orientation.

[0113] Fig.7D Description Fig. 7A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.7D , 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N are formed in the semiconductor material layers 732-1, 732-2, ..., 732-N. The cross-sectional view shown in FIG. 1 is illustrated as extending from left to right in the plane of the drawing along a second direction (D2) 705 along an axis extending outside a region in which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) are to be formed in the semiconductor material layers 732-1, 732-2, ..., 732-N. The repeating iteration of the alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the semiconductor material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N is shown at the left end of the drawing, where horizontally oriented digital lines (e.g., Figure 1 The digital lines 107-1, 107-2, ..., 107-P, etc. shown in FIG. 107-1, 107-2, ..., 107-P, etc.) can be integrated to form an electrical contact with the first source / drain region or the digital line conductive contact material, as described above in conjunction with Figures 4A-4K described.

[0114] Furthermore, although reference to first and second source / drain regions is used herein to represent two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as the "first" and / or "second" source / drain regions have a unique meaning. It is intended that only one of the source / drain regions is connected to a digit line, such as 107-2, and the other may be connected to a storage node.

[0115] In some embodiments, the conductive material 777 may be illustrated as being adjacent to the second dielectric material 733. The conductive material 777 may be adjacent to the dielectric material 741. The body contact region 795 may be illustrated as a repeating iterative structure along alternating layers of the first dielectric material 730-1, 730-2, ..., 730-N, the semiconductor material 732-1, 732-2, ..., 732-N, and the second dielectric material 733-1, 733-2, ..., 733-N.

[0116] Fig. 7E Description Fig. 7A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig. 7E The cross-sectional view shown in FIG. 70 is illustrated as extending from right to left in the plane of the drawing along a first direction (D1) 709 along an axis of a repeating iterative structure of alternating layers of a first dielectric material 730-1, 730-2, ..., 730-N, a semiconductor material 732-1, 732-2, ..., 732-N, and a second dielectric material 733-1, 733-2, ..., 733-N, intersecting across a plurality of individual vertical access lines 740-1, 740-2, ..., 740-4, and intersecting a region of semiconductor material 732-1, 732-2, ..., 732-N, wherein a channel region may be formed, spaced apart from the plurality of individual vertical access lines 740-1, 740-2, ..., 740-4 by a gate dielectric 738. Fig. 7E , a first dielectric fill material 739 is shown as separating spaces between adjacent horizontally oriented access devices, which may be combined with Figures 4A-4K The formations are described as extending into and out of the plane of the drawing sheet and may be spaced apart along a first direction ( D1 ) 709 and stacked vertically in an array extending along a third direction ( D3 ) 711 in a three-dimensional (3D) memory.

[0117] Fig. 8A In another stage of the semiconductor manufacturing process, for example, a semiconductor device is formed according to several embodiments of the present disclosure. Figure 1-3 An example method for a vertically stacked memory cell array having horizontally oriented access devices and vertically oriented access lines is described in . Fig. 8A A top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process is illustrated according to one or more embodiments. Fig. 8A In an example embodiment of the present invention, the method includes using a photolithography process to form a photolithography mask 835, 836 and / or 837 (e.g., Figures 6A-6E 635, 636 and / or 637 or Figures 7A-7E 735, 736 and / or 737) are patterned. Fig. 8A The method further describes using one or more etching processes to form a storage node region 850 (and Fig. 8A and 8C A vertical opening 851 is formed in the vertical stack 844 and extends primarily along the first horizontal direction (D1) 809. The one or more etching processes form the vertical opening 851 to expose Figures 8B-8E 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N in the vertical stack shown in FIG. Other numbered components may be similar to those in the combination of FIG. Figures 6A-6E and those components shown and discussed in 7A-7E.

[0118] In some embodiments, this process is performed after selectively removing the semiconductor material in the access device region where the first source / drain region, the channel region, and the second source / drain region of the horizontally oriented access device are formed, such as Figures 7A-7E According to an example embodiment, as Figures 8B-8E As shown in , the method includes selectively etching the second region of semiconductor material 832-1, 832-2, ..., 832-N to deposit a second source / drain region and a capacitor unit through a second horizontal opening, the second horizontal opening being back from the vertical opening 851 in the vertical stack by a second horizontal distance. In some embodiments, as Figures 8B-8E As shown in , the method includes forming a capacitor cell as a storage node in the second horizontal opening. By way of example, but not limitation, forming the capacitor includes sequentially depositing a first electrode 861 and a second electrode 856 separated by a cell dielectric 863 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor fabrication techniques and / or storage node structures may be used. A digit line 877 may be found along a plurality of separate vertical access lines 840.

[0119] Figure 8B Description Fig. 8A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8BThe cross-sectional view shown in FIG. 8 is away from a plurality of individual vertical access lines 840-1, 840-2, ..., 840-N, 840-(N+1), ..., 840-(Z-1), and shows repeated iterations of alternating layers of dielectric material 830-1, 830-2, ..., 830-(N+1) separated by horizontally oriented capacitor cells on a semiconductor substrate 800 to form a vertical stack, wherein the horizontally oriented capacitor cells have a first electrode 861 (e.g., a bottom cell contact electrode), a cell dielectric 863, and a second electrode 856 (e.g., a top common node electrode), and the vertical stack may be separated from the substrate 800 by an insulator material 820. Figure 8B As shown in FIG. 8 , the vertical direction 811 is illustrated as a third direction (D3), such as the z direction in the xyz coordinate system, similar to Figure 1-3 The third direction (D3) 111 among the first, second and third directions shown in FIG. The drawing plane extends left and right along the first direction (D1) 809. Figure 8B In an example embodiment of the present invention, a first electrode 861 (e.g., a bottom electrode to couple to a source / drain region of a horizontal access device) and a second electrode 856 are illustrated as being separated by a cell dielectric material 863 extending in a second direction (D2) into and out of the plane of the drawing along an orientation axis of horizontal access devices and horizontal storage nodes of a vertically stacked memory cell array of a three-dimensional (3D) memory.

[0120] Figure 8C Description Fig. 8A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 8C The cross-sectional view shown in FIG. 8 is illustrated as extending along a second direction (D2) 805, extending left and right along the plane of the drawing, extending along an axis of a repeating iterative structure of alternating layers of a first dielectric material 830-1, 830-2, ..., 830-N, a semiconductor material 832-1, 832-2, ..., 832-N, and a second dielectric material 833-1, 833-2, ..., 833-N, and wherein horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed within the layers of semiconductor material 832-1, 832-2, ..., 832-N along the axis. Figure 8CIn an example embodiment of the present invention, a horizontally-oriented storage node (e.g., a capacitor cell) is illustrated as having been formed in this semiconductor manufacturing process, and a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 863 are shown. However, the embodiments are not limited to this example. In other embodiments, after forming the first source / drain region, the channel region, and the second source / drain region in the region of semiconductor material 832-1, 832-2, ..., 832-N intended for positioning (e.g., position formation) of the horizontally-oriented access device (described next), a first electrode 861 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 863 may be formed.

[0121] exist Figure 8C In the example embodiment of FIG. 1 , a horizontally oriented storage node having a first electrode 861 (e.g., a bottom electrode to be coupled to a source / drain region of a horizontal access device) and a second electrode 856 (e.g., a top electrode to be coupled to a common electrode plane such as a ground plane) is shown formed in a second horizontal opening (e.g., Figure 7C 779) shown in the drawing, the second horizontal opening extends left and right along the second direction (D2) in the drawing plane to a distance from the vertical stack (eg Figure 4A 401) in the vertical opening (e.g. Figure 7C 751) by a second distance (D2 opening) and along the directional axis of the horizontal access devices and horizontal storage nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 8C , adjacent relative vertical access lines 840-3 are illustrated by dashed lines indicating locations set inwardly from the plane and orientation of the drawing sheet.

[0122] The conductive material 877 may be illustrated as being adjacent to the second dielectric material 833. The conductive material 877 may be in direct electrical contact with the top surface of the first source / drain region 875. Thus, the conductive material 877 is in electrical contact with the source / drain region 875. In some embodiments, the third dielectric material 874 may be below the first dielectric material 830, with the remaining portion being in direct contact with the conductive material 877, the first source / drain region 875, and the first portion of the low-doped semiconductor material 832. The third dielectric material 874 may form a direct electrical contact with a highly doped p-type (p+) silicon material 895 (e.g., a body region contact region of a horizontally oriented access device).

[0123] Fig.8D Description Fig. 8A, which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig.8D The cross-sectional view shown in FIG. 8 is illustrated as extending left-right in the plane of the drawing along a second direction (D2) 805 along an axis of a repeating iterative structure of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 733-2, ..., 733-N outside a region in which horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) are to be formed within the semiconductor material layers 832-1, 832-2, ..., 832-N. Figure 8C , for a three-dimensional array of vertically oriented memory cells, dielectric material 841 is shown filling spaces between horizontally oriented access devices that may be spaced apart along a first direction (D1) extending into and out of the plane of the drawing. Fig.8D In the cross-sectional view of FIG. 1 , a second electrode 856 (e.g., a top common electrode of a capacitor cell structure) is additionally shown as being present in the space between horizontally adjacent devices. Repeated iterations of alternating layers of first dielectric material 830-1, 830-2, ..., 830-N, semiconductor material 832-1, 832-2, ..., 832-N, and second dielectric material 833-1, 833-2, ..., 833-N are shown at the left end of the drawing, where horizontally oriented digital lines (e.g., Figure 1 The digit lines 107-1, 107-2, ..., 107-P, etc.) shown in FIG. 107 may be integrated to form electrical contact with a second source / drain region or digit line conductive contact material, as described in more detail below.

[0124] In some embodiments, the conductive material 877 may be illustrated as being adjacent to the second dielectric material 833. The conductive material 877 may be adjacent to the dielectric material 841. The body contact region 895 may be illustrated as a repeating iterative structure along alternating layers of the first dielectric material 830-1, 830-2, ..., 830-N, the semiconductor material 832-1, 832-2, ..., 832-N, and the second dielectric material 833-1, 833-2, ..., 833-N.

[0125] Fig. 8E Description Fig. 8A , which shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Fig. 8EThe cross-sectional view shown in FIG. 8 is illustrated as extending from right to left in the plane of the drawing along a first direction (D1) 809 along an axis of a repeating iterative structure of alternating layers of a first dielectric material 830-1, 830-2, ..., 830-N, a semiconductor material 832-1, 832-2, ..., 832-N, and a second dielectric material 833-1, 833-2, ..., 833-N, intersecting across a plurality of individual vertical access lines 840-1, 840-2, ..., 840-4, and intersecting a region of semiconductor material 832-1, 832-2, ..., 832-N, wherein a channel region may be formed, spaced apart from the plurality of individual vertical access lines 840-1, 840-2, ..., 840-4 by a gate dielectric 838. Fig. 8E , a first dielectric fill material 839 is shown as spacing the spaces between adjacent horizontally-oriented access devices and horizontally-oriented storage nodes, which horizontally-oriented access devices and horizontally-oriented storage nodes can be formed to extend into and out of the plane of the drawing as described in more detail below, and can be spaced along a first direction (D1) 809 and vertically stacked in an array extending along a third direction (D3) 811 in a three-dimensional (3D) memory.

[0126] Fig. 9 A cross-sectional view illustrating a portion of an example horizontally oriented access device coupled to a horizontally oriented storage node and coupled to a vertically oriented access line and a horizontally oriented digit line according to several embodiments of the present disclosure, which horizontally oriented access device may form part of a vertically stacked array of memory cells. The horizontally oriented access device 901 may have a first source / drain region and a second source / drain region separated by a channel region, and a gate opposite the channel region and spaced therefrom by a gate dielectric.

[0127] like Fig. 9 As shown in the example of , the first source / drain region 975-1 is illustrated as being in direct electrical contact with the horizontally oriented digital line 977-1. In some embodiments, the conductive digital lines 977-1 and 977-2 are formed of a metal composition including tungsten (W). However, the embodiments are not limited to this example. Although the terms "first" and "second" source / drain regions may be used herein to designate distinct individual source / drain regions, the terms "first" and / or "second" are not limited to the corresponding source / drain regions in the source / drain regions, and their corresponding placement and their corresponding "first" or "second" labels used herein for convenience may be interchanged within the horizontally oriented access device described herein. For example, the first source / drain region 975-1 may also be represented as the "second" source / drain region 975-1. Whether the source / drain region is labeled "first" or "second", it may be separated from another source / drain region by a channel region in the body of the horizontal access device.

[0128] exist Fig. 9 In the example of , the first source / drain region 975-1 is illustrated as being formed in the body of the low-doped p-type (p-) channel and the body region of the horizontally oriented access device 901. The first source / drain region 975-1 is separated from the vertical body contact region 995 by a dielectric material 974. As shown, interlayer dielectric (ILD) materials 930-1 and 930-2 can separate the horizontally oriented access devices of the vertically stacked memory cells. The interlayer dielectric materials 930-1 and 930-2 can be a first dielectric material type, such as an oxide-based dielectric material. However, embodiments are not limited to this example.

[0129] exist Fig. 9 In an example, horizontally oriented digital lines (e.g., 977-1 and 977-2) are formed in a second dielectric material type (e.g., a nitride-based dielectric material). However, embodiments are not limited to this example. According to an embodiment, the first dielectric type material and the second dielectric type material are different compositions and are different so that one (e.g., the second dielectric) nitride material can be selectively etched relative to the first dielectric material (e.g., an oxide material). The access device 901 in which the first dielectric materials 930-1 and 930-2 are horizontally oriented includes a first source / drain region 975-1 and a p-type channel in a body region 932-1, and the digital lines 977-1 and 977-2 form a three-layer hierarchy of vertically stacked memory cells.

[0130] like Fig. 9 As shown in the example embodiment of , the vertical body contact region 995 is formed to be in direct electrical contact with the body region 932-1 of one or more of the horizontally oriented access devices 901. In some embodiments, the vertical body contact region 995 may be a metal, such as tungsten (W). In some embodiments, the vertical body contact region 995 may be a conductively doped polysilicon material, such as a highly doped p-type (p+) polysilicon semiconductor material. However, the embodiments are not limited to these examples. As used herein, the term "highly doped" is intended to mean a high concentration of doping impurities such that there is significant interaction between dopant atoms. The p-type dopant may include boron atoms (B) and the n-type dopant may include phosphorus atoms (P). According to an embodiment, the vertical body contact region 995 is separated from the first source / drain region 975-1 and the horizontally oriented digit lines 977-1 and 977-2 by a dielectric 974 (e.g., SiN in this example).

[0131] In some embodiments, the dielectric 974 further separates a first portion of the body region 932-1 of the horizontally oriented access device 901 (eg, Figure 4J478 in the vertical body contact region 995 is spaced apart to reduce the formation of holes in the body region 932-1 between the vertical body contact region 995 and the body region 932-1. In some embodiments, the dielectric 974 further separates the first portion (e.g., Figure 4J 478) is spaced apart from the vertical body contact region 995 to reduce gate induced drain leakage (GIDL) in the horizontally oriented access device 901. In some embodiments, the horizontally oriented storage nodes (e.g., Figure 7C The capacitor unit shown in FIG. 1 is coupled to the second source / drain region ( Fig. 9 ). In such examples, the capacitor cell has a first horizontally-oriented electrode electrically coupled to the second source / drain region and a second horizontally-oriented electrode spaced apart from the first horizontally-oriented electrode by a cell dielectric.

[0132] Therefore, if Fig. 9 As shown in the example embodiment of , a vertical conductive body contact line 995 (e.g., a highly doped semiconductor material) can be deposited into the vertical opening 995 to form a conductive body contact directly and only with a portion of the low-doped semiconductor material channel and the body region 932-1 of the horizontally oriented access device.

[0133] According to an embodiment, depositing the second dielectric material 974 forms a smaller direct electrical contact area between the conductive body contact region 995 and the channel in the body region 932-1 of the horizontally oriented access device, while also electrically isolating the first source / drain region 975-1 and the digit lines 977-1 and 977-2 from direct electric arcs. The smaller direct electrical contact area between the conductive body contact region 995 and the channel in the body region 932-1 and the electrical isolation from the first source / drain region 975-1 and the digit lines 977-1 and 977-2 can reduce the capacitive coupling between the body contact region 995 and the first source / drain region 975-1 and the digit lines 977-1 and 977-2. The smaller direct electrical contact area can also block the diffusion of holes between the highly doped semiconductor material 995 and the body region 932-1.

[0134] Fig.10 1 is a block diagram of an apparatus in the form of a computing system 1000 including a memory device 1003 according to several embodiments of the present disclosure. As used herein, for example, the memory device 1003, the memory array 1010, and / or the host 1002 may also be individually considered as a "device". According to an embodiment, according to the embodiments described herein, the memory device 1002 may include at least one memory array 1010 having memory cells formed with digit lines.

[0135] In this example, system 1000 includes a host 1002 coupled to a memory device 1003 via an interface 1004. Computing system 1000 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or a device with Internet of Things (IoT) functions, as well as various other types of systems. Host 1002 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 1003. System 1000 may include separate integrated circuits, or both host 1002 and memory device 1003 may be on the same integrated circuit. For example, host 1002 may be a system controller of a memory system including multiple memory devices 1003, wherein system controller 1005 provides access to the respective memory devices 1003 by another processing resource, such as a central processing unit (CPU).

[0136] exist Fig.10 In the example shown in FIG. 1 , the host 1002 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that may be loaded thereon (e.g., from a memory device 1003 via a controller 1005). The OS and / or various applications may be loaded from the memory device 1003 by providing access commands from the host 1002 to the memory device 1003 to access data comprising the OS and / or various applications. The host 1002 may also access data utilized by the OS and / or various applications by providing access commands to the memory device 1003 to retrieve the data utilized in the execution of the OS and / or various applications.

[0137] For clarity, system 1000 has been simplified to focus on features that are particularly relevant to the present disclosure. Memory array 1010 may be a DRAM array including at least one memory cell having a digit line and a body contact region formed according to the techniques described herein. For example, memory array 1010 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1010 may include memory cells arranged in rows coupled by word lines (which may be referred to herein as access lines or select lines) and columns coupled by digit lines (which may be referred to herein as sense lines or data lines). Although in Fig.10 A single array 1010 is shown in FIG. 1 , but embodiments are not limited thereto. For example, the memory device 1003 may include several arrays 1010 (eg, arrays of DRAM cells).

[0138] The memory device 1003 includes an address circuit system 1006 to latch address signals provided through the interface 1004. The interface may include, for example, a physical interface that employs a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such protocols may be custom or proprietary, or the interface 1004 may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. A row decoder 1008 and a column decoder 1012 receive and decode address signals to access the memory array 1010. Data may be read from the memory array 1010 by sensing voltage and / or current changes on the sense lines using a sense circuit system 1011. The sense circuit system 1011 may include, for example, a sense amplifier that can read and latch a page (e.g., row) of data from the memory array 1010. The I / O circuit system 1007 may be used for bidirectional data communication with the host 1002 via the interface 1004. Read / write circuitry 1013 is used to write data to or read data from memory array 1010. As examples, circuitry 1013 may include various drivers, latch circuitry, and the like.

[0139] Control circuit system 1005 decodes signals provided by host 1002. The signals may be commands provided by host 1002. These signals may include chip enable signals, write enable signals, and address latch signals to control operations performed on memory array 1010 (including data read operations, data write operations, and data erase operations). In various embodiments, control circuit system 1005 is responsible for executing instructions from host 1002. Control circuit system 1005 may include a state machine, a sequencer, and / or some other type of control circuit system, which may be implemented in the form of hardware, firmware, or software, or any combination of the three. In some examples, host 1002 may be a controller external to memory device 1003. For example, host 1002 may be a memory controller coupled to a processing resource of a computing device.

[0140] For example, the term semiconductor may refer to a material, a wafer, or a substrate, and includes any base semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a base semiconductor structure, and other semiconductor structures. Furthermore, when reference is made to a semiconductor in the foregoing description, previous processing steps may have been utilized to form regions / junctions in the base semiconductor structure, and the term semiconductor may include the base material containing these regions / junctions.

[0141] Figures herein follow numbering conventions, wherein the first one or more digits correspond to the figure number, and the remaining digits identify the elements or components in the diagram. Similar (e.g., identical) elements or components between different figures can be identified by using similar numerals. As should be understood, the elements shown in the various embodiments herein can be added, exchanged, and / or removed, thereby providing multiple additional embodiments of the present disclosure. In addition, as should be understood, the ratio and relative scale of the elements provided in the figure are intended to illustrate embodiments of the present disclosure, and should not be understood in a restrictive sense.

[0142] As used herein, "several" or "a certain number" of something may refer to one or more of such things. For example, several or a certain number of memory cells may refer to one or more memory cells. "Multiple" something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term "coupling" may include electrical coupling, direct coupling and / or direct connection (e.g., by direct physical contact) without an intermediate element, or indirect coupling and / or connection, or wireless coupling with an intermediate element. The term coupling may further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship). An element coupled between two elements may be between the two elements and coupled to each of the two elements.

[0143] It should be appreciated that the term vertical accounts for variations from "exact" vertical due to conventional manufacturing, measurement, and / or assembly variations, and that one of ordinary skill in the art will know the meaning of the term "perpendicular". For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent to" another element, the particular element may cover the other element, may be above or lateral to the other element, and / or may be in direct physical contact with the other element. For example, lateral to may refer to a horizontal direction (e.g., a y-direction or an x-direction) that may be perpendicular to the z-direction.

[0144] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover modifications or variations of the various embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative manner and not in a limiting manner. Upon reviewing the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents granted by these claims.

Claims

1. A method for forming an array (101, 1010) of vertically stacked memory cells (110) having horizontally oriented access devices (230, 901) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840), comprising: forming layers of a first dielectric material (430, 530, 630, 730, 830, 930), a low-doped semiconductor material (432, 532, 632, 732, 832), and a second dielectric material (433, 533, 633, 733, 833) in a vertically repeated iterative manner to form a vertical stack (401); forming a vertical opening (471) in the vertical stack (401); selectively etching the second dielectric material (433, 533, 633, 733, 833) to form a horizontal opening (473) in the second dielectric material (433, 533, 633, 733, 833); Vapor-phase doping a dopant into a top surface (478) of the low-doped semiconductor material (432, 532, 632, 732, 832) in the horizontal opening (473) to form a source / drain region (475, 775, 875, 975); forming a highly doped semiconductor material (482) in the horizontal opening (473); Selectively etching the highly doped semiconductor material (482) formed in the horizontal opening (473) so that a portion of the highly doped semiconductor material (482) remains; and The remaining highly doped semiconductor material (482) is converted into a conductive material (477) having properties different from the properties of the remaining highly doped semiconductor material (482). 2 . The method of claim 1 , wherein converting the remaining highly doped semiconductor material into the conductive material comprises exposing the remaining highly doped semiconductor material to a tungsten hexafluoride material. 3 . The method of claim 1 , further comprising removing from the source / drain regions any additional material formed on the source / drain regions during the converting of the remaining highly doped semiconductor material to the conductive material.

4. The method according to claim 1, wherein: The highly doped semiconductor material comprises a highly doped polysilicon material; and The conductive material includes tungsten material.

5. The method of claim 1, further comprising: selectively etching the second dielectric material to form the horizontal opening in the second dielectric material and to form an oxide material on sidewalls of the low-doped semiconductor material in the vertical opening (434); removing the oxide material (434); and Additional highly doped semiconductor material (495, 795, 895, 995) is formed in the vertical opening to form a conductive body contact with the lowly doped semiconductor material.

6. The method of claim 1, further comprising: selectively etching the source / drain regions and the lowly doped semiconductor material to form additional horizontal openings (472); and A third dielectric material (474, 774, 874) is formed in the additional horizontal opening.

7. The method of claim 1, wherein the first dielectric material comprises an oxide material and the second dielectric material comprises a silicon nitride (SiN) material.

8. The method of claim 1, wherein: forming the highly doped semiconductor material in the horizontal opening includes forming the highly doped semiconductor material in the vertical opening; and Selectively etching the highly doped semiconductor material formed in the horizontal opening includes etching the highly doped semiconductor material formed in the vertical opening.

9. A method for forming an array (101, 1010) of vertically stacked memory cells (110) having horizontally oriented access devices (230, 901) and vertically oriented access lines (103, 203, 303, 540, 640, 740, 840), comprising: forming layers of a first dielectric material (430, 530, 630, 730, 830, 930), a low-doped semiconductor material (432, 532, 632, 732, 832), and a second dielectric material (433, 533, 633, 733, 833) in a vertically repeated iterative manner to form a vertical stack (401); forming a vertical opening (471) in the vertical stack (401); selectively etching the second dielectric material (433, 533, 633, 733, 833) to form a first horizontal opening (473) in the second dielectric material (433, 533, 633, 733, 833) horizontally back a first distance (476) from the vertical opening (471); Vapor-phase doping a dopant into a top surface (478) of the low-doped semiconductor material (432, 532, 632, 732, 832) in the first horizontal opening (473) to form a source / drain region (475, 775, 875, 975); forming a first highly doped semiconductor material (482) in the first horizontal opening (473); Selectively etching the first highly doped semiconductor material (482) formed in the first horizontal opening (473) so that a portion of the first highly doped semiconductor material (482) formed in the first horizontal opening (473) remains; converting the remaining first highly doped semiconductor material (482) into a conductive material (477) having properties different from the properties of the remaining highly doped semiconductor material (482), wherein the source / drain regions (475, 775, 875, 975) remain intact during the converting; Selectively etching the source / drain regions (475, 775, 875, 975) and the low-doped semiconductor material (432, 532, 632, 732, 832) to form a second horizontal opening (472) horizontally back from the vertical opening (471) by a second distance (483); forming a third dielectric material (474, 774, 874) in the second horizontal opening (472); and A second highly doped semiconductor material (495, 795, 895, 995) is formed in the vertical opening (471). 10 . The method of claim 9 , wherein converting the remaining first highly doped semiconductor material into the conductive material comprises selectively reacting a tungsten hexafluoride material with the remaining first highly doped semiconductor material. 11 . The method of claim 9 , wherein forming the first highly doped semiconductor material in the first horizontal opening comprises isotropically depositing the first highly doped semiconductor material in the first horizontal opening.

12. The method of claim 9, wherein selectively etching the first highly doped semiconductor material formed in the first horizontal opening comprises anisotropically etching the first highly doped semiconductor material formed in the first horizontal opening using tetramethylammonium hydroxide (TMAH). 13 . The method of claim 9 , wherein the selective etching of the first highly doped semiconductor material formed in the first horizontal opening comprises dry etching.

14. The method of claim 9, wherein: Selectively etching the second dielectric material to form the first horizontal opening in the second dielectric material forms an oxide material on sidewalls (434) of the low-doped semiconductor material in the vertical opening; and Selectively etching the source / drain regions and the lowly doped semiconductor material to form the second horizontal opening includes etching the oxide material.

15. The method of claim 9, wherein: The first distance is greater than the second distance, and The first horizontal opening has a first height (435) and the second horizontal opening has a second height (485) greater than the first height.

16. A memory cell array (101, 1010), comprising: A plurality of access transistors (230, 901) stacked one above the other, each of the access transistors (230, 901) comprising a first source / drain region (221, 321, 475, 775, 875, 975), a second source / drain region (223, 323, 778) and a channel region (225, 325) and a body region (226, 326, 932) arranged horizontally therebetween; at least one access line (103, 203, 303, 540, 640, 740, 840) vertically elongated and coupled to each of the channel regions (225, 325) of the plurality of access transistors (230, 901) with the intervention of a gate dielectric (304, 538, 638, 738, 838); a plurality of storage capacitors (227) stacked one above the other, each of the plurality of storage capacitors (227) being horizontally positioned and coupled to a corresponding second source / drain region of the second source / drain regions (223, 323, 778) of the plurality of access transistors (230, 901); a plurality of digit lines (107, 207, 977), each of the plurality of digit lines (107, 207, 977) coupled to a corresponding first source / drain region of the first source / drain regions (221, 321, 475, 775, 875, 975) of the plurality of access transistors (230, 901); and A body contact region (295, 795, 895, 995) is vertically elongated and coupled to each of the body regions (226, 326, 932) of the plurality of access transistors (230, 901). 17 . The memory cell array of claim 16 , wherein each of the plurality of digit lines comprises a material containing tungsten converted from a polysilicon material.

18. The memory cell array according to claim 17, wherein: The tungsten includes β-phase tungsten; and The polysilicon material includes n-type (n+) highly doped polysilicon material.

19. The memory cell array of claim 16, wherein the first source / drain regions of the plurality of access transistors include n-type dopants doped into a low-doped semiconductor material (432, 532, 632, 732, 832).

20. The memory cell array of claim 16, wherein a portion of the body regions of the plurality of access transistors are separated from the body contact region by a dielectric.

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