Semiconductor storage device and manufacturing method thereof

Abstract

The present disclosure discloses a semiconductor memory device and a method for forming the same. The semiconductor memory device includes a substrate, a plurality of bit lines, a strip isolation structure, a conductive residue, a plurality of columnar isolation structures, and a plurality of conductive plugs. The plurality of bit lines are located on the substrate and extend along a first direction. A plurality of word lines are located within the substrate and extend along a second direction. The strip isolation structure is located at the end of the plurality of bit lines, extends along the second direction, and includes a gap, wherein the conductive residue is located in the gap. The plurality of columnar isolation structures are located between the plurality of bit lines and are separated from each other. The plurality of conductive plugs are located between the plurality of bit lines and are separated from each other, wherein the conductive plugs and the conductive residues comprise the same conductive material.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor storage device and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory widely used as a key component in many electronic devices. Traditional DRAM devices consist of multiple memory cells arranged in an array for data storage. Each cell can be composed of a metal oxide semiconductor (MOS) transistor and a capacitor connected in series.

[0003] As the size of dynamic random access memory devices continues to shrink due to increasing integration density, establishing electrical connections between memory cells has become increasingly difficult. Furthermore, the transistors and capacitors within each memory cell of a dynamic random access memory device have a variety of structural designs, driven by product requirements and cell density. Therefore, improving dynamic random access memory manufacturing processes remains a research hotspot in the relevant field. Summary of the Invention

[0004] One of the objectives of the present invention is to provide an improved semiconductor memory device and a method for forming the same to avoid the defects in the prior art.

[0005] To achieve the above-mentioned purpose, according to one embodiment of the present invention, there is provided a semiconductor memory device, comprising: a substrate; a plurality of bit lines located on the substrate and extending along a first direction; a plurality of word lines located within the substrate; the word lines extending along a second direction; a strip isolation structure located at the end of the plurality of bit lines and extending along the second direction, wherein the upper portion of the strip isolation structure comprises a gap; a conductive residue located in the gap; a plurality of columnar isolation structures separated from each other and located between the plurality of bit lines; a plurality of conductive plugs separated from each other and located between the plurality of bit lines, wherein the conductive residue and each of the conductive plugs comprise the same conductive material.

[0006] According to another embodiment of the present invention, a method for forming a semiconductor memory device is provided, comprising: providing a substrate; forming a plurality of word lines in the substrate; forming a plurality of bit lines on the substrate, wherein each bit line extends along a first direction and each word line extends along a second direction; forming a plurality of filling patterns between the plurality of bit lines and at ends of the plurality of bit lines, and forming a plurality of first gaps surrounded by the plurality of filling patterns and the plurality of bit lines, the plurality of filling patterns being separated from each other; depositing an insulating material to fill the plurality of first gaps surrounded by the plurality of filling patterns and the plurality of bit lines, and forming a plurality of cavities surrounded by the insulating material in the plurality of first gaps; etching the insulating material to form a strip isolation structure and a plurality of columnar isolation structures, wherein the cavities in the strip isolation structures are exposed to form gaps; after etching the insulating material, removing portions of the plurality of filling patterns to form a plurality of second gaps, wherein the plurality of second gaps are surrounded by the plurality of columnar isolation structures and the plurality of bit lines; and depositing a conductive material to fill the plurality of second gaps and simultaneously fill the gaps.

[0007] According to the embodiment of the present invention, since the conductive residues in the strip isolation structure are etched, the conductive residues are not continuously distributed in a certain direction, thereby avoiding unnecessary electrical connections between the conductive residues in the strip isolation structure and surrounding components. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 shows a top view of a semiconductor memory device according to an embodiment of the present invention.

[0009] Figure 2 A top view of a semiconductor memory device according to another embodiment of the present invention is shown.

[0010] Figure 3 Shown along Figure 1 A cross-sectional view taken along section lines AA' and BB'.

[0011] Figures 4 to 8 A cross-sectional schematic diagram shows the structure of a semiconductor memory device during the manufacturing process according to a method for manufacturing the semiconductor memory device according to an embodiment of the present invention.

[0012] The description of the accompanying drawings is as follows:

[0013] 10 Semiconductor memory devices

[0014] 100 substrate

[0015] 102 Storage Area

[0016] 104 Outer District

[0017] 110 character line

[0018] 120 bit lines

[0019] 122 bit line end

[0020] 130 Fill Pattern

[0021] 140 Insulation Materials

[0022] 142 Columnar Isolation Structure

[0023] 144 Strip Isolation Structure

[0024] 150 Gap

[0025] 150' cavity

[0026] 160 doping region

[0027] 170 conductive materials

[0028] 170A bottom conductive material

[0029] 170B top conductive material

[0030] 172 Conductive plug

[0031] 172A bottom conductive layer

[0032] 172B top conductive layer

[0033] 174 Conductive residue

[0034] 200 First Gap

[0035] 300 Second Gap

[0036] 400 mask pattern

[0037] 500 insulation layer DETAILED DESCRIPTION

[0038] The following is a detailed description of the storage device and its method of forming the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are provided solely for the purpose of illustrating the present invention with greater clarity and convenience.

[0039] The preferred embodiments of the present invention are shown in the accompanying drawings by numbered elements. In addition, without departing from the spirit of the present invention, the technical features in the different embodiments described below can be replaced, recombined or mixed with each other to form another embodiment.

[0040] Figure 1 and Figure 3 A schematic diagram of a semiconductor memory device according to an embodiment of the present invention is shown, wherein Figure 1 and Figure 3 The top view and cross-sectional view of a semiconductor memory device 10 are shown, respectively. In this embodiment, the semiconductor memory device 10 may be, for example, a dynamic random access memory device, comprising a plurality of memory cells, each of which may include at least one transistor structure (not shown) for switching signals and at least one capacitor structure (not shown) for storing electrical signals. The semiconductor memory device 10 includes a substrate 100, such as a silicon substrate, an epitaxial silicon substrate, or a silicon-on-insulator (SOI) substrate. A plurality of active regions (not shown) and isolation regions (not shown) are defined within the substrate 100. The plurality of active regions are arranged parallel to and spaced apart from each other in a plane defined by a first direction (x-direction) and a second direction (y-direction), and adjacent active regions are separated by the isolation regions. The isolation regions are made of an insulating material and may surround each active region, electrically isolating adjacent active regions from each other. A plurality of word lines (not shown) extending along the second direction (y-direction) are disposed in the substrate 100 . Each word line passes through a corresponding active region (not shown) and an isolation region (not shown).

[0041] In one embodiment, the above-mentioned isolation regions and word lines in the semiconductor memory device can be formed using the following steps, but are not limited thereto. First, at least one isolation region is formed in the substrate 100, such as shallow trench isolation (STI, not shown), to define active regions (not shown) separated from each other in the substrate 100. Next, a plurality of trenches (not shown) are formed in the isolation region and the active region, and each trench is parallel to each other and extends toward the second direction (y direction). Thereafter, the following steps can be performed in sequence to form word lines. A dielectric layer is formed to cover the surface of each trench in a forward direction; a gate dielectric layer is formed in a forward direction in the lower half of the trench; a buried gate fills the lower half of each trench; and an insulating layer is formed to fill the upper half of each trench. For example, Figure 3 As shown, the structure of the word line 110 may include a stacked structure of the above-mentioned material layers. The above-mentioned word line manufacturing method is only an example, and technicians can further adjust it according to known technology and actual needs, so it will not be described in detail here.

[0042] like Figure 1 As shown, the semiconductor memory device 10 includes a memory cell region 102 and a peripheral region 104 located next to the memory cell region 102. In some embodiments, the peripheral region 104 surrounds the memory cell region 102. Figure 1Only a portion of the memory area 102 and a portion of the peripheral area 104 are shown. The memory area 102 is provided with the plurality of memory cells, and the peripheral area 104 is provided with semiconductor elements, such as logic elements, computing elements, microprocessors or other non-memory units.

[0043] A plurality of bit lines 120 are disposed on the substrate 100, spanning the peripheral region 104 and the memory region 102, for transmitting information to and from the individual memory cells in the semiconductor memory device 10 to perform operations such as reading, writing, or updating the individual memory cells. The plurality of bit lines 120 are parallel to one another and extend along a first direction (x-direction). The bit lines 120 can be made of a conductive material, such as a metal (e.g., copper, aluminum, gold, tungsten, titanium), a metal alloy, carbon, a conductively doped semiconductor, or a combination thereof. Furthermore, the ends of the bit lines 120 located in the peripheral region 104 may be connected to bit line terminals 122. The bit line terminals 122 have a greater width in the second direction (y-direction). Therefore, by disposing plugs on the bit line terminals 122, the contact resistance (Rc) between the bit lines 120 and external interconnections can be relatively low. The bit line terminals 122 can be made of the same conductive material as the bit lines 120, but are not limited thereto.

[0044] In the peripheral region 104, a strip isolation structure 144 is disposed at the ends of the plurality of bit lines 120 located in the peripheral region 104 and extends along the second direction (y-direction). The upper portion of the strip isolation structure 144 along the third direction (z-direction) includes a slit 150, and preferably, the opening of the slit 150 is exposed at the topmost surface of the strip isolation structure 144. The strip isolation structure 144 may be made of an insulating material, such as, but not limited to, an oxide, a nitride, an oxynitride, or a combination thereof. In one embodiment, the strip isolation structure 144 partially contacts the plurality of bit lines 120, for example, contacting the end portion of at least one bit line 120. In one embodiment, the slit 150 extends along the second direction (y-direction) and is continuous. In one embodiment, the opening of the slit 150 has a width in the first direction (x-direction), preferably greater than 1 nanometer. In one embodiment, the semiconductor memory device 10 may further include a plurality of filling patterns 130 disposed on the substrate 100 in the peripheral region 104 for insulating adjacent bit lines 120, defining the positions of other components located in the semiconductor memory device 10, and maintaining the mechanical strength of the semiconductor memory device 10. In one embodiment, the plurality of filling patterns 130 may be formed using the following steps, but are not limited thereto. In detail, a filling material layer (not shown) is first formed on the substrate 100 and the plurality of bit lines 120. The filling material layer may be any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, boron or phosphorus-doped silicon oxide, carbon-doped oxide, fluorine-doped oxide, or any combination thereof, but is not limited thereto. The filling material layer may be formed by, for example, ALD, PVD, CVD, spin coating, sputtering, or other suitable thin film deposition processes to deposit the filling material layer. Then, a patterning process is performed to pattern the filling material layer to form a film such as Figure 1 The multiple filling patterns 130 are shown as being separated from each other. Optionally, the multiple filling patterns 130 can be disposed on both sides of the strip isolation structure 144 along the second direction (y direction).

[0045] In the storage area 102, a plurality of columnar isolation structures 142 are separated from each other and arranged between a plurality of bit lines 120, and cover the substrate 100, for isolating the bit lines 120 from being electrically connected to other peripheral components on the substrate 100. The plurality of columnar isolation structures 142 may be made of the same insulating material as the strip isolation structure 144, but is not limited thereto. Optionally, a filling pattern 130 may be provided between the strip isolation structure 144 and the columnar isolation structure 142. Optionally, a plurality of filling patterns 130 may be provided between a plurality of bit lines 120 and a plurality of columnar isolation structures 142. Optionally, a plurality of filling patterns 130 may be provided between at least two adjacent plurality of columnar isolation structures 142. Optionally, an etching selectivity ratio may be provided between the filling pattern 130 and the columnar isolation structure 142. From Figure 1 From a top view, the plurality of columnar isolation structures 142 may be, for example, rounded or square block structures. Preferably, the tops of the plurality of columnar isolation structures 142 do not include exposed gaps 150. In one embodiment, the width of the strip-shaped isolation structures 144 in the first direction (x-direction) is greater than the width of each columnar isolation structure 142 in the first direction (x-direction).

[0046] In addition, a plurality of conductive plugs 172 are disposed separately from each other in the memory area 102 and between the plurality of bit lines 120 in the memory area 102. Preferably, the plurality of bit lines 120 are electrically connected to a portion of the substrate 100, and each conductive plug 172 is electrically connected to another portion of the substrate 100. Figure 1 From a top view of the substrate 144, the plurality of conductive plugs 172 may be, for example, rounded or square block structures. Optionally, the plurality of conductive plugs 172 are disposed between adjacent columnar isolation structures 142, and the topmost surfaces of the conductive plugs 172 are higher than the topmost surfaces of the columnar isolation structures 142. On the other hand, the conductive residues 174 are disposed in the gaps 150 of the strip isolation structures 144, and preferably, the conductive residues 174 fill the gaps 150, and the topmost surfaces of the conductive residues 174 are flush with the topmost surfaces of the strip isolation structures 144. Optionally, the conductive residues 174 and each conductive plug 172 comprise the same conductive material. In one embodiment, the conductive residues 174 are electrically insulated from the substrate 100.

[0047] Figure 2 A top view of a semiconductor memory device according to another embodiment of the present invention is shown. Figure 2 The semiconductor memory device 10 shown is similar to Figure 1 The difference of the semiconductor memory device 10 shown is that Figure 2Conductive residue 174 disposed within gap 150 of strip isolation structure 144 is discontinuous in the second direction (y-direction). This discontinuity in the second direction (y-direction) is due to the fact that the bottom surface of gap 150 has different depths at different locations along the y-direction (the depth is parallel to the third direction), resulting in conductive residue 174 only partially filling gap 150.

[0048] Figure 3 It is along Figure 1 The sectional view shown by the AA and BB lines in FIG. Figure 3 The cross-sectional view shown is to supplement Figure 1 Features not shown. Figure 3 As shown, a doped region 160 is also formed in the substrate 100, where the doped region 160 is part of the active region. The conductivity type of the doped region 160 can be n-type or p-type, and the top surface of the doped region 160 can be flush with the substrate 100. A plurality of buried word lines 110 are also formed in the substrate 100 to switch the memory cells in the semiconductor memory device to perform operations such as reading, writing, or updating the memory cells. The word lines 110 are parallel to each other and extend along the second direction (y-direction), and cross below each of the active regions.

[0049] In one embodiment, each columnar isolation structure 142 has a cavity 150', and the cavity 150' is completely covered by the columnar isolation structure 142. In contrast, a gap 150 exists in the stripe isolation structure 144. The gap 150 is filled with conductive residue 174, and the top surface of the gap 150 has an opening.

[0050] In one embodiment, the semiconductor memory device 10 may further include an insulating layer 500 covering the strip-shaped isolation structures 144, the conductive residues 174, and the plurality of pillar-shaped isolation structures 142. Optionally, the bottommost surface of the insulating layer 500 directly contacts the conductive residues 174. Optionally, the topmost surface of the insulating layer 500 is flush with the topmost surface of the conductive plugs 172. In one embodiment, each conductive plug 172 includes a bottom conductive layer 172A and a top conductive layer 172B, wherein the material of the bottom conductive layer 172A is different from the material of the top conductive layer 172B, and the bottom conductive layer 172A and the conductive residues 174 include the same conductive material. For example, the bottom conductive layer 172A may be a conductive material with good gap-filling capability, such as titanium nitride or tungsten nitride, and the top conductive layer 172B may be a material with low resistivity, such as aluminum or copper. Optionally, the bottom conductive layer 172A covers and directly contacts the doped region 160 and the columnar isolation structure 142 on both adjacent sides, and presents a U-shaped structure; the top conductive layer 172B is disposed on the bottom conductive layer 172A and fills the U-shaped structure of the bottom conductive layer 172A.

[0051] In order to enable those skilled in the art to implement the present invention, the specification further describes the method for manufacturing the semiconductor memory device of the present invention. Figures 4 to 8 As shown, Figures 4 to 8 A cross-sectional schematic diagram shows the structure of a semiconductor memory device during the manufacturing process according to a method for manufacturing the semiconductor memory device according to an embodiment of the present invention.

[0052] First, if Figure 4 As shown, a substrate 100 is provided, such as a silicon substrate, an epitaxial silicon substrate, or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) and active regions (not shown) are formed within the substrate 100. The active regions are arranged parallel to and spaced apart from each other in a plane defined by a first direction (x-direction) and a second direction (y-direction), and adjacent active regions are separated by the isolation regions. The isolation regions are made of an insulating material and surround each active region, electrically isolating adjacent active regions from each other. Furthermore, a plurality of buried word lines 110 are formed within the substrate 100 for receiving and transmitting voltage signals from individual memory cells in the semiconductor memory device. Each word line 110 is parallel to each other and extends along the second direction (y-direction), spanning beneath each active region. It should be noted that the detailed features and fabrication methods of the word lines 110 have been mentioned above and will not be repeated here.

[0053] Next, a plurality of bit lines 120 are formed on the substrate 100, wherein each bit line 120 extends along a first direction (x direction). In one embodiment, the bit lines 120 may be formed by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but are not limited thereto. In some embodiments, depending on actual use requirements, the bit lines 120 may have different extension lengths, or may all have the same length and be aligned. When forming the plurality of bit lines 120 on the substrate 100, the plurality of bit lines 120 further have bit line ends 122 formed at the ends of the peripheral region 104, and the bit line ends 122 are electrically connected to the ends of the bit lines 120 located in the peripheral region 104, thereby increasing the contact area of the bit lines 120 with the external connection, so that the bit lines 120 and the external connection can have a relatively low contact resistance (Rc).

[0054] After forming a plurality of bit lines 120 on the substrate 100, a plurality of filling patterns 130 separated from each other are formed between the plurality of bit lines 120 and at the ends of the plurality of bit lines 120. In detail, a filling material layer (not shown) is first formed on the substrate 100 and the plurality of bit lines 120. The filling material layer can be any suitable insulating material, for example, it can include silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, boron or phosphorus doped silicon oxide, carbon doped oxide, fluorine doped oxide or any combination thereof, but is not limited thereto. The filling material layer can be formed by, for example, ALD, PVD, CVD, spin coating, sputtering or other suitable thin film deposition processes to deposit the filling material layer. Then, a patterning process is performed to pattern the filling material layer to form filling patterns 130 separated from each other, thereby forming a plurality of first gaps 200 surrounded by the plurality of filling patterns 130 and the plurality of bit lines 120.

[0055] In one embodiment, the width of the first gap 200 in the peripheral region 104 in the first direction (x direction) is greater than the width of the first gap 200 in the memory region 102 in the first direction (x direction).

[0056] After forming a plurality of filling patterns 130 between the plurality of bit lines 120 and at the ends of the plurality of bit lines 120, an insulating material 140 is deposited to fill the plurality of first gaps 200 surrounded by the plurality of filling patterns 130 and the plurality of bit lines 120, and a plurality of cavities 150' surrounded by the insulating material 140 are formed in the plurality of first gaps 200, respectively. The composition of the insulating material 140 may be, for example, an oxide, a nitride, an oxynitride, or / and a combination thereof, but is not limited thereto. Optionally, the plurality of cavities 150' are completely covered by the insulating material 140, that is, the insulating material 140 does not expose the topmost surface of the cavity 150'. The cavity 150' extends along the second direction (y-direction), and the cavity 150' may be discontinuous in the second direction, thereby appearing discontinuous.

[0057] In one embodiment, because the width of the first gaps 200 in the peripheral region 104 in the first direction (x-direction) is greater than the width of the first gaps 200 in the memory region 102 in the first direction (x-direction), when the insulating material 140 is deposited to fill the plurality of first gaps 200, the width of the cavities 150' in the first gaps 200 in the peripheral region 104 in the first direction (x-direction) and the height in the third direction (z-direction) are both greater than the corresponding width and height of the cavities 150' in the first gaps 200 in the memory region 102. Preferably, the height of the cavities 150' in the first gaps 200 in the memory region 102 in the third direction (z-direction) is lower than the topmost surface of the filling pattern 130 in the third direction (z-direction), while the height of the cavities 150' in the first gaps 200 in the peripheral region 104 in the third direction (z-direction) is higher than the topmost surface of the filling pattern 130 in the third direction (z-direction).

[0058] After depositing the insulating material 140 to fill the first gaps 200 surrounded by the filling patterns 130 and the bit lines 120, Figure 5 As shown, the insulating material 140 is planarized to form a strip isolation structure 144 and a plurality of columnar isolation structures 142, wherein the cavities 150' in the strip isolation structures 144 are exposed, forming gaps 150. From a top view (not shown), the strip isolation structures 144 can extend along the second direction (y-direction), and the columnar isolation structures 142 can be, for example, block-shaped structures with rounded corners or squares. Alternatively, the planarization process can be replaced with or combined with an etching process, including but not limited to wet etching, dry etching, or a combination thereof. Alternatively, the width of the strip isolation structures 144 in the first direction (x-direction) is greater than the width of the columnar isolation structures 142 in the first direction (x-direction). Therefore, the cavities 150' in the columnar isolation structures 142 have a lower height in the third direction (z-direction) than the cavities 150' in the strip isolation structures 144. This allows the cavities 150' in the strip isolation structures 144 to be preferentially exposed when etching the insulating material 140. In addition, the bottom surface of the cavity 150 ′ in the stripe isolation structure 144 is closer to the substrate 100 in the third direction (z direction) than the bottom surface of the cavity 150 ′ in the column isolation structure 142 .

[0059] In one embodiment, due to the etching selectivity between the filling pattern 130 and the columnar isolation structure 142 and / or the stripe isolation structure 144, the height of the filling pattern 130 in the third direction (z-direction) can be considered unchanged during the planarization process. Preferably, the height of the columnar isolation structure 142 and the stripe isolation structure 144 in the third direction (z-direction) is less than the height of the filling pattern 130 in the third direction (z-direction).

[0060] In one embodiment, the slit 150 extends along the second direction (y direction) and is discontinuous. In one embodiment, the opening of the slit 150 has a width in the first direction (x direction), and preferably, the width is greater than 1 nanometer.

[0061] After etching the insulating material 140 , portions of the filling patterns 130 may be removed to form a plurality of second gaps 300 surrounded by a plurality of columnar isolation structures 142 and a plurality of bit lines 120 , wherein the removed filling patterns 130 are all filling patterns 130 located in the storage region 102 .

[0062] Then, if Figure 6 As shown, after portions of the plurality of columnar isolation structures 142 are removed to form a plurality of second gaps 300, doped regions 160 are formed in the substrate exposed by the plurality of second gaps 300. The conductivity type of the doped regions 160 can be n-type or p-type, and their top surfaces are flush with the substrate 100. Then, a conductive material 170 is deposited to fill the plurality of second gaps 300 surrounded by the plurality of columnar isolation structures 142 and the plurality of bit lines 120, and simultaneously fill the gaps 150. The conductive material 170 filled in the gaps 150 is electrically insulated from the substrate 100. The conductive material 170 may include a bottom conductive material 170A and a top conductive material 170B, wherein the material of the bottom conductive material 170A is different from the material of the top conductive material 170B. Specifically, a bottom conductive material 170A is first deposited to fill the plurality of second gaps 300 surrounded by the strip isolation structure 144, the plurality of columnar isolation structures 142, and the plurality of bit lines 120, and simultaneously fill the gaps 150. Then, a top conductive material 170B is deposited to cover the bottom conductive material 170B and fill the plurality of second gaps 300.

[0063] In one embodiment, when depositing the conductive material 170 , the filling patterns 130 may be disposed on both sides of the strip isolation structure 144 . In one embodiment, when depositing the conductive material 170 , multiple filling patterns 130 may be disposed between the multiple bit lines 120 and the multiple pillar isolation structures 142 .

[0064] Please continue to refer to Figure 6 ,like Figure 6 As shown, after depositing the conductive material 170 , a plurality of mask patterns 400 are formed to align with and cover portions of the conductive material 170 located in the second gap 300 .

[0065] Then, if Figure 7As shown, after forming a plurality of mask patterns 400, an etching process can be performed using the mask patterns as etching masks. The etching process may include, but is not limited to, dry etching, wet etching, or reactive ion etching (RIE). After the etching process is completed, the conductive material 170 deposited in the gaps 150 in the strip isolation structures 144 forms a conductive residue 174, the conductive material 170 deposited in the second gaps 300 forms a conductive plug 172, and the conductive material 170 deposited on the filling patterns 130, the columnar isolation structures 142, and the strip isolation structures 144 is completely removed, exposing the topmost surfaces of the filling patterns 130, the columnar isolation structures 142, and the strip isolation structures 144. Furthermore, the conductive plug 172 includes a bottom conductive layer 172A and a top conductive layer 172B. The material of the bottom conductive layer 172A is the same as that of the bottom conductive material 170A, and the material of the top conductive layer 172B is the same as that of the top conductive layer 170B. Optionally, after the etching process is completed, a CMP process may be further performed to make the top surfaces of the filling pattern 130 , the column isolation structure 142 , and the strip isolation structure 144 flush.

[0066] Finally, after the etching process is completed, the mask pattern 400 is removed to form Figure 8 The semiconductor memory device shown.

[0067] Afterwards, an insulating layer 500 may be formed around the conductive plug 172 to form a Figure 3 The semiconductor memory device shown. Based on actual needs, other suitable semiconductor processes may be subsequently performed to form a capacitor structure (not shown) electrically connected to the conductive plug 172, and to form interconnect structures (not shown), pads (not shown), and other components above the insulating layer 500, but the present invention is not limited thereto.

[0068] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that: Include: substrate; a plurality of bit lines located on the substrate and extending along a first direction; a plurality of word lines located in the substrate; The word line extends along a second direction; a strip-shaped isolation structure, located at ends of the plurality of bit lines and extending along the second direction, wherein an upper portion of the strip-shaped isolation structure comprises a gap; a conductive residue located in the gap; a plurality of columnar isolation structures, separated from each other and located between the plurality of bit lines; A plurality of conductive plugs are separated from each other and located between the plurality of bit lines, wherein the conductive residue and each of the conductive plugs comprise the same conductive material.

2. The semiconductor memory device according to claim 1, wherein The gap extends along the second direction and is discontinuous.

3. The semiconductor memory device according to claim 1, wherein The opening of the slit has a width in the first direction, and the width is greater than 1 nanometer.

4. The semiconductor memory device according to claim 1, wherein The width of the strip-shaped isolation structure in the first direction is greater than the width of each of the column-shaped isolation structures in the first direction.

5. The semiconductor memory device according to claim 1, wherein The conductive residue is electrically insulated from the substrate.

6. The semiconductor memory device according to claim 1, wherein The invention also includes an insulating layer covering the strip-shaped isolation structure, the conductive residue, and the plurality of column-shaped isolation structures.

7. The semiconductor memory device according to claim 6, wherein The bottommost surface of the insulating layer directly contacts the conductive residue.

8. The semiconductor memory device according to claim 1, wherein The invention further comprises a plurality of filling patterns, wherein the plurality of filling patterns are arranged between the strip-shaped isolation structures and the plurality of column-shaped isolation structures.

9. The semiconductor memory device according to claim 8, wherein The plurality of filling patterns are disposed on both sides of the strip-shaped isolation structure.

10. The semiconductor memory device according to claim 1, wherein Each of the columnar isolation structures includes a cavity.

11. The semiconductor memory device according to claim 10, wherein The bottom surface of the slit is closer to the substrate in the third direction than the bottom surface of the cavity.

12. The semiconductor memory device according to claim 1, wherein The stripe isolation structure contacts an end portion of at least one bit line among the plurality of bit lines.

13. The semiconductor memory device according to claim 1, wherein Each of the conductive plugs includes a bottom conductive layer and a top conductive layer, wherein a material of the bottom conductive layer is different from a material of the top conductive layer, and the bottom conductive layer and the conductive residue include the same conductive material.

14. A method for manufacturing a semiconductor memory device, characterized in that: Include: providing a substrate; forming a plurality of word lines in the substrate; forming a plurality of bit lines on a substrate, wherein each of the bit lines extends along a first direction and each of the word lines extends along a second direction; forming a plurality of filling patterns between the plurality of bit lines and at ends of the plurality of bit lines, and forming a plurality of first gaps surrounded by the plurality of filling patterns and the plurality of bit lines, wherein the plurality of filling patterns are separated from each other; Depositing an insulating material to fill the first gaps surrounded by the filling patterns and the bit lines, and forming a plurality of cavities surrounded by the insulating material in the first gaps; etching the insulating material to form a strip-shaped isolation structure and a plurality of column-shaped isolation structures, wherein the cavity in the strip-shaped isolation structure is exposed to form a gap; After etching the insulating material, removing portions of the plurality of filling patterns to form a plurality of second gaps, wherein the plurality of columnar isolation structures and the plurality of bit lines surround the plurality of second gaps; as well as A conductive material is deposited to fill the plurality of second gaps and the slit at the same time.

15. The method for manufacturing a semiconductor memory device according to claim 14, wherein: The gap extends along the second direction and is discontinuous.

16. The method for manufacturing a semiconductor memory device according to claim 14, wherein: The opening of the slit has a width in the first direction, and the width is greater than 1 nanometer.

17. The method for manufacturing a semiconductor memory device according to claim 14, wherein: The width of the strip-shaped isolation structure in the first direction is greater than the width of each of the column-shaped isolation structures in the first direction.

18. The method for manufacturing a semiconductor memory device according to claim 14, wherein: When depositing the conductive material, the filling patterns are arranged on both sides of the strip-shaped isolation structure.

19. The method for manufacturing a semiconductor memory device according to claim 14, wherein: When depositing the conductive material, the filling patterns are disposed between the bit lines and the column isolation structures.

20. The method for manufacturing a semiconductor memory device according to claim 14, wherein: The conductive material filled in the gap is electrically insulated from the substrate.

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