Display panel, display device, and method of manufacturing display panel

Abstract

A display panel is provided. The display panel includes a first hole in a first window area and a second hole in a second window area. The display panel includes a touch electrode layer, and the touch electrode layer includes a plurality of first touch electrodes and a plurality of second touch electrodes. In the inter-window area, a first corresponding touch electrode among the plurality of first touch electrodes and a second corresponding touch electrode among the plurality of second touch electrodes that are directly adjacent to each other are separated by a first gap having a first gap width. In the display area, a third corresponding touch electrode among the plurality of first touch electrodes and a fourth corresponding touch electrode among the plurality of second touch electrodes that are directly adjacent to each other are separated by a second gap having a second gap width. The first gap width is greater than the second gap width.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a display panel, a display device and a method for manufacturing the display panel. Background Art

[0002] Various types of touch panels have been developed. Examples of touch panels include one-glass-solution (OGS) touch panels, on-cell touch panels, and in-cell touch panels. On-cell touch panels provide high touch accuracy. On-cell touch panels can be divided into single-layer-on-cell (SLOC) touch panels and multi-layer-on-cell (MLOC) touch panels. In particular, multi-touch can be achieved in MLOC touch panels with superior touch accuracy and blanking effect. Summary of the invention

[0003] In one aspect, the present disclosure provides a display panel having an array substrate and a counter substrate assembled together; wherein the display panel has a display area configured to display an image, a first window area, a second window area, and an inter-window area between the first window area and the second window area; the display panel includes a first hole in the first window area and a second hole in the second window area; the inter-window area is directly adjacent to / adjoining the first window area and directly adjacent to the second window area; wherein the display panel includes a touch electrode layer in the display area and in the inter-window area, the touch electrode layer including a plurality of first touch electrodes and a plurality of second touch electrodes; wherein, in the inter-window area, a first corresponding first touch electrode among the plurality of first touch electrodes directly adjacent to each other and a second corresponding second touch electrode among the plurality of second touch electrodes are separated by a first gap having a first gap width; in the display area, a third corresponding first touch electrode among the plurality of first touch electrodes directly adjacent to each other and a fourth corresponding second touch electrode among the plurality of second touch electrodes are separated by a second gap having a second gap width; and the first gap width is greater than the second gap width.

[0004] Optionally, the first window area, the second window area and the inter-window area are surrounded by the display area.

[0005] Optionally, there are no display elements and thin film transistors in the first window area and the second window area; and the display panel further includes a first accessory installed in the first hole and a second accessory installed in the second hole.

[0006] Optionally, a fifth corresponding first touch electrode among the plurality of first touch electrodes and a sixth corresponding second touch electrode among the plurality of second touch electrodes, which are directly adjacent to each other, are separated by an inter-region gap extending from the inter-window region to the display region; the inter-region gap includes a first sub-gap in the inter-window region and a second sub-gap in the display region, the first sub-gap being directly connected to the second sub-gap; the first sub-gap has a first sub-gap width; the second sub-gap has a second sub-gap width; and the first sub-gap width is greater than the second sub-gap width.

[0007] Optionally, the plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines; and the line widths of the plurality of grid electrode lines directly adjacent to the first sub-gap are greater than the line widths of the plurality of grid electrode lines directly adjacent to the second sub-gap.

[0008] Optionally, the plurality of first touch electrodes are a plurality of first grid electrodes, each of the plurality of first grid electrodes includes a plurality of first grid electrode lines; the plurality of second touch electrodes are a plurality of second grid electrodes, each of the plurality of second grid electrodes includes a plurality of second grid electrode lines; the first gap has a first boundary formed by virtually connecting outer edges of the plurality of first grid electrode lines of the first corresponding first touch electrodes of the plurality of first touch electrodes and a second boundary formed by virtually connecting outer edges of the plurality of second grid electrode lines of the second corresponding second touch electrodes of the plurality of second touch electrodes; the second gap has a third boundary formed by virtually connecting outer edges of the plurality of first grid electrode lines of the third corresponding first touch electrodes of the plurality of first touch electrodes and a fourth boundary formed by virtually connecting outer edges of the plurality of second grid electrode lines of the fourth corresponding second touch electrodes of the plurality of second touch electrodes; the first gap width is a first shortest distance between the first boundary and the second boundary; and the second gap width is a second shortest distance between the third boundary and the fourth boundary.

[0009] Optionally, the plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines; the grid electrode lines include a plurality of first grid electrode lines in the inter-window area and a plurality of second grid electrode lines in the display area; a corresponding first grid electrode line among the plurality of first grid electrode lines has a first line width; a corresponding second grid electrode line among the plurality of second grid electrode lines has a second line width; the first line width is greater than the second line width; and an inter-area boundary between the inter-window area and the display area is defined by an imaginary line, and the line width of the grid electrode line transitions from the first line width to the second line width through the imaginary line.

[0010] Optionally, the grid electrode lines include inter-region grid electrode lines extending from the inter-window region to the display region; the inter-region grid electrode lines include a first sub-line in the inter-window region and a second sub-line in the display region, the first sub-line being directly connected to the second sub-line; the first sub-line has a first sub-line width; the second sub-line has a second sub-line width; and the first sub-line width is greater than the second sub-line width.

[0011] Optionally, the inter-region grid electrode line is directly adjacent to an inter-region gap extending from the inter-window region to the display region; the inter-region gap includes a first sub-gap in the inter-window region and a second sub-gap in the display region, the first sub-gap being directly connected to the second sub-gap; the first sub-gap has a first sub-gap width; the second sub-gap has a second sub-gap width; and the first sub-gap width is greater than the second sub-gap width.

[0012] Optionally, at least a first portion of a boundary of the first sub-gap in the inter-window area is formed by virtually connecting outer edges of the first sub-line of the inter-area grid electrode line; at least a second portion of a boundary of the second sub-gap in the display area is formed by virtually connecting outer edges of the second sub-line of the inter-area grid electrode line; and the first portion and the second portion are directly connected.

[0013] Optionally, the display panel also includes a plurality of filling patterns located in the same layer as the plurality of first touch electrodes and the plurality of second touch electrodes, and the plurality of filling patterns are insulated from the plurality of first touch electrodes and the plurality of second touch electrodes; wherein the plurality of filling patterns are confined to the display area, and the plurality of filling patterns do not exist in the inter-window area, the first window area, and the second window area.

[0014] Optionally, the display panel also includes a plurality of blanking grid interruptions, a corresponding one of the plurality of blanking grid interruptions disconnecting a grid electrode line in a separate grid electrode block; wherein the plurality of blanking grid interruptions are confined to the display area and are not present in the inter-window area, the first window area, and the second window area.

[0015] Optionally, the first gap includes a plurality of first parts and a plurality of second parts, each of the plurality of first parts is oriented along a first orientation, and each of the plurality of second parts is oriented along a second orientation; the second gap includes a plurality of third parts and a plurality of fourth parts, each of the plurality of third parts is oriented along the first orientation, and each of the plurality of fourth parts is oriented along the second orientation; a corresponding one of the plurality of first parts has a first part gap width; a corresponding one of the plurality of second parts has a second part gap width; a corresponding one of the plurality of third parts has a third part gap width; and a corresponding one of the plurality of fourth parts has a fourth part gap width.

[0016] Optionally, the gap width of the first portion is greater than the gap width of the third portion and / or the gap width of the fourth portion; the gap width of the second portion is greater than the gap width of the third portion and / or the gap width of the fourth portion.

[0017] Optionally, the display panel includes a touch insulation layer below the touch electrode layer and in contact with the touch electrode layer; the touch insulation layer has a first contact surface in contact with the touch electrode layer in the inter-window area and a second contact surface in contact with the touch electrode layer in the display area; the first contact surface has a first unevenness; the second contact surface has a second unevenness; and the first unevenness is greater than the second unevenness.

[0018] Optionally, the display panel includes an encapsulation layer below the touch structure, the touch structure includes a touch electrode layer, the encapsulation layer is in contact with the touch structure, the encapsulation layer has a first contact surface in contact with the touch structure in the inter-window area and a second contact surface in contact with the touch structure in the display area; the first contact surface has a first unevenness; the second contact surface has a second unevenness; and the first unevenness is greater than the second unevenness.

[0019] Optionally, the touch control structure includes a touch insulating layer between the touch electrode layer and the encapsulation layer; the touch insulating layer contacts the touch electrode layer; and the touch insulating layer is coformed according to the encapsulation layer.

[0020] Optionally, a corresponding one of the multiple first touch electrodes includes a plurality of first touch electrode blocks arranged along a first direction; a corresponding one of the multiple second touch electrodes includes a plurality of second touch electrode blocks arranged along a second direction; the multiple first touch electrode blocks are electrically connected to form a first conductive channel along the first direction, and adjacent first touch electrode blocks among the multiple first touch electrode blocks are connected through a first electrode bridge; the multiple second touch electrode blocks are electrically connected to form a second conductive channel along the second direction, and adjacent second touch electrode blocks among the multiple second touch electrode blocks are connected through a second electrode bridge; the multiple first touch electrode blocks, the multiple second touch electrode blocks, and one of the first electrode bridge and the second electrode bridge are in a first touch material layer and are made of the same material, and the other of the first electrode bridge and the second electrode bridge is in a second touch material layer different from the first touch material layer.

[0021] Optionally, the second touch material layer is between the array substrate and the first touch material layer.

[0022] Optionally, the display panel further comprises a plurality of thin film transistors in the display area and in the inter-window area; wherein the display panel comprises: a base substrate; an insulating layer on the base substrate; an active layer of a corresponding one of the plurality of thin film transistors on a side of the insulating layer away from the base substrate; a first gate insulating layer on a side of the active layer away from the base substrate; a gate electrode and a first capacitor electrode on a side of the first gate insulating layer away from the insulating layer; a second gate insulating layer on a side of the gate electrode and the first capacitor electrode away from the first gate insulating layer; a second gate insulating layer on a side of the second gate insulating layer away from the first gate A second capacitor electrode on one side of the insulating layer; an interlayer dielectric layer on the side of the second capacitor electrode away from the second gate insulating layer; a source electrode and a drain electrode on the side of the interlayer dielectric layer away from the second gate insulating layer; a passivation layer on the side of the source electrode and the drain electrode away from the interlayer dielectric layer; a first planarization layer on the side of the passivation layer away from the interlayer dielectric layer; a second planarization layer on the side of the first planarization layer away from the passivation layer; a relay electrode on the side of the second planarization layer away from the first planarization layer; and a pixel defining layer on the side of the second planarization layer away from the base substrate.

[0023] Optionally, the display panel further includes a plurality of display elements in the display area and a plurality of dummy display elements in the area between the windows; wherein the display panel includes: an anode on a side of the second planarization layer away from the first planarization layer, the anode being confined to the display area and not present in the area between the windows; a light-emitting layer in the display area and in the area between the windows, the light-emitting layer in the display area being on a side of the anode away from the second planarization layer, and the light-emitting layer in the area between the windows being on a side of the second planarization layer away from the first planarization layer; a cathode layer in the display area and in the area between the windows, the cathode layer being on a side of the light-emitting layer away from the second planarization layer; and an encapsulation layer on a side of the cathode layer away from the light-emitting layer, the encapsulation layer encapsulating the plurality of display elements in the display area and the dummy light-emitting elements in the area between the windows.

[0024] In another aspect, the present disclosure provides a display device, comprising a display panel as described herein or manufactured by a method as described herein, and an integrated circuit connected to the display panel.

[0025] On the other hand, the present disclosure provides a method for manufacturing a display panel, the display panel having an array substrate and an opposing substrate assembled together, the method comprising: forming a first hole in a first window area; and forming a second hole in a second window area; wherein the display panel is formed to have a display area configured to display an image, the first window area, the second window area, and an inter-window area between the first window area and the second window area; and the inter-window area is directly adjacent to the first window area and directly adjacent to the second window area; the method further comprises forming a touch electrode layer in the display area and the inter-window area, forming the touch electrode layer comprises forming a plurality of first touch electrode and forming a plurality of second touch electrodes; wherein forming the touch electrode layer comprises: forming a first gap having a first gap width in the inter-window area to separate a first corresponding first touch electrode among the plurality of first touch electrodes that are directly adjacent to each other and in the inter-window area from a second corresponding second touch electrode among the plurality of second touch electrodes; and forming a second gap having a second gap width in the display area to separate a third corresponding first touch electrode among the plurality of first touch electrodes that are directly adjacent to each other and in the display area from a fourth corresponding second touch electrode among the plurality of second touch electrodes; wherein the first gap width is greater than the second gap width.

[0026] Optionally, forming the touch electrode layer includes forming an inter-region gap extending from the inter-window region into the display region to separate the fifth corresponding first touch electrode among the multiple first touch electrodes and the sixth corresponding second touch electrode among the multiple second touch electrodes that are directly adjacent to each other; wherein forming the inter-region gap includes forming a first sub-gap in the inter-window region and forming a second sub-gap in the display region, the first sub-gap being directly connected to the second sub-gap; the first sub-gap has a first sub-gap width; the second sub-gap has a second sub-gap width; and the first sub-gap width is greater than the second sub-gap width.

[0027] Optionally, the plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines; and the line width of the plurality of grid electrode lines directly adjacent to the first sub-gap is greater than the line width of the plurality of grid electrode lines directly adjacent to the second sub-gap.

[0028] Optionally, forming the plurality of first touch electrodes includes forming a plurality of first grid electrodes, each of the plurality of first grid electrodes includes a plurality of first grid electrode lines; and forming the plurality of second touch electrodes includes forming a plurality of second grid electrodes, each of the plurality of second grid electrodes includes a plurality of second grid electrode lines; a first boundary of the first gap is formed by virtually connecting outer edges of a plurality of first grid electrode lines of the first corresponding first touch electrodes among the plurality of first touch electrodes, and a second boundary of the first gap is formed by virtually connecting outer edges of a plurality of second grid electrode lines of the second corresponding second touch electrodes among the plurality of second touch electrodes; a third boundary of the second gap is formed by virtually connecting outer edges of a plurality of first grid electrode lines of the third corresponding first touch electrodes among the plurality of first touch electrodes, and a fourth boundary of the second gap is formed by virtually connecting outer edges of a plurality of second grid electrode lines of the fourth corresponding second touch electrodes among the plurality of second touch electrodes; the first gap width is a first shortest distance between the first boundary and the second boundary; and the second gap width is a second shortest distance between the third boundary and the fourth boundary. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0030] Figure 1A is a plan view of a display panel according to some embodiments of the present disclosure.

[0031] Figure 1B is along Figure 1A Cross-sectional view along line A-A'.

[0032] Figure 1C is along Figure 1A Cross-sectional view along line BB'.

[0033] Figure 1D is along Figure 1A Cross-sectional view along line C-C'.

[0034] Figure 1E for Figure 1A A schematic diagram of a first window area, a second window area and an inter-window area in a display panel is shown.

[0035] Figure 1F Detailed structures in a region transitioning from a display region to a window region in a display panel according to some embodiments of the present disclosure are shown.

[0036] Figure 1G A method of forming a window area in a display panel according to some embodiments of the present disclosure is shown.

[0037] Figure 1H Detailed structures in the inter-window area in the display panel according to some embodiments of the present disclosure are shown.

[0038] Fig. 1I Detailed structures in a display area of ​​a display panel according to some embodiments of the present disclosure are shown.

[0039] Figure 1J Detailed structures in a display area of ​​a display panel according to some embodiments of the present disclosure are shown.

[0040] Figure 1K Schematic diagram of a blocking structure defining a window area and an inter-window area in a display panel according to some embodiments of the present disclosure.

[0041] Figure 2A Schematic diagram of an enlarged view of two adjacent touch electrodes in the inter-window region of a display panel according to some embodiments of the present disclosure.

[0042] Figure 2B is an enlarged schematic diagram of two adjacent touch electrodes in the display area of ​​a display panel according to some embodiments of the present disclosure.

[0043] Figure 3A is an enlarged view of a plurality of touch electrodes in an inter-window region of a display panel in some embodiments according to the present disclosure.

[0044] Figure 3B is an enlarged view of a plurality of touch electrodes in a display area of ​​a display panel in some embodiments according to the present disclosure.

[0045] Figure 4 is an enlarged view of an area around an inter-window area of ​​a display panel in some embodiments according to the present disclosure.

[0046] Figure 5 yes Figure 4 An enlarged view of the first enlarged area ZR1 in FIG.

[0047] Figure 6 yes Figure 4 An enlarged view of the second enlarged area ZR2 in FIG.

[0048] Figure 7 yes Figure 4 An enlarged view of the third enlarged area ZR3 in FIG.

[0049] Figure 8 yes Figure 4 An enlarged view of the third enlarged area ZR4 in FIG.

[0050] Fig. 9 yes Figure 4 An enlarged view of the third enlarged area ZR5 in FIG.

[0051] Fig.10 A first gap in an inter-window region in a display panel in some embodiments according to the present disclosure is shown.

[0052] Fig.11 A second gap in a display area in a display panel according to some embodiments of the present disclosure is shown.

[0053] Fig.12 is an enlarged view of an area surrounding a boundary between an inter-window area and a display area of ​​a display panel in some embodiments according to the present disclosure.

[0054] Fig.13A is a partial cross-sectional view of a display panel in an area between windows in some embodiments of the present disclosure.

[0055] Fig. 13B is a partial cross-sectional view of a display panel in a display area in some embodiments of the present disclosure.

[0056] FIG. 14A to FIG. 14B A method of manufacturing a display panel according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0057] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0058] The present disclosure provides, in particular, a display panel, a display device, and a method for manufacturing a display panel that substantially eliminates one or more problems caused by limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a display panel having an array substrate and a counter substrate assembled together. In some embodiments, the display panel has a display area configured to display an image, a first window area, a second window area, and an inter-window area between the first window area and the second window area. The display panel has a first hole located in the first window area and a second hole located in the second window area. The inter-window area is directly adjacent to the first window area and directly adjacent to the second window area. The display panel includes a touch electrode layer in the display area and in the inter-window area, the touch electrode layer including a plurality of first touch electrodes and a plurality of second touch electrodes. Optionally, in the inter-window area, the first corresponding first touch electrode in the plurality of first touch electrodes directly adjacent to each other and the second corresponding second touch electrode in the plurality of second touch electrodes are separated by a first gap having a first gap width. Optionally, in the display area, the third corresponding first touch electrode in the plurality of first touch electrodes directly adjacent to each other and the fourth corresponding second touch electrode in the plurality of second touch electrodes are separated by a second gap having a second gap width. Optionally, the first gap width is greater than the second gap width.

[0059] The inter-window area is a small area between two window areas. When encapsulating the display panel, the encapsulation layer in the inter-window area is usually unevenly topographical, resulting in an uneven surface. When the touch electrode layer is formed in the inter-window area using the related art, adjacent touch electrodes (especially grid electrode lines from adjacent touch electrodes) are prone to short circuits and various other problems due to the uneven surface below. However, the present disclosure adopts a novel and advantageous touch electrode design that eliminates these problems.

[0060] As used herein, the term "display area" refers to the area of ​​the display panel that actually displays the image. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in a liquid crystal display or the area corresponding to the light-emitting layer in an organic light-emitting diode display panel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in a liquid crystal display or the area corresponding to the pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas in two adjacent pixels.

[0061] Figure 1A is a plan view of a display panel according to some embodiments of the present disclosure. Figure 1B is along Figure 1ACross-sectional view along line A-A'. Figure 1C is along Figure 1A Cross-sectional view along line BB'. Figure 1D is along Figure 1A Cross-sectional view of line C-C' in FIG. Figures 1A to 1D In some embodiments, the display panel includes an array substrate AS and a counter substrate CS assembled together. The display panel has a display area DA configured to display an image, a first window area WR1, a second window area WR2, and an inter-window area IWR between the first window area WR1 and the second window area WR2. The inter-window area IWR is directly adjacent to the first window area WR1 and directly adjacent to the second window area WR2. Optionally, as Figure 1A As shown in FIG, the first window region WR1, the second window region WR2 and the inter-window region IWR are surrounded by the display area DA. For example, the first window region WR1, the second window region WR2 and the inter-window region IWR together form an island region, which is surrounded by the display area DA.

[0062] Reference Figure 1B and Figure 1C In some embodiments, the display panel includes a first hole H1 in the first window region WR1 and a second hole H2 in the second window region WR2. In some embodiments, at least one of the first hole H1 and the second hole H2 is a blind hole that does not completely extend through at least one layer of the array substrate AS or the counter substrate CS. Optionally, the first hole H1 is a blind hole that does not extend through the base substrate BS (such as the base substrate BS) of the array substrate AS. Figure 1B Optionally, the second hole H2 is a blind hole that does not extend through the base substrate BS of the array substrate AS (as shown in FIG. Figure 1B ). In some embodiments, at least one of the first hole H1 and the second hole H2 is a through hole that completely extends through the array substrate AS and the counter substrate CS. Optionally, the first hole H1 extends through the array substrate AS and the counter substrate CS. Optionally, the second hole H2 extends through the array substrate AS and the counter substrate CS.

[0063] Reference Figure 1B and Figure 1C In some embodiments, the display panel further includes a first accessory AY1 installed in the first hole H1 and a second accessory AY2 installed in the second hole H2. Examples of accessories include a camera lens and a fingerprint sensor.

[0064] In some embodiments, there are no display elements and thin film transistors in the first window region WR1 and the second window region WR2. Optionally, for example, in an organic light emitting diode display panel, the display element includes a plurality of light emitting diodes. Optionally, for example, in a liquid crystal display panel, the display element includes a liquid crystal layer in a plurality of sub-pixels. Figures 1B to 1D In some embodiments, the array substrate AS includes a base substrate BS, a plurality of thin film transistors TFT on the base substrate BS, and a plurality of light emitting elements LE on the base substrate BS and respectively connected to the plurality of thin film transistors TFT. Optionally, the plurality of thin film transistors TFT do not exist in the first window region WR1. Optionally, the plurality of thin film transistors TFT do not exist in the second window region WR2. Optionally, the plurality of light emitting elements LE do not exist in the first window region WR1. Optionally, the plurality of light emitting elements LE do not exist in the second window region WR2.

[0065] Reference Figures 1B to 1D In some embodiments, the array substrate AS further includes an encapsulation layer EN, which encapsulates a plurality of light emitting elements LE. Optionally, the encapsulation layer EN does not exist in the first window region WR1. Optionally, the encapsulation layer EN does not exist in the second window region WR2. Optionally, the encapsulation layer EN exists in the display region DA and the inter-window region IWR.

[0066] refer to Figures 1B to 1D In some embodiments, the counter substrate CS includes a buffer layer BUF. Optionally, the buffer layer BUF does not exist in the first window region WR1. Optionally, the buffer layer BUF does not exist in the second window region WR2. Optionally, the buffer layer BUF exists in the display region DA and the inter-window region IWR.

[0067] Reference Figures 1B to 1D In some embodiments, the counter substrate CS further includes a touch insulating layer TI. Optionally, the touch insulating layer TI does not exist in the first window region WR1. Optionally, the touch insulating layer TI does not exist in the second window region WR2. Optionally, the touch insulating layer TI exists in the display area DA and the inter-window region IWR.

[0068] Optionally, the inter-window region IWR can display an image. In one example, the display panel includes one or more light emitting elements in the inter-window region IWR. In another example, the display panel includes one or more thin film transistors in the inter-window region IWR.

[0069] Optionally, the inter-window region IWR cannot display an image. In one example, the plurality of light emitting elements LE do not exist in the inter-window region IWR. In another example, the plurality of thin film transistors TFT do not exist in the inter-window region IWR.

[0070] Reference Figures 1A to 1D In some embodiments, the display panel further includes a touch electrode layer in the display area DA and in the inter-window area IWR. The touch electrode layer includes a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2, for example, the display panel is a mutual capacitive touch display panel. Optionally, the plurality of first touch electrodes TE1 are a plurality of touch scanning electrodes, and the plurality of second touch electrodes TE2 are a plurality of touch sensing electrodes. Optionally, the plurality of first touch electrodes TE1 are a plurality of touch sensing electrodes, and the plurality of second touch electrodes TE2 are a plurality of touch scanning electrodes. Optionally, a corresponding one of the plurality of first touch electrodes TE1 includes, for example, a plurality of first touch electrode blocks in a corresponding row. Adjacent first touch electrode blocks in the plurality of first touch electrode blocks are connected by a first electrode bridge BR1. Optionally, a corresponding one of the plurality of second touch electrodes TE2 includes, for example, a plurality of second touch electrode blocks in a corresponding column. Adjacent second touch electrode blocks in the plurality of second touch electrode blocks are connected by a corresponding one of the plurality of second electrode bridges BR2.

[0071] Optionally, the plurality of first touch electrodes TE1 and the plurality of second touch electrodes TE2 are located in the same layer.

[0072] Optionally, the plurality of first touch electrodes TE1 and the plurality of second touch electrodes TE2 are located in different layers.

[0073] Optionally, the plurality of first touch electrodes TE1, the plurality of second touch electrodes TE2 and the first electrode bridge BR1 are located in the same layer. Optionally, the plurality of second electrode bridges BR2 are on a side of the touch insulation layer TI away from the buffer layer BUF. Optionally, the plurality of first touch electrodes TE1, the plurality of second touch electrodes TE2 and the first electrode bridge BR1 are located on a side of the touch insulation layer TI away from the plurality of second electrode bridges BR2.

[0074] Figure 1E for Figure 1A Schematic diagram of the first window area, the second window area and the inter-window area in the display panel shown. Figure 1E In some embodiments, the inter-window region IWR is defined by boundaries on at least four sides including a first side S1, a second side S2, a third side S3, and a fourth side S4. Optionally, the first side S1 and the second side S2 are arranged along a first direction D1 from the first window region WR1 to the second window region WR2. Optionally, the third side S2 and the fourth side S4 are arranged along a second direction D2 substantially perpendicular to the first direction D1.

[0075] Optionally, the first region boundary RB1 of the inter-window region IWR on the first side S1 does not exceed the first outer boundary O1 of the first window region WR1 directly adjacent to the inter-window region IWR. In one example, the first region boundary RB1 of the inter-window region IWR on the first side S1 is between the first outer boundary O1 of the first window region WR1 directly adjacent to the inter-window region IWR and the second outer boundary O2 of the second window region WR2 directly adjacent to the inter-window region IWR. In another example, the first region boundary RB1 of the inter-window region IWR on the first side S1 overlaps at least partially or completely with the first outer boundary O1 of the first window region WR1 directly adjacent to the inter-window region IWR. In another example, the first region boundary RB1 of the inter-window region IWR on the first side S1 does not overlap with the first outer boundary O1 of the first window region WR1 directly adjacent to the inter-window region IWR.

[0076] Optionally, the second region boundary RB2 of the inter-window region IWR on the second side S2 does not exceed the second outer boundary O2 of the second window region WR2 directly adjacent to the inter-window region IWR. In one example, the second region boundary RB2 of the inter-window region IWR on the second side S2 is between the first outer boundary O1 of the first window region WR1 directly adjacent to the inter-window region IWR and the second outer boundary O2 of the second window region WR2 directly adjacent to the inter-window region IWR. In another example, the second region boundary RB2 of the inter-window region IWR on the second side S2 overlaps at least partially or completely with the second outer boundary O2 of the second window region WR2 directly adjacent to the inter-window region IWR. In another example, the second region boundary RB2 of the inter-window region IWR on the second side S2 does not overlap with the second outer boundary O2 of the second window region WR2 directly adjacent to the inter-window region IWR.

[0077] Optionally, the third region boundary RB3 of the inter-window region IWR on the third side S3 does not exceed a first imaginary connection line C1 virtually connecting outer edges of the first window region WR1 and the second window region WR2 on the third side S3 .

[0078] Optionally, the fourth boundary RB4 of the inter-window region IWR on the fourth side S4 does not exceed a second imaginary connection line C2 virtually connecting outer edges of the first window region WR1 and the second window region WR2 on the fourth side S4.

[0079] In one example, the third region boundary RB3 of the inter-window region IWR on the third side S3 is between the first imaginary connection line C1 and the second imaginary connection line C2. In another example, the third region boundary RB3 of the inter-window region IWR on the third side S3 at least partially or completely overlaps with the first imaginary connection line C1. In another example, the third region boundary RB3 of the inter-window region IWR on the third side S3 does not overlap with the first imaginary connection line C1.

[0080] In one example, the fourth boundary RB4 of the inter-window region IWR on the third side S3 is between the first imaginary connection line C1 and the second imaginary connection line C2. In another example, the fourth boundary RB4 of the inter-window region IWR on the third side S3 at least partially or completely overlaps with the second imaginary connection line C2. In another example, the fourth boundary RB4 of the inter-window region IWR on the third side S3 does not overlap with the second imaginary connection line C2.

[0081] Figure 1F Detailed structures in a region transitioning from a display region to a window region in a display panel according to some embodiments of the present disclosure are shown. Figure 1FIn some embodiments, the area transitioning from the display area to the window area WR (e.g., the first window area WR1 or the second window area WR2) includes a base substrate BS (e.g., a flexible base substrate); an insulating layer IN on the base substrate BS; a first gate insulating layer GI1 on a side of the insulating layer IN away from the base substrate BS; a first gate metal layer GM1 on a side of the first gate insulating layer GI1 away from the insulating layer IN; a second gate insulating layer GI2 on a side of the first gate insulating layer GI1 away from the first gate insulating layer GI1; a second gate metal layer GM2 on a side of the second gate insulating layer GI2 away from the first gate insulating layer GI1; and a first gate metal layer GM2 on a side of the second gate insulating layer GM2 away from the first gate insulating layer GI1. An interlayer dielectric layer ILD on one side of the second gate insulating layer GI2; a second SD metal layer SD2 on the side of the interlayer dielectric layer ILD away from the second gate insulating layer GI2; a planarization layer PLN on the side of the second SD metal layer SD2 away from the interlayer dielectric layer ILD, a pixel definition layer PDL defining multiple sub-pixel regions for multiple light emitting elements LE, the pixel definition layer PDL on the side of the planarization layer PLN away from the base substrate BS; a cathode layer CD on the side of the pixel definition layer PDL, the planarization layer PLN, and the second SD metal layer SD2 away from the base substrate BS; an encapsulation layer EN, which encapsulates multiple light emitting elements and is on the side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 on the side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP on the side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. Optionally, the display panel further includes a passivation layer between the interlayer dielectric layer ILD and the planarization layer PLN in a region transitioning from the display region DR to the window region WR.

[0082] In some embodiments, the display panel includes a blocking structure DAM that completely surrounds the hole H (e.g., the first hole H1 or the second hole H2) in the area transitioning from the display area DR to the window area WR. In some embodiments, the blocking structure DAM includes a first blocking layer BL1 and a second blocking layer BL2 that sequentially surround the hole H. Optionally, the first blocking layer BL1 includes a first blocking sublayer BL1-1 and a second blocking sublayer BL1-2. Optionally, the second blocking layer BL2 includes a third blocking sublayer BL2-1 and a fourth blocking sublayer BL2-2. Optionally, the first blocking sublayer BL1-1 and the third blocking sublayer BL2-1 are in the same layer and are formed in a single patterning process. Optionally, the second blocking sublayer BL1-2 and the fourth blocking sublayer BL2-2 are in the same layer and are formed in a single patterning process. Optionally, the first blocking sublayer BL1-1 has a thickness less than that of the third blocking sublayer BL2-1. Optionally, the first blocking sublayer BL1-1, the third blocking sublayer BL2-1, and the planarization layer PLN are formed in the same layer and in a single patterning process. Alternatively, the second blocking sublayer BL1 - 2 , the fourth blocking sublayer BL2 - 2 , and the pixel defining layer PDL are formed in the same layer and in a single patterning process.

[0083] In some embodiments, the display panel further includes a separation layer SL (eg, a separation layer SL) on a side of the pixel defining layer PDL away from the base substrate BS in a region transitioning from the display region DR to the window region WR. Figure 1H As shown in ). Optionally, the first barrier layer BL1 further includes another sublayer in the same layer as the separation layer. Optionally, the second barrier layer BL2 further includes another sublayer in the same layer as the separation layer.

[0084] In some embodiments, the first barrier layer BL1 includes only the second barrier sublayer BL1 - 2 but does not include the first barrier sublayer BL1 - 1 .

[0085] In some embodiments, the display panel also includes a plurality of internal insulating walls IWi located in the area between the blocking structure DAM and the display area DA. A corresponding one of the plurality of internal insulating walls IWi includes a first internal wall sublayer IWi-1 and a second internal wall sublayer IWi-2. Optionally, the first internal wall sublayer IWi-1 is part of the second SD metal layer SD2. Optionally, the second internal wall sublayer IWi-2 is in the same layer as the cathode layer CD, and is optionally formed in a single patterning process with the cathode layer CD. Optionally, the total number of the plurality of internal insulating walls Iwi is in the range of 2 to 6, for example 2, 3, 4, 5 or 6.

[0086] In some embodiments, the display panel also includes a plurality of external insulating walls IWe in the area between the blocking structure DAM and the window region WR. A corresponding one of the plurality of external insulating walls IWe includes a first external wall sublayer IWe-1, a second external wall sublayer IWe-2, a third external wall sublayer IWe-3, and a fourth external wall sublayer IWe-4, and optionally, the first external wall sublayer IWe-1 is part of the first gate metal layer GM1. Optionally, the second external wall sublayer IWe-2 is part of the second gate metal layer GM2. Optionally, the third external wall sublayer IWe-3 is part of the second SD metal layer SD2. Optionally, the fourth external wall sublayer IWe-4 is in the same layer as the cathode layer CD, and is optionally formed in a single patterning process with the cathode layer CD. Optionally, the total number of the plurality of external insulating walls IWe is in the range of 2 to 8, for example, 2, 3, 4, 5, 6, 7 or 8.

[0087] In some embodiments, in the region transitioning from the display region DR to the window region WR, the display panel further includes a plurality of first signal lines SL1 and a plurality of second signal lines SL2. The plurality of first signal lines SL1 and the plurality of second signal lines SL2 are located on a side of the plurality of internal insulating walls IWi away from the blocking structure DAM. Optionally, the plurality of first signal lines SL1 are in the same layer as the second gate metal layer GM2. Optionally, the plurality of second signal lines SL2 are in the same layer as the second SD metal layer SD2. In some embodiments, in the region transitioning from the display region DR to the window region WR, the display panel further includes a plurality of third signal lines in the same layer as the first gate metal layer GM1.

[0088] Figure 1G A method of forming a window area in a display panel according to some embodiments of the present disclosure is shown. Figure 1G FIG. 2 shows the structure of the display panel before the window region WR is formed. Figure 1G The display panel is cut along the cutting line CL to remove part of the structure, thereby forming a Figure 1F Hole H shown.

[0089] Figure 1H Detailed structures in the inter-window area of ​​a display panel according to some embodiments of the present disclosure are shown. Figure 1HIn some embodiments, the display panel includes a base substrate BS (for example, a flexible base substrate) in the inter-window area; an insulating layer IN on the base substrate BS; an active layer ACT of a corresponding one of a plurality of thin film transistors TFT on a side of the insulating layer IN away from the base substrate BS; a first gate insulating layer GI1 on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce1 (both are part of the first gate metal layer) on a side of the first gate insulating layer GI1 away from the insulating layer IN; a second gate insulating layer GI2 on a side of the gate electrode G and the first capacitor electrode Ce1 away from the first gate insulating layer GI1; a second capacitor electrode Ce2 (a part of the second gate metal layer) on a side of the second gate insulating layer GI2 away from the first gate insulating layer GI1; and a first capacitor electrode Ce2 on a side of the second capacitor electrode Ce2 away from the second gate insulating layer GI1. an interlayer dielectric layer ILD on one side of the gate insulating layer GI2; a source electrode S and a drain electrode D (a part of the first SD metal layer) on the side of the interlayer dielectric layer ILD away from the second gate insulating layer; a passivation layer PVX on the side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; a second planarization layer PLN2 on the side of the first planarization layer PLN1 away from the passivation layer PVX; a relay electrode RE (a part of the second SD metal layer) on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a pixel defining layer PDL, which defines a dummy sub-pixel aperture and is on the side of the second planarization layer PLN2 away from the base substrate BS; and a dummy light emitting element DLE in the dummy sub-pixel aperture. The dummy light emitting element DLE includes a light emitting layer EL on a side of the second planarization layer PLN2 away from the first planarization layer PLN1; and a cathode layer CD on a side of the light emitting layer EL away from the second planarization layer PLN2. In the inter-window region, the dummy light emitting element DLE does not include an anode and therefore cannot emit light. The display panel also includes an encapsulation layer EN in the inter-window region, which encapsulates the dummy light emitting element DLE and is on a side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 on a side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP on a side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 on a side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.The display panel further includes a buffer layer BUF on a side of the encapsulation layer EN away from the base substrate BS in the inter-window region; a plurality of second electrode bridges BR2 on a side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 on a side of the touch insulating layer TI away from the buffer layer BUF; and an outer coating layer OC on a side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI. Optionally, the display panel does not include a passivation layer PVX in the inter-window region, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0090] Fig. 1I Detailed structures in the display area of ​​the display panel in some embodiments of the present disclosure are shown. Fig. 1IIn some embodiments, the display panel includes a base substrate BS (for example, a flexible base substrate) in the display area; an insulating layer IN on the base substrate BS; an active layer ACT of a corresponding one of a plurality of thin film transistors TFT on a side of the insulating layer IN away from the base substrate BS; a first gate insulating layer GI1 on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce1 (both are parts of a first gate metal layer) on a side of the first gate insulating layer GI1 away from the insulating layer IN; a second gate insulating layer GI2 on a side of the gate electrode G and the first capacitor electrode Ce1 away from the first gate insulating layer GI1; a second capacitor electrode Ce2 (a part of a second gate metal layer) on a side of the second gate insulating layer GI2 away from the first gate insulating layer GI1; and a first capacitor electrode Ce2 on a side of the second capacitor electrode Ce1 away from the first gate insulating layer GI1. 2, an interlayer dielectric layer ILD on the side away from the second gate insulating layer GI2; a source electrode S and a drain electrode D (a part of the first SD metal layer) on the side of the interlayer dielectric layer ILD away from the second gate insulating layer; a passivation layer PVX on the side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; a second planarization layer PLN2 on the side of the first planarization layer PLN1 away from the passivation layer PVX; a relay electrode RE (a part of the second SD metal layer) on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a pixel defining layer PDL, which defines a sub-pixel aperture and is on the side of the second planarization layer PLN2 away from the base substrate BS; and a light emitting element LE in the sub-pixel aperture. The light emitting element LE includes an anode AD on a side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL on a side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD on a side of the light emitting layer EL away from the anode AD. In the inter-window area, the dummy light emitting element DLE does not include an anode and therefore cannot emit light. The display panel also includes an encapsulation layer EN in the display area, which encapsulates the dummy light emitting element DLE and is on a side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 on a side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP on a side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 on a side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.The display panel further includes a buffer layer BUF on a side of the encapsulation layer EN away from the base substrate BS in the display area; a plurality of second electrode bridges BR2 on a side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 on a side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI. Optionally, the display panel does not include a passivation layer PVX in the display area, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0091] Figure 1J Detailed structures in the display area of ​​the display panel in some embodiments of the present disclosure are shown. Figure 1JIn some embodiments, the display panel includes a base substrate BS (for example, a flexible base substrate) in the display area; an insulating layer IN on the base substrate BS; an active layer ACT of a corresponding one of a plurality of thin film transistors TFT on a side of the insulating layer IN away from the base substrate BS; a first gate insulating layer GI1 on a side of the active layer ACT away from the base substrate BS; a gate electrode G and a first capacitor electrode Ce1 (both are part of a first gate metal layer) on a side of the first gate insulating layer GI1 away from the insulating layer IN; a second gate insulating layer GI1 on a side of the gate electrode G and the first capacitor electrode Ce1 away from the first gate insulating layer GI1; layer GI2; a second capacitor electrode Ce2 (a part of the second gate metal layer) on the side of the second gate insulating layer GI2 away from the first gate insulating layer GI1; an interlayer dielectric layer ILD on the side of the second capacitor electrode Ce2 away from the second gate insulating layer GI2; a source electrode S and a drain electrode D on the side of the interlayer dielectric layer ILD away from the second gate insulating layer; a planarization layer PLN on the side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a pixel defining layer PDL, which defines a sub-pixel aperture and is on the side of the planarization layer PLN away from the base substrate BS; and a light emitting element LE in the sub-pixel aperture. The light emitting element LE includes an anode AD on the side of the planarization layer PLN away from the interlayer dielectric layer ILD; a light emitting layer EL on the side of the anode AD away from the planarization layer PLN; and a cathode layer CD on the side of the light emitting layer EL away from the anode AD. In the inter-window region, the dummy light emitting element DLE does not include an anode and therefore cannot emit light. The display panel further includes an encapsulation layer EN in the display area, which encapsulates the dummy light emitting element DLE and is on the side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 on the side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP on the side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel further includes a buffer layer BUF on the side of the encapsulation layer EN away from the base substrate BS; a plurality of second electrode bridges BR2 on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 on the side of the touch insulating layer TI away from the buffer layer BUF; and an outer coating layer OC on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.

[0092] Figure 1K FIG. 1 is a schematic diagram of a blocking structure defining a window area and an inter-window area in a display panel according to some embodiments of the present disclosure. Figure 1K The display panel includes a first blocking structure DAM1 and a second blocking structure DAM2. The first blocking structure DAM1 completely surrounds the first hole H1, and the second blocking structure DAM2 completely surrounds the second hole H2. The first region boundary RB1 of the inter-window region IWR is adjacent to the boundary of the first blocking structure DAM1, and the second region boundary RB2 of the inter-window region IWR is adjacent to the boundary of the second blocking structure DAM2.

[0093] Figure 2A FIG. 1 is an enlarged schematic diagram of two adjacent touch electrodes in the inter-window region of a display panel according to some embodiments of the present disclosure. Figure 2A In the inter-window region, a first corresponding touch electrode among the plurality of first touch electrodes TE1 and a second corresponding touch electrode among the plurality of second touch electrodes TE2 that are directly adjacent to each other are separated by a first gap G1 having a first gap width d1.

[0094] Figure 2B FIG. 1 is an enlarged schematic diagram of two adjacent touch electrodes in the display area of ​​the display panel according to some embodiments of the present disclosure. In the display area, the third corresponding touch electrode in the plurality of first touch electrodes TE1 and the fourth corresponding touch electrode in the plurality of second touch electrodes TE2 that are directly adjacent to each other are separated by a second gap G2 having a second gap width d2.

[0095] Optionally, the first gap width d1 is greater than the second gap width d2. Optionally, the first gap width d1 is greater than the second gap width d2 by at least 20%, such as at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250% or at least 300%. Optionally, the first gap width d1 is in the range of 5 μm to 50 μm, for example, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. Optionally, the second gap width d2 is in the range of 1 μm to 10 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. In one example, the first gap width d1 is about 10 μm and the second gap width d2 is about 5.2 μm.

[0096] In some embodiments, the display panel further includes a plurality of filling patterns in the same layer as the plurality of first touch electrodes or the plurality of second touch electrodes, and the plurality of filling patterns are insulated from the plurality of first touch electrodes and the plurality of second touch electrodes. Figure 3A is an enlarged view of a plurality of touch electrodes in an inter-window region of a display panel in some embodiments according to the present disclosure. Figure 3B is an enlarged view of a plurality of touch electrodes in a display area of ​​a display panel in some embodiments according to the present disclosure. Figure 3A and Figure 3B In some embodiments, the plurality of fill patterns De are confined in the display area DA, but do not exist in the inter-window area IWR, the first window area WR1, and the second window area WR2.

[0097] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of filling patterns DE and a plurality of first touch electrodes TE1 are formed due to one or more steps of the same patterning process performed in a material deposited in the same deposition process, they are in the same layer. In another example, by simultaneously performing the steps of forming a plurality of filling patterns DE and forming a plurality of first touch electrodes TE1, a plurality of filling patterns DE and a plurality of first touch electrodes TE1 may be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0098] Figure 4 is an enlarged view of an area around the inter-window area of ​​a display panel in some embodiments according to the present disclosure. In some embodiments, the plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines. For example, the plurality of first touch electrodes have a grid pattern, for example, a mesh pattern, and the plurality of second touch electrodes have a grid pattern. The grid electrode lines typically have a line width in the range of 1 μm to 50 μm, for example, 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm.

[0099] Figure 5 yes Figure 4 An enlarged view of the first enlarged area ZR1 in FIG. Figure 6 for Figure 4 An enlarged view of the second enlarged area ZR2 in FIG. Figure 5 and Figure 6In some embodiments, the plurality of first touch electrodes TE1 are a plurality of first grid electrodes, each of which includes a plurality of first grid electrode lines ML1, and the plurality of second touch electrodes TE2 are a plurality of second grid electrodes, each of which includes a plurality of second grid electrode lines ML2. The first amplification area ZR1 is Figure 4 The second magnified area ZR2 is in the inter-window area IWR. Figure 4 In the display area DA in. The first corresponding touch electrode of the plurality of first touch electrodes TE1 and the second corresponding touch electrode of the plurality of second touch electrodes TE2 that are directly adjacent to each other are separated by a first gap G1 having a first gap width d1. The third corresponding touch electrode of the plurality of first touch electrodes TE1 and the fourth corresponding touch electrode of the plurality of second touch electrodes TE2 that are directly adjacent to each other are separated by a second gap G2 having a second gap width d2. The first gap width d1 is greater than the second gap width d2. The first gap G1 has a first boundary B1 formed by virtually connecting the outer edges of the plurality of first grid electrode lines of the first corresponding touch electrodes of the plurality of first touch electrodes TE1, and a second boundary B2 formed by virtually connecting the outer edges of the plurality of second grid electrode lines of the second corresponding touch electrodes of the plurality of second touch electrodes TE2. The second gap G2 has a third boundary B3 formed by virtually connecting the outer edges of the plurality of first grid electrode lines of the third corresponding touch electrode of the plurality of first touch electrodes TE1, and a fourth boundary B4 formed by virtually connecting the outer edges of the plurality of second grid electrode lines of the fourth corresponding touch electrode of the plurality of second touch electrodes TE2. Optionally, the first gap width d1 is the first shortest distance between the first boundary B1 and the second boundary B2. Optionally, the second gap width d2 is the second shortest distance between the third boundary B3 and the fourth boundary B4.

[0100] In some embodiments, Figure 5 and Figure 6As shown, a corresponding one of the plurality of first grid electrode lines ML1 in the inter-window region IWR has a first line width w1, and a corresponding one of the plurality of second grid electrode lines ML2 in the display area DA has a second line width w2. Optionally, the first line width w1 is greater than the second line width w2. Optionally, the first line width w1 is at least 5% greater than the second line width w2, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45% or at least 50%. Optionally, the first line width w1 is in the range of 2μm to 10μm, for example, 2μm to 3μm, 3μm to 4μm, 4μm to 5μm, 5μm to 6μm, 6μm to 7μm, 7μm to 8μm, 8μm to 9μm, or 9μm to 10μm. Optionally, the second line width w2 is in the range of 1 μm to 5 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm. In one example, the first line width w1 is about 4 μm, and the second line width w2 is about 3 μm.

[0101] Figure 7 yes Figure 4 The third zoomed-in area ZR3 spans the inter-window area IWR to Figure 4 Display area DA in the reference Figure 7 The inter-region boundary BL between the inter-window region IWR and the display region DA is defined by an imaginary line, and the line width of the grid electrode line transitions from the first line width w1 to the second line width w2 through the imaginary line. Figure 7 At least a portion of the inter-region boundary BL in is a wavy virtual line along a continuous edge of a corresponding one of the plurality of second grid electrode lines ML2.

[0102] In some embodiments, the display panel further comprises a plurality of blanking grid discontinuities. As used herein, the term "blanking grid discontinuities" refers to discontinuities in grid electrode lines in a separate grid electrode block (i.e., not gaps separating adjacent grid electrode blocks) for achieving excellent blanking effects in the display panel. In addition to locations with a plurality of blanking grid discontinuities, the grid electrode lines are otherwise interconnected at any location in a separate grid electrode block. Figure 8 yes Figure 4 An enlarged view of the third enlarged area ZR4 in FIG. Fig. 9 yes Figure 4 An enlarged view of the third enlarged area ZR5 in FIG. Figure 8 and Fig. 9 In some embodiments, the plurality of blanking grid breaks BMR are confined to the grid electrode blocks in the display area DA, but do not exist in the inter-window region IWR, the first window region WR1, and the second window region WR2.

[0103] Optionally, both the plurality of fill patterns DE and the plurality of blanking grid breaks BMR are confined to the grid electrode block in the display area DA; and the plurality of fill patterns DE and the plurality of blanking grid breaks BMR do not exist in the inter-window area IWR, the first window area WR1 and the second window area WR2.

[0104] Optionally, the plurality of blanking grid discontinuities BMR are randomly distributed in the display area DA. The plurality of blanking grid discontinuities BMR themselves do not form a pattern, so that an excellent blanking effect can be achieved. For example, the plurality of blanking grid discontinuities BMR do not have a repeating pattern and do not have rotational or translational symmetry between the grid electrode blocks.

[0105] Fig.10 FIG. 4 shows a first gap in an inter-window region in a display panel according to some embodiments of the present disclosure. Fig.10 In some embodiments, the first gap (at Figure 5 The plurality of first portions G1-1 (indicated as "G1") includes a plurality of first portions G1-1, each of which is oriented in a first orientation OR1; and a plurality of second portions G1-2, each of which is oriented in a second orientation OR2. Optionally, a corresponding one of the plurality of first portions G1-1 has a first portion gap width d1-1, and a corresponding one of the plurality of second portions G1-2 has a second portion gap width d1-2. The first portion gap width d1-1 and the second portion gap width d1-2 may be the same (e.g., Figure 5 ). Optionally, the first partial gap width d1-1 and the second partial gap width d1-2 are different from each other. Optionally, the first partial gap width d1-1 is greater than the second partial gap width d1-2. Optionally, the first partial gap width d1-1 is in the range of 5 μm to 50 μm, for example, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. Optionally, the second partial gap width d1-2 is in the range of 5μm to 50μm, for example, 5μm to 10μm, 10μm to 15μm, 15μm to 20μm, 20μm to 25μm, 25μm to 30μm, 30μm to 35μm, 35μm to 40μm, 40μm to 45μm, or 45μm to 50μm.

[0106] Fig.11 FIG. 2 shows a second gap in a display area in a display panel according to some embodiments of the present disclosure. Fig.10 In some embodiments, the second gap (at Figure 6The plurality of third portions G2-1 (indicated as "G2") includes a plurality of third portions G2-1, each of which is oriented along the first orientation OR1; and a plurality of fourth portions G2-2, each of which is oriented along the second orientation OR2. Optionally, a corresponding one of the plurality of third portions G2-1 has a third portion gap width d2-1, and a corresponding one of the plurality of fourth portions G1-2 has a fourth portion gap width d2-2. The third portion gap width d2-1 and the fourth portion gap width d2-2 may be the same (e.g. Figure 5 ). Optionally, the third partial gap width d2-1 and the fourth partial gap width d2-2 are different from each other. Optionally, the third partial gap width d2-1 is greater than the fourth partial gap width d2-2. Optionally, the third partial gap width d2-1 is in the range of 1 μm to 10 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. Optionally, the fourth portion gap width d2-2 is in the range of 1 μm to 10 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm.

[0107] In some embodiments, the partial gap width of the first gap in each orientation is greater than the partial gap width of the second gap in the same corresponding orientation. Optionally, the partial gap width of the first gap in the first orientation is greater than the partial gap width of the second gap in the first orientation, and the partial gap width of the first gap in the second orientation is greater than the partial gap width of the second gap in the second orientation. In one example, reference Fig.10 and Fig.11 , the first partial gap width d1-1 is greater than the third partial gap width d2-1, and the second partial gap width d1-2 is greater than the fourth partial gap width d2-2. In another example, the first partial gap width d1-1 is greater than the third partial gap width d2-1 and greater than the fourth partial gap width d2-2; the second partial gap width d1-2 is greater than the third partial gap width d2-1 and greater than the fourth partial gap width d2-2.

[0108] In some embodiments, the term "the first gap width is greater than the second gap width" means that the minimum partial gap width in the first gap (e.g., the second partial gap width d1-2) is greater than the minimum partial gap width in the second gap G2 (e.g., the fourth partial gap width d2-2). Optionally, the minimum partial gap width in the first gap is at least 20% greater than the minimum partial gap width in the second gap, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250%, or at least 300%.

[0109] In some embodiments, the term "the first gap width is greater than the second gap width" means that the minimum partial gap width in the first gap (e.g., the second partial gap width d1-2) is greater than the minimum partial gap width in the second gap G2 (e.g., the fourth partial gap width d2-2); and the maximum partial gap width in the first gap (e.g., the first partial gap width d1-1) is greater than the maximum partial gap width in the second gap G2 (e.g., the third partial gap width d2-1). Optionally, the minimum partial gap width in the first gap is at least 20% greater than the minimum partial gap width in the second gap, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250%, or at least 300%. ; and the maximum partial gap width in the first gap is at least 20% larger than the maximum partial gap width in the second gap, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250%, or at least 300%.

[0110] In some embodiments, the term "first gap width is greater than second gap width" means that the minimum partial gap width in the first gap (e.g., second partial gap width d1-2) is greater than any partial gap width in the second gap G2 (e.g., third partial gap width d2-1 or fourth partial gap width d2-2). Optionally, the minimum partial gap width in the first gap is at least 20% greater than any partial gap width in the second gap, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250%, or at least 300%.

[0111] In some embodiments, the term "first gap width is greater than second gap width" means that the average partial gap width in the first gap (e.g., the average of the first partial gap width d1-1 and the second partial gap width d1-2) is greater than the average gap width in the second gap G2 (e.g., the average of the third partial gap width d2-1 and the fourth partial gap width d2-2). Optionally, the average partial gap width in the first gap is at least 20% greater than the average partial gap width in the second gap, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250%, or at least 300%.

[0112] Fig.12 is an enlarged view of an area surrounding a boundary between an inter-window area and a display area of ​​a display panel in some embodiments according to the present disclosure. Fig.12 , Figure 7 A portion of the inter-region boundary BL in is a straight virtual line.

[0113] Reference Figure 7 and Fig.12In some embodiments, the grid electrode line includes an inter-regional grid electrode line IML extending from the inter-window region IWR to the display area DA. The inter-regional grid electrode line IML includes a first sub-line SL1 in the inter-window region IWR and a second sub-line SL2 in the display area DA, and the first sub-line SL1 is directly connected to the second sub-line SL2. Optionally, the first sub-line SL1 has a first sub-line sw1. Optionally, the second sub-line has a second sub-line line width sw2. Optionally, the first sub-line width sw1 is greater than the second sub-line width sw2. Optionally, the first sub-line width sw1 is the same as the first line width w1, and the second sub-line width sw2 is the same as the second line width w2. Optionally, the first sub-line width sw1 is at least 5% larger than the second sub-line width sw2, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, or at least 50%. Optionally, the first sub-line width sw1 is in the range of 2μm to 10μm, for example, 2μm to 3μm, 3μm to 4μm, 4μm to 5μm, 5μm to 6μm, 6μm to 7μm, 7μm to 8μm, 8μm to 9μm, or 9μm to 10μm. Optionally, the second sub-line width sw2 is in the range of 1μm to 5μm, for example, 1μm to 2μm, 2μm to 3μm, 3μm to 4μm, or 4μm to 5μm. In one example, the first sub-line width sw1 is about 4μm, and the second sub-line width sw2 is about 3μm.

[0114] Reference Figure 7 and Fig.12In some embodiments, the fifth corresponding touch electrode of the plurality of first touch electrodes TE1 and the sixth corresponding touch electrode of the plurality of second touch electrodes TE2, which are directly adjacent to each other, are separated by an inter-region gap IG extending from the inter-window region IWR to the display region DA. Optionally, the inter-region gap IG includes a first sub-gap SG1 in the inter-window region IWR and a second sub-gap SG2 in the display region DA, and the first sub-gap SG1 is directly connected to the second sub-gap SG2. Optionally, the first sub-gap SG1 has a first sub-gap width sd1. Optionally, the second sub-gap SG2 has a second sub-gap width sd2. Optionally, the first sub-gap width sd1 is greater than the second sub-gap width sd2. Optionally, the first sub-gap width sd1 is the same as the first gap width d1, and the second sub-gap width sd2 is the same as the second gap width d2. Optionally, the first sub-gap width sd1 is at least 20% larger than the second sub-gap width sd2, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 100%, at least 110%, at least 120%, at least 130%, at least 140%, at least 150%, at least 160%, at least 170%, at least 180%, at least 190%, at least 200%, at least 225%, at least 250% or at least 300%. Optionally, the first sub-gap width sd1 is in the range of 5 μm to 50 μm, for example, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, or 45 μm to 50 μm. Optionally, the second sub-gap width sd2 is in the range of 1 μm to 10 μm, for example, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, or 9 μm to 10 μm. In an example, the first sub-gap width sd1 is about 10 μm and the second sub-gap width sd2 is about 5.2 μm. Optionally, a plurality of grid electrode lines directly adjacent to the first sub-gap SG1 have a greater line width than a plurality of grid electrode lines directly adjacent to the second sub-gap SG2 .

[0115] Reference Fig.12In some embodiments, the grid electrode line includes an inter-regional grid electrode line IML directly adjacent to the inter-regional gap IG extending from the inter-window region IWR to the display area DA, and the inter-regional grid electrode line IML also extends from the inter-window region IWR to the display area DA. Optionally, the inter-regional gap IG includes a first sub-gap SG1 in the inter-window region IWR and a second sub-gap SG2 in the display area DA, and the first sub-gap SG1 is directly connected to the second sub-gap SG2. Optionally, the first sub-gap has a first sub-gap width sd1. Optionally, the second sub-gap has a second sub-gap width sd2. Optionally, the first sub-gap width sd1 is greater than the second sub-gap width sd2. Optionally, the first sub-gap width sd1 is the same as the first gap width d1, and the second sub-gap width sd2 is the same as the second gap width d2. Optionally, at least a first portion of a boundary of the first sub-gap SG1 in the inter-window region IWR is formed by virtually connecting outer edges of the first sub-lines SL1 of the inter-regional grid electrode lines IML, and at least a second portion of a boundary of the second sub-gap SG2 in the display region DA is formed by virtually connecting outer edges of the second sub-lines SL2 of the inter-regional grid electrode lines IML. Optionally, the first portion and the second portion are directly connected.

[0116] Fig.13A is a partial cross-sectional view of a display panel in an area between windows in some embodiments of the present disclosure. Fig. 13B is a partial cross-sectional view of a display panel in a display area according to some embodiments of the present disclosure. Fig.13A and Fig. 13B In some embodiments, the display panel includes a touch insulating layer TI located below (e.g., directly below) the touch electrode layer and in contact with the touch electrode layer (e.g., a plurality of first touch electrodes TE1). Optionally, the touch insulating layer TI has a first contact surface CS1 in contact with the touch electrode layer in the inter-window region IWR and a second contact surface CS2 in contact with the touch electrode layer in the display area DA. Optionally, the first contact surface CS1 has a first unevenness. Optionally, the second contact surface CS2 has a second unevenness. Optionally, the first unevenness is greater than the second unevenness. The higher degree of unevenness in the inter-window region IWR is due to the higher degree of unevenness in the encapsulation layer EN below the touch electrode layer, the touch insulating layer TI, and the buffer layer BUF. The present disclosure finds that when the encapsulation layer EN is formed, it is more difficult to form a flat surface in the inter-window region IWR than in the display area DA. As a result, the first contact surface CS1 has a higher unevenness than the second contact surface CS2. The touch electrode layer in the inter-window region IWR is prone to disconnection or short circuit. Having the grid electrode blocks separated by wider gaps and having larger line widths in the inter-window region IWR greatly helps prevent these problems.

[0117] On the other hand, the present disclosure provides a method for manufacturing a display panel having an array substrate and a counter substrate assembled together. In some embodiments, the method includes forming a first hole in a first window area; forming a second hole in a second window area. The display panel is formed to have a display area configured to display an image, a first window area, a second window area, and an inter-window area between the first window area and the second window area. The inter-window area is directly adjacent to the first window area and directly adjacent to the second window area. Optionally, the method also includes forming a touch electrode layer in the display area and the inter-window area. Optionally, forming the touch electrode layer includes forming a plurality of first touch electrodes and forming a plurality of second touch electrodes. Optionally, forming the touch electrode layer includes forming a first gap having a first gap width in the inter-window area to separate a first corresponding touch electrode in a plurality of first touch electrodes that are directly adjacent to each other and in the inter-window area from a second corresponding touch electrode in a plurality of second touch electrodes; and forming a second gap having a second gap width in the display area to separate a third corresponding touch electrode in a plurality of first touch electrodes that are directly adjacent to each other and in the display area from a fourth corresponding touch electrode in a plurality of second touch electrodes. Optionally, the first gap width is greater than the second gap width.

[0118] FIG. 14A to FIG. 14B A method for manufacturing a display panel according to some embodiments of the present disclosure is shown. Fig.14A , assembling the array substrate AS and the counter substrate CS together. The step of forming the array substrate AS includes forming a plurality of thin film transistors TFT on the base substrate BS, and forming a plurality of light emitting elements LE on the base substrate BS, and connecting them to the plurality of thin film transistors TFT respectively. Optionally, the step of forming the array substrate also includes forming an encapsulation layer EN encapsulating the plurality of light emitting elements LE. The step of forming the counter substrate CS includes forming a buffer layer BUF, a touch insulating layer TI on the buffer layer BUF, and a touch electrode layer on the side of the touch insulating layer TI away from the buffer layer BUF. In some embodiments, the step of forming the touch electrode layer includes forming a plurality of first touch electrodes TE1.

[0119] refer to Fig. 14B In some embodiments, the method forms a first hole H1 in the first window region WR1; and forms a second hole H2 in the second window region WR2. Therefore, the display panel is formed to have a display area DA configured to display an image, a first window region WR1, a second window region WR2, and an inter-window region IWR between the first window region WR1 and the second window region WR2. The inter-window region IWR is directly adjacent to the first window region WR1 and directly adjacent to the second window region WR2.

[0120] By forming the first hole H1 and the second hole H2, the touch electrode layer, the thin film transistor and the display element are removed from the first window area WR1 and the second window area WR2. Optionally, the encapsulation layer EN, the buffer layer BUF and the touch insulation layer TI do not exist in the first window area WR1 and the second window area WR2.

[0121] Therefore, a touch electrode layer is formed in the display area DA and in the inter-window area IWR. Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figures 4 to 8 In some embodiments, the step of forming the touch electrode layer includes forming a plurality of first touch electrodes TE1 and forming a plurality of second touch electrodes TE2.

[0122] In some embodiments, the step of forming the touch electrode layer includes forming a touch electrode material layer, and patterning the touch electrode material layer to form a plurality of first touch electrodes TE1 and a plurality of second touch electrodes TE2. In some embodiments, the step of patterning the touch electrode material layer includes forming a first gap G1 having a first gap width d1 in the inter-window region IWR to separate a first corresponding electrode in the plurality of first touch electrodes TE1 that are directly adjacent to each other and located in the inter-window region IWR from a second corresponding electrode in the plurality of second touch electrodes TE2; and forming a second gap G2 having a second gap width d2 in the display area DA to separate a third corresponding electrode in the plurality of first touch electrodes TE1 that are directly adjacent to each other and located in the display area DA from a fourth corresponding electrode in the plurality of second touch electrodes TE2. Optionally, the first gap width d1 is greater than the second gap width d2.

[0123] In some embodiments, reference Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figures 4 to 8, the step of forming the touch electrode layer includes forming an inter-region gap IG extending from the inter-window region IWR to the display area DA to separate the fifth corresponding touch electrode of the plurality of first touch electrodes TE1 and the sixth corresponding touch electrode of the plurality of second touch electrodes TE2 that are directly adjacent to each other. Optionally, forming the inter-region gap IG includes forming a first sub-gap SG1 in the inter-window region IWR and forming a second sub-gap SG2 in the display area DA, the first sub-gap SG1 being directly connected to the second sub-gap SG2. Optionally, the first sub-gap has a first sub-gap width sd1. Optionally, the second sub-gap has a second sub-gap width sd2. Optionally, the first sub-gap width sd1 is greater than the second sub-gap width sd2. Optionally, the first sub-gap width sd1 is the same as the first gap width d1, and the second sub-gap width sd2 is the same as the second gap width d2.

[0124] In some embodiments, a plurality of first touch electrodes and a plurality of second touch electrodes are formed as a grid electrode including grid electrode lines. Various suitable conductive electrode materials and various suitable manufacturing methods can be used to manufacture the touch electrode layer. For example, the conductive electrode material can be deposited on a substrate, for example, by sputtering or vapor deposition or solution coating; and patterned. Examples of conductive electrode materials for manufacturing the grid electrode pattern of the touch electrode layer include, but are not limited to, metal grids, silver nanowires, carbon nanotubes, nanogrids, graphene, and conductive polymers, such as poly(3,4-ethylenedioxythiophene monomer) polystyrene sulfonate (PEDOT:PSS). Optionally, the grid electrode pattern is made of a metal grid such as a nanosilver grid.

[0125] Optionally, the plurality of grid electrode lines directly adjacent to the first sub-gap SG1 have a larger line width than the plurality of grid electrode lines directly adjacent to the second sub-gap SG2, such as Figure 7 and Fig.12 shown.

[0126] In some embodiments, reference Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figures 4 to 8, the step of forming a plurality of first touch electrodes includes forming a plurality of first grid electrodes, each of which includes a plurality of first grid electrode lines ML1; the step of forming a plurality of second touch electrodes includes forming a plurality of second grid electrodes, each of which includes a plurality of second grid electrode lines ML2. Optionally, a first boundary B1 of the first gap G1 is formed by virtually connecting the outer edges of the plurality of first grid electrode lines of the first corresponding touch electrode in the plurality of first touch electrodes TE1, and a second boundary B2 of the first gap G1 is formed by virtually connecting the outer edges of the plurality of second grid electrode lines of the second corresponding touch electrode in the plurality of second touch electrodes TE2. Optionally, a third boundary B3 of the second gap G2 is formed by virtually connecting the outer edges of the plurality of first grid electrode lines of the third corresponding touch electrode in the plurality of first touch electrodes TE1, and a fourth boundary B4 of the second gap is formed by virtually connecting the outer edges of the plurality of second grid electrode lines of the fourth corresponding touch electrode in the plurality of second touch electrodes TE2. Optionally, the first gap width d1 is the first shortest distance between the first boundary B1 and the second boundary B2. Optionally, the second gap width d2 is the second shortest distance between the third boundary B3 and the fourth boundary B4.

[0127] In some embodiments, reference Figure 7 and Fig.12 , the plurality of first touch electrodes TE1 and the plurality of second touch electrodes TE2 are grid electrodes including grid electrode lines. The step of forming the grid electrode lines includes forming a plurality of first grid electrode lines ML1 in the inter-window region IWR, and forming a plurality of second grid electrode lines ML2 in the display area DA. Optionally, a corresponding one of the plurality of first grid electrode lines ML1 has a first line width w1. Optionally, a corresponding one of the plurality of second grid electrode lines ML2 has a second line width w2. Optionally, the first line width w1 is greater than the second line width w2. Optionally, an inter-region boundary BL between the inter-window region IWR and the display area DA is defined by an imaginary line, through which the line width of the grid electrode line transitions from the first line width w1 to the second line width w2.

[0128] In some embodiments, reference Figure 7 and Fig.12, the step of forming the grid electrode line includes forming an inter-regional grid electrode line IML extending from the inter-window region IWR to the display area DA. Optionally, the step of forming the inter-regional grid electrode line IML includes forming a first sub-line SL1 in the inter-window region IWR and forming a second sub-line SL2 in the display area DA, the first sub-line SL1 being directly connected to the second sub-line SL2. Optionally, the first sub-line SL1 has a first sub-line width sw1. Optionally, the second sub-line SL2 has a second sub-line width sw2. Optionally, the first sub-line width sw1 is greater than the second sub-line width sw2. Optionally, the first sub-line width sw1 is the same as the first line width w1, and the second sub-line width sw2 is the same as the second line width w2.

[0129] In some embodiments, reference Figure 7 and Fig.12 , the inter-regional grid electrode line IML is directly adjacent to the inter-regional gap IG extending from the inter-window region IWR to the display region DA. Optionally, forming the inter-regional gap IG includes forming a first sub-gap SG1 in the inter-window region IWR and forming a second sub-gap SG2 in the display region DA, the first sub-gap SG1 being directly connected to the second sub-gap SG2. Optionally, the first sub-gap SG1 has a first sub-gap width sd1. Optionally, the second sub-gap SG2 has a second sub-gap width sd2. Optionally, the first sub-gap width sd1 is greater than the second sub-gap width sd2.

[0130] In some embodiments, reference Figure 3A and Figure 3B The method further includes forming a plurality of filling patterns DE in the same layer as the plurality of first touch electrodes TE1 and the plurality of second touch electrodes TE2, the plurality of filling patterns DE being insulated from the plurality of first touch electrodes TE1 and the plurality of second touch electrodes TE2. Optionally, the plurality of filling patterns are confined to the display area and do not exist in the inter-window area IWR, the first window area WR1, and the second window area WR2.

[0131] In another aspect, the present disclosure provides a display device, including a display panel as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0132] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A display panel comprising an array substrate and an opposite substrate assembled together; in, The display panel has a display area configured to display an image, a first window area, a second window area, and an inter-window area between the first window area and the second window area; The display panel includes a first hole in the first window area and a second hole in the second window area; At least one of the first hole and the second hole is a blind hole that does not completely extend through at least one layer of the array substrate or the opposite substrate; or at least one of the first hole and the second hole is a through hole that completely extends through the array substrate or the opposite substrate; The inter-window region is directly adjacent to the first window region and directly adjacent to the second window region; Wherein, the display panel comprises a touch electrode layer in the display area and in the inter-window area, and the touch electrode layer comprises a plurality of first touch electrodes and a plurality of second touch electrodes; wherein, in the inter-window region, a first corresponding first touch electrode among the plurality of first touch electrodes and a second corresponding second touch electrode among the plurality of second touch electrodes that are directly adjacent to each other are separated by a first gap having a first gap width; In the display area, a third corresponding first touch electrode among the plurality of first touch electrodes and a fourth corresponding second touch electrode among the plurality of second touch electrodes that are directly adjacent to each other are separated by a second gap having a second gap width; and The first gap width is greater than the second gap width. 2 . The display panel according to claim 1 , wherein the first window area, the second window area, and the inter-window area are surrounded by the display area.

3. The display panel according to claim 1, wherein: There are no display elements and thin film transistors in the first window area and the second window area; and The display panel further includes a first accessory installed in the first hole and a second accessory installed in the second hole.

4. The display panel according to claim 1 , wherein a fifth corresponding first touch electrode among the plurality of first touch electrodes and a sixth corresponding second touch electrode among the plurality of second touch electrodes, which are directly adjacent to each other, are separated by an inter-region gap extending from the inter-window region into the display region; The inter-region gap includes a first sub-gap in the inter-window region and a second sub-gap in the display region, and the first sub-gap is directly connected to the second sub-gap; The first sub-gap has a first sub-gap width; The second sub-gap has a second sub-gap width; and The first sub-gap width is greater than the second sub-gap width.

5. The display panel according to claim 4, wherein the plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines; The line width of the plurality of grid electrode lines directly adjacent to the first sub-gap is greater than the line width of the plurality of grid electrode lines directly adjacent to the second sub-gap.

6. The display panel according to claim 1, wherein the plurality of first touch electrodes are a plurality of first grid electrodes, each of the plurality of first grid electrodes comprising a plurality of first grid electrode lines; The plurality of second touch electrodes are a plurality of second grid electrodes, each of the plurality of second grid electrodes comprising a plurality of second grid electrode lines; The first gap has a first boundary and a second boundary, the first boundary is formed by virtually connecting outer edges of a plurality of first grid electrode lines of the first corresponding first touch electrodes of the plurality of first touch electrodes, and the second boundary is formed by virtually connecting outer edges of a plurality of second grid electrode lines of the second corresponding second touch electrodes of the plurality of second touch electrodes; The second gap has a third boundary and a fourth boundary, the third boundary is formed by virtually connecting outer edges of a plurality of first grid electrode lines of the third corresponding first touch electrode among the plurality of first touch electrodes, and the fourth boundary is formed by virtually connecting outer edges of a plurality of second grid electrode lines of the fourth corresponding second touch electrode among the plurality of second touch electrodes; The first gap width is a first shortest distance between the first boundary and the second boundary; and The second gap width is a second shortest distance between the third boundary and the fourth boundary.

7. The display panel according to claim 1, wherein the plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines; The grid electrode lines include a plurality of first grid electrode lines in the inter-window area and a plurality of second grid electrode lines in the display area; A corresponding first grid electrode line among the plurality of first grid electrode lines has a first line width; A corresponding second grid electrode line among the plurality of second grid electrode lines has a second line width; The first line width is greater than the second line width; as well as An inter-region boundary between the inter-window region and the display region is defined by an imaginary line, and a line width of the grid electrode line transitions from the first line width to the second line width through the imaginary line.

8. The display panel according to claim 7, wherein the grid electrode lines include inter-region grid electrode lines extending from the inter-window region into the display region; The inter-region grid electrode line comprises a first sub-line in the inter-window region and a second sub-line in the display region, and the first sub-line is directly connected to the second sub-line; The first sub-line has a first sub-line width; The second sub-line has a second sub-line width; and The first sub-line width is greater than the second sub-line width.

9. The display panel of claim 8, wherein the inter-region grid electrode lines directly abut inter-region gaps extending from the inter-window region into the display region; The inter-region gap includes a first sub-gap in the inter-window region and a second sub-gap in the display region, and the first sub-gap is directly connected to the second sub-gap; The first sub-gap has a first sub-gap width; The second sub-gap has a second sub-gap width; and The first sub-gap width is greater than the second sub-gap width.

10. The display panel according to claim 9, wherein at least a first portion of a boundary of the first sub-gap in the inter-window region is formed by virtually connecting outer edges of the first sub-lines of the inter-region grid electrode lines; at least a second portion of a boundary of the second sub-gap in the display region is formed by virtually connecting outer edges of the second sub-lines of the inter-region grid electrode lines; and The first portion and the second portion are directly connected.

11. The display panel according to claim 1 , further comprising a plurality of filling patterns located in the same layer as the plurality of first touch electrodes and the plurality of second touch electrodes, the plurality of filling patterns being insulated from the plurality of first touch electrodes and the plurality of second touch electrodes; in, The plurality of filling patterns are limited in the display area, and do not exist in the inter-window area, the first window area, and the second window area.

12. The display panel according to claim 1, further comprising a plurality of blanking grid discontinuities, a respective one of the plurality of blanking grid discontinuities disconnecting a grid electrode line in an individual grid electrode block; in, The plurality of blanking grid discontinuities are confined in the display area and are not present in the inter-window area, the first window area, and the second window area.

13. The display panel according to claim 1, wherein the first gap comprises a plurality of first portions and a plurality of second portions, each of the plurality of first portions is oriented along a first orientation, and each of the plurality of second portions is oriented along a second orientation; The second gap includes a plurality of third portions and a plurality of fourth portions, each of the plurality of third portions being oriented along the first orientation and each of the plurality of fourth portions being oriented along the second orientation; A respective one of the plurality of first portions has a first portion gap width; A respective one of the plurality of second portions has a second portion gap width; A respective one of the plurality of third portions has a third portion gap width; as well as A corresponding one of the plurality of fourth portions has a fourth portion gap width.

14. The display panel according to claim 13, wherein the first portion gap width is greater than the third portion gap width and / or the fourth portion gap width; the second portion gap width is greater than the third portion gap width and / or the fourth portion gap width.

15. The display panel according to claim 1, wherein the display panel comprises a touch insulating layer below the touch electrode layer and in contact with the touch electrode layer; The touch insulating layer has a first contact surface in contact with the touch electrode layer in the inter-window area and a second contact surface in contact with the touch electrode layer in the display area; The first contact surface has a first unevenness; The second contact surface has a second unevenness; and The first unevenness is greater than the second unevenness.

16. The display panel according to claim 1, wherein the display panel comprises an encapsulation layer below a touch structure, the touch structure comprises a touch electrode layer, and the encapsulation layer contacts the touch structure. The encapsulation layer has a first contact surface in contact with the touch structure in the inter-window area and a second contact surface in contact with the touch structure in the display area; The first contact surface has a first unevenness; The second contact surface has a second unevenness; and The first unevenness is greater than the second unevenness.

17. The display panel according to claim 16, wherein the touch control structure comprises a touch insulation layer between the touch electrode layer and the encapsulation layer; The touch insulation layer is in contact with the touch electrode layer; and The touch insulating layer is coformed with the encapsulation layer.

18. The display panel according to claim 1, wherein: A corresponding one of the plurality of first touch electrodes includes a plurality of first touch electrode blocks arranged along a first direction; A corresponding one of the plurality of second touch electrodes includes a plurality of second touch electrode blocks arranged along a second direction; The plurality of first touch electrode blocks are electrically connected to form a first conductive channel along the first direction, and adjacent first touch electrode blocks among the plurality of first touch electrode blocks are connected via a first electrode bridge; The plurality of second touch electrode blocks are electrically connected to form a second conductive path along the second direction, and adjacent second touch electrode blocks among the plurality of second touch electrode blocks are connected via a second electrode bridge; The plurality of first touch electrode blocks, the plurality of second touch electrode blocks, and one of the first electrode bridge and the second electrode bridge are in a first touch material layer and are made of the same material, and The other of the first electrode bridge and the second electrode bridge is in a second touch material layer different from the first touch material layer.

19. The display panel according to claim 18, wherein: The second touch material layer is between the array substrate and the first touch material layer.

20. The display panel according to claim 1, further comprising a plurality of thin film transistors in the display area and in the inter-window area; in, The display panel comprises: base substrate; an insulating layer on the base substrate; an active layer of a corresponding one of the plurality of thin film transistors on a side of the insulating layer away from the base substrate; a first gate insulating layer on a side of the active layer away from the base substrate; a gate electrode and a first capacitor electrode on a side of the first gate insulating layer away from the insulating layer; a second gate insulating layer on a side of the gate electrode and the first capacitor electrode away from the first gate insulating layer; a second capacitor electrode on a side of the second gate insulating layer away from the first gate insulating layer; an interlayer dielectric layer on a side of the second capacitor electrode away from the second gate insulating layer; a source electrode and a drain electrode on a side of the interlayer dielectric layer away from the second gate insulating layer; a passivation layer on a side of the source electrode and the drain electrode away from the interlayer dielectric layer; a first planarization layer on a side of the passivation layer away from the interlayer dielectric layer; a second planarization layer on a side of the first planarization layer away from the passivation layer; a relay electrode on a side of the second planarization layer away from the first planarization layer; and A pixel defining layer is provided on a side of the second planarization layer away from the base substrate.

21. The display panel according to claim 1, further comprising a plurality of display elements in the display area and a plurality of dummy display elements in the inter-window area; in, The display panel comprises: an anode on a side of the second planarization layer remote from the first planarization layer, the anode being confined to the display region and not present in the inter-window region; a light-emitting layer in the display area and in the area between the windows, the light-emitting layer in the display area being on a side of the anode away from the second planarization layer, and the light-emitting layer in the area between the windows being on a side of the second planarization layer away from the first planarization layer; a cathode layer in the display region and in the inter-window region, the cathode layer being on a side of the light emitting layer away from the second planarization layer; and An encapsulation layer on a side of the cathode layer away from the light emitting layer, the encapsulation layer encapsulating the plurality of display elements in the display region and the dummy display element in the inter-window region.

22. A display device comprising a display panel according to any one of claims 1 to 21, and an integrated circuit connected to the display panel.

23. A method for manufacturing a display panel, the display panel having an array substrate and an opposite substrate assembled together, the method comprising: forming a first hole in the first window region; as well as forming a second hole in the second window region; wherein the display panel is formed to have a display area configured to display an image, the first window area, the second window area, and an inter-window area between the first window area and the second window area; and The inter-window region is directly adjacent to the first window region and directly adjacent to the second window region; The method further includes forming a touch electrode layer in the display area and the inter-window area, wherein forming the touch electrode layer includes forming a plurality of first touch electrodes and forming a plurality of second touch electrodes; Wherein, forming the touch electrode layer comprises: forming a first gap having a first gap width in the inter-window region to separate a first corresponding first touch electrode from a second corresponding second touch electrode from the plurality of second touch electrodes that are directly adjacent to each other and in the inter-window region; and forming a second gap having a second gap width in the display area to separate a third corresponding first touch electrode among the plurality of first touch electrodes and a fourth corresponding second touch electrode among the plurality of second touch electrodes that are directly adjacent to each other and in the display area; The first gap width is greater than the second gap width.

24. The method according to claim 23, wherein: forming the touch electrode layer includes forming an inter-region gap extending from the inter-window region into the display region to separate a fifth corresponding first touch electrode of the plurality of first touch electrodes and a sixth corresponding second touch electrode of the plurality of second touch electrodes that are directly adjacent to each other; wherein forming the inter-region gap comprises forming a first sub-gap in the inter-window region and forming a second sub-gap in the display region, the first sub-gap being directly connected to the second sub-gap; The first sub-gap has a first sub-gap width; The second sub-gap has a second sub-gap width; and The first sub-gap width is greater than the second sub-gap width.

25. The method according to claim 24, wherein: The plurality of first touch electrodes and the plurality of second touch electrodes are grid electrodes including grid electrode lines; The line width of the plurality of grid electrode lines directly adjacent to the first sub-gap is greater than the line width of the plurality of grid electrode lines directly adjacent to the second sub-gap.

26. The method according to any one of claims 23 to 25, wherein forming the plurality of first touch electrodes comprises forming a plurality of first grid electrodes, each of the plurality of first grid electrodes comprising a plurality of first grid electrode lines; as well as forming the plurality of second touch electrodes comprises forming a plurality of second grid electrodes, each of the plurality of second grid electrodes comprising a plurality of second grid electrode lines; A first boundary of the first gap is formed by virtually connecting outer edges of a plurality of first grid electrode lines of the first corresponding first touch electrodes among the plurality of first touch electrodes, and a second boundary of the first gap is formed by virtually connecting outer edges of a plurality of second grid electrode lines of the second corresponding second touch electrodes among the plurality of second touch electrodes; A third boundary of the second gap is formed by virtually connecting outer edges of a plurality of first grid electrode lines of the third corresponding first touch electrode among the plurality of first touch electrodes, and a fourth boundary of the second gap is formed by virtually connecting outer edges of a plurality of second grid electrode lines of the fourth corresponding second touch electrode among the plurality of second touch electrodes; The first gap width is a first shortest distance between the first boundary and the second boundary; and The second gap width is a second shortest distance between the third boundary and the fourth boundary.

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