Integrated circuit having a drain well comprising multiple regions

Abstract

The present disclosure relates to an integrated circuit having a drain well including a plurality of regions. The integrated circuit includes: a drift region in a substrate; a drain in the substrate, the drain including a doped drain well, the doped drain well including: a first region having a first concentration of a first dopant; and a second region having a second concentration of the first dopant, wherein the first concentration is less than the second concentration; and a gate electrode above the drift region and separated from the doped drain well by a distance greater than zero in a direction parallel to a top surface of the substrate.

Description

Technical Field

[0001] The present disclosure generally relates to integrated circuits having a drain well including multiple regions. Background Art

[0002] Laterally diffused metal-on-silicon (LDMOS) is a planar field-effect transistor used for power amplification in integrated circuits. LDMOS device fabrication involves multiple implantations in a P-type silicon substrate or P-type epitaxial layer. Power amplifiers boost low-power signals to higher power levels and drive devices such as antennas. Summary of the Invention

[0003] According to one embodiment of the present disclosure, an integrated circuit is provided, comprising: a drift region in a substrate; a drain in the substrate, wherein the drain comprises a doped drain well, wherein the doped drain well comprises: a first region, wherein the first region has a first concentration of a first dopant; and a second region, wherein the second region has a second concentration of the first dopant, and the first concentration is less than the second concentration; and a gate electrode above the drift region, the gate electrode being separated from the doped drain well by a distance greater than 0 in a direction parallel to the top surface of the substrate.

[0004] According to another embodiment of the present disclosure, a method for manufacturing an integrated circuit is provided, comprising: forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type, the drain well comprising a first region having a first concentration of a first dopant and a second region having a second concentration of the first dopant, the second concentration being different from the first concentration of the first dopant; forming a source well in the substrate, the source well having a second dopant type opposite to the first dopant type, the source well being adjacent to the drift region in the substrate; forming a gate electrode above the top surface of the substrate above the drift region and the source well and laterally separated from the drain well; and forming a drain low density doping (LDD) region in the second region of the drain well.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a source well in a substrate; a drift region in the substrate; a drain well in the substrate, the drain well including a drain low-density doped LDD region and separated from the source well by the drift region, wherein the drain well includes a first region and a second region, the first region having a first concentration of a first dopant, and the second region having a second concentration of the first dopant; and a first width of the first region between the drift region and the second region at the top surface of the substrate is smaller than a second width of the first region between the drift region and the second region at the bottom of the second region; and a gate electrode above the source well and the drift region, the gate electrode being laterally separated from the drain well at the top surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional view of a laterally diffused metal on silicon (LDMOS) according to some embodiments.

[0007] Figure 2 is a flow chart of a method of manufacturing an LDMOS according to some embodiments.

[0008] Figure 3A-3J is a cross-sectional view of an LDMOS during a manufacturing process according to some embodiments.

[0009] Figure 4A-4B is a cross-sectional view of an LDMOS according to some embodiments.

[0010] Figures 5A-5E is a cross-sectional view of an LDMOS during a manufacturing process according to some embodiments.

[0011] Figure 6 is a graph of breakdown voltage of LDMOS devices according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "below," "above," "above," etc., may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Laterally diffused metal oxide semiconductor (LDMOS) devices are transistors with dopants in the substrate that form source and drain wells and a drift region suitable for applications such as power amplifiers. LDMOS devices, like bipolar junction transistors (BJTs), have high breakdown voltages and operate over a wide voltage range with fast switching times and high currents. LDMOS devices are a type of asymmetric power metal oxide semiconductor field effect transistor (MOSFET) with lower on-resistance and higher blocking voltage than other MOSFETs. The current between the source and drain wells of an LDMOS is controlled by the electric field induced (via the gate electrode) in the drift region of the substrate between the source and drain wells of the LDMOS device. The current in an LDMOS device primarily flows laterally parallel to the top surface of the substrate between the source and drain wells of the device. LDMOS devices can be fabricated as either P-type or N-type MOSFETs.

[0015] In semiconductor devices designed to carry high currents, such as LDMOS devices, the base or drain can sometimes experience a phenomenon known as the Kirk effect. The Kirk effect occurs when the base / drain experiences "base pushout," which causes the base width to expand as high current (e.g., a high concentration of carriers) flows between the drain and source (e.g., of an LDMOS device). In LDMOS devices, base pushout occurs when the density of minority carriers injected into the drain depletion region becomes comparable to the doping level in the drain. The large number of carriers compensates for the ions in the depletion region, reducing the electric field between the source and drain. When the carrier charge density matches or exceeds the charge density of the depletion region of the drain well, the depletion region disappears and the carrier transit time over the channel length increases, reducing the overall switching speed of the LDMOS device.

[0016] Reducing the channel length (which occurs in subsequent generations of semiconductor devices) to reduce the switching time of the device tends to make the device more susceptible to base pushout and reduces the breakdown voltage of the device during operation. To increase the breakdown voltage of LDMOS, the gate polysilicon of LDMOS extends above the drift region of LDMOS. The overlapping gate electrode acts as a field plate to maintain the breakdown voltage of LDMOS.

[0017] In an LDMOS device having a drain well including a single dopant concentration region, reducing the device size results in faster switching times and lower breakdown voltages. By increasing the number of dopant concentration regions in the drain well of the LDMOS, a smaller channel length is maintained at a breakdown voltage comparable to that of an LDMOS device having a single dopant concentration region in the drain well. Furthermore, increasing the number of dopant concentration regions in the drain well improves the LDMOS device's resistance to the Kirk effect. In some embodiments, a drain well having multiple dopant concentration regions can withstand higher currents without carrier saturation, which increases the carrier transit time across the channel. Furthermore, the base pushout does not achieve a carrier density that would saturate the second, higher dopant concentration region in the drain well upon reaching the first, lower dopant concentration region in the drain well. Furthermore, by increasing the spacing between the dopant concentration regions in the drain well at the top surface of the substrate, the breakdown voltage is also improved. An example of an LDMOS device having multiple dopant concentration regions (regions) in a drain well, as well as a method for manufacturing an LDMOS device having a drain well including multiple regions, is described below.

[0018] Figure 1 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 1 , substrate 102 includes a drift region 104, a source well 110, and a drain well 107. In some embodiments, substrate 102 is a P-type substrate comprising silicon and a P-type dopant such as boron. Source well 110 is a P-doped well, drain well 107 is an N-doped well, and drift region 104 includes a net concentration of N-type dopant. In some embodiments, source well is an N-doped well, drain well is a P-doped well, and drift region includes a net concentration of P-type dopant. One of ordinary skill in the art will understand that other configurations are within the scope of the present disclosure, including the use of different dopant types.

[0019] The drain well 107 includes a first doped region 118A (N1), a second doped region 118B (N2), a third doped region 118C (N3), and a fourth doped region 118D (N4). The first doped region 118A separates the second doped region 118B from the drift region 104. The second doped region 118B separates the third doped region 118C from the first doped region 118A. The third doped region 118C separates the fourth doped region 118D from the second doped region 118B. The fourth doped region 118D separates the drain LDD region 126A from the third doped region 118C.

[0020] The first doping region 118A has the lowest dopant atomic concentration among the doping regions of the drain well 107. The dopant concentration of the drift region 104 (the same type of dopant in the drain well 107) is lower than the dopant concentration in the first doping region 118A. The fourth doping region 118D has the highest dopant atomic concentration among the regions of the drain well 107. The dopant concentrations of the second doping region 118B and the third doping region 118C are between the concentrations in the first doping region 118A and the fourth doping region 118D. The dopant concentration of the second doping region 118B is higher than the dopant concentration in the first doping region 118A and lower than the dopant concentration in the third doping region 118C.

[0021] The drift region 104 extends a drift region depth D0 below the top surface of the substrate 102. Depth D0, as well as other depths described below, are measured parallel to a first direction 198 extending perpendicular to the top surface of the substrate 102. A second direction 199 extends perpendicular to the first direction 198. Second direction 199 extends parallel to the top surface of the substrate 102, along the shortest distance from the drain well 107 to the source well 110 beneath the gate dielectric 111. A first doped region 118A has a first region depth D1 below the top surface of the substrate 102, a second doped region 118B has a second region depth D2 below the top surface of the substrate 102, a third doped region 118C has a third region depth D3 below the top surface of the substrate 102, and a fourth doped region 118D has a fourth region depth D4 below the top surface of the substrate 102. In the integrated circuit 100, D0>D1>D2>D3>D4. In some embodiments, D0>D1=D2>D3>D4. In some embodiments, D0>D1>D2=D3>D4. In some embodiments, D0>D1>D2>D3=D4. In some embodiments, D0>D1=D2>D3=D4. In some embodiments, D0>D1=D2=D3>D4. In some embodiments, D0>D1=D2=D3>D4. In some embodiments, D0>D1>D2=D3=D4. In some embodiments, D0>D1=D2=D3=D4. In some embodiments, D0>D1=D2=D3=D4. In some embodiments, one or more of the doped regions has a region depth equal to the drift region depth D0 (e.g., D0=D1=D2=D3=D4).

[0022] In some embodiments, the first region depth 118A (D1) is within a range of 20% to 100% of the doping region depth D0 (e.g., (0.2)×D0≤D1≤D0). In some embodiments, the second region depth 118B (D2) is within a range of 20% to 100% of the doping region depth D0 (e.g., (0.2)×D0≤D2≤D0). In some embodiments, the third region depth 118C (D3) is within a range of 20% to 100% of the doping region depth D0 (e.g., (0.2)×D0≤D3≤D0). In some embodiments, the fourth region depth 118D (D4) is within a range of 20% to 100% of the doping region depth D0 (e.g., (0.2)×D0≤D4≤D0). In some embodiments, the depth of the doped region in the drain well is not less than the depth of the LDD region in the drain well (eg, see drain LDD region 126A). In some embodiments, the depth ratios between D0, D1, D2, D3, and D4 are different from the above examples.

[0023] The doped regions 118A-118D have doped region widths measured along the second direction 199 from the edge of the drain farthest from the gate electrode 112 (W0) to the edge of the doped region closest to the gate electrode 112. The first doped region 118A has a first region width W1. The second doped region 118B has a second region width W2 that is less than the first region width W1. The third doped region 118C has a third region width W3 that is less than the second region width W2. The fourth doped region 118D has a fourth region width W4 that is less than the third region width W3 (e.g., W1>W2>W3>W4). In some embodiments, the widths W1-W4 differ from the above examples.

[0024] In some embodiments, at the top surface of the substrate, the first region width W1 is the same as the second region width W2 (see, e.g., Figure 5B-5C In some embodiments, at the top surface of the substrate, the first region width W1 is greater than the second region width W2 (see, for example, Figure 5D-5E In some embodiments, at the top surface of the substrate, the third region width W3 is the same as the fourth region width W4 (see, for example, Figure 5C In some embodiments, the third region width W3 is greater than the fourth region width W4 (see below). Figure 5D-5E ).

[0025] For something like Figure 5DEmbodiments of the drain well 507 in FIG: In some embodiments, the first region width W1 is wider than the width of the top of the second doped region W2B or the width of the bottom of the second region W2A. In some embodiments, the width of the top of the second doped region W2B and the width of the bottom of the second region W2A are both wider than the third region width W3. In some embodiments, the third region width W3 is greater than the width of the top of the fourth doped region W4B and the width of the bottom of the fourth region W4A.

[0026] For something like Figure 5E Embodiments of the drain well 507 in FIG: In some embodiments, the first region top width W1B and the first region bottom width W1A are both greater than the second region top width W2B and the second region bottom width W2A. In some embodiments, the second region top width W2B and the second region bottom width W2A are both greater than the third region top width W3B and the third region bottom width W3A. In some embodiments, the third region top width W3B and the third region bottom width W3A are both greater than the fourth region top width W4B and the fourth region bottom width W4A.

[0027] A drain LDD region 126A is located at the top surface of the drain well 107 and within the fourth doped region 118D. The drain LDD region 126A has the same type of dopant as the doped regions 118A-118D of the drain well 107, and has a dopant concentration greater than the dopant concentration in the drift region 104 or any of the doped regions 118A-118D. The drain LDD region 126A has a drain LDD silicide 128A at its top surface and directly abuts the contact 132A.

[0028] The drift region 104 abuts the source well 110 and separates the source well 110 from the drain well 107. Doped regions 118A-118D in the drain well 107 are separated from the source well 110 by the drift region 104. In embodiments of LDMOS devices having a smaller or larger number of doped regions in the drain well, the drift region separates the doped regions from the source well.

[0029] The source well 110 abuts the top surface of the substrate 102 and abuts the drift region 104. The source well 110 includes a source LDD region 126B, which includes an N-doped source LDD region 126C and a P-doped source LDD region 126D. The N-doped source LDD region 126C directly abuts the P-doped source LDD region 126D at the top surface of the source well 110 in the substrate 102, and the N-doped source LDD region 126C is closer to the gate electrode 112 than the P-doped source LDD region 126D. The source LDD region 126B is covered by a source LDD silicide 128B, which extends across the N-doped source LDD region 126C and the P-doped source LDD region 126D. The source LDD silicide 128B directly abuts the contact 132B.

[0030] The gate dielectric 111 abuts the top surface of the drift region 104 and the top surface of the source well 110 and is separated from the source LDD region 126B (or from the N-doped source LDD region 126C) by a spacer 114. The spacer 114 is on both the source well side and the drain well side of the gate electrode 112 and the gate dielectric 111. The interface between the gate electrode 112 and the spacer 114 on the drain well side of the gate electrode 112 is a gate separation distance 133 from the inner edge of the first doped region 118A (e.g., the edge closer to the gate electrode, or the interface between the drift region 104 and the source well 110). The gate separation distance 133 is approximately linearly related to the breakdown voltage of the device. The gate electrode silicide 128C covers a portion of the top surface of the gate electrode 112. A portion of the top surface of the gate electrode 112 on the drain well side of the gate electrode exposes the gate electrode material but does not expose the gate electrode silicide.

[0031] An interlayer dielectric (ILD) 130 extends over the top surfaces of the drain LDD silicide 128A, the drain well 107, the drift region 104, the spacer 114, the gate electrode 112, the gate electrode silicide 128C, and the source LDD silicide 128B. The ILD layer 130 is a layer of dielectric material deposited, for example, by chemical vapor deposition (CVD), to electrically isolate the source well 110 (or the source LDD region 126B and the source LDD silicide 128B and the contact 132B) from the gate electrode 112 and the gate electrode silicide 128C, the gate electrode contact (not shown), the drain well 107, the drain LDD region 126A, the drain LDD silicide 128A, and the spacer 132A. Contact 132A extends completely through ILD 130 to electrically connect to drain LDD silicide 128A, and contact 132B extends completely through ILD 130 to electrically connect to source LDD silicide 128B.

[0032] Figure 2 is a flow chart of a method 200 of fabricating an LDMOS according to some embodiments.

[0033] Method 200 includes operation 202, in which a drift region is formed in a substrate. When forming the drift region in the substrate, operation 202 includes a step for covering the substrate with a patterned material layer, for example, a substrate comprising a P-doped semiconductor material. Operation 202 includes a step for performing a doping process to produce a drift region in the substrate. In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate. Operation 202 involves the formation of a drift region 304, as described below. Figure 3A As described in.

[0034] In some embodiments, covering the substrate with the patterned material layer includes depositing a photoresist layer on the top surface of the substrate. In some embodiments, covering the substrate with the patterned material layer includes depositing a hard mask material layer above the top surface of the substrate and then depositing the patterned material layer. Operation 202 includes steps associated with transferring a pattern to the patterned material layer, and developing the patterned material to form an opening therein that exposes the top surface of the substrate. In some embodiments, transferring the pattern to the patterned material layer includes performing a photolithography process and a development process to create an opening in the mask material layer corresponding to the location of the drift region in the substrate. In some embodiments, transferring the pattern to the patterned material layer includes performing an electron beam or ultraviolet pattern transfer process, and developing the patterned material to form an opening therethrough. In embodiments of operation 202 that includes a step for depositing a hard mask material layer above the top surface of the substrate, the operation also includes steps associated with performing an etching process to remove portions of the hard mask material layer exposed by the opening in the patterned material layer (e.g., an isotropic plasma etching process) to expose the substrate beneath the hard mask material layer.

[0035] In some embodiments, the doping process includes depositing an epitaxial material layer over the substrate in the opening of the mask material layer, and annealing the substrate to promote migration of dopants from the epitaxial material layer into the substrate to form the drift region.

[0036] In some embodiments, the doping process includes performing an implantation process with dopant atoms to create a drift region. In some embodiments, the dopant atoms are N-type atoms, such as phosphorus (P) or arsenic (As). In some embodiments, the dopant atoms are P-type atoms, such as boron (B) or gallium (Ga). Implanting the dopant atoms into the substrate involves steps associated with: adjusting the implantation angle (θ 漂移 ) and the implantation energy (keV) to adjust the shape and depth of the drift region, and the implantation duration (seconds) to adjust the dopant concentration in the drift region. In some embodiments, the implantation process includes a step for forming a drift region having a depth of not less than 50 nanometers (nm) and not more than 200 nm. In some embodiments, the drift region includes not less than 1×10 10 / cm 2 and not more than 1×10 11 / cm 2In some embodiments where the drift region has a thickness of less than 50 nm, the implantation process for forming the drift well becomes complicated in order to form multiple doped regions in the drift region. In embodiments where the drift region has a thickness greater than 200 nm, no additional benefit is gained in terms of reduced leakage current or process flexibility compared to drift regions with a thickness between 100 nm and 200 nm. In embodiments where the dopant concentration is less than 1 × 10 10 / cm 2 In an embodiment of the invention, the low dopant concentration makes it more difficult to switch the transistor to the ON state, and the drift region contributes to the overall resistance of the integrated circuit. 11 / cm 2 In embodiments where the dopant concentration is less than 1 , no additional benefit is obtained in promoting fast switching of the transistor. In LDMOS devices, the dopant concentration of the drift region is less than the dopant concentration in any doped region of the drain well.

[0037] In operation 202 , after the doping process, the patterned material layer (and any hard mask material deposited on the substrate) is removed and the substrate is prepared for further operations of the method.

[0038] Figure 3A is a cross-sectional view of integrated circuit 300 during a fabrication process according to some embodiments. Elements of integrated circuit 300 that have similar structure and / or function to elements of integrated circuit 100 described above have the same reference numerals, increased by 200.

[0039] exist Figure 3A In the embodiment of the present invention, substrate 302 is a semiconductor substrate having a drift region 304 therein. Substrate 302 is a P-doped silicon substrate. In some embodiments, the substrate is silicon, silicon germanium, GaAs, or some other semiconductor material suitable for manufacturing LDMOS devices. Drift region 304 is doped with N-type dopants to have an excess of N-type dopants relative to the concentration of P-type dopants in substrate 302. Drift region 304 has a drift region depth D0 measured from the top surface of substrate 302 to the bottom of drift region 304. Figure 3A , W0 represents the edge of the drift region 304 .

[0040] A layer of patterned material 306A is deposited over substrate 302 with openings 324A therein exposing the top surface of substrate 302. A hard mask 309A is located between patterned material 306A and the top surface of substrate 302. Openings 324A extend through both patterned material 306A and hard mask 309A.

[0041] Dopant atoms are implanted along an implant vector 308A having an implant angle 390A relative to a reference line 389 that is perpendicular to the top surface of the substrate 302 (and the top surface of the drift region 304). The implant vector 308A is at 0° relative to the reference line 389. In some embodiments, the implant vector for the dopant atoms has an implant angle that is no greater than 10° and no less than -10° relative to the reference line 389. In the implant process that forms the drift region, an implant angle that is close to vertical (e.g., about 0°) provides the most precise dimensional control over the edge of the drift region and the distance between the source or drain well in the substrate near the drift region. An implant angle that deviates from vertical (e.g., an implant angle > |±10°|) causes the drift region to widen, which causes the switching times of transistors in the integrated circuit to shift.

[0042] The implantation of dopant atoms is performed along the implantation vector in a second direction 399 (see below, see also above) Figure 1 In a plane extending in a second direction 199 in the direction of the drift region, the injection vector is at an injection angle relative to a reference line that is perpendicular to the upper surface of the substrate. An injection vector with no offset relative to the reference line (i.e., injection angle = 0°) indicates that the atoms approach the surface perpendicularly to the surface. An injection vector with a negative injection angle relative to the reference line indicates that the atoms approach the surface with a motion component from the drift region (or the space above the drift region) toward the position of the gate electrode. An injection vector with a positive injection angle relative to the reference line indicates that the atoms approach the surface with a motion component from the drift region (or the space above the drift region) away from the gate electrode. In some embodiments, dopant atoms for the drift region are implanted with an injection vector with a zero degree (0°) injection angle or a positive injection angle.

[0043] The patterned material 306A is a photoresist layer. In some embodiments, the patterned material is a dielectric material layer (e.g., silicon dioxide, silicon nitride, etc.) that has been etched to form an opening above the substrate at the location of the drift region. In some embodiments, a dielectric material layer is used as the patterning material because the implantation process has a high implantation energy to drive the dopant atoms deep into the substrate and the photoresist is insufficient to shield the source well (see Figure 1 The substrate in the region of the source well 110 in the source well is protected from drift region dopant atoms.

[0044] Method 200 includes operation 204, in which a source well is formed in the substrate. Operation 204 includes steps for covering the substrate with a patterned material layer, for transferring a pattern to the patterned material layer, for modifying the patterned material to form an opening therein, and for performing a doping process to create a source well in the substrate. Operation 204 is associated with the formation of source region 310, as follows Figure 3B As stated.

[0045] In some embodiments, covering the substrate with the patterned material layer includes depositing a photoresist layer on the top surface of the substrate. In some embodiments, covering the substrate with the patterned material layer includes depositing a hard mask material layer above the top surface of the substrate and then depositing the patterned material layer. In some embodiments, transferring the pattern to the patterned material layer includes performing a photolithography process and a development process to create openings in the mask material layer corresponding to the location of the drift region in the substrate. In some embodiments, transferring the pattern to the patterned material layer includes performing an electron beam or ultraviolet pattern transfer process, and developing the patterned material to form an opening therethrough. In an embodiment of operation 204 that includes a step for depositing a hard mask material layer above the top surface of the substrate, the operation also includes a step associated with performing an etching process to remove portions of the hard mask material layer exposed by the openings in the patterned material layer (e.g., an isotropic plasma etching process) to expose the substrate beneath the hard mask material layer.

[0046] In some embodiments, the doping process includes depositing an epitaxial material layer over the substrate in the opening of the mask material layer, and annealing the substrate to promote migration of dopants from the epitaxial material layer into the substrate to form the source well.

[0047] In some embodiments, the doping process includes performing an implantation process with dopant atoms to create a source well. In some embodiments, the dopant atoms are N-type atoms, such as phosphorus (P) or arsenic (As). In some embodiments, the dopant atoms are P-type atoms, such as boron (B) or gallium (Ga). In the step for the doping process, the source well is doped by adding a dopant of the opposite type to the dopant in the drift region.

[0048] Implanting dopant atoms into the substrate of the source well involves adjusting the injection angle (θ 源极 ) and implant energy (keV) to adjust the shape and depth of the source well, and the implant duration (seconds) to adjust the dopant concentration in the source well. In some embodiments, dopant atoms for the source well (see source well 310) are added to the substrate with an orthogonal implant vector (e.g., approaching the substrate without lateral movement), so that the dopant atoms move directly downward into the substrate, forming a vertical interface between the source well and the drain well. By avoiding overlap between the source well and the drift region, the resistance to switching the LDMOS device to the "on" state is reduced.

[0049] Figure 3B is a cross-sectional view of integrated circuit 300 during a manufacturing process according to some embodiments. Figure 3B With Figure 3A Elements with identical structures and / or functions are provided with the same reference numerals.

[0050] exist Figure 3B , a hard mask 309B is deposited over the top surface of the substrate 302, and a layer of patterned material 306B is deposited over the hard mask 309B. An opening 342B extends through the layer of patterned material 306B and through the hard mask 309B, exposing the top surface of the substrate 302. Dopant atoms are deposited with an injection vector 308B that is substantially parallel to a reference line 389 (e.g., an injection angle 390B of 0°). This causes the source well 310 to extend downward into the substrate to a source well depth DS. The source well depth DS is less than the drift region depth D0. In some embodiments, DS>D0. The source well 310 abuts the drift region 304 with a boundary extending in a first direction 398.

[0051] Patterned material 306B is a photoresist layer. In some embodiments, patterned material 306B is a patterned material compatible with electron beam lithography, ultraviolet (UV) lithography, or some other pattern transfer technique known to practitioners in the semiconductor fabrication art.

[0052] Method 200 includes operation 206, wherein a gate electrode is formed over the top surface of the substrate. Operation 206 includes a step for depositing a gate dielectric material over the top surface of the substrate. Operation 206 also includes a step for depositing a gate electrode material over the gate dielectric material. Operation 206 includes a step for performing a patterning process and an etching process to form at least one gate electrode over the top surface of the substrate. Operation 206 is related to forming the following Figure 3C , wherein the gate electrode includes a gate dielectric 311 , a gate electrode material 312 and a spacer 314 .

[0053] The step of depositing a gate dielectric material over the top surface of the substrate includes, for example, steps associated with chemical vapor deposition (CVD) or atomic layer deposition (ALD) of a dielectric material over the top surface of the substrate. In some embodiments, the deposited dielectric material is silicon dioxide. In some embodiments, the deposited dielectric material is an aluminum oxide material. In some embodiments, the deposited dielectric material is a high-κ (κ = dielectric constant) material, with κ being at least 3.2.

[0054] The step of depositing a gate electrode material over the gate dielectric material includes steps associated with depositing a semiconductor material over the top surface of the substrate. In some embodiments, the gate electrode material is a type IV semiconductor material. In some embodiments, the gate electrode comprises polysilicon or some other semiconductor material suitable for LDMOS devices in integrated circuits. In some embodiments, the gate electrode material is a dummy gate electrode material used to adjust the position of spacers used to form doped regions in the drain well of the LDMOS device (see below).

[0055] Performing a patterning process includes steps for: depositing a patterned material layer over a gate electrode material; transferring a pattern to the patterned material layer; and modifying the patterned material layer by forming an opening according to the transferred pattern, wherein a remaining portion of the patterned material corresponds to a portion of the surface of the substrate that is to remain as a gate electrode of, for example, an LDMOS device, a semiconductor device.

[0056] The step of performing an etching process includes performing an etching process to remove the exposed portion of the gate electrode (and subsequently the exposed portion of the gate dielectric material) to expose the substrate, including at least some of the source wells and drift regions of each LDMOS device of the semiconductor device. Operation 206 also includes steps for preparing the surface for the other operations of method 200.

[0057] Operation 206 further includes a step for forming spacers on the sides of the gate electrode material and the gate dielectric material to electrically isolate the gate electrode material from other electronic components in the LDMOS device. In some embodiments, the step for forming the spacers includes performing a conformal deposition of a dielectric material (spacer material) over the gate electrode material and the substrate, and performing an anisotropic etching process to expose the top surface of the gate electrode material and the substrate, leaving a portion of the spacer material on the sides of the gate electrode material and the gate dielectric material. In the following Figure 3C A cross-sectional view of the gate electrode and gate dielectric material consistent with the performance of operation 206 is provided in FIG.

[0058] Figure 3C is a cross-sectional view of an integrated circuit 300 during a manufacturing process according to some embodiments. Figure 3C In the embodiment of the present invention, the gate dielectric 311 is directly against the substrate 302 above the source well 310 and the drift region 304, as well as the interface between the source well 310 and the drift region 304. In some embodiments, the gate dielectric 311 is a silicon dioxide layer. In some embodiments, the gate dielectric 311 is a high-κ dielectric material or some other dielectric material suitable for electrically isolating the gate electrode material 312 from the source well 310 and the drift region 304d.

[0059] Method 200 includes operation 208, wherein a doped region of a drain well is formed. As described below, Figure 3C-3F A cross-sectional view of a semiconductor device during a manufacturing process including the step of forming a doped region is provided.

[0060] Operation 208 includes steps for depositing a mask material layer over the substrate and the gate electrode, depositing a pattern material layer over the mask layer, and steps associated with forming openings in the pattern material layer and the mask material layer. Operation 208 also includes steps for performing a doping process to form a drain well or a doped region of the drain well. Figure 3C A non-limiting exemplary embodiment of mask material 316C over the top surface of substrate 302 consistent with the performance of operation 208 is provided.

[0061] Two or more doping processes are performed to form a drain well for an integrated circuit, based on the design specifications of the LDMOS device. In some embodiments, the two or more doping processes have different implantation vectors or implantation angles. In some embodiments, the two or more doping processes have different implantation depths (e.g., the doped regions have different region depths). The pattern of implantation angles and implantation depths is adjusted, and spacers are added to a mask layer to shift the openings through which dopant atoms are added, resulting in multiple doped regions that serve as drains for the semiconductor device.

[0062] The step of depositing a mask material layer on the substrate includes depositing a dielectric material on the top surface of the substrate. In some embodiments, the dielectric material is silicon dioxide. In some embodiments, the dielectric material is silicon nitride, silicon oxynitride, spin-on glass, borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or one of hard mask materials suitable for front-end integration solutions of semiconductor devices. The mask material is dense enough to resist the impact from dopant atoms, which are guided to the substrate to form the doped region of the drain well. The mask material is used to manufacture LDMOS devices in one or more doping processes. Therefore, the mask material with a higher density can better protect the drift region of the LDMOS device without corrosion or cracking.

[0063] Steps associated with depositing a patterned material layer over the mask layer include steps associated with depositing a photoresist or patterning material that is compatible with e-beam, ultraviolet (UV) patterning, and other patterning techniques familiar in semiconductor manufacturing.

[0064] Steps associated with forming openings in the patterned material layer and the mask material layer include performing a photolithography process and a development process, performing an electron beam lithography process and a development process, or performing an ultraviolet (UV) lithography process or other pattern transfer process compatible with LDMOS device fabrication.

[0065] The steps associated with the doping process for forming the drain well include a process of depositing an epitaxial dopant atomic layer containing a material over a substrate in an opening formed in a mask layer / patterned material and performing an annealing process to drive the dopant into the substrate (as described above), or a process of implanting dopant atoms from a dopant atom source.

[0066] In some embodiments, the doping process includes performing an implantation process with dopant atoms to create a drift region. In some embodiments, the dopant atoms are N-type atoms, such as phosphorus (P) or arsenic (As). In some embodiments, the dopant atoms are P-type atoms, such as boron (B) or gallium (Ga). Implanting the dopant atoms into the substrate involves steps associated with: adjusting the implantation angle (θ 漏极区 ) and the implant energy (keV) to adjust the shape and depth of the drift region, and the implant duration (seconds) to adjust the dopant concentration in the drift region. In some embodiments, the implant angle is in the range of 0° to +60°. In some embodiments, the implant angle is in the range of 0° to -60°. During the manufacturing process, implant angles more extreme than ±60° are more likely to overlap with another doped region in the drain well. The implant angle is related to the angle of the edge of the sidewall closest to the source in the integrated circuit. The implant angle for the implant process is selected based on the pattern of the edge angles of the doped regions in the drain well. For example, see Figure 5C , the doped regions 518A-518D in the drain well 507 of the integrated circuit 500 have both vertical and non-vertical edges of the doped regions alternating as: vertical, non-vertical, vertical, non-vertical. Figure 5D In FIG, doped regions 518A-518D in the drain well 507 of the integrated circuit 501 have both vertical and non-vertical edges closest to the source 507, alternating as: non-vertical, vertical, non-vertical, vertical. Figure 5EIn the embodiment, all doped regions 518A-518D of the integrated circuit 502 have non-vertical edges closest to the source 507 that alternate as: negative angle, positive angle, negative angle, positive angle. The implantation angles of the dopant atoms added to the substrate are alternated between implants, or the intervals between the implant boundaries of subsequent implants are alternated to provide spatial resolution between the doped regions of the drain well. For example, in some embodiments, the first doped region is formed with a negative implantation angle (-) and the second doped region is formed with a normal (0°) implantation angle. In some embodiments, the first doped region is formed with a normal implantation angle (0°) and the second doped region is formed with a positive (+) implantation angle. In some embodiments, the first doped region is formed with a positive implantation angle (+) and the second doped region is formed with a negative (-) implantation angle. In some embodiments, a first doped region is formed using a first implant shield (e.g., mask layer 316C) at a positive (+) implant angle, a normal (0°) implant angle, or a negative (-) implant angle, and a second doped region is formed using a second implant shield (e.g., spacer 320) at a positive (+) implant angle, a normal (0°) implant angle, or a negative (-) implant angle. The alternating implant angles and the pattern of implant shields are adjusted according to the specifications of the LDMOS device being manufactured. For example, in some embodiments, the implant angles of the second and fourth implants are adjusted to be positive (+) so that there is a gap between the top edges of the regions on either side of the second and / or third doped regions (see, e.g., below). Figure 5E ).

[0067] The number of implantation processes performed to form the LDMOS device is determined based on the semiconductor device specifications used by the manufacturer during the manufacturing process. In some embodiments of the method, the doping process is performed two, three, four, or more times to form the doped well. In some embodiments, the doping process for the doped region of the drain well is performed at a 0° implantation angle. In some embodiments, the doping process for the doped region of the drain well is performed at a negative implantation angle. In some embodiments, the doping process for the doped region of the drain well is performed at a positive implantation angle. In some embodiments, as further described below, the drain well is formed with alternating implantation angles to form its doped regions. Figure 3C-3F To illustrate the order in which steps are performed to form an LDMOS device having four doped regions. Figure 4A-4B and Figures 5A-5E Alternative embodiments of LDMOS devices having positive implant angles, negative implant angles, and a 0° (normal) implant angle, fabricated according to the method described below, are described.

[0068] Each doped region of the drain well has an associated implant vector, region depth (related to the implant energy), and implant dose to achieve a dopant concentration and region profile for the doped region of the drain well. For example, a doped region with a normal implant angle (e.g., a 0° implant angle) has a boundary closest to the source well that extends straight down from the top surface of the substrate (see, e.g., Figure 3B The doped region 318B (region N2) of the drain well 307 in the substrate is implanted with a positive implant angle. The doped region with the positive implant angle has a boundary closest to the source well, which is closer to the source well at the top surface of the substrate and farther away from the source well deeper in the substrate (see Figure 5D The doped region 518D (region N4) of the drain well 507 in the substrate is doped with a negative implant angle. The doped region with the negative implant angle has a boundary closest to the source well, which is closer to the source well deep in the substrate and is farthest from the source well at the top surface of the substrate (see, for example, Figure 5A Doped region 518A (region N1) of the drain well 507 in the embodiment.

[0069] A first doped region receives a first region implant dose to a first region dopant concentration from dopant atoms added at a first implant vector having a first implant angle. The first region dopant concentration is the result of the drift region implant dose plus the first region implant dose. A second doped region receives a second region implant dose to a second region dopant concentration from dopant atoms added at a second implant vector having a second implant angle. The second region dopant concentration is the result of the first implant dose and the second implant dose. Each subsequent implant dose achieves an implant concentration that is the sum of the previous implant doses implanted into the volume by the implant process, including the drift region implant dose (e.g., a third doped region has a third dopant concentration that is the result of the third dose plus the second dose plus the first dose plus the drift region dose).

[0070] In some embodiments, the doped regions of the drain well are implanted to different depths (see, for example, Figure 3F In some embodiments, the doped regions of the drain well are implanted to the same depth, but with different associated implantation angles (see, e.g., Figure 5C 、 Figure 5D and Figure 5E ,exist Figure 5C In the example, the doped regions alternate between negative and normal (e.g. 0°) implantation angles. Figure 5D In the case of doping, the doped regions alternate between normal and positive implantation angles, or Figure 5E In the example, doped regions alternate between negative and positive implant angles).

[0071] In some embodiments, two doped regions are implanted over the substrate using a single mask layer. In some embodiments, spacers are added to the sidewalls of the mask layer to advance the sidewalls of the mask layer away from the source well and toward the drain well (or toward the drain LDD region location), thereby protecting the first implanted region and / or the second implanted region from subsequent dopant atom implantation (see, for example, Figure 3E The middle spacer 320 is in close proximity to the mask layer 316, as described below).

[0072] Figure 3C-3F is a cross-sectional view of integrated circuit 300 during a manufacturing process according to some embodiments.

[0073] exist Figure 3C , a mask material layer 316C has been deposited over the gate electrode material 312 and spacers 314 on the source well and drain well sides of the gate electrode. A patterned material layer 306C is above the top surface of the mask material layer 316C. An opening 324C extends through the mask material layer 316C and the patterned material layer 306C to expose the top surface of the substrate 302 in the drift region 304. Dopant atoms are added during an implantation process along an implant vector 308C at an implant angle 390C relative to a reference line 389. A first doped region 318A extends downward from the top surface of the drift region 304 to a first region depth D1, serving as a first portion of the doped drain 307.

[0074] In some embodiments, the first doped region 318A is doped with dopant atoms at an implantation vector of 0° to 60°. In some embodiments, the implantation energy of the doped atoms is relatively high (50-1000 keV), and the dopant atoms are added to not less than about 1×10 12 / cm 2 to no more than about 1×10 16 / cm 2 Low dopant atomic concentration. Implantation energies greater than 1000 keV are more likely to damage the substrate and cause excessive diffusion during annealing to repair damage to the substrate. Implantation energies less than 50 keV may leave a small manufacturing margin for the implantation process of the second, third, and / or fourth doping regions for the drain well. The dopant concentration range in the first doping region implant is sufficient to produce a concentration gradient at the boundary between, for example, the doping region and the drain well, or the doping region and a doping region with a higher dopant concentration (e.g., the second, third, or fourth implantation region).

[0075] exist Figure 3D, opening 324D extends through patterned material layer 306C and mask material layer 316C. Dopant atoms are added along implant vector 308D at implant angle 390D relative to reference line 389. Implant angle 390D is a normal (0°) implant angle. Doped region 318B has been formed in substrate 302 within doped region 318A, extending downward from the top surface of substrate 302 to a region depth D2 and having a region width W2 from the edge of drain well D0. Region depth D2 is less than region depth D1. In some embodiments, region depth D2 is the same as region depth D1.

[0076] exist Figure 3E , spacers 320 have been added to the sidewalls of the mask material layer 316C, forming new openings 324E. Dopant atoms for the doped region 318C are added along an implant vector 308E at an implant angle 390E relative to a reference line 389. The doped region 318C has a region depth D3 extending downward from the top surface of the substrate 302 and a region width W3 measured from the edge of the drain well D0. The doped region 318C is separated from the doped region 318A by the doped region 318B. The doped region 318C has a greater dopant concentration than the doped region 318B, the doped region 318A, and the drift region 304. The spacers 320 drift the edge of the implantable region of the drain well 307 away from the gate electrode so that implants after the formation of the spacers 320 also drift away from the gate electrode, and previous implants (e.g., in the doped regions 318A and 318B) are protected to be implanted in the drift region 304 and the drain LDD region (see Figure 3G The doped regions between the drain LDD regions 326A and the drain LDD regions 326A have a set of sequentially increasing dopant concentrations. In some embodiments, the thickness of the spacer 320 along the second direction 399 is in a range of 2 nm to 20 nm, but other spacer thicknesses are also within the scope of the present disclosure. In some embodiments, the spacer 320 is manufactured by removing the patterned material 306C from the top surface of the mask material layer 316C, depositing a second dielectric material over the top surface of the mask material layer 316C, and performing a set of steps related to depositing the patterned material, transferring the pattern to the patterned material, forming an opening in the patterned material, and etching the second dielectric material to produce a large thickness spacer (e.g., a thickness greater than 100 nm).

[0077] exist Figure 3F, dopant atoms are added to the substrate 302 along the dopant vector 308F through the spacer 320 on one side of the mask material layer 316C through the opening 324F to form a doped region 318D. The doped region 318D is separated from the doped region 318B by the doped region 314C. The dopant concentration of the doped region 318D is greater than the dopant concentration of the drift region 304 or any of the doped regions 318A-318C. The doped region 318D has a region depth D4 extending downward from the top surface of the substrate 302 and a region width W4 from the edge (W0) of the drain well 307. In some embodiments, the region depth D4 is the same as the region depth D3. In some embodiments, the region depth D4 is less than the region depth D3. Figure 3F In addition to the drain LDD region (see Figure 3G The drain well 307 is complete except for the drain LDD region 326A in the drain well. A drain LDD region is formed in the drain well according to operation 210 of the method 200.

[0078] Method 200 includes operation 210, in which an LDD region is formed in a substrate. Operation 210 involves Figure 3G The integrated circuit 300 includes steps associated with removing the mask material layer 316C and the spacers 320 to expose the substrate 302, the spacers 314, and the gate electrode material 312. Operation 210 also includes steps associated with forming a hard mask material 309G on the top surface of the substrate 302, depositing a patterned material layer 306G over the hard mask material 309G, and transferring the pattern to the patterned material layer 306G to form openings therein, exposing portions of the substrate (and the gate electrode) for a doping process that forms LDD regions in the source and drain wells and also adds dopant atoms to the exposed portions of the gate electrode material. Operation 210 also includes steps associated with removing the mask material layer and the patterned material used to form the first set of LDD regions (regions) and depositing a second patterned material layer, transferring the pattern thereto, forming openings in the second patterned material layer to dope the material, and performing a doping process on the source well to complete the formation of the source LDD region, as described below. In the following discussion, for clarity in describing the locations of the openings and membranes during the manufacturing process, reference is made to Figure 3G and Figure 3H components.

[0079] The steps associated with removing the mask material layer 306C and the spacers 320 to expose the substrate 302, the spacers 314, and the gate electrode material 312 are performed, for example, by a liquid etching or wet etching process, which removes the dielectric material of the mask material layer 306C and the spacers 320 without etching the spacers 314 or the doped substrate. In some embodiments, an annealing process is performed on the substrate after each doped region has been formed in the substrate or in the drain well 307 to repair damage to the substrate caused by the doping process (implantation of dopant atoms). In some embodiments, a single annealing process is performed after forming the drain well 307 and before performing the first LDD region implantation process to realign the atoms of the substrate and prevent substrate corrosion caused by implantation damage.

[0080] The steps associated with forming a hard mask material (see hard mask material 309G) are associated with forming a layer of silicon carbide, silicon nitride, or some other dielectric material, which can be grown on the exposed semiconductor material by, for example, epitaxial deposition, or deposited on the substrate and gate electrode by chemical vapor deposition (CVD) to protect portions of the source well and doped regions (particularly low dopant concentration doped regions) from high-dose implantation processes. A patterned material layer is deposited over the hard mask material and patterned according to a process used in semiconductor device fabrication (photolithography, UV lithography, e-beam lithography, etc.), and openings are formed therein according to the transferred pattern.

[0081] Forming openings in the patterned material layer and through the hard mask material includes forming openings corresponding to the locations of the LDD regions in the source well 310 and the drain well 307, with a portion of the gate electrode extending over the source well 310 and the drift region 304. Forming the openings also includes steps such as an etching process for removing the exposed hard mask material at the bottom of the openings in the patterned material layer and exposing the substrate in the source well 310 and the drain well 307 and the top surface of the gate electrode, as described above (see Figure 3G The first opening 324G1 and the second opening 324G2 in the embodiment of the present invention are shown in FIG.

[0082] The doping process includes adding dopant atoms to form a drain well LDD region (see drain LDD region 326A) and a source well LDD region (see source LDD region 326C). Dopants are added through the first and second openings along an implantation vector 308G at an implantation angle (see implantation angle 390G). When fabricating the LDD region of the LDMOS device, the dopant atom energy is adjusted to maintain a shallow implantation depth and a high implantation dose.

[0083] Steps associated with fabricating the source LDD region 326D (e.g., completing the source LDD region 326B) include steps for removing a patterned material layer (see patterned material 306G), a mask material layer (see mask material layer 316G), and steps for depositing a new patterned material layer (see patterned material layer 306H) and forming an opening therein to expose a source well adjacent to the first source well LDD region formed in the substrate.

[0084] The doping process for forming the first source well LDD region includes adding dopant atoms to the substrate at a normal (0°) or near-normal implantation angle to provide the first source well LDD region and the second source well LDD region (see Figure 3H The interface between the source well LDD regions 326C and 326D is perpendicular to the top surface of the source well.

[0085] Figure 3G-3H is a cross-sectional view of integrated circuit 300 during a manufacturing process according to some embodiments.

[0086] exist Figure 3G 304, and the drift region 304. A hard mask material 309G extends above the top surface of the substrate 302 in the source well 310, the drift region 304, and the drain well 307. A patterned material layer 306G is above the hard mask material 309G. A first opening 324G1 extends through the patterned material layer 306G and the hard mask material 309G to expose the source well 310, a portion of the spacer 314 on the source well side of the gate electrode material 312, and a portion of the gate electrode material 312 above the source well 310 and above the drift region 304. A portion of the gate electrode material 312 closest to the drain well 307 and a portion of the spacer 314 on the drain well side of the gate electrode material 312 are covered by the patterned material layer 306C. A second opening 324G2 extends through the patterned material layer 306G and the hard mask material 309G to expose a portion of the drain well 307: the doped region 318D.

[0087] The first doping process for forming LDD regions in the LDMOS device adds N-type dopant atoms to the substrate. Dopant atoms are added through second opening 324G2 along implantation vector 308G at an implantation angle 390G relative to reference line 389, thereby forming drain LDD region 326A in drain well 307. Dopant atoms are added through first opening 324G1 along implantation vector 308G at reference line 389 to source well 310, forming source LDD region 326C of source LDD region 326B. Implantation angle 390D is a normal (0°) angle relative to reference line 389. Implantation of dopant atoms into doped region 318D is performed at an implantation energy that adds dopant atoms only to doped region 318D and not to doped regions with low dopant atom concentrations (e.g., doped regions 318C, 318B, or 318A).

[0088] exist Figure 3H , the hard mask material 309G and the patterned material layer have been removed, and a patterned material layer 309H has been deposited over the drain well 307, the gate electrode material 312, and the source well 310. An opening 324H extends through the patterned material layer 306H to expose a portion of the source well 310 adjacent to the source LDD region 326C. P-type dopant atoms are added to the source well 310 to complete the source LDD region 326B. The dopant atoms are added along the implant vector 308H at an implant angle 390H relative to the reference line 389. The implant angle 390H is a normal angle (0° implant angle). The source LDD region 326B includes a source LDD region 326C that includes a net remaining N-type dopant and is adjacent to the source LDD region 326D that includes a net remaining P-type dopant. The patterned material layer 306H protects the gate electrode material 312 and the drain well 307 from being implanted with P-type dopant atoms during the formation of the source LDD region 326D.

[0089] The method 200 includes an optional operation 212 in which a silicide layer is formed on a top surface of the LDD region and a top surface of the gate electrode. Figure 3I The integrated circuit 300 is shown after performing steps associated with forming a silicide layer on the top surface of the LDD region and the top surface of the gate electrode. The steps associated with forming the silicide layer include steps associated with depositing a patterned material layer over the substrate and the gate electrode, transferring the pattern to the patterned material layer, and forming an opening in the patterned material layer. Other steps associated with forming the silicide layer include sputtering a thin metallic coating on the top surfaces of the gate electrode, source LDD region, and drain LDD region of the LDMOS device, and annealing the LDMOS device to intermix the thin metallic coating with the gate electrode material, the source LDD region, and the drain LDD region.

[0090] In some embodiments, the thin metallization coating is a layer of tungsten, cobalt, titanium, tantalum, platinum, palladium, or other metal suitable for forming a silicide layer for electrical contact with transistors in a semiconductor device. In some embodiments, the annealing process used for the LDMOS device is a rapid laser annealing process to promote rapid heating and cooling, thereby limiting the extent of melting or interdiffusion of metal atoms and the material of the LDD region. By reducing the amount of melting or interdiffusion, the dopant profile in the source and drain LDD regions is preserved without diffusing into the rest of the source or drain wells of the LDMOS device.

[0091] Figure 3I is a cross-sectional view of an integrated circuit 300 during a manufacturing process according to some embodiments. Figure 3I In the embodiment, the patterned material layer 306I is located above the drain well 307 and the drift region 304, the top surface of the spacer 314 on the drain well side of the gate electrode material 312, and the top surface of the gate electrode material 312 closest to the drain well 307. The drain LDD silicide 328A is on the top surface of the drain LDD region 326A, the source LDD silicide 328B is on the top surface of the source LDD region 326B (both the source LDD region 326C and the source LDD region 326D), and the gate electrode silicide 328C is on the top surface of the gate electrode material 312 that is not covered by the patterned material layer 306I. The gate electrode silicide 328C is separated from the spacer 314 on the drain well side of the gate electrode material 312.

[0092] The method 200 includes operation 214 , in which contacts are formed to the source well and the drain well. Figure 3J The integrated circuit 300 is performed after operation 214. In operation 214, a dielectric material (interlayer dielectric, ILD) is deposited on the substrate including the source and drain wells and the gate electrode. A patterned material layer is deposited on the top surface of the ILD layer, the pattern is transferred to the patterned material layer, and an opening is formed therein to expose the top surface of the ILD layer. An etching process is performed to form openings through the ILD layer, exposing the source LDD silicide, the drain LDD silicide, and the gate electrode silicide. A metallic material (contact material) is deposited in the openings through the ILD layer to form an electrical connection with the exposed silicide layer at the bottom of the ILD layer, and the LDMOS device is planarized by a chemical mechanical polishing process to expose the top surface of the LDMOS device for the other manufacturing steps of the LDMOS device.

[0093] Figure 3J is a cross-sectional view of an integrated circuit 300 during a manufacturing process according to some embodiments. Figure 3JIn [description], an interlayer dielectric (ILD) layer 330 is deposited over the top surfaces of the drain well 307, the source well 310, and the gate electrode material 312. The ILD layer 330 is a dielectric material, such as, silicon dioxide, BPSG, FSG, or other insulating materials suitable for electrically isolating the components of the LDMOS from each other in a semiconductor device.

[0094] Contacts 332A and 332B extend through the ILD 330. Contact 332A extends through the ILD 330 to make electrical connection with the drain LDD silicide 328A. Contact 332B extends through the ILD 330 to make electrical connection with the source LDD silicide 328B. The gate electrode contact 332C extends through the ILD 330 to make electrical connection with the gate electrode silicide 328C. The contacts are made of a conductive material, such as, tungsten, cobalt, titanium, platinum, palladium, or other metal or metal alloy compatible with the LDMOS device.

[0095] Figure 4A-4B is a cross-sectional view of an integrated circuit 400 according to some embodiments. Figure 4A is a cross-sectional view of an integrated circuit 400, including two doped regions (N1 and N3) in the drain well 407, while in Figure 3J In [description], the drain well 307 has four doped regions: N1, N2, N3, and N4. Components of the integrated circuit 400 having a structure and / or function similar to those of the components of the integrated circuit 300 (as Figure 3J shown) have the same reference numerals, incremented by 100.

[0096] In Figure 4A In [description], the integrated circuit 400 includes a LDMOS device having a drain well 407 that includes two doped regions, doped region 418A and doped region 418C, instead of the four doped regions (318A - 318D) of the integrated circuit 300, as described in Figure 3J above.

[0097] In Figure 4A In [description], the doped region 418A has a region depth D1, and the doped region 418C has a region depth D3, where D3 < D1. The doped region 418A has a region width W1, and the doped region 418C has a region width W3, where W3 < W1. In some embodiments, the region depths of the two doped regions are the same. The doped region 418A has a lower dopant atom concentration than the doped region 418C, and a higher dopant atom concentration than the drift region 404.

[0098] In an embodiment of an LDMOS device having two doped regions (e.g., integrated circuit 400), the doped regions are fabricated by two normal (0°) doping processes for the drain well, the two normal (0°) doping processes having the same implant vector (e.g., two positive implant vectors, two normal (0°) implant vectors, or two negative implant vectors), and a spacer is added to one side of the mask layer between a first doping process forming the first doped region and a second doping process forming the second doped region. Other methods for fabricating an LDMOS device having two doped regions are further described below.

[0099] exist Figure 4B In the embodiment, the integrated circuit 450 includes an LDMOS device having a drain well 407, which includes three doped regions (eg, N1, N2, and N4): a doped region 418A, a doped region 418B, and a doped region 418D, instead of the above Figure 3J The four doped regions (318A-318D) of the integrated circuit 300 are described. In an embodiment of an LDMOS device having three doped regions, the doped regions are manufactured by three doping processes for the drain well. The doped regions are distinguished from each other by modifying the injection angle at which the doping process is performed, modifying the position of the edge of the doped region (by, for example, adding a spacer on one side of the mask (see the above-mentioned spacer 320), or a combination of injection angle modification and spacer addition). The doped regions are also distinguished from each other by the dopant concentration therein, which is caused by modifying the injection dose of the doped region, or modifying the injection time of the doping process. Figure 4B In the embodiment of the present invention, doped region 418A has a first dopant concentration that is less than the dopant concentration in doped region 418B and the dopant concentration in doped region 418D. Doped region 418A has a region depth D1 from the top surface of substrate 402 that is greater than the region depth D2 of doped region 418B and the region depth D4 of doped region 418D. Doped region 418A has a region width W1 that is greater than the region width W2 of doped region 418B and the region width W3 of doped region 418D.

[0100] Figures 5A-5C is a cross-sectional view of an integrated circuit 500 during a manufacturing process according to some embodiments. In the cross-sectional view of the integrated circuit 500, the doped region has a combination of non-vertical edges and vertical edges closest to the source 510 (see Figures 5A-5C , where N1 and N3 have angled vertical edges closest to source 510, and where N2 and N4 have vertical edges closest to source 510).

[0101] With Figure 3C components of the integrated circuit 300 that have similar structures or functions Figure 5AElements of the integrated circuit 500 in FIG. 5 have the same reference numerals, increased by 200. Measurements involving the same structural features have the same reference numerals without modification. Figure 5A In FIG. 5 , a doped region 518A has been formed in the substrate 502 (or in the drift region 504 ), and its region depth D1 is less than the drift region depth D0 .

[0102] The dopant atoms added to the doped region 518A have an implantation vector 508C at an implantation angle 590C relative to a reference line 589. The mask material layer 516C protects the drift region in the shadow of the mask material layer 516C, preventing dopant atoms from being implanted into the implantation shadow. The doped region 518A has a lower zone width W1A and an upper zone width W1B, where W1B < W1A. The zone flare width F1 at the top of the doped region is less than the zone flare width F2 at the bottom of the doped region. The zone flare width F1 and the zone flare width F2 are measured from the edge of the doped region 518A to a projection line extending downward from the edge of the mask material layer 516C on the top surface of the substrate 502. The edge of the doped region below the mask material layer 516C has an edge angle 591 that corresponds to the implantation angle 590C relative to the reference line 589. The absolute values ​​of zone expansion width F1 and zone expansion width F2 are different from each other because they are measured at different distances from the top surface of the substrate. However, if zone expansion width F2 is measured at a distance farther from the top surface of the substrate than zone expansion width F1, then when the implantation angle 590C is negative (-), F2 is always greater than F1.

[0103] With the above Figure 5A The components of the integrated circuit 500 have the same structure or function Figure 5B Components of integrated circuit 500 in FIG. 504 have the same reference numerals. Doped region 518B is formed by adding dopant atoms along an implant vector 508D having a normal (0°) implant angle 590D relative to reference line 589. A region width W2 of doped region 518B is constant relative to the depth of the edge of the doped region from the top surface of substrate 502. A region depth D1 of doped region 518A is greater than a region depth D2 of doped region 518B. Region depth D1 is greater than region depth D2, and both region depth D1 and region depth D2 are constant across drift region 504. In some embodiments, region depth D1 is equal to region depth D2. Doped region 518A has a lower dopant concentration than doped region 518B.

[0104] exist Figure 5C, dopant atoms are added to doped region 518D along implant vector 508F having an implant angle 590F relative to reference line 589. Implant angle 590F is a normal (0°) implant angle. Doped region 518C separates doped region 518B from doped region 518D. Doped regions 518A and 518C have the same profile (e.g., due to the negative implant angle), and doped regions 518B and 518D have the same profile (e.g., due to the normal (0°) implant angle). The zone expansion characteristics of doped region 518C (e.g., wider at the bottom and narrower at the top) are similar to the zone expansion characteristics of doped region 518A (wherein zone expansion F1 < zone expansion F2 when zone expansion F2 is measured deeper within substrate 502 than zone expansion F1). The doped regions 518A- 518D have similar dopant concentrations as described above for the doped regions 318A- 318D of the integrated circuit 300 .

[0105] In an embodiment of an LDMOS device similar to integrated circuit 500, for regions implanted at a negative (-) implant angle, the region opening at the top of the doped region is reduced to approximately zero (0) nanometer spacing, and the doped region has a smaller concentration (and a non-vertical region edge). In some embodiments, the doped regions are separated from each other at the top surface by modifying the implant angle at which some doping processes are performed, or by modifying the location of the edges of the doped regions (e.g., by adding spacers (see spacer 520) on one side of the mask material, or a combination of implant angle modification and spacer addition). The implant angles of the doped regions of integrated circuit 500 are as follows: {-0-0}.

[0106] Figure 5D is a cross-sectional view of an integrated circuit 501 during a manufacturing process according to some embodiments. Figure 5D In the embodiment of the present invention, the doped regions have alternating vertical edges and non-vertical edges closest to the source 510 (e.g., doped region 518A has a vertical edge closest to the source 510, doped region 518B has a non-vertical edge closest to the source 510, doped region 518C has a vertical edge closest to the source 510, and doped region 518D has a non-vertical edge closest to the source 510). In the integrated circuit 501, the doped region 518A is formed by, for example, a doping process that uses the top angle of the mask material layer 516C instead of the bottom angle of the mask material layer (see Figure 3D316C in the mask material layer 516C) to protect the substrate from the effects of the implanted dopant atoms. For example, the mask material layer 516C extends to the inner edge of the doped region 518A, indicating that the implant angle of the dopant atoms added to form the doped region 518A has a normal implant vector (e.g., an implant angle of 0°). The upper edge of the doped region 518B deviates from the edge of the mask material layer 516C on the top surface of the substrate 502. Adding dopant atoms to form the doped region 518B with a positive (+) implant angle utilizes the upper corner of the mask material layer 516C to protect the substrate in the doped region 518A closest to the mask material layer 516C from the effects of the added dopant atoms. Therefore, at the top surface, the doped regions 518A and 518B are separated from each other on the top surface. Similarly, the doped region 518C is aligned with the edge of the spacer 520 and has a constant width W3, which indicates that the implant angle of the doped region 518C is approximately 0°. Doped region 518D is separated from spacer 520 on the top surface of substrate 502, indicating that the implantation angle of doped region 518D is positive (+). The implantation angles of the doped regions of integrated circuit 503 are as follows: {0+0+}.

[0107] Figure 5E is a cross-sectional view of integrated circuit 503 during a manufacturing process according to some embodiments. Figure 5E In FIG, all doped regions of integrated circuit 503 have non-vertical edges closest to source 510. The drain well 507 of integrated circuit 503 is different from the drain well of integrated circuit 501, as described below. Figure 5E In FIG5 , doped region 518A has been formed with a negative implant angle, doped region 518B has been formed with a positive implant angle, doped region 518C has been formed with a negative implant angle, and doped region 518D has been formed with a positive implant angle. Thus, the implant angles of the doped regions for integrated circuit 503 are as follows: {-+-+}. Doped region 518A has a region depth D1, doped region 518B has a region depth D2, doped region 518C has a region depth D3, and doped region 518D has a region depth D4, where D4<D3<D2<D1. Doped region 518A has a lower region width W1A and an upper region width W1B, where W1A>W1B. Doped region 518B has a lower region width W2A and an upper region width W2B, where W2A>W2B. Doped region 518C has a lower region width W3A and an upper region width W3B, where W3A>W3B. Doped region 518D has a lower region width W4A and an upper region width W4B, where W4A>W4B. Furthermore, W1A>W1B>W2A>W2B>W3A>W3B>W4A>W4B. Thus, at the top surface of substrate 502, each doped region is separated from the edge of the adjacent doped region, further improving the ability of the drain well to avoid Kirk effect (base pushout) during high current operation.

[0108] Figure 6 6 is a graph 600 of the breakdown voltage of an LDMOS device based on the data provided above, relating to the separation distance (μm) between the gate electrode and the drain well, and the associated breakdown voltage (V) for the separation distances provided above. The breakdown voltage of the LDMOS device is a function of the distance between the edge of the gate electrode closest to the drain well and the edge of the doped region with the second lowest dopant concentration in the drain well closest to the gate electrode. In a non-limiting example, the separation distance 133 in the integrated circuit 100 is the distance between the top edge of the doped region 118A and the nearest edge of the gate electrode 112. For the gate electrode closest to the drain well (see above), the separation distance 133 is the distance between the top edge of the doped region 118A and the nearest edge of the gate electrode 112. Figure 1 The edge of the drain well 107 in the drain well and the second doped region of the drain well (see above Figure 1 As the distance between the inner edge of the doped region 118A of the drain well 107 in the LDMOS device increases, the breakdown voltage of the LDMOS device increases by about 14 volts (V) per micron (μm).

[0109] In some embodiments, an LDMOS device having a separation distance of 1-3 μm between the gate electrode and the drain well has a breakdown voltage of approximately 20 volts. In some embodiments, an LDMOS device having a separation distance of 3-5 μm between the gate electrode and the drain well has a breakdown voltage of approximately 50 volts. In some embodiments, an LDMOS device having a separation distance of 5-7 μm between the gate electrode and the drain well has a breakdown voltage of approximately 70 volts. In some embodiments, an LDMOS device having a separation distance of 7-9 μm between the gate electrode and the drain well has a breakdown voltage of approximately 100 volts. In some embodiments, an LDMOS device having a separation distance of 20-40 μm between the gate electrode and the drain well has a breakdown voltage of approximately 500 volts. In some embodiments, the breakdown voltage is approximately 1200 V. In some embodiments, an LDMOS device having a separation distance of 40-60 μm between the gate electrode and the drain well has a breakdown voltage of approximately 700 volts. Therefore, the correlation between the breakdown voltage and the separation distance between the gate electrode and the drain well is approximately 14.8 V / μm.

[0110] A system of one or more computers may be configured to perform specific operations or actions through software, firmware, hardware, or a combination thereof installed on the system, which software, firmware, hardware, or a combination thereof, in operation, causes or results in the system performing an action. One or more computer programs may be configured to perform specific operations or actions by including instructions that, when executed by a data processing device, cause the device to perform an action. One general aspect includes an integrated circuit. The integrated circuit also includes: a drift region in a substrate; a drain in the substrate, wherein the drain may include a doped drain well, wherein the doped drain well may include: a first region, wherein the first region has a first concentration of a first dopant; and a second region, wherein the second region has a second concentration of the first dopant, and the first concentration is less than the second concentration; and a gate electrode above the drift region, the gate electrode being separated from the doped drain well by a distance greater than zero in a direction parallel to the top surface of the substrate. Other embodiments of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method.

[0111] Implementations may include one or more of the following features. The drift region of the integrated circuit has a third concentration of the first dopant, and the third concentration is less than the first concentration. The second region is separated from the drift region by the first region. The drain may also include a drain low density doping (LDD) region, and the first region of the doped drain well is separated from the drain LDD region by the second region. The third region separates the second region from the drain LDD region and has a third concentration of the first dopant, the third concentration being greater than the second concentration of the first dopant in the second region. The fourth region separates the third region from the drain LDD region, the fourth region having a fourth concentration of the first dopant, the fourth concentration being greater than the third concentration of the first dopant in the third region. The first region has a first depth below the top surface of the substrate, and the second region has a second depth below the top surface of the substrate, and the first depth is different from the second depth. The first region has a first depth below the top surface of the substrate, and the second region has the first depth below the top surface of the substrate. The first region has a first width at the top surface of the substrate between the second region and the drift region, and has a second width at the bottom of the drift region between the second region and the drift region, wherein the first width and the second width are different widths measured in a direction parallel to the top surface of the substrate. The integrated circuit may include: a gate electrode above the top surface of the substrate; and an electrode silicide layer extending across less than the entire top surface of the gate electrode. Implementations of the described techniques may include hardware, methods, or processes on a computer-accessible medium, or computer software.

[0112] One general aspect includes a method of manufacturing an integrated circuit. The manufacturing method also includes forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type, the drain well including a first region having a first concentration of the first dopant and a second region having a second concentration of the first dopant, the second concentration being different from the first concentration of the first dopant; forming a source well in the substrate, the source well having a second dopant type opposite to the first dopant type, the source well being adjacent to the drift region in the substrate; forming a gate electrode above a top surface of the substrate above the drift region and the source well and laterally separated from the drain well; and forming a drain low density doping (LDD) region in the second region of the drain well. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0113] Implementations may include one or more of the following features. Forming a drain well in the drift region in the method may also include: depositing spacers on each side of the gate electrode; depositing a mask layer above the gate electrode and the substrate; forming an opening in the mask layer to expose the drift region; and forming a first region by implanting a dopant of a first dopant type into the drift region at a first implantation angle. Forming a drain well in the drift region may also include: forming a second region by implanting a dopant of the first dopant type into the first region at a second implantation angle, wherein the first implantation angle is different from the second implantation angle. The method may include forming a silicide layer on the top surface of the source LDD region, the drain LDD region, and the exposed portion of the gate electrode. Forming the first region may also include implanting a dopant of the first dopant type to a first depth at the first implantation angle, and forming the second region may also include implanting a dopant of the first dopant type into the first region at the second implantation angle to a first depth. The method may include forming a second spacer on a side of the mask layer above the drift region; forming a third region in the substrate by implanting a dopant of a first dopant type into the second region at a third implant angle to a third depth; and forming a drain LDD region in the third region. A fourth implant angle is less than the third implant angle, and the drain LDD region is formed in the fourth region. Implementations of the described techniques may include hardware, methods, or processes on a computer-accessible medium, or computer software.

[0114] One general aspect includes a device. The device also includes: a source well in a substrate; a drift region in the substrate; and a drain well in the substrate, the drain well including a drain LDD region and separated from the source well by the drift region, wherein the drain LDD region and the drift region are adjacent to and separate the source well from the drain well, and wherein the drain well includes a first region and a second region, the first region having a first concentration of a first dopant and the second region having a second concentration of the first dopant; and a first width of the first region between the drift region and the second region at a top surface of the substrate is smaller than a second width of the first region between the drift region and the second region at a bottom of the second region. The device also includes a gate electrode above the source well and the drift region, the gate electrode being laterally separated from the drain well at the top surface of the substrate. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the method.

[0115] Implementations may include one or more of the following features. The drain LDD region of the device has a third concentration of the first dopant; the first concentration of the first dopant is less than the second concentration of the first dopant; and the second concentration of the first dopant is less than the third concentration of the first dopant. The drift region has a fourth concentration of the first dopant that is less than the first concentration of the first dopant in the first region. Implementations of the described techniques may include hardware, methods or processes, or computer software on a computer-accessible medium.

[0116] It will be readily apparent to those skilled in the art that one or more of the disclosed embodiments achieve one or more of the aforementioned advantages. After reading the foregoing description, those skilled in the art will be able to realize various variations, substitutions of equivalents, and various other embodiments as broadly disclosed herein. The protection therefore intended to be granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0117] Example 1 is an integrated circuit comprising: a drift region in a substrate; a drain in the substrate, wherein the drain comprises a doped drain well, wherein the doped drain well comprises: a first region, wherein the first region has a first concentration of a first dopant; and a second region, wherein the second region has a second concentration of the first dopant, and the first concentration is less than the second concentration; and a gate electrode above the drift region, the gate electrode being separated from the doped drain well by a distance greater than 0 in a direction parallel to a top surface of the substrate.

[0118] Example 2 is the integrated circuit of Example 1, wherein the drift region has a third concentration of the first dopant, and the third concentration is less than the first concentration.

[0119] Example 3 is the integrated circuit of Example 1, wherein the second region is separated from the drift region by the first region.

[0120] Example 4 is the integrated circuit of Example 1, wherein the drain further comprises a drain low density doping (LDD) region, and the first region of the doped drain well is separated from the drain LDD region by the second region.

[0121] Example 5 is the integrated circuit described in Example 4, further including: a third region, wherein the third region separates the second region from the drain LDD region and has a third concentration of the first dopant, and the third concentration is greater than the second concentration of the first dopant in the second region.

[0122] Example 6 is the integrated circuit described in Example 5, further including: a fourth region, wherein the fourth region separates the third region from the drain LDD region, and the fourth region has a fourth concentration of the first dopant, and the fourth concentration is greater than the third concentration of the first dopant in the third region.

[0123] Example 7 is the integrated circuit of Example 1, wherein the first region has a first depth below the top surface of the substrate, the second region has a second depth below the top surface of the substrate, and the first depth is different from the second depth.

[0124] Example 8 is the integrated circuit of Example 1, wherein the first region has a first depth below the top surface of the substrate, and the second region has the first depth below the top surface of the substrate.

[0125] Example 9 is the integrated circuit of Example 1, wherein the first region has a first width between the second region and the drift region at the top surface of the substrate, and has a second width between the second region and the drift region at the bottom of the drift region, wherein the first width and the second width are different widths measured in a direction parallel to the top surface of the substrate.

[0126] Example 10 is the integrated circuit of Example 1, further comprising: a gate electrode over the top surface of the substrate; and an electrode silicide layer extending across less than the entire top surface of the gate electrode.

[0127] Example 11 is a method of manufacturing an integrated circuit, comprising: forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type, the drain well including a first region having a first concentration of a first dopant and a second region having a second concentration of the first dopant, the second concentration being different from the first concentration of the first dopant; forming a source well in the substrate, the source well having a second dopant type opposite to the first dopant type, the source well being adjacent to the drift region in the substrate; forming a gate electrode above the top surface of the substrate above the drift region and the source well and laterally separated from the drain well; and forming a drain low density doping (LDD) region in the second region of the drain well.

[0128] Example 12 is the method described in Example 11, wherein forming a drain well in the drift region further includes: depositing spacers on respective sides of the gate electrode; depositing a mask layer over the gate electrode and the substrate; forming an opening in the mask layer to expose the drift region; and forming the first region by implanting dopants of the first dopant type into the drift region at a first implantation angle.

[0129] Example 13 is the method described in Example 12, wherein forming a drain well in the drift region further comprises forming the second region by implanting dopants of the first dopant type into the first region at a second implantation angle, wherein the first implantation angle is different from the second implantation angle.

[0130] Example 14 is the method described in Example 13, wherein forming an opening in the mask layer to expose the drift region further includes: forming an opening in the mask layer, wherein an edge of the mask layer adjacent to the drift region is laterally separated from the gate electrode and the interface between the drift region and the source well.

[0131] Example 15 is the method described in Example 13, wherein forming the first region further includes implanting dopants of the first dopant type to a first depth at the first implantation angle, and forming the second region further includes implanting dopants of the first dopant type into the first region to the first depth at the second implantation angle.

[0132] Example 16 is the method described in Example 13, further comprising: forming a second spacer on one side of the mask layer above the drift region; forming a third region in the substrate by implanting dopants of the first dopant type into the second region at a third injection angle to a third depth; and forming the drain LDD region in the third region.

[0133] Example 17 is the method described in Example 13, further including: forming a second spacer on one side of the mask layer above the drift region; forming a third region in the substrate by injecting dopants of the first dopant type into the second region at a third injection angle to a third depth; forming a fourth region in the substrate by injecting dopants of the first dopant type into the third region at a fourth injection angle to a fourth depth, wherein the fourth injection angle is smaller than the third injection angle; and forming the drain LDD region in the fourth region.

[0134] Example 18 is a semiconductor device comprising: a source well in a substrate; a drift region in the substrate; a drain well in the substrate, the drain well comprising a drain low-density doped LDD region and separated from the source well by the drift region, wherein the drain well comprises a first region and a second region, the first region having a first concentration of a first dopant, and the second region having a second concentration of the first dopant; and a first width of the first region between the drift region and the second region at the top surface of the substrate is smaller than a second width of the first region between the drift region and the second region at the bottom of the second region; and a gate electrode above the source well and the drift region, the gate electrode being laterally separated from the drain well at the top surface of the substrate.

[0135] Example 19 is the device of Example 18, wherein the drain LDD region has a third concentration of the first dopant; the first concentration of the first dopant is less than the second concentration of the first dopant; and the second concentration of the first dopant is less than the third concentration of the first dopant.

[0136] Example 20 is the device of Example 18, wherein the drift region has a fourth concentration of the first dopant that is less than the first concentration of the first dopant in the first region.

Claims

1. An integrated circuit comprising: drift region, in the substrate; A drain, in the substrate, wherein the drain comprises a doped drain well, wherein the doped drain well comprises: a first region, wherein the first region has a first concentration of a first dopant; and a second region, wherein the second region has a second concentration of the first dopant, a topmost surface of the first region is coplanar with a topmost surface of the second region, and the first concentration is less than the second concentration; and a gate electrode above the drift region, the gate electrode being separated from the doped drain well by a distance greater than 0 in a direction parallel to the top surface of the substrate, wherein the first zone has a first width between the second zone and the drift region at the top surface of the substrate, and has a second width between the second zone and the drift region at the bottom of the second zone, wherein the first width and the second width are different widths measured in a direction parallel to the top surface of the substrate.

2. The integrated circuit according to claim 1, wherein: The drift region has a third concentration of the first dopant, and the third concentration is less than the first concentration.

3. The integrated circuit according to claim 1, wherein: The second region is separated from the drift zone by the first region.

4. The integrated circuit according to claim 1, wherein: The drain further includes a drain low density doping (LDD) region, and the first region of the doped drain well is separated from the drain LDD region by the second region.

5. The integrated circuit of claim 4 , further comprising: a third region, wherein the third region separates the second region from the drain LDD region and has a third concentration of the first dopant, the third concentration being greater than the second concentration of the first dopant in the second region.

6. The integrated circuit of claim 5 , further comprising: A fourth region separates the third region from the drain LDD region, the fourth region having a fourth concentration of the first dopant greater than the third concentration of the first dopant in the third region.

7. The integrated circuit according to claim 1, wherein: The first region has a first depth below the top surface of the substrate, the second region has a second depth below the top surface of the substrate, and the first depth is different from the second depth.

8. The integrated circuit according to claim 1, wherein: The first region has a first depth below a top surface of the substrate, and the second region has the first depth below a top surface of the substrate.

9. The integrated circuit of claim 1 , further comprising: The gate electrode is above the top surface of the substrate; as well as The electrode silicide layer extends across less than the entire top surface of the gate electrode.

10. A method of manufacturing an integrated circuit, comprising: forming a drift region in a substrate, the drift region having a first dopant type; forming a drain well in the drift region, the drain well having the first dopant type, the drain well including a first region having a first concentration of the first dopant and a second region having a second concentration of the first dopant, the second concentration being different from the first concentration of the first dopant, a topmost surface of the first region being coplanar with a topmost surface of the second region, wherein a first width of the first region between the drift region and the second region at the top surface of the substrate is different from a second width of the first region between the drift region and the second region at a bottom of the second region; forming a source well in the substrate, the source well having a second dopant type opposite to the first dopant type, the source well being adjacent to the drift region in the substrate; forming a gate electrode over the top surface of the substrate above the drift region and the source well and laterally spaced apart from the drain well; and A drain low density doping (LDD) region is formed in the second region of the drain well.

11. The method according to claim 10, wherein: Forming a drain well in the drift region further comprises: depositing spacers on respective sides of the gate electrode; depositing a mask layer over the gate electrode and the substrate; forming an opening in the mask layer to expose the drift region; and The first region is formed by implanting a dopant of the first dopant type into the drift region at a first implantation angle.

12. The method according to claim 11, wherein Forming a drain well in the drift region further comprises: The second region is formed by implanting a dopant of the first dopant type into the first region at a second implant angle, wherein the first implant angle is different from the second implant angle.

13. The method according to claim 12, wherein: Forming an opening in the mask layer to expose the drift region further comprises: An opening is formed in the mask layer, wherein an edge of the mask layer adjacent to the drift region is laterally separated from the gate electrode and an interface between the drift region and the source well.

14. The method according to claim 12, wherein: Forming the first region further includes implanting dopants of the first dopant type to a first depth at the first implant angle, and forming the second region further includes implanting dopants of the first dopant type into the first region to the first depth at the second implant angle.

15. The method according to claim 12, further comprising: forming a second spacer on a side of the mask layer above the drift region; forming a third region in the substrate by implanting a dopant of the first dopant type into the second region to a third depth at a third implantation angle; as well as The drain LDD region is formed in the third region.

16. The method according to claim 12, further comprising: forming a second spacer on a side of the mask layer above the drift region; forming a third region in the substrate by implanting a dopant of the first dopant type into the second region at a third implantation angle to a third depth; forming a fourth region in the substrate by implanting a dopant of the first dopant type into the third region to a fourth depth at a fourth implant angle, wherein the fourth implant angle is less than the third implant angle; as well as The drain LDD region is formed in the fourth region.

17. A semiconductor device comprising: a source well, in the substrate; a drift region in the substrate; A drain well, in the substrate, the drain well includes a drain low density doping LDD region and is separated from the source well by the drift region, wherein, The drain well includes a first region and a second region, the first region having a first concentration of a first dopant, the second region having a second concentration of the first dopant, a topmost surface of the first region being coplanar with a topmost surface of the second region; and a first width of the first region between the drift region and the second region at the top surface of the substrate is smaller than a second width of the first region between the drift region and the second region at the bottom of the second region; as well as A gate electrode is above the source well and the drift region, the gate electrode being laterally separated from the drain well at a top surface of the substrate.

18. The device according to claim 17, wherein The drain LDD region has a third concentration of the first dopant; The first concentration of the first dopant is less than the second concentration of the first dopant; and The second concentration of the first dopant is less than the third concentration of the first dopant.

19. The device according to claim 17, wherein The drift region has a fourth concentration of the first dopant that is less than the first concentration of the first dopant in the first region.

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