Single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layer and preparation method thereof

Abstract

The present invention provides a single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layers and a preparation method thereof. The resonator sequentially includes a silicon substrate, a support layer, and a single-crystal piezoelectric thin-film layer from bottom to top, and a cavity is formed between the silicon substrate, the support layer, and the single-crystal piezoelectric thin-film layer; an upper electrode layer and a lower electrode layer are respectively arranged on the upper and lower sides of the single-crystal piezoelectric thin-film layer, and the lower electrode layer is located in the cavity; an upper load layer and a lower load layer are respectively arranged at the upper and lower ends of the single-crystal piezoelectric thin-film layer, and the upper load layer and the lower load layer are symmetrically distributed up and down with respect to the single-crystal piezoelectric thin-film layer. By adopting a symmetric load layer design, the present invention can effectively reduce the parasitic waveform of the FBAR resonator at the resonance peak position. The present invention is applicable to the processing technology of single-crystal FBAR resonators using a bonding process, and further reduces the loss of the FBAR resonator on the basis of the single-crystal piezoelectric layer, which is beneficial to constructing a high-quality bulk acoustic wave filter with low insertion loss.

Description

Technical Field

[0001] The present invention relates to the technical field of bulk acoustic wave resonators, and particularly to a single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layers and a preparation method thereof. Background Art

[0002] 5G high-frequency filters are irreplaceable core components in the radio frequency communication front end, undertaking the main filtering and frequency selection functions. They are one of the key devices in the field of mobile communication and also one of the most promising third-generation semiconductor devices generally recognized in the industry. With the commercialization of 5G frequency bands such as N41, N77, and N78, the carrier frequency of wireless transmission signals is higher, and performance parameters such as the quality factor of surface acoustic wave filters will drop significantly due to working principles and other factors. Bulk acoustic wave filters have become the only choice for 5G frequency band filters. The establishment of 5G communication has promoted the exponential growth of the terminal bulk acoustic wave filter market.

[0003] Currently, the main resonance region of the mainstream cavity-type FBAR resonator consists of a sandwich structure of electrode - piezoelectric layer - electrode. This cavity-type FBAR resonator with such a structure has improved the carrier frequency to a certain extent, but parasitic phenomena will occur near the resonance peak or anti-resonance peak of the bulk acoustic wave resonator, still dragging down the performance of the overall device. Summary of the Invention

[0004] Aiming at the problems existing in the prior art, the present invention provides a single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layers and a preparation method thereof, solving the problems of parasitic resonance and large insertion loss existing in the existing single-crystal thin-film bulk acoustic wave resonators. The technical solution of the present invention is as follows:

[0005] In the first aspect, the present invention provides a single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layers, which sequentially includes a silicon substrate, a support layer, and a single-crystal piezoelectric thin-film layer from bottom to top. A cavity is formed between the silicon substrate, the support layer, and the single-crystal piezoelectric thin-film layer; an upper electrode layer and a lower electrode layer are respectively arranged on the upper and lower sides of the single-crystal piezoelectric thin-film layer, and the lower electrode layer is located in the cavity; an upper load layer and a lower load layer are respectively arranged at the upper and lower ends of the single-crystal piezoelectric thin-film layer. The upper load layer and the lower load layer respectively surround along the edges of the upper electrode layer and the lower electrode layer, and the upper load layer and the lower load layer are symmetrically distributed up and down with respect to the single-crystal piezoelectric thin-film layer.

[0006] Further, the support layer is made of silicon dioxide and has a thickness of 2 μm to 3.5 μm.

[0007] Further, the single-crystal piezoelectric thin-film layer is made of AlN and has a thickness of 500 nm to 4 μm.

[0008] Further, the materials of the upper electrode layer and the lower electrode layer are any one of Mo, Pt, Ti, and Au, and the thickness is 50 nm to 1 μm.

[0009] Further, the materials of the upper load layer and the lower load layer are any one of Mo, Pt, Ti, and Au, the thickness is 50 nm to 2 μm, and the width is 50 nm to 10 μm.

[0010] Further, the number of the upper load layer and the lower load layer is both one or more, and they form a polyhedral frame structure.

[0011] Further, when the number of the upper load layer and the lower load layer is more than one, the multiple polyhedral frame structures are arranged in a nested manner with one surrounding another, there is a certain distance between adjacent polyhedral frame structures, the outermost polyhedral frame structures are respectively arranged along the edges of the upper electrode layer and the lower electrode layer in a surrounding manner, and the other layer of polyhedral frame structures are respectively arranged on the upper electrode layer and the lower electrode layer.

[0012] Preferably, the polyhedral frame structure is a regular pentahedral frame structure.

[0013] In a second aspect, the present invention provides a method for manufacturing a single-crystal thin-film bulk acoustic resonator with optimized symmetric load layers, including the following steps:

[0014] Step S1: Use two silicon substrates, and deposit a single-crystal piezoelectric thin film layer on the first silicon substrate.

[0015] Step S2: Deposit a support layer on the single-crystal piezoelectric thin film of the epitaxial wafer obtained in step S1 and perform photolithographic patterning, so that the number of finally formed support layers is 2, and they are respectively distributed on both sides of the single-crystal piezoelectric thin film layer.

[0016] Step S3: Grow a lower electrode layer on the single-crystal piezoelectric thin film layer of the chip structure obtained in step S2.

[0017] Step S4: Sputter or evaporate a lower load layer on the single-crystal piezoelectric thin film layer of the chip structure obtained in step S3 and perform photolithographic patterning, so that the lower load layer is arranged along the edge of the lower electrode layer in a surrounding manner.

[0018] Step S5: Take the second silicon substrate, bond the chip structure obtained in step S4 to the second silicon substrate in a flip-chip manner, and remove the first silicon substrate to achieve film transfer.

[0019] Step S6: Sputter or evaporate an upper electrode layer on the single-crystal piezoelectric thin film layer of the chip structure obtained in step S5.

[0020] Step S7, sputter or evaporate a load layer on the single-crystal piezoelectric thin film of the chip structure obtained in step S6 and perform photolithographic patterning so that the upper load layer is arranged to surround along the edge of the upper electrode layer, and the preparation is completed.

[0021] Compared with the prior art, the technical effects of the present invention are as follows:

[0022] By adopting a symmetric load layer design, the present invention can effectively reduce the parasitic waveform of the FBAR resonator at the resonance peak position; in addition, the present invention is applicable to the processing technology of the single-crystal FBAR resonator for the bonding process, and further reduces the loss of the FBAR resonator on the basis of the single-crystal piezoelectric layer, which is beneficial to constructing a high-quality bulk acoustic wave filter with low insertion loss. Description of the Drawings

[0023] Figure 1 It is a schematic structural diagram of the epitaxial wafer obtained in step S1 in the preparation method of the specific embodiment of the present invention.

[0024] Figure 2 It is a schematic structural diagram of the chip structure obtained in step S2 in the preparation method of the specific embodiment of the present invention.

[0025] Figure 3 It is a schematic structural diagram of the chip structure obtained in step S3 in the preparation method of the specific embodiment of the present invention.

[0026] Figure 4 It is a schematic structural diagram of the chip structure obtained in step S4 in the preparation method of the specific embodiment of the present invention.

[0027] Figure 5 It is a schematic structural diagram of the chip structure obtained in step S5 in the preparation method of the specific embodiment of the present invention.

[0028] Figure 6 It is a schematic structural diagram of the single-crystal thin film bulk acoustic wave resonator with optimized symmetric load layer finally obtained by the present invention.

[0029] Figure 7 It is a top view of the single-crystal thin film bulk acoustic wave resonator optimized by a group of symmetric load layers of the present invention. The pentagonal part covered by the load layer is the electrode layer, which is represented in blank form.

[0030] Figure 8 It is a schematic structural diagram of the single-crystal thin film bulk acoustic wave resonator optimized by 2 groups of symmetric load layers of the present invention.

[0031] Figure 9 It is a top view of the single-crystal thin film bulk acoustic wave resonator optimized by 2 groups of symmetric load layers of the present invention.

[0032] Figure 10 It is a comparison diagram of the admittance curves of the resonator in Embodiment 1 and the resonator in Comparative Example 1 of the present invention, whereFigure 10-1 is the admittance curve of the resonator in Embodiment 1, Figure 10-2 is the admittance curve of the resonator in Comparative Example 1. Figure 11 is the admittance curve of the resonator in Embodiment 2 of the present invention (the dotted line represents 0 sets of load layers, the solid line represents only the upper load layer is provided, and the dashed line represents 2 sets of symmetric load layers).

[0033] Figures 1 to 8 Explanation of reference numerals: 101 single crystal piezoelectric thin film layer; 102 silicon substrate 1; 103 support layer; 104 lower electrode layer; 105 lower load layer; 106 upper electrode layer; 107 upper load layer; 108 silicon substrate 2. Detailed Description of the Invention

[0034] In the description of the present invention, it should be noted that for those not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. For reagents or instruments whose manufacturers are not specified, they are all conventional products that can be obtained through commercial purchase.

[0035] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments to help those skilled in the art have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention. The protection scope of the present invention includes but is not limited to the following embodiments. Any modification made to the details and forms of the technical solution of the present invention without departing from the spirit and scope of the present application falls within the protection scope of the present invention.

[0036] Embodiment 1

[0037] This embodiment provides a single crystal thin film bulk acoustic resonator with optimized symmetric load layers. As Figure 6 shown, it sequentially includes a silicon substrate 108, a support layer 103, and a single crystal piezoelectric thin film layer 101 in order from bottom to top. A cavity is formed between the silicon substrate 108, the support layer 103, and the single crystal piezoelectric thin film layer 101; an upper electrode layer 106 and a lower electrode layer 104 are respectively provided on the upper and lower sides of the single crystal piezoelectric thin film layer 101, and the lower electrode layer 104 is located in the cavity; an upper load layer 107 and a lower load layer 105 are respectively provided at the upper and lower ends of the single crystal piezoelectric thin film layer 101, and the upper load layer 107 and the lower load layer 105 are symmetrically distributed up and down with respect to the single crystal piezoelectric thin film layer 101.

[0038] As Figure 7As shown, in this embodiment, the upper load layer 107 and the lower load layer 105 are single and both have a regular pentahedron frame structure, and are respectively arranged around the edges of the upper electrode layer 106 and the lower electrode layer 104. The width of the upper load layer 107 and the lower load layer 105 is set to 1.25 μm. This width is obtained by analyzing the acoustic wave scattering in the resonator according to the simulation calculation results, and taking one-fourth of the acoustic wave wavelength for the lateral transmission as the width of the load layer, and the thickness is 150 nm.

[0039] More specifically, in this embodiment, the thickness of the silicon substrate is 575 μm. The support layer 103 is a silicon dioxide support layer with a thickness of 2 μm. The single-crystal piezoelectric thin film layer is made of AlN with a thickness of 2 μm. The upper electrode and the lower electrode are made of Mo with a thickness of 200 nm.

[0040] The resonator upper electrode layer 106, the single-crystal piezoelectric thin film layer 101, and the resonator lower electrode layer 104 together form a piezoelectric oscillation sandwich structure. By forming the sandwich structure, the performance loss introduced by the external circuit can be further reduced. At the same time, by symmetrically setting the upper and lower load layers, the parasitic characteristics of the resonator can be significantly reduced. The resonator of this embodiment can be better applied to frequency bands above 3 GHz.

[0041] The preparation method of the above resonator includes the following steps:

[0042] Step S1, use two silicon substrates. Pickle and perform organic cleaning on the first silicon substrate 102 to make the substrate surface clean, and then deposit a single-crystal piezoelectric thin film on the first silicon substrate; as Figure 1 shown.

[0043] Step S2, deposit a support layer on the single-crystal piezoelectric thin film of the epitaxial wafer obtained in Step S1 and perform photolithographic patterning to make the number of finally formed support layers 2, and they are respectively distributed on both sides of the single-crystal piezoelectric thin film; as Figure 2 shown.

[0044] Step S3, sputter or evaporate the resonator lower electrode 104 and the lower load layer 105 on the single-crystal piezoelectric thin film of the chip structure obtained in Step S2; as Figure 3 shown.

[0045] Step S4, sputter or evaporate the lower load layer on the single-crystal piezoelectric thin film of the chip structure obtained in Step S3 and perform photolithographic patterning to make it in the shape of a regular pentahedron; as Figure 4 shown.

[0046] Step S5, take the second silicon substrate, bond the chip structure obtained in Step S4 to the second silicon substrate in a flip-chip manner, transfer the single-crystal piezoelectric thin film layer 101, the lower electrode 104, and the lower load layer 105, and use mechanical thinning and chemical mechanical polishing methods to remove the first silicon substrate; asFigure 5 as shown

[0047] Step S6, sputter or evaporate an electrode 106 on the single-crystal piezoelectric thin film layer 101 of the chip structure obtained in Step S5;

[0048] Step S7, sputter or evaporate a load layer 107 on the single-crystal piezoelectric thin film layer 101 of the chip structure obtained in Step S6 and perform photolithographic patterning to make it a regular pentahedron, and perform electrical connection by evaporating metal to lead out the upper electrode, and the preparation is completed, as Figure 6 shown..

[0049] Specifically, in this specific embodiment, the method for growing the single-crystal piezoelectric thin film includes one or more combinations of PVD, MOCVD, PLD, and ALD. The method for growing the lower electrode of the resonator is magnetron sputtering, and the method for depositing the silicon dioxide dielectric layer is the plasma-enhanced chemical vapor deposition method PECVD.

[0050] Specifically, in the solution of this embodiment, the upper electrode of the second radio frequency coupling capacitor is any one of metals Mo, Pt, Ti, and Au, and the lower electrode of the second radio frequency coupling capacitor is any one of metals Mo, Pt, Ti, and Au.

[0051] The admittance curve of the resonator obtained in this embodiment is as Figure 10-1 shown, the resonance curve is smooth without parasitic peaks, and the quality factor is high.

[0052] Embodiment 2

[0053] This embodiment provides a single-crystal thin film bulk acoustic wave resonator with optimized symmetric load layers. The difference from Embodiment 1 is that the numbers of the upper load layer and the lower load layer are 3 respectively, and they are arranged in a nested manner of one surrounding one. The adjacent polyhedral frame structures are spaced 0.25 μm apart, and the innermost polyhedral frame structures are respectively arranged along the edges of the upper electrode layer and the lower electrode layer. The structural schematic diagrams are as Figure 8 and 9 shown.

[0054] The admittance curve of the resonator obtained in this embodiment is as Figure 11 shown. The dotted line represents 0 groups of load layers, the dashed line represents only 1 group of upper load layers, and the solid line represents 2 groups of symmetric load layers, proving that the resonance curves of multiple groups of load layers are smooth without parasitic peaks and the quality factor is high.

[0055] Comparative Example 1

[0056] This comparative example provides a radio frequency bulk acoustic wave resonator. The difference between this resonator and the resonator in Embodiment 1 is that it has no load layer structure, and the others are the same as the resonator in Embodiment 1. The admittance curves of this resonator and the resonator obtained in Embodiment 1 are measured. AsFigure 10 As shown above Figure 10-2 is the admittance curve of the bulk acoustic wave resonator of Comparative Example 1, and below Figure 10-1 is the admittance curve of the bulk acoustic wave resonator of Example 1. Since the present invention has a special symmetrically arranged load layer structure, which can significantly enhance the parasitic parameter suppression characteristics of the bulk acoustic wave filter, it can be seen from Figure 9 that the symmetrically distributed load layer effectively reduces the parasitic parameters.

[0057] In summary, in the present invention, by setting the load layer, the parasitic characteristics of the resonator can be significantly reduced. At the same time, by setting a symmetrically distributed first-order or multi-order complex layer array on both the upper and lower electrodes, the stray factors introduced by the load layer can be further balanced, so that a bulk acoustic wave resonator with a high quality factor and a smooth resonance curve can be obtained, solving the problem of parasitic peaks in the resonance waveform of traditional single-crystal thin-film bulk acoustic wave resonators. In addition, the present invention only needs to prepare a load layer with the same material on the upper electrode and the lower electrode, without the need to additionally prepare functional film layers or external capacitance resistors, reducing the preparation difficulty and thus the preparation cost.

[0058] The above-described embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.

Claims

1. A single crystal thin film bulk acoustic wave resonator with optimized symmetric load layer, characterized in that: It sequentially includes a silicon substrate, a support layer, and a single-crystal piezoelectric thin film layer in the order from bottom to top. A cavity is formed between the silicon substrate, the support layer, and the single-crystal piezoelectric thin film layer; an upper electrode layer and a lower electrode layer are respectively provided on the upper and lower sides of the single-crystal piezoelectric thin film layer, and the lower electrode layer is located in the cavity; an upper load layer and a lower load layer are respectively arranged at the upper and lower ends of the single-crystal piezoelectric thin film layer, the upper load layer and the lower load layer are respectively arranged to surround along the edges of the upper electrode layer and the lower electrode layer, and the upper load layer and the lower load layer are symmetrically distributed up and down with respect to the single-crystal piezoelectric thin film layer; The number of the upper load layer and the lower load layer is both one or more, and they are in a polyhedral frame structure; when the number of the upper load layer and the lower load layer is multiple, the multiple polyhedral frame structures are arranged in a nested manner of one surrounding another, and there is a certain distance between adjacent polyhedral frame structures. The outermost polyhedral frame structures are respectively arranged to surround along the edges of the upper electrode layer and the lower electrode layer, and the other layer polyhedral frame structures are respectively arranged on the upper electrode layer and the lower electrode layer.

2. The single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layer according to claim 1, wherein: The support layer is made of silicon dioxide and has a thickness of 2 μm to 3.5 μm.

3. A single crystal thin film bulk acoustic wave resonator with optimized symmetric load layer according to claim 1, characterized in that: The single-crystal piezoelectric thin film layer is made of AlN and has a thickness of 500 nm to 4 μm.

4. A single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layer according to claim 1, characterized in that: The materials of the upper electrode layer and the lower electrode layer are any one of Mo, Pt, Ti, and Au, and the thickness is 50 nm to 1 μm.

5. The single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layer according to claim 1, characterized in that: The materials of the upper load layer and the lower load layer are any one of Mo, Pt, Ti, and Au, the thickness is 50 nm to 2 μm, and the width is 50 nm to 10 μm.

6. A single-crystal thin-film bulk acoustic wave resonator with optimized symmetric load layer according to claim 1, characterized in that: The polyhedral frame structure is a regular pentahedron frame structure.

7. A preparation method of a single-crystal thin film bulk acoustic resonator with optimized symmetric load layers according to any one of claims 1 to 6, comprising the following steps: Step S1, using two silicon substrates, depositing a single-crystal piezoelectric thin film layer on the first silicon substrate; Step S2, depositing a support layer on the single-crystal piezoelectric thin film of the epitaxial wafer obtained in step S1 and performing photolithographic patterning treatment so that the finally formed number of support layers is 2 and they are respectively distributed on both sides of the single-crystal piezoelectric thin film layer; Step S3, growing a lower electrode layer on the single-crystal piezoelectric thin film layer of the chip structure obtained in step S2; Step S4, sputtering or evaporating a lower load layer on the single-crystal piezoelectric thin film layer of the chip structure obtained in step S3 and performing photolithographic patterning treatment so that the lower load layer is arranged to surround along the edge of the lower electrode layer; Step S5, taking the second silicon substrate, bonding the chip structure obtained in step S4 to the second silicon substrate in a flip-chip manner, and removing the first silicon substrate to achieve film transfer; Step S6, sputtering or evaporating an upper electrode layer on the single-crystal piezoelectric thin film layer of the chip structure obtained in step S5; Step S7, sputtering or evaporating an upper load layer on the single-crystal piezoelectric thin film of the chip structure obtained in step S6 and performing photolithographic patterning treatment so that the upper load layer is arranged to surround along the edge of the upper electrode layer, and the preparation is completed.

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