Reconfigurable Viterbi decoding system and decoding method thereof

Abstract

The present application relates to Viterbi decoding technology, and discloses a reconfigurable Viterbi decoding system and a decoding method thereof, which improves decoding efficiency and reduces power consumption while being compatible with decoding work of convolutional codes with different coding parameters. The system includes a branch metric unit, a path metric unit, a survivor path management unit, a traceback unit, a bit width control unit, and a state memory with a maximum bit width of M bits; the state memory is provided with N-bit byte enable, each byte enable controls the bit width of M / N bits of the state memory, and the state memory can reconfigure the current read / write bit width according to the N-bit byte enable and store the output result of the path metric unit and the output result of the survivor path management unit according to the current read / write bit width; the bit width control unit is used to output the N-bit byte enable matching the minimum read / write bit width of the convolutional code to be decoded to the state memory, wherein the minimum read / write bit width is obtained according to the sum of the path metric bit width and the survivor path bit width of the convolutional code to be decoded.

Description

Technical Field

[0001] The present application relates to a Viterbi decoding technology, and in particular to a reconfigurable Viterbi decoding technology. Background Art

[0002] In the navigation signal system, in order to improve the error correction performance of the navigation message, error correction control coding is generally used, that is, by introducing redundancy in the navigation message, the receiving end can recover the original signal within a certain error range (caused by noise, interference or fading) after receiving the signal, avoiding the re-receiving of the navigation message. According to the way of introducing redundancy or the different encoding methods, error control coding can be divided into block code / convolutional code, linear code / non-linear code, systematic code / non-systematic code, etc. Among them, the convolutional code, the code sequence after encoding is not only related to the information bits of the current code group, but also to the sequence of the adjacent code group, and has better performance than other codes.

[0003] Viterbi decoding, as an efficient convolutional code decoding method, is a maximum likelihood decoding algorithm proposed by Viterbi in 1967.

[0004] Traditional Viterbi decoders are often set for codes with specific constraint lengths, and decoding circuits with different code constraint lengths are not compatible. In addition, since traditional Viterbi decoders generally operate at a fixed frequency under a specific voltage, in order to adapt to different application scenarios, they generally use a voltage reduction method to reduce the frequency of the application to achieve low power consumption. However, this is limited by the frequency and voltage requirements of different IPs in the system, and the flexibility is not high. Summary of the invention

[0005] The purpose of the present application is to provide a reconfigurable Viterbi decoding system and a decoding method thereof, which can improve decoding efficiency and reduce power consumption while being compatible with decoding of convolutional codes with different coding parameters.

[0006] The present application discloses a reconfigurable Viterbi decoding system for processing a convolutional code to be decoded to obtain a decoding result, comprising a branch metric unit, a path metric unit, a survivor path management unit and a backtracking unit, and the system further comprises:

[0007] A state memory, wherein the maximum bit width of the state memory is M bits, the state memory is provided with an N-bit byte enable, each bit of the byte enable controls the M / N-bit bit width of the state memory, M>N>0, the state memory determines the current read / write bit width according to the N-bit byte enable reconfigurable, and stores the output result of the path metric unit and the output result of the surviving path management unit according to the current read / write bit width;

[0008] A bit width control unit is used to output an N-bit byte matching the minimum read / write bit width of the convolutional code to be decoded and enable it to the state memory, wherein the minimum read / write bit width is obtained according to the sum of the path metric bit width and the survivor path bit width of the convolutional code to be decoded.

[0009] In a preferred example, M=64, N=2, 4 or 8.

[0010] In a preferred embodiment, M=64, N=2;

[0011] The bit width control unit is further used for, when the minimum read / write bit width of the convolutional code to be decoded is 32 bits, outputting a 2-bit byte matching the minimum read / write bit width to enable the state memory, so that the current read / write bit width of the state memory is 32 bits, and when the minimum read / write bit width of the convolutional code to be decoded is 64 bits, outputting a 2-bit byte matching the minimum read / write bit width to enable the state memory, so that the current read / write bit width of the state memory is 64 bits.

[0012] In a preferred example, the bit width control unit includes a bit width control register and a bit width control circuit;

[0013] The bit width control register sends a control signal to the bit width control circuit according to the minimum read / write bit width, and the bit width control circuit generates and outputs an N-bit byte enable matching the minimum read / write bit width according to the control signal.

[0014] In a preferred example, the system further includes a data storage device for storing the convolutional code to be decoded and the decoding result.

[0015] The present application also discloses a decoding method based on a reconfigurable Viterbi decoding system, which is used to process a convolutional code to be decoded to obtain a decoding result. The system includes a branch metric unit, a path metric unit, a surviving path management unit and a backtracking unit. The system also includes a state memory, the maximum bit width of the state memory is M bits, and the state memory is provided with an N-bit byte enable, and each bit of the byte enable controls the bit width of the state memory of M / N bits, M>N>0;

[0016] The method comprises:

[0017] Outputting N-bit bytes matching the minimum read / write bit width of the convolutional code to be decoded and enabling them to the state memory according to the minimum read / write bit width of the convolutional code to be decoded, wherein the minimum read / write bit width is obtained according to the sum of the path metric bit width and the survivor path bit width of the convolutional code to be decoded;

[0018] The current read / write bit width of the state memory is reconfigurable according to the N-bit byte enable, and the output result of the path metric unit and the output result of the survivor path management unit are stored in the state memory according to the current read / write bit width.

[0019] The present application also discloses a decoding method based on a reconfigurable Viterbi decoding system, which is used to process a convolutional code to be decoded to obtain a decoding result. The system includes a branch metric unit, a path metric unit, a surviving path management unit and a backtracking unit. The reconfigurable Viterbi decoding system also includes a state memory and a configuration register. The maximum bit width of the state memory is M bits. The state memory is provided with an N-bit byte enable. Each bit of the byte enable controls the M / N bit bit width of the state memory, where M>N>0. The configuration register is used to store the working mode code and the parameters of the convolutional code to be decoded.

[0020] The method comprises:

[0021] Determine N-bit byte enable and read / write cycle control parameters matching the working mode code according to the working mode code and the convolutional code parameter to be decoded;

[0022] The current read / write bit width is reconfigurably enabled according to the N-bit byte, and the output result of the path metric unit and the output result of the surviving path management unit are stored in the state memory according to the current read / write bit width and the read / write cycle control parameter.

[0023] In a preferred example, the working mode code includes codes corresponding to a high performance mode and a low power consumption mode;

[0024] When the working mode code is a code corresponding to the high-performance mode, determining an N-bit byte enable matching the working mode code so that the current read / write bit width of the state memory is P*M / N bits;

[0025] When the working mode code is a code corresponding to the low performance mode, determining an N-bit byte enable matching the working mode code so that the current read and write bit width of the state memory is Q*M / N bits;

[0026] Among them, P is greater than Q.

[0027] In a preferred example, the N-bit byte enable and read / write cycle control parameters matching the working mode code are determined according to the working mode code and the convolutional code parameters to be decoded, so that the current read / write bit width of the state memory during reading is different from the current read / write bit width during writing.

[0028] The present application also discloses a reconfigurable Viterbi decoding system for processing a convolutional code to be decoded to obtain a decoding result. The system includes a branch metric unit, a path metric unit, a survivor path management unit and a backtracking unit. The system also includes:

[0029] A state memory, wherein the maximum bit width of the state memory is M bits, the state memory is provided with an N-bit byte enable, each bit of the byte enable controls the M / N bit bit width of the state memory, M>N>0, the state memory determines the current read / write bit width according to the N-bit byte enable reconfigurable, and stores the output result of the path metric unit and the output result of the surviving path management unit according to the current read / write bit width and the read / write cycle control parameter;

[0030] Configuration registers for storing working mode encoding and convolutional code parameters;

[0031] A read / write control unit is used to determine N-bit byte enable and read / write cycle control parameters matching the working mode code according to the working mode code and the convolutional code parameters to be decoded.

[0032] Compared with the prior art, the present invention has at least the following advantages and effects:

[0033] A state memory with a byte enable function is adopted, a bit width control unit is set, and the byte enable of the state memory is matched and configured through the bit width control unit according to different encoding parameters of the convolutional code to be decoded to reconstruct the current read and write bit width of the state memory. It is compatible with the decoding of convolutional codes with different encoding parameters and can improve the decoding efficiency and save power consumption to a certain extent.

[0034] Furthermore, by pre-storing the working mode code and convolution code parameters through the configuration register, and determining the byte enable and read / write cycle control parameters of the state memory matching the working mode code according to the working mode code and the convolution code parameters to be decoded through the read / write control unit, the adaptability adjustment of the decoding speed and power consumption can be realized for the convolution codes of different coding systems and different application scenarios without changing the system operating frequency, thereby improving the flexibility of the system. For example, for a navigation receiver, the working speed requirements for working in cold areas and warm areas are often different. The working mode of the decoding system working in cold areas can be configured as a low power mode, and the working mode of the decoding system working in warm areas can be configured as a high performance mode, so as to adapt to the power consumption requirements of different temperature areas.

[0035] In addition, one of the implementations of the present application can achieve rate matching and adjustable access between the data path and the memory by simply adding a very small control circuit between the operation logic and the memory, thereby being suitable for different application scenarios.

[0036] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the structure of a traditional Viterbi decoder.

[0038] Figure 2 It is a schematic diagram of the structure of a reconfigurable Viterbi decoding system according to the first embodiment of the present application.

[0039] Figure 3 is a circuit diagram of an example bit width control unit for a 2-bit byte enabled state memory according to the present application.

[0040] Figure 4 is a circuit diagram of an example bit width control unit for a 4-bit byte enabled state memory according to the present application.

[0041] Figure 5 It is a flowchart of a decoding method based on a reconfigurable Viterbi decoding system according to the second embodiment of the present application.

[0042] Figure 6 It is a flowchart of a decoding method based on a reconfigurable Viterbi decoding system according to the third embodiment of the present application.

[0043] Figure 7 This is a schematic diagram of the read and write cycles of two working modes according to an embodiment of the third implementation mode of the present application; wherein (a) is a schematic diagram of the read and write cycles of the high-performance mode, and (b) is a schematic diagram of the read and write cycles of the low-power mode.

[0044] Figure 8 is a schematic diagram of the structure of an example butterfly unit.

[0045] Fig. 9 It is a schematic diagram of the structure of an example reconfigurable Viterbi decoding system according to the fourth embodiment of the present application. DETAILED DESCRIPTION

[0046] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0047] Description of some concepts:

[0048] Convolutional code: Compared with linear block code, convolutional code makes full use of the correlation between several adjacent code elements for encoding, thereby achieving the purpose of improving the error correction capability of channel transmission.

[0049] Reconfigurable: Compared with dedicated integrated circuits, reconfigurable technology is a programmable technology that can change circuit functions as needed. At the same time, unlike software-programmable CPUs, it is generally believed that reconfigurable technology can be changed in hardware to achieve the purpose of increasing flexibility.

[0050] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0051] like Figure 1 As shown in the figure, the traditional Viterbi decoder mainly consists of five parts: branch metric unit, path metric unit, survivor path management unit, backtracking unit and control unit. Among them, for each set of observation bit data input, the branch metric unit will directly calculate the state metric value and send it to the path metric unit; the path metric unit adds the old path metric value to the corresponding newly generated state metric value, and after comparison, selects the smaller branch of the two path metric values ​​that reach the same state to update the path metric value, and in order to prevent overflow, each path metric result is normalized by subtracting the minimum value of the last path metric result, and the path metric unit stores and manages the current path information according to the calculation result; under the control of the control unit, the survivor path management unit compares all stored branch path metric values ​​and selects the minimum value of the branch path metric value; the backtracking unit calculates the decoding output according to the survivor path corresponding to the minimum value of the branch path metric value; each unit works in coordination under the control of the control unit.

[0052] The various implementations of the present application are an improvement on the traditional Viterbi decoder.

[0053] The first embodiment of the present application relates to a reconfigurable Viterbi decoding system for processing a convolutional code to be decoded to obtain a decoding result, and its structure is as follows: Figure 2 As shown, the system includes a branch metric unit, a path metric unit, a survivor path management unit, a backtracking unit, a state memory and a bit width control unit.

[0054] Specifically, the maximum bit width of the state memory is M bits, and the state memory is provided with N-bit byte enable (byte_en0~byte_enN-1), each byte enable controls the bit width of the state memory of M / N (M divided by N) bits, M>N>0, M and N are integers, and the state memory can determine the current read and write bit width according to the reconfigurable N-bit byte enable, and stores the output result of the path measurement unit and the output result of the surviving path management unit according to the current read and write bit width.

[0055] The bit width control unit is used to output an N-bit byte matching the minimum read / write bit width of the convolutional code to be decoded and enable it to the state memory, wherein the minimum read / write bit width is obtained by summing the path metric bit width and the surviving path bit width of the convolutional code to be decoded.

[0056] Wherein, M may be, for example but not limited to, equal to 64, 32, 16, etc. Optionally, when M is equal to 64, N may be equal to 2, 4, or 8. Optionally, when M is equal to 32, N may be equal to 2 or 4. Optionally, when M is equal to 16, N may be equal to 2.

[0057] In one embodiment, M=64, N=2, and the bit width control unit is further used for, when the minimum read / write bit width of the convolutional code to be decoded is 32 bits, outputting a 2-bit byte enable matching the minimum read / write bit width to the state memory, so that the current read / write bit width of the state memory is 32 bits, and M / N=32 at this time, and 1 bit of the 2-bit byte enable is valid; when the minimum read / write bit width of the convolutional code to be decoded is 64 bits, outputting a 2-bit byte enable matching the minimum read / write bit width to the state memory, so that the current read / write bit width of the state memory is 64 bits, and M / N=32 at this time, and 2 bits of the 2-bit byte enable are valid. In another embodiment, M=64, N=4, and the bit width control unit is further used for, when the minimum read / write bit width of the convolutional code to be decoded is 16 bits, outputting a 4-bit byte enable matching the minimum read / write bit width to the state memory, so that the current read / write bit width of the state memory is 16 bits, at this time M / N=16, and 1 bit in the 4-bit byte enable is valid; when the minimum read / write bit width of the convolutional code to be decoded is 32 bits, outputting a 4-bit byte enable matching the minimum read / write bit width to the state memory, so that the current read / write bit width of the state memory is 32 bits, at this time M / N=16 , 2 bits are valid in the 4-bit byte enable; when the minimum read / write bit width of the convolutional code to be decoded is 48 bits, a 4-bit byte enable matching the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 48 bits. At this time, M / N=16, and 3 bits are valid in the 4-bit byte enable; when the minimum read / write bit width of the convolutional code to be decoded is 64 bits, a 4-bit byte enable matching the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 64 bits. At this time, M / N=16, and 4 bits are valid in the 4-bit byte enable.In another embodiment, M=64, N=8, and the bit width control unit is further used for, when the minimum read / write bit width of the convolutional code to be decoded is 8 bits, outputting an 8-bit byte enable matching the minimum read / write bit width to the state memory, so that the current read / write bit width of the state memory is 8 bits, at this time M / N=8, and 1 bit in the 8-bit byte enable is valid; when the minimum read / write bit width of the convolutional code to be decoded is 16 bits, outputting an 8-bit byte enable matching the minimum read / write bit width to the state memory, so that the current read / write bit width of the state memory is 16 bits, in this case When M / N=8, 2 bits of the 8-bit byte enable are valid; when the minimum read / write bit width of the convolutional code to be decoded is 24 bits, an 8-bit byte enable matching the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 24 bits. At this time, M / N=8, 3 bits of the 8-bit byte enable are valid; when the minimum read / write bit width of the convolutional code to be decoded is 32 bits, an 8-bit byte enable matching the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 32 bits. At this time, M / N=8, 4 bits of the 8-bit byte enable are valid; when the minimum read / write bit width of the convolutional code to be decoded is 40 bits, an 8-bit byte enable matching the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 40 bits. At this time, M / N=8, and 5 bits of the 8-bit byte enable are valid; when the minimum read / write bit width of the convolutional code to be decoded is 48 bits, an 8-bit byte enable matching the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 48 bits. At this time, M / N=8, and the 8-bit byte enable is valid. 6 bits are valid; when the minimum read / write bit width of the convolutional code to be decoded is 56 bits, an 8-bit byte enabling that matches the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 56 bits. At this time, M / N=8, and 7 bits are valid in the 8-bit byte enabling; when the minimum read / write bit width of the convolutional code to be decoded is 64 bits, an 8-bit byte enabling that matches the minimum read / write bit width is output to the state memory, so that the current read / write bit width of the state memory is 64 bits. At this time, M / N=8, and 8 bits are valid in the 8-bit byte enabling.

[0058] For example, taking the (2, 1, 3) and (2, 1, 7) convolutional codes as examples, the constraint length of the (2, 1, 3) convolutional code is 3. According to the backtracking depth equal to 7 times the constraint length, it is 21, which can be expanded by 11 bits for path metric storage. The required read and write bit width is 32 bits. Similarly, the (2, 1, 7) convolutional code requires a read and write bit width of 64 bits. Then the decoding system can be designed to select a state memory with a maximum bit width of 64 bits, and configure N=2. The bit width control unit is used when the convolutional code to be decoded is When the product code is a (2, 1, 3) convolutional code, a 2-bit byte enable "10" or "01" matching the minimum read / write bit width is output to the state memory; when the convolutional code to be decoded is a (2, 1, 7) convolutional code, a 2-bit byte enable "11" matching the minimum read / write bit width is output to the state memory. In this way, the word width of the state memory can be flexibly configured according to different convolutional code parameters through the flexible application of the byte enable signal of the state memory, thereby achieving the purpose of making the same system compatible with convolutional codes of different constraint lengths.

[0059] Optionally, the bit width control unit includes a bit width control register and a bit width control circuit, the bit width control register sends a control signal to the bit width control circuit according to the minimum read and write bit width, and the bit width control circuit generates and outputs an N-bit byte enable matching the minimum read and write bit width according to the control signal.

[0060] For example, Figure 3 The circuit diagram of an example bit width control unit of a state memory for a 2-bit byte enable (byte_en0, byte_en1) is shown. The bit width register may include a configuration register (REG0). The bit width control circuit includes an inverter and two multiplexers. The specific logic control method is shown in Table 1 below, where the address signal A0 is generated by a survivor path management unit based on the configuration of register REG0.

[0061] Table 1

[0062] REG0 A0 byte_en0 byte_en1 1 × 1 1 0 1 0 1 0 0 1 0

[0063] like Figure 4The circuit diagram of an example bit width control unit of a state memory for a 4-bit byte enable (byte_en0, byte_en1, byte_en2, byte_en3) is shown. The bit width register may include two configuration registers (REG0, REG1). The bit width control circuit includes two NOT gate units, two AND gate units and six NOR gate units. The specific logic control method is shown in Table 2 below, where the address signals A0 and A1 are generated by the survivor path management unit based on the configuration of the registers REG0 and REG1. It should be noted that the details listed in the two example bit width control units are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0064] Table 2

[0065] REG0 REG1 A0 A1 byte_en0 byte_en1 byte_en3 byte_en4 1 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 X 1 1 0 0 1 0 0 X 1 1 0 0 1 0 1 X 0 0 1 1 1 0 1 X 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1

[0066] Optionally, the system also includes a data storage device for storing the convolutional code to be decoded and the decoding result.

[0067] The decoding system of this embodiment can be an improvement on the traditional Viterbi decoder, and the decoding system can also include a control unit for coordinating and controlling the branch metric unit, the path metric unit, the survivor path management unit, and the backtracking unit in the system. In one embodiment, the control unit is also used to control the reconstruction work between the state memory and the bit width control unit in the system. In another embodiment, the reconstruction work between the state memory and the bit width control unit is controlled by an external trigger, such as but not limited to a manual trigger.

[0068] The second embodiment of the present application relates to a decoding method based on a reconfigurable Viterbi decoding system, which is used to process a convolutional code to be decoded to obtain a decoding result. The system includes a branch metric unit, a path metric unit, a surviving path management unit, a backtracking unit and a state memory. The maximum bit width of the state memory is M bits. The state memory is provided with an N-bit byte enable. Each bit of the byte enable controls the bit width of the state memory of M / N bits, M>N>0, and M and N are integers; Figure 5 The decoding method comprises the following steps:

[0069] In step 501, an N-bit byte matching the minimum read / write bit width of the convolutional code to be decoded is output and enabled to the state memory, wherein the minimum read / write bit width is obtained by summing the path metric bit width and the survivor path bit width of the convolutional code to be decoded.

[0070] Then, the process proceeds to step 502, where the current read / write bit width of the state memory is determined based on the N-bit byte enabling reconfiguration, and the output result of the path metric unit and the output result of the surviving path management unit are stored in the state memory based on the current read / write bit width.

[0071] Optionally, the decoding system further includes a data storage device for storing the convolutional code to be decoded and the decoding result.

[0072] The first embodiment is a system embodiment corresponding to the present embodiment. The technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.

[0073] The third embodiment of the present application relates to a decoding method based on a reconfigurable Viterbi decoding system, which is used to process a convolutional code to be decoded to obtain a decoding result. The system includes a branch metric unit, a path metric unit, a surviving path management unit, a traceback unit, a state memory and a configuration register, wherein the maximum bit width of the state memory is M bits, the state memory is provided with an N-bit byte enable, and each bit byte enable controls the M / N bit bit width of the state memory, M>N>0, M and N are integers, and the configuration register is used to store the working mode code and the parameters of the convolutional code to be decoded; Figure 6 The decoding method comprises the following steps:

[0074] In step 601, N-bit byte enable and read / write cycle control parameters matching the working mode code are determined according to the working mode code and the parameters of the convolutional code to be decoded.

[0075] Afterwards, enter step 602, determine the current read / write bit width based on the N-bit byte enable reconfigurable, and store the output result of the path metric unit and the output result of the surviving path management unit in the state memory based on the current read / write bit width and read / write cycle control parameters.

[0076] Optionally, the working mode code includes codes corresponding to the high-performance mode and the low-power mode. Specifically, when the working mode code is a code corresponding to the high-performance mode, it is determined that the N-bit byte enable that matches the working mode code makes the current read and write bit width of the state memory P*M / N bits; when the working mode code is a code corresponding to the low-performance mode, it is determined that the N-bit byte enable that matches the working mode code makes the current read and write bit width of the state memory Q*M / N bits, where P>Q>0, and P and Q are positive integers. Optionally, in step 601, "determining the N-bit byte enable and read-write cycle control parameters that match the working mode code according to the working mode code and the convolutional code parameters to be decoded" can make the current read and write bit width of the state memory different when reading and when writing.

[0077] Optionally, in step 601, "determining N-bit byte enable and read / write cycle control parameters that match the working mode code according to the working mode code and the convolutional code parameters to be decoded" includes determining N-bit byte enable that matches the working mode code according to the working mode code and determining the read / write cycle control parameters according to the convolutional code parameters to be decoded, and also includes determining N-bit byte enable that matches the working mode code according to the working mode code and the convolutional code parameters to be decoded and determining the read / write cycle control parameters according to the working mode code and the convolutional code parameters to be decoded.

[0078] Optionally, the determination of the N-bit byte enable in step 601 can be implemented by controlling the bit width control unit of the embodiment of the first embodiment. Wherein, M can be, for example but not limited to, equal to 64, 32, 16, etc. Optionally, when M is equal to 64, N can be equal to 2, 4 or 8. Optionally, when M is equal to 32, N can be equal to 2 or 4. Optionally, when M is equal to 16, N can be equal to 2.

[0079] In one embodiment, P=N=2Q=2, using Figure 3 The bit width control unit shown in the figure configures REG0=1 in high-performance mode and REG0=0 in low-power mode. Based on the configuration of register REG0=0, the survivor path management unit generates the address signal A0 shown in Table 3 below.

[0080] Table 3

[0081] REG0 A0 byte_en0 byte_en1 0 1 0 1 0 0 1 0

[0082] In another embodiment, P=N=2Q=4, using Figure 4 The bit width control unit shown in the figure configures REG0=0 and REG1=0 in high-performance mode, and generates the address signal A0A1 shown in Table 4 based on the configuration of register REG0 through the survivor path management unit, wherein A0A1 is in accordance with Table 4; configures REG0=0 and REG1=0 in low-power mode, and generates the address signal shown in Table 5 based on the configuration of register REG0 through the survivor path management unit.

[0083] Table 4

[0084] REG0 REG1 A0 A1 byte_en0 byte_en1 byte_en3 byte_en4 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1

[0085] Table 5

[0086]

[0087]

[0088] Optionally, the determination of the read / write cycle control parameters in step 601 can be implemented by controlling a read / write cycle control unit. In one embodiment, the read / write cycle control unit includes a configurable register and a configurable counter, and the configurable counter is configured to be quaternary or octal through the configurable register to control the read / write cycle control parameters, such as Figure 7 (a) shows a schematic diagram of the read and write cycle in the high-performance mode. In this mode, the counter in the read and write cycle control unit can be configured as a quaternary counter. According to the base number of the counter, the 000-001 cycle of the counter is set as the read cycle, and the 010-011 cycle of the counter is set as the write cycle. Figure 7 (b) shows a schematic diagram of the read and write cycle in low power consumption mode. In this mode, the counter in the read and write cycle control unit can be configured as an octal counter. According to the base number of the counter, the 000 to 011 cycle of the counter is set as the read cycle, and the 100 to 111 cycle of the counter is set as the write cycle.

[0089] For example, taking the (2, 1, 7) convolutional code as an example, its minimum read and write bit width is 64 bits, then according to a butterfly unit (such as Figure 8 As shown), two input states, a total of 128 bits of data, 2 cycles to read, two output states, a total of 128 bits, 2 cycles to write. The decoding system can be set to use a state memory with a maximum bit width of 64 bits with N=2, a 2-bit byte enable matching the high-performance mode is "11", and the read and write cycle control parameters can be, for example, Figure 7 (a); the 2-bit byte enable matching the low power mode is "01" or "10", and the read and write cycle control parameters can be, for example, Figure 7 (b) as shown.

[0090] Optionally, the system also includes a data storage device for storing the convolutional code to be decoded and the decoding result.

[0091] The fourth embodiment of the present application relates to a reconfigurable Viterbi decoding system, which is used to process a convolutional code to be decoded to obtain a decoding result, and the system includes a branch metric unit, a path metric unit, a survivor path management unit, a backtracking unit, a state memory, a configuration register, and a read-write control unit;

[0092] Among them, the maximum bit width of the state memory is M bits, the state memory is provided with N-bit byte enable, each byte enable controls the M / N bit width of the state memory, M>N>0, the state memory can reconfigure the current read and write bit width according to the N-bit byte enable, and stores the output result of the path metric unit and the output result of the surviving path management unit according to the current read and write bit width and the read and write cycle control parameters; the configuration register is used to store the working mode code and the convolution code parameters; the read and write control unit is used to determine the N-bit byte enable and read and write cycle control parameters matching the working mode code according to the working mode code and the convolution code parameters to be decoded.

[0093] Among them, "determining the N-bit byte enable and read-write cycle control parameters matching the working mode code according to the working mode code and the convolutional code parameters to be decoded" includes determining the N-bit byte enable matching the working mode code according to the working mode code and determining the read-write cycle control parameters according to the convolutional code parameters to be decoded, and also includes determining the N-bit byte enable matching the working mode code according to the working mode code and the convolutional code parameters to be decoded and determining the read-write cycle control parameters according to the working mode code and the convolutional code parameters to be decoded.

[0094] Optionally, the system also includes a data storage device for storing the convolutional code to be decoded and the decoding result.

[0095] The decoding system of this embodiment can be an improvement on the traditional Viterbi decoder, and the decoding system can also include a control unit for coordinating and controlling the branch metric unit, the path metric unit, the surviving path management unit and the backtracking unit in the system. In one embodiment, the control unit is also used to control the reconstruction work between the state memory, the configuration register and the read-write control unit in the system. In another embodiment, the reconstruction work between the state memory, the configuration register and the read-write controller is controlled by an external trigger, such as but not limited to a manual trigger.

[0096] like Fig. 9 The structure diagram of a reconfigurable Viterbi decoding system according to an example of the present embodiment is shown, wherein the register outputs the working mode code and the parameters of the convolutional code to be decoded to the read-write control unit based on an external trigger, and the read-write control unit determines the N-bit byte enable and read-write cycle control parameters matching the working mode code according to the working mode code and the parameters of the convolutional code to be decoded, and then sends the corresponding read enable signal, address signal, and byte enable signal to the state memory in the read cycle, and sends the corresponding write enable signal, address signal, and byte enable signal to the state memory in the write cycle, so as to control the state memory to store the output result of the path metric unit and the output result of the surviving path management unit. It should be noted that the details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0097] The third implementation manner is a method implementation manner corresponding to the present implementation manner. The technical details in the third implementation manner can be applied to the present implementation manner, and the technical details in the present implementation manner can also be applied to the third implementation manner.

[0098] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the element. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0099] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A reconfigurable Viterbi decoding system for processing a convolutional code to be decoded to obtain a decoding result, comprising a branch metric unit, a path metric unit, a survivor path management unit and a backtracking unit, characterized in that: The system further comprises: A state memory, wherein the maximum bit width of the state memory is M bits, the state memory is provided with an N-bit byte enable, each bit of the byte enable controls the M / N-bit bit width of the state memory, M>N>0, the state memory determines the current read / write bit width according to the N-bit byte enable reconfigurable, and stores the output result of the path metric unit and the output result of the surviving path management unit according to the current read / write bit width; A bit width control unit is used to output an N-bit byte matching the minimum read / write bit width of the convolutional code to be decoded and enable it to the state memory, wherein the minimum read / write bit width is obtained according to the sum of the path metric bit width and the survivor path bit width of the convolutional code to be decoded.

2. The reconfigurable Viterbi decoding system according to claim 1, wherein: M=64, N=2, 4 or 8.

3. The reconfigurable Viterbi decoding system according to claim 2, wherein: M=64, N=2; The bit width control unit is further used for, when the minimum read / write bit width of the convolutional code to be decoded is 32 bits, outputting a 2-bit byte matching the minimum read / write bit width to enable the state memory, so that the current read / write bit width of the state memory is 32 bits, and when the minimum read / write bit width of the convolutional code to be decoded is 64 bits, outputting a 2-bit byte matching the minimum read / write bit width to enable the state memory, so that the current read / write bit width of the state memory is 64 bits.

4. The reconfigurable Viterbi decoding system according to claim 1, wherein: The bit width control unit includes a bit width control register and a bit width control circuit; The bit width control register sends a control signal to the bit width control circuit according to the minimum read / write bit width, and the bit width control circuit generates and outputs an N-bit byte enable matching the minimum read / write bit width according to the control signal.

5. The reconfigurable Viterbi decoding system according to claim 1, wherein: The system also includes a data storage device for storing the convolutional code to be decoded and the decoding result.

6. A decoding method based on a reconfigurable Viterbi decoding system, used for processing a convolutional code to be decoded to obtain a decoding result, the system comprising a branch metric unit, a path metric unit, a survivor path management unit and a backtracking unit, characterized in that: The system further comprises a state memory, wherein the maximum bit width of the state memory is M bits, and the state memory is provided with N-bit byte enable, and each bit byte enable controls the bit width of the state memory of M / N bits, M>N>0; The method comprises: Outputting N-bit bytes matching the minimum read / write bit width of the convolutional code to be decoded and enabling them to the state memory according to the minimum read / write bit width of the convolutional code to be decoded, wherein the minimum read / write bit width is obtained according to the sum of the path metric bit width and the survivor path bit width of the convolutional code to be decoded; The current read / write bit width of the state memory is reconfigurable according to the N-bit byte enable, and the output result of the path metric unit and the output result of the survivor path management unit are stored in the state memory according to the current read / write bit width.

7. A decoding method based on a reconfigurable Viterbi decoding system, for processing a convolutional code to be decoded to obtain a decoding result, the system comprising a branch metric unit, a path metric unit, a survivor path management unit and a backtracking unit, characterized in that: The reconfigurable Viterbi decoding system also includes a state memory and a configuration register, wherein the maximum bit width of the state memory is M bits, the state memory is provided with an N-bit byte enable, each bit of the byte enable controls the M / N-bit bit width of the state memory, M>N>0, and the configuration register is used to store the working mode code and the parameters of the convolutional code to be decoded; The method comprises: Determine N-bit byte enable and read / write cycle control parameters matching the working mode code according to the working mode code and the convolutional code parameter to be decoded; Determine the current read / write bit width according to the N-bit byte enabling reconfiguration, and store the output result of the path metric unit and the output result of the surviving path management unit in the state memory according to the current read / write bit width and the read / write cycle control parameter; Wherein, the working mode code includes codes corresponding to a high performance mode and a low power consumption mode; When the working mode code is a code corresponding to the high-performance mode, determining an N-bit byte enable matching the working mode code so that the current read / write bit width of the state memory is P*M / N bits; When the working mode code is a code corresponding to the low power consumption mode, determining that an N-bit byte that matches the working mode code is enabled so that the current read / write bit width of the state memory is Q*M / N bits; Among them, P is greater than Q; Furthermore, the N-bit byte enable and read / write cycle control parameters matching the working mode code are determined according to the working mode code and the convolutional code parameters to be decoded, so that the current read / write bit width of the state memory during reading is different from the current read / write bit width during writing.

8. A reconfigurable Viterbi decoding system for processing a convolutional code to be decoded to obtain a decoding result, the system comprising a branch metric unit, a path metric unit, a survivor path management unit and a backtracking unit, characterized in that: The system further comprises: A state memory, wherein the maximum bit width of the state memory is M bits, the state memory is provided with an N-bit byte enable, each bit of the byte enable controls the M / N bit bit width of the state memory, M>N>0, the state memory determines the current read / write bit width according to the N-bit byte enable reconfigurable, and stores the output result of the path metric unit and the output result of the surviving path management unit according to the current read / write bit width and the read / write cycle control parameter; Configuration registers for storing working mode encoding and convolutional code parameters; A read / write control unit, used to determine N-bit byte enable and read / write cycle control parameters matching the working mode code according to the working mode code and the convolutional code parameters to be decoded; Wherein, the working mode code includes codes corresponding to a high performance mode and a low power consumption mode; When the working mode code is a code corresponding to the high-performance mode, determining an N-bit byte enable matching the working mode code so that the current read / write bit width of the state memory is P*M / N bits; When the working mode code is a code corresponding to the low power consumption mode, determining that an N-bit byte that matches the working mode code is enabled so that the current read / write bit width of the state memory is Q*M / N bits; Among them, P is greater than Q; Furthermore, the N-bit byte enable and read / write cycle control parameters matching the working mode code are determined according to the working mode code and the convolutional code parameters to be decoded, so that the current read / write bit width of the state memory during reading is different from the current read / write bit width during writing.

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