Active pen

Abstract

The present invention provides an active pen which prevents delay in reception of uplink signals. The active pen (2) includes: a tip electrode (21) and a ring electrode (22) disposed at mutually different positions; a transmission circuit which transmits a downlink signal (DS) by supplying a change to the tip electrode (21) using a booster circuit; a reception circuit which detects an uplink signal (US) using the ring electrode (22); and a blocking filter (26) which blocks a change in potential of the tip electrode (21) from affecting a potential of the uplink signal (US) detected by the reception circuit.

Description

Technical Field

[0001] This invention relates to an active pen, and more particularly to an active pen for both sending and receiving. Background Technology

[0002] An active pen is known to be configured to receive uplink signals transmitted by a sensor controller, and on the other hand, to transmit downlink signals to the sensor controller. An example of such an active pen is disclosed in Patent Document 1.

[0003] Patent Document 1 discloses various active pens, among which a dual-mode stylus is an active pen corresponding to both bidirectional communication (i.e., a first communication method) and unidirectional communication from the active pen to the sensor controller (i.e., a second communication method). The dual-mode stylus is configured such that if an uplink signal is received, it operates using the first communication method; if a pen touch operation is detected when no uplink signal is received, it operates using the second communication method.

[0004] Examples of communication methods for an active pen are disclosed in each of Patent Documents 2 to 5.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent No. 6059410

[0008] Patent Document 2: International Publication No. 2017 / 029836

[0009] Patent Document 3: International Publication No. 2015 / 111159

[0010] Patent Document 4: US Patent No. 8,536,471

[0011] Patent Document 5: U.S. Patent Application Publication No. 2012-0105362 Summary of the Invention

[0012] The problem that the invention aims to solve

[0013] The dual-mode stylus described in Patent Document 1 is configured to perform uplink signal reception and downlink signal transmission by time division. However, if transmission and reception are performed by time division in this way, uplink signals cannot be received during the downlink signal transmission period (e.g., a period of approximately 4 ms). As a result, uplink signal reception is delayed, and the start of operation under the first communication method is sometimes delayed, thus requiring improvement.

[0014] Therefore, one of the objectives of this invention is to provide an active pen that can prevent delays in the reception of uplink signals.

[0015] Methods for solving problems

[0016] The active pen on the first side of the present invention includes: first and second electrodes disposed at different positions; a transmitting circuit that transmits a downlink signal by providing a change to the first electrode using a boost circuit; a receiving circuit that uses the second electrode to detect an uplink signal; and a blocking filter that prevents the change in the potential of the first electrode from affecting the potential of the uplink signal detected by the receiving circuit.

[0017] The active pen of the second side of the present invention includes: a first operating mode, which performs processing to detect an uplink signal arriving at the second electrode while a downlink signal is being transmitted from the first electrode; and a second operating mode, which performs time division of the transmission of the downlink signal from the first electrode and the detection of the uplink signal arriving at the second electrode, wherein if the uplink signal is detected during operation in the first operating mode, the active pen switches to the second operating mode.

[0018] Invention Effects

[0019] According to a first aspect of the invention, the active pen can simultaneously receive uplink signals and transmit downlink signals, rather than through time division. Therefore, delays in receiving uplink signals can be prevented.

[0020] According to a second aspect of the invention, an active pen that is unaware of the uplink signal transmission timing of the sensor controller before the sensor controller is detected can simultaneously receive uplink signals and transmit downlink signals. On the other hand, an active pen that is unaware of the uplink signal transmission timing of the sensor controller once the uplink signal is detected can perform uplink signal reception and downlink signal transmission by time division. Therefore, it is possible to prevent delays in uplink signal reception and to detect uplink signals with low noise once they are detected. Attached Figure Description

[0021] Figure 1 This is a diagram showing the structure of the position detection system 1 according to an embodiment of the present invention.

[0022] Figure 2 yes Figure 1 The state transition diagram of integrated circuit 25 is shown.

[0023] Figure 3This is a diagram illustrating the operation of the active pen 2 and the sensor controller 31, which is a sensor controller 31-1 corresponding to the first communication method.

[0024] Figure 4 This is a diagram illustrating the operation of the active pen 2 and the sensor controller 31, which is a sensor controller 31-2 corresponding to the second communication method.

[0025] Figure 5 It is shown schematically. Figure 1 The diagram shows the structure within the active pen 2.

[0026] Figure 6 It is shown Figure 5 The diagram shows the structure of the first example of the blocking filter 26, namely the blocking filter 26a.

[0027] Figure 7 It shows the use Figure 6 The diagram shows the results of the simulation of each signal based on the structure.

[0028] Figure 8 This diagram illustrates the structure of a receiver circuit provided within integrated circuit 25 for receiving the uplink signal US1 by extracting only the edge signal formed from the edge of the uplink signal US1.

[0029] Figure 9 It is shown by Figure 8 The diagram shows an example of the output signal FO generated by the receiving circuit.

[0030] Figure 10 It is shown Figure 5 The diagram shows the structure of the second example of the blocking filter 26, namely the blocking filter 26b.

[0031] Figure 11 It shows the use Figure 10 The diagram shows the results of the simulation of each signal based on the structure.

[0032] Figure 12 It shows the use Figure 10 The diagram shows the results of the simulation of each signal based on the structure.

[0033] Figure 13 It is shown Figure 5 The diagram shows the structure of the third example of the blocking filter 26, namely the blocking filter 26c.

[0034] Figure 14 It shows the use Figure 13 The diagram shows the results of the simulation of each signal based on the structure.

[0035] Figure 15 It is shown Figure 5 The diagram shows the structure of the fourth example of the blocking filter 26, namely the blocking filter 26d.

[0036] Figure 16 It shows the use Figure 15 The diagram shows the results of the simulation of each signal based on the structure.

[0037] Figure 17 It is shown Figure 5 The diagram shows the structure of the fifth example of the blocking filter 26, namely the blocking filter 26e. Detailed Implementation

[0038] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a diagram illustrating the structure of a position detection system 1 according to an embodiment of the present invention. As shown in the diagram, the position detection system 1 is configured to include an active pen 2 and a position detection device, i.e., an electronic device 3, for detecting the active pen 2. Examples of the electronic device 3 include a tablet computer and a device equipped with a digitizer.

[0040] The electronic device 3 has a touch surface 3a, a group of sensor electrodes 30 disposed directly below the touch surface 3a, a sensor controller 31 connected to the sensor electrode group 30, and a host processor 32 that controls the various parts of the sensor controller 31. The sensor controller 31 is an integrated circuit that communicates with the active pen 2 via the sensor electrode group 30, derives the position of the active pen 2 within the touch surface 3a, acquires data from the active pen 2, and supplies the derived position and acquired data to the host processor 32 each time. The host processor 32 is the central processing unit of the electronic device 3, configured to execute various programs including drawing applications. The drawing application is a program that generates digital ink based on the position and data supplied from the sensor controller 31, stores it in the memory within the electronic device 3, and displays it on a display.

[0041] When the active pen 2 approaches the touch surface 3a, an electrostatic capacitance CX is generated between the active pen 2 and the sensor electrode group 30. The sensor controller 31 is configured to exchange charges (electrostatic coupling) with the active pen 2 through this electrostatic capacitance CX, thereby enabling communication with the active pen 2.

[0042] The active pen 2 is an active electrostatic stylus (dual stylus) corresponding to both bidirectional communication (i.e., the first communication method) and unidirectional communication from the active pen 2 to the sensor controller 31 (i.e., the second communication method). The first communication method is, for example, the communication method described in Patent Document 2 (AES2.0 mode), and the second communication method is, for example, the communication method described in Patent Document 3 (AES1.0 mode), the communication method described in Patent Document 4, or the communication method described in Patent Document 5.

[0043] Hereinafter, the signal transmitted from the sensor controller 31 to the active pen 2 will be referred to as the uplink signal US, and the signal transmitted from the active pen 2 to the sensor controller 31 will be referred to as the downlink signal DS. The uplink signal US consists of a pulse wave (rectangular wave) formed by spreading each transmitted bit using a chip string (spreading code) of a specified chip length. The chip length of the uplink signal US1 (= the pulse period of the uplink signal US1) is, for example, 1 μsec or 2 μsec, and the edge duration (rise or fall) is, for example, 10 nsec. In the case of AES 2.0, the pulse period of the Manchester-coded pulse wave is 2 μsec. On the other hand, the downlink signal DS consists of a pulse wave (rectangular wave) or a signal based on a sine wave (including a sine wave signal of a specified frequency and a signal modulated from that sine wave signal). Details regarding the downlink signal DS will be described later.

[0044] like Figure 1 As shown, the active pen 2 is configured with a core 20, a pen tip electrode 21 (first electrode), a ring electrode 22 (second electrode), a pressure sensor 23, a battery 24, an integrated circuit 25, and a blocking filter 26. The core 20 is a component that forms the pen shaft of the active pen 2. The top end of the core 20 forms the pen tip of the active pen 2, and the end abuts against the pressure sensor 23. The pen tip electrode 21 and the ring electrode 22 are conductors disposed at different positions. The pen tip electrode 21 is disposed at the pen tip of the active pen 2, and the ring electrode 22 is disposed in a position closer to the center of the active pen 2 than the pen tip electrode 21, surrounding the core 20.

[0045] Pressure sensor 23 is a sensor that detects the pressure applied to the top of the core 20. The pressure detected by pressure sensor 23 is supplied to integrated circuit 25 as the pen pressure value. Battery 24 provides the power required for the operation of integrated circuit 25.

[0046] Integrated circuit 25 is an integrated circuit composed of various circuits including a boost circuit, a transmitting circuit, a receiving circuit, and a processing circuit. The transmitting circuit is connected to the pen tip electrode 21 and the ring electrode 22, and functions to transmit the downlink signal DS by providing a change to the pen tip electrode 21 or the ring electrode 22 through the boost circuit. The receiving circuit is connected to the ring electrode 22, and functions to receive the uplink signal US by detecting the uplink signal US through the ring electrode 22. The processing circuit generates the downlink signal DS and transmits the generated downlink signal DS through the transmitting circuit. In the case of the first communication method, the generation of the downlink signal DS is based on the uplink signal US received by the receiving circuit.

[0047] Blocking filter 26 is a filter circuit inserted between ring electrode 22 and integrated circuit 25. The detailed structure of blocking filter 26 will be described later, but it is a circuit designed to enable simultaneous detection of the uplink signal US using ring electrode 22 and transmission of the downlink signal DS from pen tip electrode 21.

[0048] In detail, the potential rise caused by the boost circuit used to transmit the downlink signal DS can reach 18-20V. Therefore, the potential change of the pen tip electrode 21 accompanying the transmission of the downlink signal DS will also affect the receiving circuit. As a result, the potential of the uplink signal US detected by the receiving circuit will overlap with that of the downlink signal DS, making it difficult to detect the uplink signal US simultaneously with the transmission of the downlink signal DS. When the active pen 2 is in a hovering state and the ring electrode 22 is far from the sensor electrode group 30, the received strength of the uplink signal US decreases, making the detection of the uplink signal US even more difficult. The blocking filter 26 functions to prevent the potential change of the pen tip electrode 21 accompanying the transmission of the downlink signal DS from affecting the potential of the uplink signal US detected by the receiving circuit in the integrated circuit 25, thereby enabling the simultaneous detection of the uplink signal US using the ring electrode 22 and the transmission of the downlink signal DS from the pen tip electrode 21.

[0049] Figure 2 This is a state transition diagram of integrated circuit 25. As shown in the diagram, integrated circuit 25 is configured to operate in any of the following modes: discovery mode (first operation mode), first mode (second operation mode), and second mode.

[0050] The discovery mode is the operating mode of the integrated circuit 25 when it has not yet detected the electronic device 3. The integrated circuit 25 is configured to enter the discovery mode first when power is supplied. In addition, the first and second modes are the operating modes of the integrated circuit 25 for communicating with the sensor controller 31 corresponding to the first and second communication methods, respectively.

[0051] In the following description, the uplink signal US described in the first communication method will sometimes be referred to as uplink signal US1, the signal transmitted from the pen tip electrode 21 in the downlink signal DS used in the first communication method will be referred to as downlink signal DS1a, and the signal transmitted from the ring electrode 22 will be referred to as downlink signal DS1b. Additionally, the signal transmitted from the pen tip electrode 21 in the downlink signal DS used in the second communication method will sometimes be referred to as downlink signal DS2a, and the signal transmitted from the ring electrode 22 will be referred to as downlink signal DS2b.

[0052] The integrated circuit 25, which enters the discovery mode, uses the ring electrode 22 to detect the uplink signal US1 and transmits the downlink signal DS2a from the pen tip electrode 21 (step S1). The detection and transmission are not performed by time division, but are executed simultaneously.

[0053] In step S1, the integrated circuit 25, which detects the uplink signal US1, enters the first mode (step S2) and begins communication based on the first communication method. Specifically, firstly, the transmission and reception schedules of the uplink signal US1 and downlink signals DS1a and DS1b are obtained based on the reception timing of the detected uplink signal US1. Then, the integrated circuit 25 first transmits the downlink signals DS1a and DS1b according to the transmission and reception schedule (step S10). If the reception timing of the uplink signal US1 arrives (step S11), the detection action of the uplink signal US1 is executed (step S12). The transmission in step S10 and the detection action in step S12 are executed through time division.

[0054] Here, the uplink signal US1 is a signal modulated by an instruction representing a command relative to the active pen 2. Additionally, the downlink signal DS1a is a signal comprising, for example, an unmodulated pulse wave or sine wave position signal and a data signal modulated by the data possessed by the active pen 2.

[0055] The position signal is used by the sensor controller 31 to determine the position of the pen tip of the active pen 2. On the other hand, the data signal is used by the sensor controller 31 to acquire various data from the active pen 2. Regarding the data signal, the integrated circuit 25 is configured to acquire data transmitted via the data signal according to the instructions contained in the uplink signal US1 received from the sensor controller 31. In addition to the aforementioned pen pressure value, the acquired data may also include a pen ID stored in the built-in memory of the integrated circuit 25, switch information indicating the on / off state of a switch provided on the surface of the active pen 2, etc.

[0056] The downlink signal DS1b consists only of an unmodulated pulse wave or sine wave position signal. However, the pulse wave or sine wave constituting the downlink signal DS1b has a different frequency (pulse period) than the pulse wave or sine wave constituting the downlink signal DS1a. This is so that the sensor controller 31 can distinguish and receive the downlink signals DS1a and DS1b. The sensor controller 31 derives the position of the ring electrode 22 based on the downlink signal DS1b and derives the distance between it and the position of the pen tip derived based on the position signal within the downlink signal DS1a, thereby obtaining the tilt of the active pen 2.

[0057] If the uplink signal US1 is detected as a result of the uplink signal US1 detection action performed in step S12, the integrated circuit 25 maintains the first mode and returns to step S10 to transmit downlink signals DS1a and DS1b (step S13). On the other hand, if the uplink signal US1 is not detected, the integrated circuit 25 exits the first mode and returns to the discovery mode to continue processing (step S14). It should be noted that the integrated circuit 25 may also exit the first mode and return to the discovery mode if the uplink signal US1 is not detected for a predetermined number of consecutive times.

[0058] During the discovery mode, integrated circuit 25 also monitors the pen pressure value. If, as a result, the pen pressure value is detected to be greater than 0, integrated circuit 25 determines that the tip of the active pen 2 has contacted the touch surface 3a (pen touch has occurred) and enters the second mode (step S3), and begins communication based on the second communication method.

[0059] Specifically, integrated circuit 25 first increments the variable Count by 1 each time (step S21) while repeatedly transmitting downlink signals DS2a and DS2b (step S20).

[0060] Here, downlink signals DS2a and DS2b are the same as downlink signals DS1a and DS1b. Based on downlink signals DS2a and DS2b, the sensor controller 31 obtains the position and tilt of the active pen 2, and acquires various data from the active pen 2, similar to the first communication method. However, since the uplink signal US1 is absent, it is impossible to request data from the active pen 2 from the sensor controller 31.

[0061] When the variable Count reaches a predetermined value N, the integrated circuit 25 restores the variable Count to 1 (step S22) and performs a pen touch determination (step S23). The pen touch determination is essentially a determination of whether the pen pressure value is 0. If the pen pressure value is not 0, the integrated circuit 25 determines that the active pen 2 is in a pen touch state; conversely, if the pen pressure value is 0, it determines that the active pen 2 is not in a pen touch state (i.e., in a hover state). If the active pen 2 is determined to be in a pen touch state, the integrated circuit 25 maintains the second mode, returns to step S20, and continues transmitting downlink signals DS2a and DS2b (step S24). Conversely, if the active pen 2 is determined not to be in a pen touch state, the integrated circuit 25 exits the second mode and returns to the discovery mode to continue processing (step S25).

[0062] Figure 3 and Figure 4 This diagram illustrates the operation of the active pen 2 and the sensor controller 31. Figure 3 The sensor controller 31-1 shown illustrates the sensor controller 31 corresponding to the first communication method. Figure 3 The sensor controller 31-2 shown illustrates the sensor controller 31 corresponding to the second communication method. Hereinafter, while referring to this… Figure 3 and Figure 4 Meanwhile, the operation of the active pen 2 and the sensor controller 31 is explained in detail again.

[0063] First refer to Figure 3 The sensor controller 31 has not yet entered the detection mode. While transmitting the downlink signal DS2a from the pen tip electrode 21, it also detects the uplink signal US1 arriving at the ring electrode 22. It should be noted that "R" in the figure represents the signal detection action (reception action). On the other hand, the sensor controller 31-1 transmits the uplink signal US1 at a predetermined period UpIntv, and performs downlink signal DS1a and DS1b detection actions when the uplink signal US1 is not being transmitted.

[0064] If, at time t1, the active pen 2 enters the receptive region of uplink signal US1 (pen placement), then at the subsequent time t2, integrated circuit 25 receives uplink signal US1. Upon receiving uplink signal US1, integrated circuit 25 enters the first mode. Subsequently, through a transmit / receive schedule determined by the timing of uplink signal US1 reception, the transmission of downlink signals DS1a and DS1b and the detection of uplink signal US1 are repeatedly executed via time division. Although in Figure 3 Not shown, but if the uplink signal US1 is not received even after performing the uplink signal US1 detection action, the integrated circuit 25 will restore its operating mode to the discovery mode.

[0065] Next refer to Figure 4 If no uplink signal US1 is received, integrated circuit 25, upon detecting that the pen pressure value has become 0 at time t3, enters the second mode. Then, during the period in the second mode, it repeatedly transmits downlink signals DS2a and DS2b. If the pen is lifted at time t4, integrated circuit 25 exits the second mode and returns to the discovery mode at time t5, which is T''s distance from time t4. The duration of time T is determined by... Figure 2 The specified value N is determined as shown. If the pen touch state is returned during time T, the integrated circuit 25 will not return to the discovery mode but will continue to the second mode.

[0066] Next, regarding the blocking filter 26 used to enable simultaneous detection of the uplink signal US using the ring electrode 22 and transmission of the downlink signal DS from the pen tip electrode 21, while referring to the appendix... Figure 1 Please provide a detailed explanation.

[0067] Figure 5 This is a schematic diagram illustrating the structure within the active pen 2. As shown in the diagram, a blocking filter 26 is inserted into the wiring connecting the loop electrode 22 and the integrated circuit 25. Therefore, the uplink signal US1 arriving at the loop electrode 22 is supplied to the integrated circuit 25 via the blocking filter 26.

[0068] Figure 5The electrostatic capacitance CY shown represents the parasitic capacitance generated between the pen tip electrode 21, the wiring connecting the pen tip electrode 21 and the integrated circuit 25, the ring electrode 22, and the integrated circuit 25. Due to this parasitic capacitance CY, if a downlink signal DS2a is sent from the pen tip electrode 21 when the uplink signal US1 arrives at the ring electrode 22, the downlink signal DS2a will overlap with the uplink signal US1. The blocking filter 26 removes only the downlink signal DS2a from the uplink signal US1 that has overlapped with it, thus ensuring that only the uplink signal US1 is supplied to the integrated circuit 25.

[0069] Various structures can be adopted for the specific structure of the blocking filter 26. Therefore, five types of blocking filters 26a to 26e are illustrated below, and each is described in detail.

[0070] Figure 6 This diagram illustrates the structure of the first example of the blocking filter 26, namely the blocking filter 26a. The diagram shows an example where the downlink signal DS2a is composed of a signal based on a sine wave of a specified frequency. Such a downlink signal DS2a is used, for example, in AES 1.0, where the specified frequency is 1.8 MHz.

[0071] Here, in the diagram and afterwards Figure 10 and Figure 13 The structure of the active pen 2 and sensor controller 31 is shown using an equivalent circuit. Specifically, firstly, oscillator V1 corresponds to sensor controller 31 and generates uplink signal US1. Oscillator V2 corresponds to the transmitting circuit within integrated circuit 25 and generates downlink signal DS2a. The electrostatic capacitance CX represents the capacitance formed between the ring electrode 22 and sensor electrode group 30 (see reference). Figure 1 The electrostatic capacitance C1 represents the electrostatic capacitance formed between the ring electrode 22 and the wiring and ground terminal connecting the ring electrode 22 and the integrated circuit 25. Voltage Vring corresponds to the signal appearing at the ring electrode 22 (the uplink signal US1 overlapping the state of the downlink signal DS2a), and voltage Vfiltout corresponds to the output signal of the blocking filter 26. The circuit within the integrated circuit 25 supplied with voltage Vfiltout is actually a receiving circuit, but... Figure 6 and the following Figure 10 and Figure 13 The diagram simply illustrates the series circuit of capacitor C2 and resistor R1. Voltage Vrxin corresponds to the signal received by the receiving circuit that accepts voltage Vfiltout as input.

[0072] Figure 6The example blocking filter 26a is composed of a band-stop filter (notch filter) that blocks a specific frequency band including the frequency specified above (the carrier frequency of the downlink signal DS2a). Specifically, as... Figure 6 As shown, the blocking filter 26a is configured to include a first circuit and a second circuit. The first circuit consists of two resistors, each with a resistance value of R, connected in series, with the connection point of these two resistors grounded via a capacitor with a capacitance value of 2C. The second circuit consists of two capacitors, each with a capacitance value of C, connected in series, with the connection point of these two capacitors grounded via a resistor with a resistance value of R / 2. The first and second circuits are connected in parallel between the ring electrode 22 and the integrated circuit 25. The capacitance value C and the resistance value R are set in such a way that the notch frequency 1 / 2πCR is equal to the aforementioned specified frequency.

[0073] Figure 7 It shows the use Figure 6 The diagram shows the simulation results for each signal. It illustrates the uplink signal US1, voltage Vring, voltage Vfiltout, and voltage Vrxin. In this simulation, the specified frequency was set to 1.8 MHz, and the pulse period of the uplink signal US1 was set to 2 μsec. During period X in the diagram of voltage Vring, the downlink signal DS2a appears in a state that does not overlap with the uplink signal US1.

[0074] like Figure 7 As shown, in voltage Vring, the downlink signal DS2a overlaps with the uplink signal US1. On the other hand, in voltages Vfiltout and Vrxin, the uplink signal US1 appears alone. From this result, it can be understood that the blocking filter 26a selectively blocks the downlink signal DS2a.

[0075] However, as from Figure 7 As understood, the uplink signal US1 appearing in voltages Vfiltout and Vrxin is not the original pulse wave, but rather an edge signal obtained by extracting only the edge of the pulse wave. Therefore, the receiving circuit within integrated circuit 25 needs to be configured to receive the uplink signal US1 through this edge signal. The structure of such a receiving circuit will be described in detail below.

[0076] Figure 8 This diagram illustrates the structure of the receiving circuit provided within the integrated circuit 25 for receiving the uplink signal US1 via the aforementioned edge signal. As shown in the diagram, the integrated circuit 25 in this case is configured to include an amplifier circuit 40, a ΔΣ modulation unit 41, a pulse density detection unit 42, a gain control unit 43, an edge-matched filter 44, a pattern storage unit 45, and an uplink signal recovery unit 46.

[0077] Amplifier circuit 40 is from Figure 6 The circuit shown amplifies the voltage Vfiltout after the output of the blocking filter 26a and supplies it to the ΔΣ modulation unit 41 as the output signal DO. The amplifier circuit 40 is composed of a variable gain amplifier configured such that the amplification rate can be controlled by the gain control unit 43.

[0078] The ΔΣ modulation unit 41 is a functional unit that performs feedback processing on the output signal DO of the amplifier circuit 40 by comparing it with at least two reference potentials VTP and VTN (VTP = -VTN > 0) corresponding to positive and negative values ​​respectively, and processing the comparison result. Figure 8 As shown, it is configured to have a subtraction circuit 41a, an addition circuit 41b, a comparison circuit 41c, and delay circuits 41d and 41e.

[0079] The comparator circuit 41c compares the output signal IO of the summing circuit 41b with the reference potentials VTP and VTN. It is configured with three output terminals: an output terminal for the comparison result, a positive output terminal (+1), and a negative output terminal (-1). The signal output from the output terminal for the comparison result constitutes the output signal CO of the ΔΣ modulation unit 41.

[0080] The comparator circuit 41c operates as follows: When the output signal IO of the summing circuit 41b exceeds the reference potential VTP, the comparator circuit 41c outputs +1 as the output signal CO, sets the potential of the positive output terminal high, and sets the potential of the negative output terminal low. Conversely, when the output signal IO of the summing circuit 41b is lower than the reference potential VTN, the comparator circuit 41c outputs -1 as the output signal CO, sets the potential of the negative output terminal high, and sets the potential of the positive output terminal low. In all other cases, the comparator circuit 41c outputs 0 as the output signal CO, and sets the potentials of both the positive and negative output terminals low. As a result of this operation of the comparator circuit 41c, the output signal CO of the comparator circuit 41c becomes a 3-valued pulse signal taking any one of +1, 0, or -1.

[0081] The comparator circuit 41c is configured to operate periodically with a length shorter than that of the chip string constituting the uplink signal US1. Therefore, the output signal CO becomes a pulse signal relative to the chip string constituting the uplink signal US1, where one chip comprises multiple chips (e.g., four chips).

[0082] Delay circuit 41d is a circuit that makes the potential of the positive output terminal of comparator circuit 41c a multiple of Δ, for example, delayed by 1 clock cycle (1 chip of output signal CO), and then feeds it back to subtraction circuit 41a. Similarly, delay circuit 41e is a circuit that makes the potential of the negative output terminal of comparator circuit 41c a multiple of -Δ, delayed by for example, 1 clock cycle, and then feeds it back to subtraction circuit 41a. It should be noted that the specific value of Δ is suitable to be set to be equal to the reference potential VTP.

[0083] The subtraction circuit 41a outputs a signal obtained by subtracting the potential corresponding to the output signals of the delay circuits 41d and 41e from the output signal DO of the amplifier circuit 40. Based on this subtraction, when the output signal IO one clock cycle before the clock exceeds the reference potential VTP, the potential level of the input signal of the summing circuit 41b decreases; when the output signal IO one clock cycle before the clock is below the reference potential VTN, the potential level of the input signal of the summing circuit 41b increases. Therefore, the effect of keeping the potential level of the output signal IO of the summing circuit 41b within a certain range is achieved.

[0084] The adder circuit 41b is a circuit that outputs a signal obtained by integrating the output signal of the subtractor circuit 41a. The output signal IO of the adder circuit 41b is the signal obtained by adding the output signal of the subtractor circuit 41a to the output signal of the adder circuit 41b before clock 1.

[0085] The pulse density detection unit 42 is a functional unit that detects the pulse density of the output signal CO of the ΔΣ modulation unit 41 and notifies the result to the gain control unit 43. The gain control unit 43 performs the following function: based on the pulse density notified from the pulse density detection unit 42, it controls the gain of the amplifier circuit 40, thereby preventing the output signal CO from being fixed due to the absolute value of the output signal DO being too large or too small.

[0086] The pattern storage unit 45 is composed of a storage circuit that stores a 3-value chip string consisting of multiple chips with any value of +1, 0, or 1 as a known pattern for each of the multiple spreading codes (2-value chip strings) that the sensor controller 31 may use in the transmission of the uplink signal US.

[0087] The edge-matched filter 44 has a first-in-first-out shift register configured to store a chip string of the number of chips corresponding to one spreading code. Each time the output signal CO of the ΔΣ modulation unit 41 acquires one chip, it is stored in this shift register. Furthermore, each time a new chip is stored, the correlation between the chip string stored in the shift register at that time and the respective correlations between the chip string and the multiple known patterns stored in the pattern storage unit 45 are calculated, and the results are successively supplied as the output signal FO to the uplink signal recovery unit 46.

[0088] When the output signal FO reaches a predetermined value or higher, the uplink signal recovery unit 46 determines that a spreading code corresponding to the pattern used in calculating the output signal FO has been detected. Then, it recovers the uplink signal US1 based on the continuously detected spreading code. The integrated circuit 25 receives the command sent by the sensor controller 31 by demodulating the recovered uplink signal US1.

[0089] Figure 9 It is shown by Figure 8 The diagram shows an example of the output signal FO generated by the receiving circuit. However, this diagram also shows the case where the correlation was calculated using a pattern corresponding to the chip string of the received uplink signal US1. Additionally, Figure 9 (c) represents the case where the voltage Vfiltout is input to the receiving circuit, but for comparison, in Figure 9 (a) illustrates the case where a noise-free, ideal uplink signal US is input to the receiving circuit. Figure 9 (b) illustrates the case where the voltage Vring is input to the receiving circuit. From Figure 9 The results shown demonstrate that, through combination Figure 6 The blocking filter 26a shown and Figure 8 The receiving circuit shown is able to correctly receive the uplink signal US1, just as it would be if a noise-free, ideal uplink signal US were input into the receiving circuit.

[0090] Figure 10 This diagram illustrates the structure of a second example of the blocking filter 26, namely blocking filter 26b. The diagram shows an example where the downlink signal DS2a is composed of a pulse wave. However, compared to the uplink signal US1, which is also a pulse wave, the pulse period of the downlink signal DS2a is significantly longer, and the edge duration is also longer. For example, the pulse period is, for instance, 4μsec to 40μsec, and the edge duration is, for instance, 100nsec to 5μsec.

[0091] The blocking filter 26b is composed of a high-pass filter 50 that blocks the pulse wave (second pulse wave) constituting the uplink signal US1 (first pulse wave). The specific structure of the high-pass filter 50 is as follows: Figure 10 As shown, a suitable CR filter is configured as a capacitor with capacitance C connected at one end to the ring electrode 22 and the other end to the integrated circuit 25, and a resistive element with resistance R connected between the other end of the capacitor and the ground terminal. The capacitance C and resistance R are configured such that the blocking filter 26b allows the uplink signal US1 to pass through while blocking the downlink signal DS2a.

[0092] Figure 11 It shows the use Figure 10 The diagram shows the simulation results of each signal. It illustrates the uplink signal US1, downlink signal DS2a, voltage Vring, and voltage Vfiltout. Figure 11 In the example, the pulse period of the uplink signal US1 is set to 2 μsec, and the pulse period of the downlink signal DS2a is set to 40 μsec. In addition, the duration of the edge period E1 of the uplink signal US1 is set to 10 nsec, and the duration of the edge period E2 of the downlink signal DS2a is set to 2 μsec.

[0093] like Figure 11 As shown, in voltage Vring, the downlink signal DS2a overlaps with the uplink signal US1; on the other hand, in voltage Vfiltout, the downlink signal DS2a almost disappears. From this result, it can be understood that the downlink signal DS2a is also selectively blocked by the blocking filter 26b. However, in… Figure 11 In the example, the uplink signal US1 appearing at voltage Vfiltout is not the original pulse wave, but an edge signal obtained by extracting only the edge of the pulse wave. Therefore, as the receiving circuit within integrated circuit 25, it is preferable to use a circuit with a reference, similar to the first example. Figure 8 The receiving circuit of the described structure.

[0094] Here, in use Figure 10 In the case of the blocking filter 26b with the structure shown, if the difference between the edge duration E2 of the downlink signal DS2a and the edge duration E1 of the uplink signal US1 becomes smaller, it may be difficult to remove the downlink signal DS2a from the voltage Vring. Specific examples will be given below to illustrate this.

[0095] Figure 12 and Figure 11 Similarly, it shows the use of Figure 10 The structure is illustrated in the figure showing the simulation results of each signal. (Compared to...) Figure 11 The difference lies in setting the edge duration E2 of the downlink signal DS2a to 200 ns. For example... Figure 12 As shown, in this case, the edge of the downlink signal DS2a is clearly residual on the voltage Vfiltout.

[0096] Figure 13 This diagram shows the structure of a third example of the blocking filter 26, namely blocking filter 26c. Using blocking filter 26c solves the problem of blocking filter 26b described above. The following is a detailed explanation.

[0097] The blocking filter 26c has the features shown in Figure 10 The high-pass filter 50 is equipped with a mute circuit 51 at its downstream end. The mute circuit 51 is configured to have a switching element SW and a clock circuit CLK connected between the other end of the capacitor constituting the high-pass filter 50 and ground. The switching element SW has a non-inverting input terminal and an inverting input terminal, configured to prevent the output of filter 26c from being grounded when the potential difference between the non-inverting input terminal and the inverting input terminal is greater than a predetermined value; otherwise, grounding is not performed. The clock circuit CLK is configured to output a signal that is high during the edge of the downlink signal DS2a and low during other periods, and supplies this signal to the non-inverting input terminal of the switching element SW. Through the operation of the switching element SW and the clock circuit CLK, the output (voltage Vfiltout) of filter 26c is muted during the edge of the downlink signal DS2a.

[0098] Figure 14 It shows the use Figure 13 The results of the simulation of each signal are shown in the figure. The waveforms of the uplink signal US1 and the downlink signal DS2a are compared with... Figure 12 The examples are the same. For example, compare... Figure 14 and Figure 12 As understood, in Figure 14 In the example, the edge of the downlink signal DS2a disappears from the voltage Vfiltout. From this result, it can be understood that the mute circuit 51 serves to remove the downlink signal DS2a from the voltage Vring.

[0099] Here, if the mute circuit 51 is used, the pulse of the uplink signal US1 may be partially missing. Therefore, similar to the first and second examples, in the third example, as the receiving circuit within the integrated circuit 25, it is also preferable to use a circuit with a reference... Figure 8 The receiving circuit described herein. In this way, the uplink signal US1 can be recovered through the correlation operation of the edge-matched filter 44. Therefore, even if the pulse of the uplink signal US1 is slightly missing due to the action of the mute circuit 51, the uplink signal US1 can still be received correctly.

[0100] Figure 15 This is a diagram showing the structure of a fourth example of the blocking filter 26, namely the blocking filter 26d. As shown in the figure, the blocking filter 26d is configured to include a gain circuit 52 and a differential circuit 53.

[0101] Gain circuit 52 controls and outputs the amplitude of downlink signal DS2a. The input of gain circuit 52 is connected to the output of the transmitting circuit within integrated circuit 25, and the output is connected to the inverting input terminal of differential circuit 53. Gain circuit 52 attenuates the amplitude of downlink signal DS2a to the same level as the downlink signal DS2a superimposed on uplink signal US1 via parasitic capacitance CY.

[0102] The differential circuit 53 is a circuit that subtracts the output signal of the gain circuit 52 from the uplink signal US1 that arrives at the ring electrode 22. The non-inverting input terminal of the differential circuit 53 is connected to the ring electrode 22. Therefore, the uplink signal US1, which overlaps with the downlink signal DS2a via the parasitic capacitance CY, is input to the non-inverting input terminal of the differential circuit 53. As described above, the output signal of the gain circuit 52 becomes the downlink signal DS2a, attenuated to the same amplitude as the downlink signal DS2a overlapping the uplink signal US1. Therefore, the output signal of the differential circuit 53 becomes the uplink signal US1 without overlap with the downlink signal DS2a.

[0103] Figure 16 It shows the use Figure 15 The diagram shows the results of the simulation of each signal based on the structure. Figure 16 (a) shows the uplink signal US1 generated by sensor controller 31. Figure 16 (b) to (d) respectively show the occurrences of Figure 15 The signals of nodes n1 to n3 are shown. It should be noted that... Figure 16 The example shown is that both the uplink signal US1 and the downlink signal DS2a are composed of pulse waves, and the pulse period of the downlink signal DS2a is much longer than that of the uplink signal US1.

[0104] As from Figure 16 As understood, the signal appearing at node n1 becomes an overlap of the uplink signal US1 generated by sensor controller 31 and the downlink signal DS2a appearing at node n2. Furthermore, the signal appearing at node n3, as a result of removing the downlink signal DS2a from the signal appearing at node n2, becomes a signal with the same waveform as the original uplink signal US1. From this result, it can be understood that the blocking filter 26d effectively removes the downlink signal DS2a from the signal arriving at the ring electrode 22.

[0105] Here, although Figure 15 and Figure 16The example is not considered, but in the actual gain circuit 52, the uplink signal US1, which is wound into the pen tip electrode 21 side via the parasitic capacitance CY, will overlap at the input. Since the effect of this overlap cannot be ignored, the component of the uplink signal US1 needs to be removed from the downlink signal DS2a within the blocking filter 26. The blocking filter 26, which can achieve this removal, will be explained in the fifth example described below.

[0106] Figure 17 This is a diagram showing the structure of the fifth example of the blocking filter 26, namely the blocking filter 26e. As shown in the figure, the blocking filter 26e is configured to include an FIR (Finite Impulse Response) filter 54, a subtractor 55, and a feedback circuit 56.

[0107] FIR filter 54 is a digital filter configured to extract only specific signal components. In the blocking filter 26e, FIR filter 54 functions as a filter circuit that removes the uplink signal US1 component from the downlink signal DS2a output from the transmitting circuit within integrated circuit 25, and as a gain circuit that controls the amplitude of the downlink signal DS2a and outputs it. Subtractor 55 and... Figure 15 The differential circuit 53 shown is also a differential circuit that subtracts the output signal of the FIR filter 54 from the uplink signal US1 that has arrived at the ring electrode 22.

[0108] Feedback circuit 56 controls the amplitude of the downlink signal DS2a in the FIR filter 54 in a way that reduces the amplitude of the output signal of the subtractor 55 (i.e., reduces the output energy). Specifically, the LMS (least mean squares) algorithm is preferably used to control the values ​​of the coefficients included in the transfer function of the FIR filter 54. As a result of the control of feedback circuit 56, the signal output from the FIR filter 54 becomes a signal close to the pure downlink signal DS2a without the component of the uplink signal US1. Therefore, according to the blocking filter 26e, it is possible to effectively remove the downlink signal DS2a from the signal arriving at the ring electrode 22 even if the uplink signal US1 is superimposed on the input of the FIR filter 54 via the parasitic capacitance CY.

[0109] As explained above, according to the active pen 2 of this embodiment, since a blocking filter 26 is provided between the ring electrode 22 and the integrated circuit 25, the reception of the uplink signal US1 and the transmission of the downlink signal DS2a can be performed simultaneously instead of through time division. Therefore, delays in the reception of the uplink signal US1 can be prevented.

[0110] Furthermore, according to the active pen 2 of this embodiment, in the stage (discovery mode) where the uplink signal US of the sensor controller 31 has not yet been detected and the transmission timing of the uplink signal US of the sensor controller 31 is unknown, the reception of the uplink signal US and the transmission of the downlink signal DS can be performed simultaneously. On the other hand, in the stage (first mode) where the transmission timing of the uplink signal US of the sensor controller 31 is known once the uplink signal US is detected, the reception of the uplink signal US and the transmission of the downlink signal DS can be performed by time division. Therefore, it is possible to prevent delay in the reception of the uplink signal US and to detect the uplink signal US in a state with less noise once the uplink signal US is detected. In addition, since the downlink signal DS can be transmitted from both the pen tip electrode 21 and the ring electrode 22, the tilting of the active pen 2 can be utilized.

[0111] While the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments in any way, and the present invention can certainly be implemented in various ways without departing from its spirit.

[0112] For example, in the above embodiment, the case of using an uplink signal US1 that is a pulse wave was described, but the present invention can also be suitably applied to the case of using an uplink signal US composed of a signal based on a sine wave. In this case, when using Figure 6 In the case of the blocking filter 26a shown, the uplink signal US can be set as a signal based on a sine wave whose frequency is not included in the specific frequency band blocked by the blocking filter 26a.

[0113] In addition, in the above embodiment, an example of a blocking filter 26 being fixedly inserted between the loop electrode 22 and the integrated circuit 25 was described. However, it is also possible to set a first path via the blocking filter 26, a second path without the blocking filter 26, and a switch to switch them. By controlling the switch from the integrated circuit 25, the first path is enabled when the uplink signal US1 is detected and the downlink signal DS2a is transmitted simultaneously (discovery mode), and the second path is enabled in other cases (first and second modes).

[0114] Furthermore, in the above embodiments, an example of applying the present invention to an active pen 2 that is a dual-mode stylus has been described, but the present invention can be widely applied to active pens 2 that need to simultaneously transmit downlink signal DS and receive uplink signal US.

[0115] Label Explanation

[0116] 1. Position Detection System

[0117] 2. Active pen

[0118] 3 Electronic devices

[0119] 3a Touch surface

[0120] 20 cores

[0121] 21. Pen tip electrode

[0122] 22 Ring Electrode

[0123] 23 Pressure Sensor

[0124] 24 batteries

[0125] 25 Integrated Circuits

[0126] 26, 26a~26e Blocking Filters

[0127] 30 Sensor Electrode Group

[0128] 31 Sensor Controller

[0129] 32 host processors

[0130] 40 Amplifier Circuit

[0131] 41 ΔΣ modulation section

[0132] 41a Subtraction Circuit

[0133] 41b Adder Circuit

[0134] 41C Comparator Circuit

[0135] 41d and 41e Delay circuits

[0136] 42 Pulse Density Detection Unit

[0137] 43 Gain Control Section

[0138] 44 Edge-matched filters

[0139] 45 Pattern Storage Unit

[0140] 46 Uplink signal recovery unit

[0141] 50 high-pass filter

[0142] 51 Silent Circuit

[0143] 52 Gain Circuit

[0144] 53 Differential Circuit

[0145] 54 FIR Filter

[0146] 55 Subtractor

[0147] 56 Feedback Circuit

[0148] C2 electrostatic capacitor

[0149] CLK clock circuit

[0150] CX electrostatic capacitor

[0151] CY parasitic capacitance

[0152] DS, DS1a, DS1b, DS2a, DS2b downlink signals

[0153] During the E1 and E2 edge periods

[0154] SW switching element

[0155] US and US1 uplink signals.

Claims

1. An active pen, comprising: The first and second electrodes are positioned at different locations. The transmitting circuit transmits downlink signals by using a boost circuit to provide a change to the first electrode; The receiving circuit uses the second electrode to detect the uplink signal; and A blocking filter is used to prevent changes in the potential of the first electrode from affecting the potential of the uplink signal detected by the receiving circuit.

2. The active pen according to claim 1, The downlink signal is a sine wave based on a specified frequency. The blocking filter is a band-stop filter that blocks a specific frequency band including the specified frequency.

3. The active pen according to claim 2, The uplink signal is composed of pulse waves.

4. The active pen according to claim 2, The uplink signal is a sine wave based on a frequency not included in the specific frequency band.

5. The active pen according to claim 1, The uplink signal is the first pulse wave. The downlink signal is a second pulse wave whose edge duration differs from that of the first pulse wave. The blocking filter is a high-pass filter configured to allow the first pulse wave to pass through while blocking the second pulse wave.

6. The active pen according to claim 1, The uplink signal and the downlink signal are both pulse waves. The blocking filter includes: A high-pass filter is configured to allow pulse waves constituting the uplink signal to pass through while blocking pulse waves constituting the downlink signal; and A muting circuit silences the input to the receiving circuit during the edge of the downlink signal.

7. The active pen according to claim 6, The silencing circuit is positioned between the high-pass filter and the receiving circuit.

8. The active pen according to claim 6 or 7, The receiving circuit is configured to receive the uplink signal through correlation operations.

9. The active pen according to claim 1, The blocking filter includes: A gain circuit controls and outputs the amplitude of the downlink signal; The differential circuit outputs the signal obtained by subtracting the output signal of the gain circuit from the uplink signal that has arrived at the second electrode.

10. The active pen according to claim 9, The blocking filter also includes a feedback circuit that controls the amount of control the gain circuit has on the amplitude of the downlink signal in a manner that reduces the amplitude of the output signal of the differential circuit.

11. The active pen according to any one of claims 1 to 7, It also includes an integrated circuit, which includes the transmitting circuit and the receiving circuit. The integrated circuit controls the receiving circuit in such a way that it detects the uplink signal arriving at the second electrode while the transmitting circuit is transmitting the downlink signal from the first electrode.

12. An active pen, comprising: The first operating mode involves processing the detection of an uplink signal arriving at the second electrode while a downlink signal is being transmitted from the first electrode; and The second operating mode involves time-division of the transmission of the downlink signal from the first electrode and the detection of the uplink signal arriving at the second electrode. If the uplink signal is detected during an action in the first action mode, the active pen switches to the second action mode.

13. The active pen according to claim 12, The first electrode is an electrode disposed on the tip of the active pen. The second electrode is a ring electrode configured to surround the axis of the active pen.

14. The active pen according to claim 12 or 13, If the uplink signal is not detected for a predetermined number of consecutive times during the transition to the second action mode, the active pen switches back to the first action mode.

15. The active pen according to claim 12 or 13, comprising: The transmitting circuit transmits the downlink signal by using a boost circuit to provide a change to the first electrode; The receiving circuit uses the second electrode to detect the uplink signal; and A blocking filter is used to prevent changes in the potential of the first electrode from affecting the potential of the uplink signal detected by the receiving circuit.

16. The active pen according to claim 15, The downlink signal is a sine wave based on a specified frequency. The blocking filter is a band-stop filter that blocks a specific frequency band including the specified frequency.

17. The active pen according to claim 15, The uplink signal is the first pulse wave. The downlink signal is a second pulse wave whose edge duration differs from that of the first pulse wave. The blocking filter is a high-pass filter configured to allow the first pulse wave to pass through while blocking the second pulse wave.

18. The active pen according to claim 15, The blocking filter includes: A gain circuit controls and outputs the amplitude of the downlink signal; and The differential circuit outputs the signal obtained by subtracting the output signal of the gain circuit from the uplink signal that has arrived at the second electrode.

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