Using importance resampling to reduce memory inconsistency in light sampling

Abstract

Disclosed is a method for reducing memory inconsistencies in light sampling using importance resampling, specifically devices, systems, and techniques for incorporating light effects into computer-generated graphics. In at least one embodiment, before rendering a frame of graphics, a virtual scene comprising a plurality of lights is rendered by randomly sampling a set of lights from the plurality of lights. A subset of the set of lights is selected and used to render pixels within one or more portions of the frame.

Description

[0001] Priority claim

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 068,906, filed on August 21, 2020, entitled “RESAMPLING TECHNIQUE FOR RESERVIOR-BASED LIGHTING,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] At least one embodiment relates to computer graphics. For example, at least one embodiment relates to a processor or computing system for rendering graphics images using the various novel techniques described herein. Background Art

[0004] Light processing in computer graphics can consume significant amounts of time, memory, processing power, and other computational resources. This is particularly true for techniques designed to produce good visual quality (which may include, but is not limited to, ray tracing) and when the scene being rendered includes many lights. Therefore, improvements could be made to techniques for processing light in computer graphics. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example of a system for rendering a virtual scene using light resampling according to at least one embodiment is shown;

[0006] Figure 2 An example of a process for rendering a frame of a virtual scene by sampling from at least a scene light list and partially resampling from memory is shown in accordance with at least one embodiment;

[0007] Figure 3 An example of a process for rendering a frame of a virtual scene by partially resampling from memory in accordance with at least one embodiment is shown;

[0008] Figure 4 shows an example of light in a virtual area according to at least one embodiment;

[0009] Figure 5 Depicting an example of randomly selecting a light from a list of scene lights in accordance with at least one embodiment;

[0010] Figure 6 Depicted are examples of rendering a tile based on selection of one or more pre-sampled photon sets in accordance with at least one embodiment;

[0011] Figure 7 is an illustration of reservoir-based spatiotemporal importance resampling ("ReSTIR") candidate selection using an aggregation approach in accordance with at least one embodiment;

[0012] Figure 8 is an illustration of ReSTIR candidate selection using a scattering approach in accordance with at least one embodiment;

[0013] Figure 9 is an illustration of subpool reorganization according to at least one embodiment;

[0014] Figure 10 is an illustration of rendering a frame using multiple open tiles according to at least one embodiment;

[0015] Figure 11 is an illustration of an example process including pre-randomization and render-time stages according to at least one embodiment;

[0016] Figure 12 An exemplary data center is shown in accordance with at least one embodiment;

[0017] Figure 13 A processing system according to at least one embodiment is shown;

[0018] Figure 14 A computer system according to at least one embodiment is shown;

[0019] Figure 15 A system according to at least one embodiment is shown;

[0020] Figure 16 An exemplary integrated circuit according to at least one embodiment is shown;

[0021] Figure 17 A computing system according to at least one embodiment is shown;

[0022] Figure 18 An APU is shown according to at least one embodiment;

[0023] Figure 19 A CPU according to at least one embodiment is shown;

[0024] Figure 20 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0025] Figure 21A and Figure 21B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0026] Figure 22A A graphics core according to at least one embodiment is shown;

[0027] Figure 22B GPGPU according to at least one embodiment is shown;

[0028] Figure 23A A parallel processor according to at least one embodiment is shown;

[0029] Figure 23B illustrates a processing cluster according to at least one embodiment;

[0030] Figure 23C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0031] Figure 24 A graphics processor according to at least one embodiment is shown;

[0032] Figure 25 A processor according to at least one embodiment is shown;

[0033] Figure 26 A processor according to at least one embodiment is shown;

[0034] Figure 27 illustrates a graphics processor core according to at least one embodiment;

[0035] Figure 28 illustrates a PPU according to at least one embodiment;

[0036] Figure 29 shows a GPC according to at least one embodiment;

[0037] Figure 30 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0038] Figure 31 illustrates a software stack for a programming platform according to at least one embodiment;

[0039] Figure 32 According to at least one embodiment, Figure 31 CUDA implementation of the software stack;

[0040] Figure 33 According to at least one embodiment, Figure 31 ROCm implementation of the software stack;

[0041] Figure 34 According to at least one embodiment, Figure 31 OpenCL implementation of the software stack;

[0042] Figure 35 illustrates software supported by a programming platform according to at least one embodiment;

[0043] Figure 36 According to at least one embodiment, Figures 31-34 Compiled code executed on the programming platform;

[0044] Figure 37 According to at least one embodiment, Figures 31-34 More detailed compiled code executed on the programming platform;

[0045] Figure 38 Transforming source code before compiling it according to at least one embodiment is shown;

[0046] Figure 39A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0047] Figure 39B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 39A CUDA source code system;

[0048] Figure 39C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 39A CUDA source code system;

[0049] Figure 40 According to at least one embodiment, Figure 39C An example kernel converted by the CUDA to HIP conversion tool;

[0050] Figure 41 More details are shown according to at least one embodiment. Figure 39C A non-CUDA-enabled GPU;

[0051] Figure 42 shows how threads of an exemplary CUDA grid are mapped to Figure 41 different computational units; and

[0052] Figure 43 Illustrated is how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. DETAILED DESCRIPTION

[0053] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0054] In at least one embodiment, an embodiment of a method for rendering computational graphics incorporates reservoir-based lighting techniques such as Reservoir Spatiotemporal Importance Resampling (ReSTIR), including adaptations to optimize computer hardware and memory usage, including issues such as memory access latency, cache coherence, cache utilization, thrashing, and so on.

[0055] The embodiments disclosed herein may be used in a variety of applications, devices, and environments, including those described herein. The techniques described herein may be used to render complex graphics scenes, such as those that may be generated in video games, special effects, computer animation, computer-aided design, and the like.

[0056] In various embodiments, the techniques described herein are used to render graphics scenes in situations where high rendering speed is required. For example, some operations and techniques described herein can be performed before rendering a computer graphics frame, or performed at a periodicity less than every frame to improve the efficiency of each frame rendered.

[0057] In various embodiments, the techniques described herein are useful for non-graphics applications and problem spaces that share similar rendering or ray tracing features. For example, the embodiments described herein may be applicable to simulating the effects of acoustic or electromagnetic transmissions involving many emitters.

[0058] Figure 1 An example of a system for rendering a virtual scene using light resampling according to at least one embodiment is shown. Figure 1 In example 100 , computing device 102 generates graphics output to drive display on screen 108 .

[0059] In at least one embodiment, computing device 102 generates graphical output using a graphics pipeline 104 and a graphics card 106. In at least one embodiment, graphics card 106 includes one or more processors, such as a graphics processing unit. In at least one embodiment, graphics pipeline 104 includes software, hardware, or a combination of software and hardware to generate graphical output. Graphics pipeline 104 can generate graphical output according to a multi-stage process, such as including Figure 1 The process of stages 110-118 is depicted within the graphics pipeline 104. Although stages 110-118 are Figure 1 Although depicted as a sequence, embodiments may omit some of the depicted stages 110-118, perform some of the operations 110-118 in an order other than that described (such as in parallel), or include operations other than Figure 1 Therefore, Figure 1The order in which the description is made should not be construed as limiting the potential embodiments to only those that conform to the described order.

[0060] In at least one embodiment, graphics pipeline 104 includes software, hardware, or a combination of hardware and software to implement a multi-stage process for converting application data into graphics data suitable (with or without certain post-pipeline steps) for display by screen 108. For example, graphics pipeline 104 may generate a frame of video data, which may then be converted into signals to drive the display of the frame on screen 108. In at least one embodiment, these stages may include an application stage 110, a geometry stage 112, a transformation stage 114, a lighting and shading stage 116, and a rasterization and texturing stage 118.

[0061] In at least one embodiment, one or more of stages 110 - 118 utilize a light sampling algorithm (including but not necessarily limited to ReSTIR) to incorporate light effects into the rendering of the virtual scene.

[0062] In at least one embodiment, the virtual scene 120 includes a simulated or computer-generated environment, such as a landscape, a building, a sports field, or other area. The virtual scene 120 may sometimes be referred to as or include a virtual environment. The virtual environment may be associated with data structures, graphical assets, and other data that define the content and structure of the virtual environment. For example, in at least one embodiment, the virtual scene is based on a virtual environment that includes a wireframe model of the landscape, various textures and objects residing within the scene, and the like. The virtual environment may also include lights placed at various locations within the scene.

[0063] In some cases, there may be a large number of such lights, which can present numerous challenges when rendering a depiction of the virtual scene 120. Handling these many lights is a difficult problem in computer graphics, particularly for ray tracing-based algorithms. For example, one approach to rendering a virtual scene is to evaluate all light sources in the scene for each shading point. However, increasing the light count can also increase the number and complexity of rays to be traced, which can also increase the time, computational resources, and complexity of the rendering process.

[0064] In at least one embodiment, a subset of lights is selected from a list 122 of all lights in a virtual scene 120. The subset is selected based on at least a partially random process, and the selected subset is stored in a portion of a memory 124. In at least one embodiment, the selected subset is stored in a data structure record corresponding to a subdivision or cell of the virtual scene. In other embodiments, the selected subset is not tied to or associated with any particular area of ​​the virtual scene. In other embodiments, the lights are randomly selected with a probability proportional to the intensity of the light or the overall importance of the scene. In other embodiments, the lights are randomly selected with a probability proportional to the importance of the given light's contribution to the subdivision of the virtual scene. A stochastic technique or process, sometimes referred to as a random technique or process, generally refers to a technique that includes a random, pseudo-random, or quasi-random factor. Examples of stochastic or random factors may include, but are not necessarily limited to, pseudo-random number generators, Monte Carlo sequences, and deterministic hashing.

[0065] Once stored in a portion of memory 124, the selected set of photons can be used to render pixels in a depiction of a virtual scene. However, the process of selecting lights from light list 122 can present various obstacles to efficient rendering. As noted, the light selection process is at least partially random, and thus such access to light list 122 can also be at least partially random and involve accessing widely separated areas of memory. List 122 can also be very large, potentially including thousands, tens of thousands, or even millions of lights. Consequently, accessing selected lights from the list can result in various inefficiencies, such as inefficiencies related to memory access latency, cache coherence, cache utilization, jitter, and the like.

[0066] In at least one embodiment, a light refers to a virtual illumination source. In at least one embodiment, this can include a source that emits or reflects light. A light can be associated with properties including the light's position in the virtual scene and an intensity value. For example, a light can be associated with x, y, and z values ​​representing the light's position in the virtual scene, as well as a value indicating the light's brightness. A light can also be associated with additional properties, such as parameters describing intensity, color, diffusion pattern, and the like. As used herein, the term light generally refers to data describing the light, such as data representing characteristics and parameters such as these.

[0067] In at least one embodiment, stages 110-118 of graphics pipeline 104 utilize lights stored in memory portion 124 to render portions of a virtual scene. In at least one embodiment, computing device 102 renders a graphics frame by first randomly selecting a subset of lights from light list 122 and storing this subset in memory portion 124. In at least one embodiment, this is done before rendering the frame. During frame rendering, computing device 102 randomly selects one or more lights from memory portion 124 to render a pixel. Note that random sampling of lights refers to selecting lights from a pool of lights using one or more random processes. In at least one embodiment, a random process includes any technique for selecting lights from a pool that includes at least some element of randomness, pseudo-randomness, or quasi-randomness. In at least one embodiment, the random process selects lights based on a probability proportional to the light's intensity, such that brighter lights are more likely to be selected than dimmer lights. The pool of lights refers to the lights that are candidates for selection.

[0068] Figure 2 An example of the process of rendering a frame of a virtual scene by sampling from a list of scene lights and partially resampling from memory is shown in accordance with at least one embodiment.

[0069] Although example process 200 is depicted as a series of operations, it should be understood that in embodiments, the depicted operations may be altered in various ways and that some operations may be omitted, reordered, or performed in parallel with other operations unless an order is explicitly stated or logically implied, such as when the input of one operation is dependent on the output of another operation.

[0070] Figure 2 The operations depicted can be performed by Figure 1 The system 100 described in the accompanying drawings is implemented by a system such as the system 100 described in the accompanying drawings, wherein the system includes at least one processor and a memory storing instructions that, in response to being executed by the at least one processor, cause the system to perform the described operations. In at least one embodiment, the operations are performed by a combination of hardware and software, wherein the hardware includes one or more APUs, CPUs, GPUs, PPUs, GPGPUs, parallel processors, processing clusters, graphics processors, multiprocessors, etc., as depicted by the various figures herein. In at least one embodiment, the software includes libraries such as any one of CUDA, OpenGL, OpenLC, ROCm, and may also include operating system software.

[0071] At 202, in at least one embodiment, the system creates a probability density function for one or more lights in the light list 122. In at least one embodiment, the probability density function indicates the likelihood of selecting a given light. In at least one embodiment, the probability density function incorporates the effects of various parameters, such as light intensity, color, distance to the point to be rendered, etc., so that some lights (e.g., those most likely to contribute significantly to the illumination) are more likely to be selected than other lights.

[0072] In at least one embodiment, an alternative to a probability density function is used. In at least one embodiment, the lights are randomly selected, with an equal probability of selecting a given light. In at least one embodiment, for this scenario, random numbers can be used to generate indices into the light list. Various structures (such as trees or arrays) can be used to store this list and can be used to facilitate selecting lights in conjunction with one or more random processes, which in some embodiments can include the use of a random number generator.

[0073] At 204, in at least one embodiment, the system selects a subset of lights from the list of lights. In at least one embodiment, the lights are selected using one or more random processes, such as those just described with respect to probability density functions. The number of lights selected for the subset can vary between embodiments based on factors such as the size of the portion to be rendered, the size of memory structures such as processor caches, and so on. In at least one embodiment, the set of lights and the subset of those lights are selected so that the lighting information can be stored in one or more levels of processor cache.

[0074] At 206, in at least one embodiment, the system stores the set of photons in a memory portion. The memory portion can be a portion of computer memory, such as an area of ​​memory implemented by a random access memory ("RAM") device, or an area of ​​virtual computer memory. In at least one embodiment, the memory portion is a contiguous area of ​​physical or virtual computer memory. In at least one embodiment, the memory portion is memory located within a processor cache. In at least one embodiment, reading or writing light information using high-level data structures (e.g., arrays or linked lists defined in a programming language) will result in the set of photons being stored in the memory portion. For example, reading light information from a portion of RAM may result in the light information also being stored in the cache memory portion.

[0075] At 208, in at least one embodiment, the system selects and stores additional subsets of lights. The number of subsets selected and loaded can vary between embodiments. In at least one embodiment, the subsets are selected and loaded into the memory portion so that the subsets remain effectively accessible (e.g., in a cache) as long as needed during rendering of a given frame. A suitable number of subsets can generally be found through experimentation or by considering the memory characteristics of the particular system on which rendering is performed, and can also depend on variations in the algorithm used to render pixels within a frame. For example, a multiprocessor system with multiple caches can load a sufficient number of subsets so that each cache includes a memory portion with a subset of lights.

[0076] At 210, in at least one embodiment, a graphics frame is rendered based on lights resampled from lights stored in a memory portion. In at least one embodiment, the frame is subdivided into tiles, and each tile is rendered using one or more lights sampled from the memory portion. In at least one embodiment, after rendering these tiles, other tiles are rendered using different subsets loaded into a separate memory portion. This process can then be repeated until the entire frame is rendered.

[0077] Figure 3 An example of a process for rendering a frame of a virtual scene by partially resampling from a memory according to at least one embodiment is shown. Although the example process 300 is depicted as a series of operations, it should be understood that in embodiments, the depicted operations may be altered in various ways, and some operations may be omitted, reordered, or performed in parallel with other operations unless an order is explicitly stated or logically implied, such as when the input of one operation depends on the output of another operation.

[0078] Figure 3 The operations shown can be performed by Figure 1 The system 100 described in the accompanying drawings is implemented by a system such as the system 100 described in the accompanying drawings, wherein the system includes at least one processor and a memory storing instructions that, in response to being executed by the at least one processor, cause the system to perform the described operations. In at least one embodiment, the operations are performed by a combination of hardware and software, wherein the hardware includes one or more APUs, CPUs, GPUs, PPUs, GPGPUs, parallel processors, processing clusters, graphics processors, multiprocessors, etc., as depicted by the various figures herein. In at least one embodiment, the software includes libraries such as any one of CUDA, OpenGL, OpenLC, ROCm, and may also include operating system software.

[0079] In at least one embodiment, at 302, the system performs pre-frame processing, including sampling lights from a list of all scene lights and storing the sampled lights in one or more memory portions. In at least one embodiment, the sampling is performed from fewer than all scene lights, but rather from a pool of lights that includes a large number of lights, such that sampling from such a pool can cause performance issues due to issues such as inefficient use of available processor cache. For example, in at least one embodiment, the pool may be small enough to fit in the L3 cache, but too large to fit in the more efficient L2 cache.

[0080] In at least one embodiment, pre-frame processing refers to processing performed before rendering an individual frame of a computer-generated depiction of a scene. As used herein, a frame generally refers to one of a series of frames generated to produce an animation sequence, but in some embodiments, it may also be used to refer to a single instance of a computer-generated image.

[0081] In at least one embodiment, at 304, the system selects a tile to render. In at least one embodiment, a frame is subdivided into tiles, each tile representing a portion of the frame. In at least one embodiment, the size or number of tiles is based at least in part on factors such as the number of samples drawn from the light list, the size of the memory portion storing the samples, the number of processors, GPUs, etc. available for rendering, the number of available threads, etc.

[0082] In at least one embodiment, the system selects a portion of memory from which light will be resampled at 306. In at least one embodiment, this is accomplished by assigning a processor or execution thread for rendering a tile that is configured such that the processor or thread draws samples from the selected portion of memory.

[0083] In at least one embodiment, at 308, the system renders the pixels within the tile by sampling from the identified memory portion. As described in greater detail herein, in at least one embodiment, the pixels within the tile can be rendered by randomly resampling one or more lights from the samples stored in the memory portion and using the light information stored in the memory portion to determine how to render the pixel. For example, in at least one embodiment, ray tracing can be performed using the resampled lights.

[0084] In at least one embodiment, at 310, the system determines whether any additional tiles need to be rendered. If so, the operations described with respect to elements 304 through 308 may be performed again. In at least one embodiment, a new memory portion is used for each tile rendered. In at least one embodiment, a given memory portion is reused for a first set of tiles, a new memory portion is selected for use for a second set of tiles, and so on. In at least one embodiment, multiple sets of tiles are rendered in parallel, and in at least one embodiment, each set of tiles may use a different memory portion.

[0085] In at least one embodiment, the system outputs the rendered frame at 312. In at least one embodiment, this includes providing data for the completed frame to another component within the system, such as a component driving a display.

[0086] In at least one embodiment, rendered pixels near tile edges are adjusted using additional random factors (including random, pseudo-random, quasi-random, and / or deterministic factors) to reduce or prevent artifacts in the rendered image. For example, dithering can be used in conjunction with element 308 above so that for pixels near tile boundaries, the set of memory portions from which light is selected varies based on some randomizing element or noise.

[0087] Figure 4 An example of light in a virtual area is shown according to at least one embodiment. Figure 4 In example 400 of FIG. 4 , virtual area 402 is a three-dimensional area depicted from a top view and a side view. Terrain 408 is included in the depicted example of virtual area 402, but virtual area 402 may include or omit various features, such as depicted terrain 408, as well as other features not depicted in the figure, such as people, obstacles, walls, and other objects.

[0088] In at least one embodiment, lights 410 are also included in virtual area 502, located at various locations within area 402. These lights 410 emit illumination that can be factored into renderings of computer-generated images based on virtual area 402. There can be many such lights 410, perhaps numbering in the hundreds, thousands, or millions. In some approaches, processing this number of lights can be challenging or impractical.

[0089] Figure 5 An example of randomly selecting a light from a scene light list is depicted in accordance with at least one embodiment. In example 500, a scene 506 includes a plurality of scene lights 508. There may be a very large number of scene lights 508, such as hundreds, thousands, or millions of lights. These lights may be stored in a memory or storage device as a scene light list 504.

[0090] In at least one embodiment, scene light list 504 includes one or more memory arrays in which information describing scene lights 508 is stored. For descriptive purposes, information describing scene lights may be referred to herein as light information, light data, or light. In at least one embodiment, scene light list 504 includes a data structure such as an array, a linked list, a tree, a B-tree, or the like. Scene light list 504 may be stored in random access memory ("RAM"), long-term storage (e.g., a solid-state or mechanical disk drive), or in some other structure. It should be understood that these examples are intended to be illustrative and, therefore, should not be construed in a manner that limits potential embodiments to only those including the specific examples provided.

[0091] In at least one embodiment, the sampled light 502 is identified from the scene light list 504 based on one or more at least partially random processes, which may include various random, quasi-random, or pseudo-random factors. For example, in at least one embodiment, the scene light list 504 has N lights stored in an array A having N storage locations. In this exemplary embodiment, the random process may generate a random number between 0 and N-1 and obtain an access to the light stored at A[N]. As depicted in example 500, each access may be to a different portion of the scene light list 504. As depicted in example 500, each access to the list 504 may be to a different random location. It should be understood that these examples are intended to be illustrative and, therefore, should not be construed in a manner that limits potential embodiments to only those including the specific examples provided.

[0092] In at least one embodiment, the ReSTIR algorithm relies on randomization to generate images in which many lights are present, but in some cases, this randomization can lead to poor performance. However, as described herein, the use of pre-randomization of samples can address these performance issues. For example, the techniques described herein use per-frame pre-processing techniques to sufficiently permute or perturb samples to maintain (unbiased) image convergence. In at least one embodiment, these pre-randomized samples are stored in a data structure that can be accessed in a manner that avoids inefficient use of cache memory. For example, by appropriately sizing, arrays or other structures can be stored in processor caches. Pre-randomized samples can provide efficiency gains by moving non-uniform memory accesses to a pre-processing stage, rather than causing non-uniform memory accesses during per-pixel rendering. Additional performance can be achieved if this pre-processing stage is shorter or uses less memory than other per-pixel candidate generation techniques.

[0093] Rendering techniques such as ReSTIR can decouple computation frequency using iterative applications of resampled importance resampling (RIS):

[0094]

[0095] This decomposes the integral ∫f0(x)f1(x)f2(x)dx into a sum of terms evaluated at different frequencies. Some implementations of this may lead to inconsistency issues and poor performance. For example, in an embodiment employing techniques such as ReSTIR, the inconsistency issue may be due to the sample x k The sparse distribution on a possibly long list results. However, in at least one embodiment, it is possible to select a sample set {x k Importance resampling (“RIS”) is applied again before ∑i=1,i=0 ...

[0096] The techniques described in this paper can be further understood by examining two degenerate forms of RIS. Assume a standard RIS estimator:

[0097]

[0098] Then two degenerate cases are examined, (i.e., as well as ):

[0099]

[0100]

[0101] The first one looks like stratified sampling on random strata. In the second one, RIS is still applied by first selecting M samples and then selecting a subset N of them. However, it gives the same estimator as if N items were sampled directly. Note that the elements Can be crossed out.

[0102] Likewise, a technique like ReSTIR could take something similar to the following:

[0103]

[0104] This uses the inconsistent light list {L} and first samples it into a smaller subset {x k}, and then subsample this set into (even) smaller subsets of size N1 {x j}, and then subsample it into subsets of size N0 {x i}.

[0105] In at least one embodiment, pre-randomization may still use samples distributed according to p(x), but from a smaller, more consistent set in memory.

[0106]

[0107] This subsamples {L} into four subsets: {L}→{x l}→{x k}→{x j}→{x i}. The inner and the degenerated:

[0108]

[0109] In at least one embodiment, the numerical estimate is:

[0110]

[0111] It can be calculated by taking the domain {L}, where in at least one embodiment, {L} is a set of emission triangles corresponding to the scene light. In at least one embodiment, N3 samples are then drawn from {L} according to the distribution p(x) to obtain {x l}. Due to the insertion of {x l} is based on p(x), so {x l} has been distributed according to p(x). This means that from {x l} uniformly sample N2 samples to obtain {x k Then, the embodiment continues to select from the sample set {x k} in the sample {x j} and {x i}.

[0112] Resampling forms can be categorized as stratified or unstratified. As mentioned above, the form with nested sums is a stratified approach:

[0113]

[0114] This uses M*N candidates x ij .

[0115] The non-hierarchical form can be expressed as:

[0116]

[0117] This may only require M candidates x j And these candidates can be reused to draw all N samples. In this pre-randomized form of RIS:

[0118]

[0119] If giving up some degree of stratification is acceptable, then one can actually draw pre-randomized sets from the sum:

[0120]

[0121] Since this is done without the additional set of N3 samples {x l}, so this may not be a significant factor in some embodiments.

[0122] In at least one embodiment, multiple sets {x l} but using fewer than the number needed for full stratification (in this case, it would be N0N1N2 different sets {x l}), there can also be partial stratification. And no matter where it is placed, the degenerate item All cancel out, which demonstrates flexibility. Various embodiments can be based on how this "partial stratification" occurs in various pre-randomization algorithms, as described herein.

[0123] In an example embodiment, a pre-randomization phase and a render-time phase are performed. Figure 11 An example illustration of such an algorithm is depicted in .

[0124] The pre-randomization stage may include: 1) inputting the light sample list L, the number of subsets to be generated S i ={x l} and the size K of each subset; and 2) for each S i Subset, extract K lights from L according to the "initial light candidate" probability density function p(x). For example, p(x)∝L e (x), which is the emission power of each light.

[0125] At render time, for each pixel, instead of sampling M samples from the total list of light samples {L} using the distribution p(x), we draw M samples from a pre-randomized set of light samples S i ={x l} uniformly draw M samples from one of them. This uniform sampling can be done in a stratified and staggered manner to ensure that S i The traversal of is maximally consistent.

[0126] Figure 6 An example of rendering a tile based on selection of one or more pre-sampled subsets of lights is depicted in accordance with at least one embodiment. As shown in example 600, a frame 602 can be subdivided into tiles, and each tile can be rendered separately. In at least one embodiment, multiple subsets of lights are generated during pre-frame processing. In at least one embodiment, each subset is stored in a separate data structure or memory portion. An embodiment of a rendering algorithm may include a step in which a subset of lights is selected for rendering a tile. During rendering, each pixel is selected from a subset S of the original light list {L}. iTo ensure warp consistency, active threads that share processor cache or other memory resources should sample from the same subset S i Medium resampling.

[0127] All pixels in some image tiles can be obtained from the same S i For example, in example 600, all pixels from the first tile 604 are rendered based on pixels resampled from subset S1, pixels from the second tile 606 are rendered using pixels resampled from S2, pixels from the third tile 608 are rendered using pixels resampled from S3, and pixels from the fourth tile 610 are rendered using pixels resampled from S4.

[0128] In at least one embodiment, the target tile size is configured based on the hardware configuration. Experiments have shown that in some embodiments, 8x8 and 16x16 tiles can produce good performance. In these embodiments, larger tiles introduce artifacts, while using 4x4 image tiles increases inconsistencies, which reduces performance.

[0129] Figure 7 is an illustration of a possible approach for candidate selection for sampling techniques such as ReSTIR. In example 700, a clustering approach is used. As shown in example 700, frame 702 is composed of individual pixels 706, 708, each of which is rendered based on a subset of lights randomly drawn from light list 402. In this example, it is assumed that this subset is identified before rendering the frame and reused for each pixel within frame 702. To render pixel 706, 32 reads from list 704 are performed, from #1 to #32, to obtain information from lights 710 in the identified subset, but stored in light list 704, which includes all scene lights (4 million scene lights in this example). Subsequently, when rendering another pixel 708, using the same subset of lights, the system can again perform reads #1 to #32 to access the same subset of lights from light list 704. However, because other pixels may have already been rendered using different lights (e.g., lights from another subset), the lights from the original subset are no longer in the cache. Therefore, this approach can have problematic performance characteristics.

[0130] Figure 8 is an illustration of ReSTIR candidate selection using a scattering approach according to at least one embodiment. As described herein, light can be pre-randomized into “sub-pools” S i, as shown in example 800. Furthermore, example 800 illustrates that embodiments can vary how sub-pools are distributed across the screen. In at least one embodiment, screen tiles can be drawn from one or more sub-pools. In at least one embodiment, this is defined by a reuse parameter. For example, in at least one embodiment, each light in a sub-pool is reused a predetermined number of times, as indicated by the reuse parameter. In at least one embodiment, the tile size dynamically changes based on the indicated reuse parameter.

[0131] In at least one embodiment, one or more subsets of lights 804 are generated from a list of all scene lights. The list of all scene lights can be quite large, for example, four million lights in one example. The number and size of the one or more subsets of lights 804 can vary depending on the configuration. In one example, the one or more subsets of lights include multiple subpools, each subpool including 1024 lights.

[0132] In at least one embodiment, one or more subsets of light 804 are generated by sampling or shuffling light from all scene lights. In at least one embodiment, one or more random processes, such as random number generation, are used in the sampling or shuffling.

[0133] In at least one embodiment, some or all of one or more subsets are stored in memory portion 812. For example, in at least one embodiment, Figure 8 As shown, a sub-pool comprising 1024 lights is stored in the memory portion 812. This sub-pool can then be used to render pixels within each tile 806, 808 of the frame 802 by drawing pre-randomized samples from the sub-pool in the memory portion 812.

[0134] In at least one embodiment, this pre-randomization approach provides various advantages. For example, if attention is paid to promoting subpool S i If the statistical distribution of the light samples is consistent, then there can be flexibility in how the subpools are created. For example, subpools can be created in a cheaper way, such as by shuffling between photon pools, e.g. Figure 9 This avoids inconsistent memory reads into the global light list {L} (in this example, 4 million entries long).

[0135] Figure 9900 is an illustration of a subpool reshuffle according to at least one embodiment. In at least one embodiment, multiple subpools 904-908 are loaded into one or more memory portions, such as one or more portions of L1 / L2 / DRAM 910. These subpools can be read in steps 1A, 1B, and 1C and used to render tiles of a frame. In steps 2A and 2B, the lights in subpools 904, 906, and 908 are shuffled. For example, in at least one embodiment, some lights in subpool 904 are swapped with some lights in another subpool 906 based on one or more random processes. As described in example 900, the shuffling can occur over time. In at least one embodiment, read and write operations to L1 / L2 / DRAM 910 can overlap, as shown by the overlap of read steps 1A, 1B, and 1C and write steps 3A, 3B, and 3C along timeline 902.

[0136] Figure 10 is an illustration of rendering a frame using multiple open tiles, according to at least one embodiment. An open tile may be a tile for which at least a subset of lights is sampled from a large number of scene lights. This subset can be made available for rendering by loading it into a memory portion separate from the memory or storage device that holds the scene lights. When multiple tiles are open, they can share a single subpool or rely on multiple subpools being loaded into the memory portion.

[0137] In at least one embodiment, multiple tiles are opened all at once, and there is a cycle between multiple sub-pools. Figure 10 As shown, frame 1002 can be divided into T = 16 tiles, each with 2 x 2 pixels, using four samples per pixel. The current subpool can then be used for one sample from each of the T = 16 tiles. In this example, 16 subpools need to be loaded into memory portion 1012 to complete all 16 tiles, as each tile uses 2 x 2 x 4 = 16 samples. In at least one embodiment, each subpool serves two samples per pixel, thus using 32 subpools. In at least one embodiment, the number of tiles is increased to T = 32, again using 32 subpools. It should be understood that these examples are intended to be illustrative and should not be interpreted in a manner that limits the scope of potential embodiments to only those embodiments in conjunction with the specific examples provided. In various embodiments, these parameters can be adjusted to values ​​that best utilize the available hardware. Generally, suitable values ​​can be determined through experimentation and consideration of hardware characteristics, which may include the size of processor caches, such as the L1, L2, and L3 processor caches.

[0138] In at least one embodiment, the pre-randomization techniques described herein provide various additional advantages. Sampling lights can be an expensive operation, especially for a heterogeneous set of light types, such as emitting triangles, spheres, meshes, planes, cylinders, etc. Control flow divergence on SIMD processors can also be a significant cause or performance degradation. With pre-randomization, this expensive divergence is moved outside of the performance-sensitive inner rendering loop. Instead, it happens before rendering, and far fewer times per frame. Different light types can be divided into different light pools S i , or one could use consistent SIMD control flow to sample the lights and then as a second step, randomize into subpools.

[0139] In at least one embodiment, the pre-randomization techniques described herein improve the efficiency of handling dynamic lights. As lights move through a scene and change intensity, it may be necessary to update the current position of the light, update the intensity of the light, and possibly update the sampling distribution used to select the light. By pre-randomizing the lights, these updates can be done on a smaller number of lights. For example, in at least one embodiment, only those lights that are in a selected subpool S of a frame are updated. i The light in was completely renewed.

[0140] In at least one embodiment, the pre-randomization techniques described herein allow for greater flexibility. For example, using tiles allows for flexible changes in the shape and domain of light sampling.

[0141] Figure 11 is an illustration of an example process including pre-randomization and render-time phases according to at least one embodiment. Although example process 1100 is depicted as a series of operations, it should be understood that in embodiments, the depicted operations may be varied in various ways, and some operations may be omitted, reordered, or performed in parallel with other operations unless an order is explicitly stated or logically implied, such as when the input of one operation depends on the output of another operation.

[0142] Figure 11 The operations depicted can be performed by Figure 1 The system 100 described in the accompanying drawings may be implemented by a system such as the system 100 described in the accompanying drawings, the system including at least one processor and a memory storing instructions that, in response to being executed by the at least one processor, cause the system to perform the described operations. In at least one embodiment, the operations are performed by a combination of hardware and software, wherein the hardware includes one or more APUs, CPUs, GPUs, PPUs, GPGPUs, parallel processors, processing clusters, graphics processors, multiprocessors, etc., as shown in the various figures herein. In at least one embodiment, the software includes libraries such as any one of CUDA, OpenGL, OpenLC, ROCm, and may also include operating system software.

[0143] At 1102, in at least one embodiment, the system receives a list of light samples L, a plurality of subsets S to be generated, i ={x i} and the size K of each subset.

[0144] At 1104, in at least one embodiment, the system generates a probability function p(x) for each S according to the initial light candidate probability function p(x). i The subset extracts K lights from L.

[0145] In at least one embodiment, the previous operations 1102, 1104 are performed during a pre-randomization phase 1110, in which a subset S is extracted from the light list L. i During a second render-time phase 1112 comprising operations 1106 and 1108 , the subset is used to render a graphics frame.

[0146] At 1106, in at least one embodiment, the system selects a randomized set of photons S from the pre-randomized set of photons S. i ={x i} uniformly sample M samples from one of the S. As shown in 1108, the system can perform uniform sampling in a layered and interleaved manner to i Improve cache coherence during this time. Figure 9 Depicted are examples of sampling performed in a layered and interleaved manner.

[0147] A photon pool can be associated with a particular group of pixels, texels, or voxels. A photon pool can be used to select smaller sub-pools. This can correspond to a hierarchical reduction of inconsistencies, essentially building a random data structure from random, pseudo-random, or quasi-random selections of light. In at least one embodiment, the random data structure includes a hierarchy of samples, each hierarchy including samples selected from the hierarchy below it by an at least partially random process. If using sub-pools and screen tiles in certain situations results in banding artifacts, the photon pool can be dynamically resized to make performance and quality trade-offs. The number and size of sub-pools can vary by user device to control performance, memory utilization, and quality for various hardware types with different capabilities.

[0148] Data Center

[0149] Figure 12 An example data center 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 1200 includes, but is not limited to, a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0150] In at least one embodiment, Figure 12As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, grouped computing resources 1214, and node computing resources ("node CRs") 1216(1)-1216(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 1216(1)-1216(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NWI / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1216(1)-1216(N) may be a server having one or more of the above-mentioned computing resources.

[0151] In at least one embodiment, the grouped computing resources 1214 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0152] In at least one embodiment, resource coordinator 1212 may configure or otherwise control one or more nodes CR 1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may comprise a software design infrastructure ("SDI") management entity for data center 1200. In at least one embodiment, resource coordinator 1212 may comprise hardware, software, or some combination thereof.

[0153] In at least one embodiment, Figure 12 As shown, the framework layer 1220 includes but is not limited to a job scheduler 1232 , a configuration manager 1234 , a resource manager 1236 , and a distributed file system 1238 .

[0154] In at least one embodiment, the framework layer 1220 may include a framework that supports the software 1252 of the software layer 1230 and / or one or more applications 1242 of the application layer 1240. In at least one embodiment, the software 1252 or the applications 1242 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1220 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize a distributed file system 1238 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 1232 may include a Spark driver to facilitate scheduling workloads supported by various layers of the data center 1200. In at least one embodiment, the configuration manager 1234 may be capable of configuring different layers, such as the software layer 1230 and the framework layer 1220, which includes Spark and a distributed file system 1238 for supporting large-scale data processing. In at least one embodiment, the resource manager 1236 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 1238 and the job scheduler 1232. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 1214 on the data center infrastructure layer 1210. In at least one embodiment, the resource manager 1236 can coordinate with the resource coordinator 1212 to manage these mapped or allocated computing resources.

[0155] In at least one embodiment, the software 1252 included in the software layer 1230 may include software used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0156] In at least one embodiment, the one or more applications 1242 included in the application layer 1240 may include one or more types of applications used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. The one or more types of applications may include, but are not limited to, CUDA applications.

[0157] In at least one embodiment, any of configuration manager 1234, resource manager 1236, and resource coordinator 1212 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1200 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0158] Computer-based systems

[0159] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0160] Figure 13 A processing system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, system 1300 includes one or more processors 1302 and one or more graphics processors 1308 and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1302 or processor cores 1307. In at least one embodiment, processing system 1300 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0161] In at least one embodiment, the processing system 1300 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 1300 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 1300 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1300 is a television or set-top box device having one or more processors 1302 and a graphical interface generated by one or more graphics processors 1308.

[0162] In at least one embodiment, each of the one or more processors 1302 includes one or more processor cores 1307 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1307 is configured to process a specific instruction set 1309. In at least one embodiment, the instruction set 1309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1307 can each process a different instruction set 1309, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 1307 can also include other processing devices, such as a digital signal processor (DSP).

[0163] In at least one embodiment, processor 1302 includes cache memory 1304. In at least one embodiment, processor 1302 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1302. In at least one embodiment, processor 1302 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share this logic among processor cores 1307 using known cache coherence techniques. In at least one embodiment, processor 1302 also includes a register file 1306. Processor 1302 can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1306 can include general purpose registers or other registers.

[0164] In at least one embodiment, one or more processors 1302 are coupled to one or more interface buses 1310 to transmit communication signals, such as address, data, or control signals, between the processors 1302 and other components in the system 1300. In at least one embodiment, the interface bus 1310 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1310 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1302 includes an integrated memory controller 1316 and a platform controller hub 1330. In at least one embodiment, the memory controller 1316 facilitates communication between storage devices and other components of the processing system 1300, while the platform controller hub (PCH) 1330 provides connections to input / output (I / O) devices via a local I / O bus.

[0165] In at least one embodiment, the storage device 1320 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 1320 can be used as system memory for the processing system 1300 to store data 1322 and instructions 1321 for use when one or more processors 1302 execute applications or processes. In at least one embodiment, the memory controller 1316 is also coupled to an optional external graphics processor 1312, which can communicate with one or more graphics processors 1308 in the processor 1302 to perform graphics and media operations. In at least one embodiment, a display device 1311 can be connected to the processor 1302. In at least one embodiment, the display device 1311 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (such as a DisplayPort). In at least one embodiment, the display device 1311 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0166] In at least one embodiment, the platform controller hub 1330 enables peripheral devices to connect to the storage device 1320 and the processor 1302 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1346, a network controller 1334, a firmware interface 1328, a wireless transceiver 1326, a touch sensor 1325, and a data storage device 1324 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1324 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1325 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1326 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1328 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 1334 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1310. In at least one embodiment, the audio controller 1346 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1300 includes an optional legacy I / O controller 1340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 1300. In at least one embodiment, the platform controller hub 1330 can also be connected to one or more universal serial bus (USB) controllers 1342, which connect input devices such as a keyboard and mouse 1343 combination, a camera 1344, or other USB input devices.

[0167] In at least one embodiment, instances of memory controller 1316 and platform controller hub 1330 may be integrated into a discrete external graphics processor, such as external graphics processor 1312. In at least one embodiment, platform controller hub 1330 and / or memory controller 1316 may be external to one or more processors 1302. For example, in at least one embodiment, processing system 1300 may include external memory controller 1316 and platform controller hub 1330, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1302.

[0168] Figure 14A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 1400 is formed by a processor 1402, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 1400 can include, but is not limited to, components such as the processor 1402, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 1400 can include a processor such as the Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1400 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0169] In at least one embodiment, the computer system 1400 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0170] In at least one embodiment, computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1400 is a single-processor desktop or server system. In at least one embodiment, computer system 1400 may be a multi-processor system. In at least one embodiment, processor 1402 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1402 may be coupled to a processor bus 1410 that may transmit data signals between processor 1402 and other components in computer system 1400.

[0171] In at least one embodiment, processor 1402 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1402. In at least one embodiment, processor 1402 may include a combination of internal and external caches. In at least one embodiment, register file 1406 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and an instruction pointer register.

[0172] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1402. The processor 1402 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1408 may include logic for processing a packed instruction set 1409. In at least one embodiment, by including the packed instruction set 1409 in the instruction set of the general-purpose processor 1402, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1402. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0173] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0174] In at least one embodiment, a system logic chip can be coupled to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1416, and the processor 1402 can communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 can provide a high-bandwidth memory path 1418 to the memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1416 can initiate data signals between the processor 1402, the memory 1420, and other components in the computer system 1400, and bridge data signals between the processor bus 1410, the memory 1420, and the system I / O 1422. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to the memory 1420 via a high-bandwidth memory path 1418 , and the graphics / video card 1412 may be coupled to the MCH 1416 via an Accelerated Graphics Port (“AGP”) interconnect 1414 .

[0175] In at least one embodiment, computer system 1400 may use system I / O 1422 as a proprietary hub interface bus to couple MCH 1416 to I / O controller hub ("ICH") 1430. In at least one embodiment, ICH 1430 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub ("FlashBIOS") 1428, a wireless transceiver 1426, a data store 1424, a traditional I / O controller 1423 including user input 1425 and a keyboard interface, a serial expansion port 1427 (e.g., USB), and a network controller 1434. Data store 1424 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0176] In at least one embodiment, Figure 14 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 14 An exemplary SoC may be shown. In at least one embodiment, Figure 14 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1400 are interconnected using a Compute Express Link (CXL) interconnect.

[0177] Figure 15 A system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1500 is an electronic device that utilizes a processor 1510. In at least one embodiment, the system 1500 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0178] In at least one embodiment, system 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, USB (Revisions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 15 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 15 An exemplary SoC may be shown. In at least one embodiment, Figure 15 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0179] In at least one embodiment, Figure 15 The system may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit ("NFC") 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset ("EC") 1535, a trusted platform module ("TPM") 1538, a BIOS / firmware / flash memory ("BIOS, FWFlash") 1522, a DSP 1560, a solid-state disk ("SSD") or a hard disk drive ("HDD") 1520, a wireless local area network unit ("WLAN") 1550, a Bluetooth unit 1552, a wireless wide area network unit ("WWAN") 1556, a global positioning system (GPS) 1555, a camera ("USB 3.0 camera") 1554 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1515 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0180] In at least one embodiment, other components may be communicatively coupled to processor 1510 through the components discussed above. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1562, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1562 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as the WLAN unit 1550 and the Bluetooth unit 1552 and the WWAN unit 1556 may be implemented as a next generation form factor (NGFF).

[0181] Figure 16 An exemplary integrated circuit 1600 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1600 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I / O controller. 2 S / I 2 IC controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0182] Figure 17A computing system 1700 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1700 includes a processing subsystem 1701 having one or more processors 1702 and system memory 1704 communicating via an interconnect path that may include a memory hub 1705. In at least one embodiment, memory hub 1705 may be a separate component within a chipset assembly or integrated within one or more processors 1702. In at least one embodiment, memory hub 1705 is coupled to an I / O subsystem 1711 via a communication link 1706. In at least one embodiment, I / O subsystem 1711 includes an I / O hub 1707, which enables computing system 1700 to receive input from one or more input devices 1708. In at least one embodiment, I / O hub 1707 may enable a display controller, included in one or more processors 1702, to provide output to one or more display devices 1710A. In at least one embodiment, the one or more display devices 1710A coupled to I / O hub 1707 may include local, internal, or embedded display devices.

[0183] In at least one embodiment, the processing subsystem 1701 includes one or more parallel processors 1712 coupled to the memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, the communication link 1713 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1712 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1712 form a graphics processing subsystem that can output pixels to one of one or more display devices 1710A coupled via the I / O hub 1707. In at least one embodiment, the one or more parallel processors 1712 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1710B.

[0184] In at least one embodiment, system storage unit 1714 can be connected to I / O hub 1707 to provide a storage mechanism for computing system 1700. In at least one embodiment, I / O switch 1716 can be used to provide an interface mechanism to enable connections between I / O hub 1707 and other components, such as network adapter 1718 and / or wireless network adapter 1719, which can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1720. In at least one embodiment, network adapter 1718 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1719 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0185] In at least one embodiment, computing system 1700 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1707. Figure 17 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0186] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1712, memory hub 1705, processor 1702, and I / O hub 1707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1700 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I / O subsystem 1711 and display device 1710B are omitted from computing system 1700.

[0187] Processing system

[0188] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0189] Figure 18 An accelerated processing unit ("APU") 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1800 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1800 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1800 includes, but is not limited to, a core complex 1810, a graphics complex 1840, a fabric 1860, an I / O interface 1870, a memory controller 1880, a display controller 1892, and a multimedia engine 1894. In at least one embodiment, the APU 1800 can include, but is not limited to, any combination of any number of core complexes 1810, any number of graphics complexes 1840, any number of display controllers 1892, and any number of multimedia engines 1894. For purposes of illustration, multiple instances of similar objects are denoted herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0190] In at least one embodiment, core complex 1810 is a CPU, graphics complex 1840 is a GPU, and APU 1800 is a processing unit that is not limited to integrating 1810 and 1840 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1810, while other tasks may be assigned to graphics complex 1840. In at least one embodiment, core complex 1810 is configured to execute primary control software associated with APU 1800, such as an operating system. In at least one embodiment, core complex 1810 is the main processor of APU 1800, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1810 issues commands that control the operations of graphics complex 1840. In at least one embodiment, core complex 1810 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1840 may be configured to execute device executable code derived from CUDA source code.

[0191] In at least one embodiment, core complex 1810 includes, but is not limited to, cores 1820(1)-1820(4) and L3 cache 1830. In at least one embodiment, core complex 1810 may include, but is not limited to, any number of cores 1820 and any combination of any number and type of caches. In at least one embodiment, cores 1820 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1820 is a CPU core.

[0192] In at least one embodiment, each core 1820 includes, but is not limited to, a fetch / decode unit 1822, an integer execution engine 1824, a floating-point execution engine 1826, and an L2 cache 1828. In at least one embodiment, the fetch / decode unit 1822 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1824 and the floating-point execution engine 1826. In at least one embodiment, the fetch / decode unit 1822 can simultaneously dispatch one micro-op to the integer execution engine 1824 and another micro-op to the floating-point execution engine 1826. In at least one embodiment, the integer execution engine 1824 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1826 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1822 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1824 and the floating-point execution engine 1826.

[0193] In at least one embodiment, each core 1820(i) can access an L2 cache 1828(i) included in the core 1820(i), where i is an integer representing a specific instance of the core 1820. In at least one embodiment, each core 1820 included in a core complex 1810(j) is connected to the other cores 1820 included in the core complex 1810(j) via an L3 cache 1830(j) included in the core complex 1810(j), where j is an integer representing a specific instance of the core complex 1810. In at least one embodiment, a core 1820 included in a core complex 1810(j) can access all L3 caches 1830(j) included in the core complex 1810(j), where j is an integer representing a specific instance of the core complex 1810. In at least one embodiment, the L3 cache 1830 can include, but is not limited to, any number of slices.

[0194] In at least one embodiment, graphics complex 1840 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1840 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1840 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1840 is configured to perform both graphics-related operations and graphics-independent operations.

[0195] In at least one embodiment, graphics complex 1840 includes, but is not limited to, any number of compute units 1850 and L2 cache 1842. In at least one embodiment, compute units 1850 share L2 cache 1842. In at least one embodiment, L2 cache 1842 is partitioned. In at least one embodiment, graphics complex 1840 includes, but is not limited to, any number of compute units 1850 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1840 includes, but is not limited to, any amount of dedicated graphics hardware.

[0196] In at least one embodiment, each compute unit 1850 includes, but is not limited to, any number of SIMD units 1852 and shared memory 1854. In at least one embodiment, each SIMD unit 1852 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1850 can execute any number of thread blocks, but each thread block executes on a single compute unit 1850. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1852 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1854.

[0197] In at least one embodiment, fabric 1860 is a system interconnect that facilitates data and control transfers across core complex 1810, graphics complex 1840, I / O interface 1870, memory controller 1880, display controller 1892, and multimedia engine 1894. In at least one embodiment, APU 1800 may include, but is not limited to, any number and type of system interconnects in addition to or in lieu of fabric 1860 that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1800. In at least one embodiment, I / O interface 1870 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1870. In at least one embodiment, peripheral devices coupled to I / O interface 1870 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0198] In at least one embodiment, display controller 1892 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 1894 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1880 facilitates data transfer between APU 1800 and unified system memory 1890. In at least one embodiment, core complex 1810 and graphics complex 1840 share unified system memory 1890.

[0199] In at least one embodiment, the APU 1800 implements a memory subsystem including, but not limited to, any number and type of memory controllers 1880 and memory devices that can be dedicated to a component or shared among multiple components (e.g., shared memory 1854). In at least one embodiment, the APU 1800 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1928, L3 cache 1830, and L2 cache 1842), each of which can be private to a component or shared among any number of components (e.g., core 1820, core complex 1810, SIMD units 1852, compute units 1850, and graphics complex 1840).

[0200] Figure 19A CPU 1900 is shown according to at least one embodiment. In at least one embodiment, the CPU 1900 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1900 can be configured to execute application programs. In at least one embodiment, the CPU 1900 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1900 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1900 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1900 includes, but is not limited to, any number of core complexes 1910, fabric 1960, I / O interfaces 1970, and memory controller 1980.

[0201] In at least one embodiment, core complex 1910 includes, but is not limited to, cores 1920(1)-1920(4) and L3 cache 1930. In at least one embodiment, core complex 1910 may include, but is not limited to, any number of cores 1920 and any combination of any number and type of caches. In at least one embodiment, cores 1920 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1920 is a CPU core.

[0202] In at least one embodiment, each core 1920 includes, but is not limited to, a fetch / decode unit 1922, an integer execution engine 1924, a floating-point execution engine 1926, and an L2 cache 1928. In at least one embodiment, the fetch / decode unit 1922 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1924 and the floating-point execution engine 1926. In at least one embodiment, the fetch / decode unit 1922 can simultaneously dispatch one micro-op to the integer execution engine 1924 and another micro-op to the floating-point execution engine 1926. In at least one embodiment, the integer execution engine 1924 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1926 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1922 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1924 and the floating-point execution engine 1926.

[0203] In at least one embodiment, each core 1920(i) can access an L2 cache 1928(i) included in the core 1920(i), where i is an integer representing a specific instance of the core 1920. In at least one embodiment, each core 1920 included in a core complex 1910(j) is connected to the other cores 1920 in the core complex 1910(j) via an L3 cache 1930(j) included in the core complex 1910(j), where j is an integer representing a specific instance of the core complex 1910. In at least one embodiment, a core 1920 included in a core complex 1910(j) can access all L3 caches 1930(j) included in the core complex 1910(j), where j is an integer representing a specific instance of the core complex 1910. In at least one embodiment, the L3 cache 1930 can include, but is not limited to, any number of slices.

[0204] In at least one embodiment, fabric 1960 is a system interconnect that facilitates data and control transfers across core complexes 1910(1)-1910(N) (where N is an integer greater than zero), I / O interface 1970, and memory controller 1980. In at least one embodiment, CPU 1900 may include, in addition to or in lieu of fabric 1960, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1900. In at least one embodiment, I / O interface 1970 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1970. In at least one embodiment, peripheral devices coupled to I / O interface 1970 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0205] In at least one embodiment, memory controller 1980 facilitates data transfers between CPU 1900 and system memory 1990. In at least one embodiment, core complex 1910 and graphics complex 1940 share system memory 1990. In at least one embodiment, CPU 1900 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1980 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1900 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1928 and L3 cache 1930), each of which can be private to a component or shared among any number of components (e.g., core 1920 and core complex 1910).

[0206] Figure 20 An exemplary accelerator integrated slice 2090 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0207] The application effective address space 2082 within system memory 2014 stores a process element 2083. In one embodiment, the process element 2083 is stored in response to a GPU call 2081 from an application 2080 executing on processor 2007. The process element 2083 contains the processing state of the corresponding application 2080. The work descriptor (WD) 2084 contained in the process element 2083 can be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 2084 is a pointer to a job request queue in the application effective address space 2082.

[0208] Graphics acceleration module 2046 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 2084 to graphics acceleration module 2046 to start a job in a virtualized environment can be included.

[0209] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 2046 or individual graphics processing engine. Because the graphics acceleration module 2046 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 2046 is allocated.

[0210] In operation, the WD fetch unit 2091 in the accelerator integrated slice 2090 fetches the next WD 2084, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 2046. Data from the WD 2084 can be stored in registers 2045 for use by the memory management unit (MMU) 2039, the interrupt management circuit 2047, and / or the context management circuit 2048, as shown. For example, one embodiment of the MMU 2039 includes segment / page roaming circuitry for accessing the segment / page tables 2086 within the OS virtual address space 2085. The interrupt management circuit 2047 can process interrupt events (INT) 2092 received from the graphics acceleration module 2046. When executing graph operations, the effective address 2093 generated by the graphics processing engine is converted into a real address by the MMU 2039.

[0211] In one embodiment, the same register set 2045 is replicated for each graphics processing engine and / or graphics acceleration module 2046 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 2090. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0212] Table 1 – Registers initialized by the hypervisor

[0213] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0214] Example registers that may be initialized by the operating system are shown in Table 2.

[0215] Table 2 – Operating System Initialization Registers

[0216]

[0217]

[0218] In one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0219] Figure 21A and Figure 21B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0220] Figure 21A An exemplary graphics processor 2110 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 21B An additional exemplary graphics processor 2140 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 21A The graphics processor 2110 is a low power graphics processor core. In at least one embodiment, Figure 21B The graphics processor 2140 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2110, 2140 can be Figure 16 A variant of the graphics processor 1610.

[0221] In at least one embodiment, the graphics processor 2110 includes a vertex processor 2105 and one or more fragment processors 2115A-2115N (e.g., 2115A, 2115B, 2115C, 2115D through 2115N-1 and 2115N). In at least one embodiment, the graphics processor 2110 can execute different shader programs via separate logic, such that the vertex processor 2105 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2115A-2115N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2105 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 2115A-2115N use the primitives and vertex data generated by the vertex processor 2105 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 2115A-2115N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct3D API.

[0222] In at least one embodiment, the graphics processor 2110 additionally includes one or more MMUs 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B. In at least one embodiment, the one or more MMUs 2120A-2120B provide a mapping of virtual to physical addresses for the graphics processor 2110, including for the vertex processor 2105 and / or the fragment processors 2115A-2115N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2125A-2125B. In at least one embodiment, the one or more MMUs 2120A-2120B may synchronize with other MMUs within the system, including with the one or more MMUs 2120A-2120B. Figure 16 One or more MMUs associated with one or more application processors 1605, graphics processor 1615, and / or video processor 1620 enable each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2130A-2130B enable the graphics processor 2110 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0223] In at least one embodiment, graphics processor 2140 includes Figure 21AOne or more MMUs 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B of the graphics processor 2110. In at least one embodiment, the graphics processor 2140 includes one or more shader cores 2155A-2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F, through 2155N-1 and 2155N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2140 includes an inter-core task manager 2145 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2155A-2155N and a tiling unit 2158 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0224] Figure 22A FIG2 shows a graphics core 2200 according to at least one embodiment. In at least one embodiment, the graphics core 2200 may include Figure 16 In at least one embodiment, the graphics core 2200 may be Figure 21B 2155N. In at least one embodiment, the graphics core 2200 includes a shared instruction cache 2202, texture units 2218, and cache / shared memory 2220, which are common to execution resources within the graphics core 2200. In at least one embodiment, the graphics core 2200 may include multiple slices 2201A-2201N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2200. The slices 2201A-2201N may include support logic including local instruction caches 2204A-2204N, thread schedulers 2206A-2206N, thread dispatchers 2208A-2208N, and a set of registers 2210A-2210N. In at least one embodiment, the slices 2201A-2201N may include a set of additional function units (AFUs) 2212A-2212N, floating point units (FPUs) 2214A-2214N, integer arithmetic logic units (ALUs) 2216A-2216N, address calculation units (ACUs) 2213A-2213N, double precision floating point units (DPFPUs) 2215A-2215N, and matrix processing units (MPUs) 2217A-2217N.

[0225] In one embodiment, the FPUs 2214A-2214N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2215A-2215N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2216A-2216N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2217A-2217N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2217A-2217N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2212A-2212N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0226] Figure 22B A general purpose graphics processing unit (GPGPU) 2230 is shown in at least one embodiment. In at least one embodiment, GPGPU 2230 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 2230 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, GPGPU 2230 can be directly linked to other instances of GPGPU 2230 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 2230 includes a host interface 2232 to enable connection to a host processor. In at least one embodiment, host interface 2232 is a PCIe interface. In at least one embodiment, host interface 2232 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2230 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 2236A-2236H using a global scheduler 2234. In at least one embodiment, the compute clusters 2236A-2236H share a cache memory 2238. In at least one embodiment, the cache memory 2238 can serve as a higher level cache for the cache memories within the compute clusters 2236A-2236H.

[0227] In at least one embodiment, GPGPU 2230 includes memory 2244A-2244B coupled to compute cluster 2236A-2236H via a set of memory controllers 2242A-2242B. In at least one embodiment, memory 2244A-2244B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0228] In at least one embodiment, computing clusters 2236A-2236H each include a set of graphics cores, such as Figure 22A The graphics core 2200, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2236A-2236H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0229] In at least one embodiment, multiple instances of GPGPU 2230 can be configured to operate as a compute cluster. Compute clusters 2236A-2236H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2230 communicate via host interface 2232. In at least one embodiment, GPGPU 2230 includes an I / O hub 2239 that couples GPGPU 2230 to GPU link 2240, enabling direct connection to other instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2230 are located in separate data processing systems and communicate via a network device accessible via host interface 2232. In at least one embodiment, GPU link 2240 may be configured to connect to a host processor, in addition to or in place of host interface 2232. In at least one embodiment, GPGPU 2230 may be configured to execute CUDA programs.

[0230] Figure 23AA parallel processor 2300 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0231] In at least one embodiment, parallel processor 2300 includes parallel processing unit 2302. In at least one embodiment, parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of parallel processing unit 2302. In at least one embodiment, I / O unit 2304 can be directly connected to other devices. In at least one embodiment, I / O unit 2304 connects to other devices using a hub or switch interface (e.g., memory hub 2305). In at least one embodiment, the connection between memory hub 2305 and I / O unit 2304 forms a communication link. In at least one embodiment, I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, where host interface 2306 receives commands for performing processing operations and memory crossbar switch 2316 receives commands for performing memory operations.

[0232] In at least one embodiment, when host interface 2306 receives command buffers via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to dispatch commands or other work items to processing array 2312. In at least one embodiment, scheduler 2310 ensures that processing array 2312 is properly configured and in a valid state before dispatching tasks to processing array 2312. In at least one embodiment, scheduler 2310 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling rapid preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2312 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2312 by scheduler 2310 logic within a microcontroller that includes scheduler 2310 .

[0233] In at least one embodiment, the processing array 2312 can include up to "N" processing clusters (e.g., cluster 2314A, cluster 2314B, through cluster 2314N). In at least one embodiment, each cluster 2314A-2314N of the processing array 2312 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2310 can allocate work to the clusters 2314A-2314N of the processing array 2312 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 2310 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2312. In at least one embodiment, different clusters 2314A-2314N of the processing array 2312 can be assigned to process different types of programs or to perform different types of computations.

[0234] In at least one embodiment, the processing array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2312 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2312 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0235] In at least one embodiment, the processing array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2302 may transfer data from system memory via the I / O units 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to the system memory.

[0236] In at least one embodiment, when parallel processing unit 2302 is used to perform graph processing, scheduler 2310 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2314A-2314N of processing array 2312. In at least one embodiment, portions of processing array 2312 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2314A-2314N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2314A-2314N for further processing.

[0237] In at least one embodiment, the processing array 2312 can receive processing tasks to be executed via the scheduler 2310, which receives commands defining the processing tasks from the front end 2308. In at least one embodiment, the processing tasks can include an index of data to be processed, which can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2310 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2308. In at least one embodiment, the front end 2308 can be configured to ensure that the processing array 2312 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0238] In at least one embodiment, each of the one or more instances of parallel processing unit 2302 can be coupled to parallel processor memory 2322. In at least one embodiment, parallel processor memory 2322 can be accessed via memory crossbar 2316, which can receive memory requests from processing array 2312 and I / O unit 2304. In at least one embodiment, memory crossbar 2316 can access parallel processor memory 2322 via memory interface 2318. In at least one embodiment, memory interface 2318 can include multiple partition units (e.g., partition unit 2320A, partition unit 2320B, through partition unit 2320N), which can each be coupled to a portion of parallel processor memory 2322 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory cells, such that the first partition unit 2320A has a corresponding first memory cell 2324A, the second partition unit 2320B has a corresponding memory cell 2324B, and the Nth partition unit 2320N has a corresponding Nth memory cell 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory devices.

[0239] In at least one embodiment, memory units 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2324A-2324N, allowing partition units 2320A-2320N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2322. In at least one embodiment, local instances of parallel processor memory 2322 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0240] In at least one embodiment, any of the clusters 2314A-2314N of the processing array 2312 can process data to be written to any memory unit 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar 2316 can be configured to transmit the output of each cluster 2314A-2314N to any partition unit 2320A-2320N or to another cluster 2314A-2314N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with a memory interface 2318 via the memory crossbar 2316 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2316 has connections to memory interface 2318 for communicating with I / O unit 2304, as well as connections to local instances of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory that is not local to parallel processing unit 2302. In at least one embodiment, memory crossbar switch 2316 can use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0241] In at least one embodiment, multiple instances of parallel processing unit 2302 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2302 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2302 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2302 or parallel processor 2300 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0242] Figure 23B FIG2 shows a processing cluster 2394 according to at least one embodiment. In at least one embodiment, the processing cluster 2394 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2394 is Figure 23AIn at least one embodiment, a processing cluster 2394 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster 2394.

[0243] In at least one embodiment, the operation of the processing cluster 2394 can be controlled by a pipeline manager 2332 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2332 Figure 23A The scheduler 2310 receives instructions and manages the execution of these instructions through the graphics multiprocessor 2334 and / or the texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2394. In at least one embodiment, one or more instances of the graphics multiprocessor 2334 may be included within the processing cluster 2394. In at least one embodiment, the graphics multiprocessor 2334 may process data, and the data crossbar 2340 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2332 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 2340.

[0244] In at least one embodiment, each graphics multiprocessor 2334 within a processing cluster 2394 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0245] In at least one embodiment, instructions transmitted to the processing cluster 2394 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop by the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0246] In at least one embodiment, the graphics multiprocessor 2334 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2334 can abandon the internal cache and use cache memory within the processing cluster 2394 (e.g., L1 cache 2348). In at least one embodiment, each graphics multiprocessor 2334 can also access a partition unit (e.g., Figure 23A L2 cache within partition units 2320A-2320N) of the graphics multiprocessor 2334 is shared across all processing clusters 2394 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2334 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2302 can be used as global memory. In at least one embodiment, processing cluster 2394 includes multiple instances of graphics multiprocessor 2334, which can share common instructions and data, which can be stored in L1 cache 2348.

[0247] In at least one embodiment, each processing cluster 2394 may include an MMU 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in Figure 23A2348 or a cache line index.

[0248] In at least one embodiment, the processing clusters 2394 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2334 outputs processed tasks to a data crossbar 2340 to provide the processed tasks to another processing cluster 2394 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2316. In at least one embodiment, a pre-raster operations unit (preROP) 2342 is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which can communicate with a partitioning unit (e.g., a partitioning unit) as described herein. Figure 23A In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0249] Figure 23C A graphics multiprocessor 2396 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2396 is Figure 23B2366. The graphics multiprocessor 2396 is coupled to the pipeline manager 2332 of the processing cluster 2394. In at least one embodiment, the graphics multiprocessor 2396 has an execution pipeline that includes, but is not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more GPGPU cores 2362, and one or more LSUs 2366. The GPGPU cores 2362 and the LSUs 2366 are coupled to the cache memory 2372 and the shared memory 2370 via a memory and cache interconnect 2368.

[0250] In at least one embodiment, the instruction cache 2352 receives a stream of instructions to be executed from the pipeline manager 2332. In at least one embodiment, the instructions are cached in the instruction cache 2352 and dispatched for execution by the instruction unit 2354. In one embodiment, the instruction unit 2354 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2362. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2356 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 2366.

[0251] In at least one embodiment, register file 2358 provides a set of registers for the functional units of graphics multiprocessor 2396. In at least one embodiment, register file 2358 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2362, LSU 2366) connected to graphics multiprocessor 2396. In at least one embodiment, register file 2358 is divided between each functional unit such that a dedicated portion of register file 2358 is allocated to each functional unit. In at least one embodiment, register file 2358 is divided between the different thread groups being executed by graphics multiprocessor 2396.

[0252] In at least one embodiment, the GPGPU cores 2362 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 2396. The GPGPU cores 2362 may be architecturally similar or the architectures may differ. In at least one embodiment, a first portion of the GPGPU core 2362 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2308 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2396 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2362 may also include fixed-function or special-function logic.

[0253] In at least one embodiment, the GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0254] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network that connects each functional unit of the graphics multiprocessor 2396 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a crossbar interconnect that allows the LSU 2366 to implement load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 can operate at the same frequency as the GPGPU core 2362, resulting in very low latency for data transfers between the GPGPU core 2362 and the register file 2358. In at least one embodiment, the shared memory 2370 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2396. In at least one embodiment, the cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2336. In at least one embodiment, the shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2372, threads executing on GPGPU core 2362 may also programmatically store data in shared memory.

[0255] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0256] Figure 24A graphics processor 2400 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, ring interconnect 2402 couples graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0257] In at least one embodiment, the graphics processor 2400 receives batches of commands via a ring interconnect 2402. In at least one embodiment, the input commands are interpreted by a command streamer 2403 in a pipeline front end 2404. In at least one embodiment, the graphics processor 2400 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2403 provides the commands to a geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command streamer 2403 provides the commands to a video front end 2434, which is coupled to a media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2433 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate execution threads for thread execution resources provided by at least one graphics core 2480A.

[0258] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources featuring modular graphics cores 2480A-2480N (sometimes referred to as core slices), each of which has multiple sub-cores 2450A-2450N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 can have any number of graphics cores 2480A-2480N. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low-power processor having a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A-2480N, each of which includes a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units (EUs) 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each of the sub-cores 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources 2470 include a shared cache and pixel operation logic.

[0259] Figure 25A processor 2500 is shown for use in accordance with at least one embodiment. In at least one embodiment, the processor 2500 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2500 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 2510 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating-point form, may operate with packed data elements associated with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, the processor 2510 may execute instructions to accelerate CUAD programs.

[0260] In at least one embodiment, processor 2500 includes an in-order front end ("Front End") 2501 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 2501 may include several units. In at least one embodiment, instruction prefetcher 2526 retrieves instructions from memory and provides them to instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") for execution. In at least one embodiment, instruction decoder 2528 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2530 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, microcode ROM 2532 provides the microinstructions necessary to complete the operation.

[0261] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2528. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2532 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 completes the micro-op sequencing for the instruction, the front end 2501 of the machine may resume fetching micro-ops from the trace cache 2530.

[0262] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2503 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory microinstruction queue 2542, an integer / floating-point microinstruction queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2504, and a simple floating-point scheduler ("simple FP scheduler") 2506. In at least one embodiment, the fast scheduler 2502, the slow / general purpose floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to as "microinstruction schedulers 2502, 2504, 2506." The allocator / register renamer 2540 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 2540 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2540 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2542 for memory operations and an integer / floating point microinstruction queue 2544 for non-memory operations, preceding the memory scheduler 2546 and the microinstruction schedulers 2502, 2504, 2506. In at least one embodiment, the microinstruction schedulers 2502, 2504, 2506 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2502 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2504 and the simple floating point scheduler 2506 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2502, 2504, 2506 arbitrate on dispatch ports to schedule microinstructions for execution.

[0263] In at least one embodiment, execution block 2511 includes, but is not limited to, integer register file / branch network 2508, floating point register file / branch network ("FP register file / branch network") 2510, address generation units ("AGUs") 2512 and 2514, fast arithmetic logic units ("fast ALUs") 2516 and 2518, slow ALU 2520, floating point ALU ("FP") 2522, and floating point move unit ("FP move") 2524. In at least one embodiment, integer register file / branch network 2508 and floating point register file / bypass network 2510 are also referred to herein as "register files 2508, 2510." In at least one embodiment, AGUS 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating point ALU 2522, and floating point move unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

[0264] In at least one embodiment, register files 2508 and 2510 may be arranged between microinstruction schedulers 2502, 2504, and 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / bypass network 2508 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2510 performs floating-point operations. In at least one embodiment, each of register files 2508 and 2510 may include, but is not limited to, a bypass network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2508 and 2510 can communicate data with each other. In at least one embodiment, integer register file / bypass network 2508 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / bypass network 2510 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0265] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 can execute instructions. In at least one embodiment, register files 2508 and 2510 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2500 can include, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, and combinations thereof. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2522 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2516 and 2518. In at least one embodiment, the fast ALUs 2516 and 2518 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to the slow ALU 2520, as the slow ALU 2520 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by the AGUs 2512 and 2514. In at least one embodiment, the fast ALUs 2516, 2518, and slow ALUs 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALUs 2516, 2518, and slow ALUs 2520 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2522 and floating point shift unit 2524 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2522 and floating point shift unit 2524 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0266] In at least one embodiment, the microinstruction schedulers 2502, 2504, and 2506 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2500, processor 2500 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0267] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0268] Figure 26 A processor 2600 is shown in accordance with at least one embodiment. In at least one embodiment, the processor 2600 includes, but is not limited to, one or more processor cores (cores) 2602A-2602N, an integrated memory controller 2614, and an integrated graphics processor 2608. In at least one embodiment, the processor 2600 may include additional cores, up to and including the additional processor core 2602N represented by the dashed box. In at least one embodiment, each processor core 2602A-2602N includes one or more internal cache units 2604A-2604N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2606.

[0269] In at least one embodiment, the internal cache units 2604A-2604N and the shared cache unit 2606 represent a cache memory hierarchy within the processor 2600. In at least one embodiment, the cache memory units 2604A-2604N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2606 and 2604A-2604N.

[0270] In at least one embodiment, the processor 2600 may also include a set of one or more bus controller units 2616 and a system agent core 2610. In at least one embodiment, the one or more bus controller units 2616 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2610 provides management functions for various processor components. In at least one embodiment, the system agent core 2610 includes one or more integrated memory controllers 2614 to manage access to various external memory devices (not shown).

[0271] In at least one embodiment, one or more processor cores 2602A-2602N include support for simultaneous multithreading. In at least one embodiment, system agent core 2610 includes components for coordinating and operating processor cores 2602A-2602N during multithreaded processing. In at least one embodiment, system agent core 2610 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2602A-2602N and graphics processor 2608.

[0272] In at least one embodiment, processor 2600 further includes a graphics processor 2608 to perform graphics processing operations. In at least one embodiment, graphics processor 2608 is coupled to a shared cache unit 2606 and a system agent core 2610 including one or more integrated memory controllers 2614. In at least one embodiment, system agent core 2610 also includes a display controller 2611 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2611 may also be a separate module coupled to graphics processor 2608 via at least one interconnect, or may be integrated within graphics processor 2608.

[0273] In at least one embodiment, a ring-based interconnect 2612 is used to couple the internal components of the processor 2600. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2608 is coupled to the ring interconnect 2612 via I / O links 2613.

[0274] In at least one embodiment, I / O link 2613 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2618 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2602A-2602N and graphics processor 2608 uses embedded memory module 2618 as a shared LLC.

[0275] In at least one embodiment, the processor cores 2602A-2602N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2602A-2602N are heterogeneous in terms of ISA, where one or more processor cores 2602A-2602N execute a common instruction set, while one or more other processor cores 2602A-2602N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2602A-2602N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2600 can be implemented on one or more chips or as a SoC integrated circuit.

[0276] Figure 27 A graphics processor core 2700 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 2700 is included within a graphics core array. In at least one embodiment, graphics processor core 2700 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2700 is an example of a graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2700 can include fixed function blocks 2730 coupled to multiple sub-cores 2701A-2701F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0277] In at least one embodiment, fixed function block 2730 includes a geometry / fixed function pipeline 2736, which may be shared by all sub-cores in graphics processor 2700, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2736 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0278] In at least one embodiment, fixed function block 2730 also includes a graphics SoC interface 2737, a graphics microcontroller 2738, and a media pipeline 2739. Graphics SoC interface 2737 provides an interface between graphics core 2700 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2738 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2700, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2739 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2739 implements media operations via requests to computational or sampling logic within sub-cores 2701A-2701F.

[0279] In at least one embodiment, the SoC interface 2737 enables the graphics core 2700 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2737 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2700 and the CPU within the SoC. In at least one embodiment, the SoC interface 2737 may also implement power management controls for the graphics core 2700 and enable interfaces between the clock domain of the graphics core 2700 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2737 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2739 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., the geometry and fixed function pipeline 2736, the geometry and fixed function pipeline 2714) when graph processing operations are to be performed.

[0280] In at least one embodiment, the graphics microcontroller 2738 can be configured to perform various scheduling and management tasks for the graphics core 2700. In at least one embodiment, the graphics microcontroller 2738 can perform graph and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2702A-2702F, 2704A-2704F in the sub-cores 2701A-2701F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2700 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2738 may also facilitate a low power or idle state for the graphics core 2700, thereby providing the graphics core 2700 with the ability to save and restore registers across low power state transitions within the graphics core 2700 independent of the operating system and / or graphics driver software on the system.

[0281] In at least one embodiment, graphics core 2700 may have more or fewer sub-cores than the sub-cores 2701A-2701F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2700 may also include shared function logic 2710, shared and / or cache memory 2712, geometry / fixed function pipelines 2714, and additional fixed function logic 2716 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2710 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2700. Shared and / or cache memory 2712 may be LLC for the N sub-cores 2701A-2701F within graphics core 2700 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2714 may be included in place of geometry / fixed function pipeline 2736 within fixed function block 2730 and may include the same or similar logic units.

[0282] In at least one embodiment, graphics core 2700 includes additional fixed-function logic 2716, which may include various fixed-function acceleration logic for use by graphics core 2700. In at least one embodiment, additional fixed-function logic 2716 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, a full geometry pipeline and a culling pipeline within geometry / fixed-function pipelines 2716, 2736, which are additional geometry pipelines that may be included in additional fixed-function logic 2716. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2716 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0283] In at least one embodiment, the additional fixed function logic 2716 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0284] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2701A-2701F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2701A-2701F includes multiple EU arrays 2702A-2702F, 2704A-2704F, thread dispatch and inter-thread communication (TD / IC) logic 2703A-2703F, 3D (e.g., texture) samplers 2705A-2705F, media samplers 2706A-2706F, shader processors 2707A-2707F, and shared local memory (SLM) 2708A-2708F. Each EU array 2702A-2702F, 2704A-2704F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2703A-2703F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, 3D samplers 2705A-2705F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2706A-2706F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2701A-2701F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2701A-2701F may utilize shared local memory 2708A-2708F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0285] Figure 28A parallel processing unit ("PPU") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2800 is configured with machine-readable code that, if executed by PPU 2800, causes PPU 2800 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2800 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2800. In at least one embodiment, PPU 2800 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2800 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 28 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0286] In at least one embodiment, one or more PPUs 2800 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2800 are configured to accelerate CUDA programs. In at least one embodiment, a PPU 2800 includes, but is not limited to, an I / O unit 2806, a front-end unit 2810, a scheduler unit 2812, a work distribution unit 2814, a hub 2816, a crossbar switch ("Xbar") 2820, one or more general processing clusters ("GPCs") 2818, and one or more partitioning units ("memory partitioning units") 2822. In at least one embodiment, a PPU 2800 is connected to a host processor or other PPUs 2800 via one or more high-speed GPU interconnects ("GPU interconnects") 2808. In at least one embodiment, a PPU 2800 is connected to a host processor or other peripheral devices via a system bus or interconnect 2802. In one embodiment, the PPU 2800 is connected to local memory including one or more memory devices ("memory") 2804. In at least one embodiment, the memory devices 2804 include, but are not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high-bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0287] In at least one embodiment, the high-speed GPU interconnect 2808 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2800 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2800 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2808 transmits data and / or commands to other units of the PPU 2800, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via a hub 2816. Figure 28 Other components that may not be explicitly shown.

[0288] In at least one embodiment, the I / O unit 2806 is configured to receive data from the host processor ( Figure 282806). In at least one embodiment, the I / O unit 2806 communicates with the host processor directly via the system bus 2802 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2806 can communicate with one or more other processors (e.g., one or more PPUs 2800) via the system bus 2802. In at least one embodiment, the I / O unit 2806 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2806 implements an interface for communicating with external devices.

[0289] In at least one embodiment, the I / O unit 2806 decodes packets received via the system bus 2802. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2800 to perform various operations. In at least one embodiment, the I / O unit 2806 sends the decoded commands to various other units of the PPU 2800 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2810 and / or to the hub 2816 or other units of the PPU 2800, such as one or more copy engines, video encoders, video decoders, power management units, etc. ( Figure 28 In at least one embodiment, I / O unit 2806 is configured to route communications between the various logical units of PPU 2800.

[0290] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2800 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2800—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2802 via memory requests transmitted via the I / O unit 2806 over the system bus 2802. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2800, so that the front end unit 2810 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2800.

[0291] In at least one embodiment, the front end unit 2810 is coupled to a scheduler unit 2812 that configures the various GPCs 2818 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2812 is configured to track state information related to the various tasks managed by the scheduler unit 2812, where the state information may indicate which GPC 2818 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2812 manages multiple tasks that execute on one or more GPCs 2818.

[0292] In at least one embodiment, the scheduler unit 2812 is coupled to a work distribution unit 2814, which is configured to dispatch tasks for execution on the GPCs 2818. In at least one embodiment, the work distribution unit 2814 tracks a plurality of scheduled tasks received from the scheduler unit 2812 and manages a pending task pool and an active task pool for each GPC 2818. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2818; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2818, such that as a task in a GPC 2818 completes execution, the task is evicted from the active task pool of the GPC 2818, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2818. In at least one embodiment, if an active task is idle on a GPC 2818, such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2818 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2818.

[0293] In at least one embodiment, work distribution unit 2814 communicates with one or more GPCs 2818 via XBar 2820. In at least one embodiment, XBar 2820 is an interconnect network that couples many units of PPU 2800 to other units of PPU 2800 and can be configured to couple work distribution unit 2814 to a specific GPC 2818. In at least one embodiment, one or more other units of PPU 2800 can also be connected to XBar 2820 through hub 2816.

[0294] In at least one embodiment, tasks are managed by a scheduler unit 2812 and assigned to one of the GPCs 2818 by a work distribution unit 2814. The GPC 2818 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2818, routed to a different GPC 2818 via an XBar 2820, or stored in memory 2804. In at least one embodiment, the results can be written to memory 2804 via a partition unit 2822, which implements a memory interface for writing data to or reading data from memory 2804. In at least one embodiment, the results can be transferred to another PPU 2800 or CPU via a high-speed GPU interconnect 2808. In at least one embodiment, the PPU 2800 includes, but is not limited to, U partition units 2822, which equal the number of separate and distinct memory devices 2804 coupled to the PPU 2800.

[0295] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2800. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2800, and the PPU 2800 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2800, and the driver core outputs the tasks to one or more streams processed by the PPU 2800. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0296] Figure 29 FIG2 shows a GPC 2900 according to at least one embodiment. In at least one embodiment, the GPC 2900 is Figure 282818. In at least one embodiment, each GPC 2900 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2900 includes, but is not limited to, a pipeline manager 2902, a pre-raster operations unit ("PROP") 2904, a raster engine 2908, a work distribution crossbar ("WDX") 2916, a memory management unit ("MMU") 2918, one or more data processing clusters ("DPCs") 2906, and any suitable combination of components.

[0297] In at least one embodiment, the operation of the GPC 2900 is controlled by a pipeline manager 2902. In at least one embodiment, the pipeline manager 2902 manages the configuration of one or more DPCs 2906 to process tasks assigned to the GPC 2900. In at least one embodiment, the pipeline manager 2902 configures at least one of the one or more DPCs 2906 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, a DPC 2906 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2914. In at least one embodiment, the pipeline manager 2902 is configured to route packets received from a work distribution unit to appropriate logic within the GPC 2900, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 2904 and / or raster engine 2908, while other packets may be routed to a DPC 2906 for processing by a primitive engine 2912 or an SM 2914. In at least one embodiment, pipeline manager 2902 configures at least one of DPCs 2906 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2902 configures at least one of DPCs 2906 to execute at least a portion of a CUDA program.

[0298] In at least one embodiment, PROP unit 2904 is configured to route data generated by raster engine 2908 and DPC 2906 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 28Memory partitioning unit 2822, etc., described in more detail. In at least one embodiment, PROP unit 2904 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2908 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2908 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2908 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2906).

[0299] In at least one embodiment, each DPC 2906 included in a GPC 2900 includes, but is not limited to, an M-pipeline controller ("MPC") 2910; a primitive engine 2912; one or more SMs 2914; and any suitable combination thereof. In at least one embodiment, the MPC 2910 controls the operation of the DPC 2906, routing packets received from the pipeline manager 2902 to appropriate units within the DPC 2906. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2912, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2914.

[0300] In at least one embodiment, SM 2914 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2914 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2914 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different set of data based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 30 At least one embodiment of SM 2914 is described in more detail.

[0301] In at least one embodiment, the MMU 2918 provides a communication channel between the GPC 2900 and the memory partition unit (e.g., Figure 28 The MMU 2918 provides an interface between the memory and the partition unit 2822, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2918 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0302] Figure 30 Streaming Multiprocessor ("SM") 3000 is shown in accordance with at least one embodiment. In at least one embodiment, SM 3000 is Figure 29SM 2914. In at least one embodiment, SM 3000 includes, but is not limited to, an instruction cache 3002; one or more scheduler units 3004; a register file 3008; one or more processing cores ("cores") 3010; one or more special function units ("SFUs") 3012; one or more load / store units ("LSUs") 3014; an interconnect network 3016; a shared memory / level 1 ("L1") cache 3018; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 3000. In at least one embodiment, scheduler unit 3004 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 3000. In at least one embodiment, the scheduler unit 3004 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 3004 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing core 3010, SFU 3012, and LSU 3014) during each clock cycle.

[0303] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0304] In at least one embodiment, the dispatch unit 3006 is configured to send instructions to one or more of the functional units, and the scheduler unit 3004 includes, but is not limited to, two dispatch units 3006 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0305] In at least one embodiment, each SM 3000 includes, but is not limited to, a register file 3008 that provides a set of registers for the functional units of SM 3000. In at least one embodiment, register file 3008 is partitioned between each functional unit, allocating a dedicated portion of register file 3008 to each functional unit. In at least one embodiment, register file 3008 is partitioned between the different warps executed by SM 3000, and register file 3008 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 3000 includes, but is not limited to, a plurality of L processing cores 3010. In at least one embodiment, SM 3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3010. In at least one embodiment, each processing core 3010 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3010 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0306] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 3010. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0307] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0308] In at least one embodiment, each SM 3000 includes, but is not limited to, M SFUs 3012 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 3012 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 3012 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 3000. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 3018. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 3000 includes, but is not limited to, two texture units.

[0309] In at least one embodiment, each SM 3000 includes, but is not limited to, N LSUs 3014 that implement load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM 3000 includes, but is not limited to, an interconnection network 3016 that connects each functional unit to the register file 3008, and the LSUs 3014 connect to the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnection network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3008, and to connect the LSUs 3014 to memory locations in the register file 3008 and the shared memory / L1 cache 3018.

[0310] In at least one embodiment, shared memory / L1 cache 3018 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 3000 and the primitive engines, as well as between threads within the SM 3000. In at least one embodiment, shared memory / L1 cache 3018 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 3000 to the partition unit. In at least one embodiment, shared memory / L1 cache 3018 is used, in at least one embodiment, to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 3018, L2 cache, and memory is a backing store.

[0311] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure each thread generates unique results, use SM 3000 to execute the program and perform computations, use shared memory / L1 cache 3018 to communicate between threads, and use LSU 3014 to read and write global memory through shared memory / L1 cache 3018 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 3000 writes commands to scheduler unit 3004 that can be used to start new work on a DPC.

[0312] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0313] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0314] Software Construction for General Computing

[0315] The following figures illustrate, but are not limited to, exemplary software architectures for implementing at least one embodiment.

[0316] Figure 31 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL or IntelOneAPI.

[0317] In at least one embodiment, the programming platform's software stack 3100 provides an execution environment for applications 3101. In at least one embodiment, applications 3101 may include any computer software capable of being launched on the software stack 3100. In at least one embodiment, applications 3101 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0318] In at least one embodiment, the application 3101 and software stack 3100 run on hardware 3107. In at least one embodiment, the hardware 3107 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, the software stack 3100 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, the software stack 3100 can be used with devices from different vendors. In at least one embodiment, the hardware 3107 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 3107, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within the hardware 3107 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0319] In at least one embodiment, the programming platform's software stack 3100 includes, but is not limited to, a plurality of libraries 3103, a runtime 3105, and device kernel drivers 3106. In at least one embodiment, each of the libraries 3103 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 3103 may include, but are not limited to, prewritten code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 3103 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 3103 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 2903 are associated with corresponding APIs 3102, which may include one or more APIs that expose the functions implemented in the libraries 3103.

[0320] In at least one embodiment, the application 3101 is written as source code that is compiled into executable code as follows in conjunction with Figures 36-38 3101. In at least one embodiment, the executable code of application 3101 can run at least in part on an execution environment provided by software stack 3100. In at least one embodiment, during the execution of application 3101, code that needs to run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 3105 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 3105 can include any technically feasible runtime system capable of supporting the execution of application 3101.

[0321] In at least one embodiment, runtime 3105 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 3104). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0322] In at least one embodiment, the runtime library and corresponding API 3104 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0323] In at least one embodiment, the device kernel driver 3106 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 3106 can provide APIs such as API 3104 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 3106 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3106 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without requiring the device kernel driver 3106 to compile the IR code at runtime.

[0324] Figure 32 According to at least one embodiment, Figure 31 3201. In at least one embodiment, the CUDA software stack 3200, on which the application 3201 can be launched, includes a CUDA library 3203, a CUDA runtime 3205, a CUDA driver 3207, and a device kernel driver 3208. In at least one embodiment, the CUDA software stack 3200 executes on hardware 3209, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0325] In at least one embodiment, the application 3201, the CUDA runtime 3205, and the device kernel driver 3208 can perform similar functions as the application 3101, the runtime 3105, and the device kernel driver 3106, respectively. Figure 313206 . In at least one embodiment, the CUDA driver 3207 includes a library (libcuda.so) that implements the CUDA driver API 3206. In at least one embodiment, similar to the CUDA runtime API 3204 implemented by the CUDA runtime library (cudart), the CUDA driver API 3206 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3206 differs from the CUDA runtime API 3204 in that the CUDA runtime API 3204 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3204, in at least one embodiment, the CUDA driver API 3206 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3206 may expose functions for context management that are not exposed by the CUDA runtime API 3204. In at least one embodiment, the CUDA driver API 3206 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 3204. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 3205, can be considered separate from the driver components, including the user-mode CUDA driver 3207 and the kernel-mode device driver 3208 (sometimes also referred to as a "display" driver).

[0326] In at least one embodiment, the CUDA libraries 3203 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 3201). In at least one embodiment, the CUDA libraries 3203 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers. In at least one embodiment, the CUDA libraries 3203 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0327] Figure 33 According to at least one embodiment, Figure 313300 . In at least one embodiment, the ROCm software stack 3300 , on which an application 3301 can be launched, includes a language runtime 3303 , a system runtime 3305 , thunks 3307 , and a ROCm kernel driver 3308 . In at least one embodiment, the ROCm software stack 3300 executes on hardware 3309 , which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0328] In at least one embodiment, application 3301 may execute a combination of the above Figure 31 In addition, in at least one embodiment, the language runtime 3303 and the system runtime 3305 can perform functions similar to those described above in conjunction with the application 3101 discussed above. Figure 31 The language runtime 3303 and the system runtime 3305 have similar functionality to the runtime 3105 discussed above. In at least one embodiment, the language runtime 3303 differs from the system runtime 3305 in that the system runtime 3305 is a language-agnostic runtime that implements the ROCr system runtime API 3304 and leverages the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3305, the language runtime 3303 is an implementation of a language-specific runtime API 3302 layered on top of the ROCr system runtime API 3304. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 32 Similar functions to the CUDA runtime API 3204 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0329] In at least one embodiment, thunk (ROCt) 3307 is an interface that can be used to interact with the underlying ROCm driver 3308. In at least one embodiment, the ROCm driver 3308 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 31 The HSA kernel driver 3106 may function similarly to the discussed device kernel driver 3106. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0330] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3300 above the language runtime 3303 and provide Figure 32 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDAcuBLAS, a rocFFT library similar to CUDAcuFFT for computing FFTs, and the like.

[0331] Figure 34 According to at least one embodiment, Figure 31 3400. In at least one embodiment, the OpenCL software stack 3400, on which an application 3401 can be launched, includes an OpenCL framework 3410, an OpenCL runtime 3406, and a driver 3407. In at least one embodiment, the OpenCL software stack 3400 executes on hardware 3209 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0332] In at least one embodiment, the application 3401, the OpenCL runtime 3406, the device kernel driver 3407 and the hardware 3408 can each execute in conjunction with the above Figure 31 Similar functionality is discussed for application 3101, runtime 3105, device kernel driver 3106, and hardware 3107. In at least one embodiment, application 3401 also includes an OpenCL kernel 3402 having code to be executed on the device.

[0333] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3403 and runtime API 3405. In at least one embodiment, runtime API 3405 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 3405 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 3403 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0334] In at least one embodiment, a compiler 3404 is also included in the OpenCL framework 3410. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3404, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0335] Figure 35 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 3504 is configured to support various programming models 3503, middleware and / or libraries 3502, and frameworks 3501 that applications 3500 can rely on. In at least one embodiment, application 3500 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0336] In at least one embodiment, the programming platform 3504 can be a combination of the above Figure 32、 Figure 33 and Figure 34 In at least one embodiment, the programming platform 3504 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 3504 supports multiple programming models 3503, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3503 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3503 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute (VulcanCompute).

[0337] In at least one embodiment, the library and / or middleware 3502 provides an abstract implementation of the programming model 3504. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3504, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3502 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3502 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0338] In at least one embodiment, application framework 3501 relies on libraries and / or middleware 3502. In at least one embodiment, each application framework 3501 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0339] Figure 36 Compiled code is shown in accordance with at least one embodiment to Figures 31-34In at least one embodiment, compiler 3601 receives source code 3600, which includes both host code and device code. In at least one embodiment, compiler 3601 is configured to convert source code 3600 into host executable code 3602 for execution on the host and device executable code 3603 for execution on the device. In at least one embodiment, source code 3600 can be compiled offline before executing the application, or compiled online during execution of the application.

[0340] In at least one embodiment, source code 3600 may include code in any programming language supported by compiler 3601, such as C++, C, Fortran, etc. In at least one embodiment, source code 3600 may be included in a single-source file that has a mix of host code and device code and indicates the location of the device code. In at least one embodiment, the single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 3600 may include multiple source code files rather than a single source file in which the host code and device code are separated.

[0341] In at least one embodiment, compiler 3601 is configured to compile source code 3600 into host executable code 3602 for execution on a host and device executable code 3603 for execution on a device. In at least one embodiment, compiler 3601 performs operations including parsing source code 3600 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3600 comprises a single source file, compiler 3601 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3603 and host executable code 3602, respectively, and link device executable code 3603 and host executable code 3602 together in a single file, as described below with respect to Figure 37 discussed in more detail.

[0342] In at least one embodiment, host executable code 3602 and device executable code 3603 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3602 may include native object code, while device executable code 3603 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3602 and device executable code 3603 may include target binary code.

[0343] Figure 37 is compiled code according to at least one embodiment to Figures 31-34 3701 is a more detailed illustration of the execution of the program on one of the programming platforms of FIG. In at least one embodiment, the compiler 3701 is configured to receive the source code 3700, compile the source code 3700, and output an executable file 3710. In at least one embodiment, the source code 3700 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, which includes both host code and device code. In at least one embodiment, the compiler 3701 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0344] In at least one embodiment, compiler 3701 includes a compiler front end 3702, a host compiler 3705, a device compiler 3706, and a linker 3709. In at least one embodiment, compiler front end 3702 is configured to separate device code 3704 from host code 3703 in source code 3700. In at least one embodiment, device code 3704 is compiled by device compiler 3706 into device executable code 3708, which, as described, may include binary code or IR code. In at least one embodiment, host code 3703 is separately compiled by host compiler 3705 into host executable code 3707. In at least one embodiment, for NVCC, host compiler 3705 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3706 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3705 and the device compiler 3706 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0345] In at least one embodiment, after source code 3700 is compiled into host executable code 3707 and device executable code 3708, linker 3709 links host and device executable code 3707 and 3708 together in executable file 3710. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0346] Figure 383802. Figure 36 discussed.

[0347] In at least one embodiment, the conversion performed by the conversion tool 3801 is used to port the source code 3800 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, the conversion tool 3801 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the conversion of the source code 3800 may include parsing the source code 3800 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figures 39A-40 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3801 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3800.

[0348] Configuring GPUs for general computing

[0349] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0350] Figure 39AA system 3900 is shown configured to compile and execute CUDA source code 3910 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3900 includes, but is not limited to, CUDA source code 3910, a CUDA compiler 3950, a host executable 3970(1), a host executable 3970(2), a CUDA device executable 3984, a CPU 3990, a CUDA-enabled GPU 3994, a GPU 3992, a CUDA to HIP conversion tool 3920, HIP source code 3930, a HIP compiler driver 3940, an HCC 3960, and an HCC device executable 3982.

[0351] In at least one embodiment, CUDA source code 3910 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3990, GPU 3992, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3990.

[0352] In at least one embodiment, CUDA source code 3910 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, global functions 3912, device functions 3914, host functions 3916, and host / device functions 3918 can be intermixed within CUDA source code 3910. In at least one embodiment, each global function 3912 is executable on the device and callable from the host. Thus, in at least one embodiment, one or more of the global functions 3912 can serve as an entry point for the device. In at least one embodiment, each global function 3912 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3912 define a kernel that is executable on and callable from a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0353] In at least one embodiment, each device function 3914 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3916 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3916 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0354] In at least one embodiment, CUDA source code 3910 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA Runtime API 3902. In at least one embodiment, the CUDA Runtime API 3902 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3910 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, CUDA APIs include, but are not limited to, the CUDA Runtime API 3902, the CUDA Driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA Runtime API 3902, the CUDA Driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0355] In at least one embodiment, the CUDA compiler 3950 compiles input CUDA code (e.g., CUDA source code 3910) to generate host executable code 3970(1) and CUDA device executable code 3984. In at least one embodiment, the CUDA compiler 3950 is NVCC. In at least one embodiment, the host executable code 3970(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3990. In at least one embodiment, the CPU 3990 can be any processor optimized for sequential instruction processing.

[0356] In at least one embodiment, the CUDA device executable code 3984 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3994. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3994). In at least one embodiment, the CUDA-enabled GPU 3994 can be any processor optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3994 was developed by NVIDIA Corporation of Santa Clara, California.

[0357] In at least one embodiment, the CUDA to HIP conversion tool 3920 is configured to convert CUDA source code 3910 into functionally similar HIP source code 3930. In at least one embodiment, the HIP source code 3930 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, mechanisms for defining global functions 3912. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3912 defined in the HIP code are only callable from the host.

[0358] In at least one embodiment, HIP source code 3930 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, HIP source code 3930 may also include any number of calls to any number of functions specified in the HIP runtime API 3932. In one embodiment, the HIP runtime API 3932 includes, but is not limited to, functionally similar versions of a subset of the functions included in the CUDA runtime API 3902. In at least one embodiment, HIP source code 3930 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, a HIP API includes, but is not limited to, the HIP runtime API 3932, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0359] In at least one embodiment, the CUDA to HIP conversion tool 3920 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3920 converts any number of calls to functions specified in the CUDA runtime API 3902 to any number of calls to functions specified in the HIP runtime API 3932.

[0360] In at least one embodiment, the CUDA to HIP conversion tool 3920 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3920 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3920, correctly converting the CUDA code to HIP code may require modifications (e.g., manual editing).

[0361] In at least one embodiment, HIP compiler driver 3940 is a front end that determines target device 3946 and then configures a compiler compatible with target device 3946 to compile HIP source code 3930. In at least one embodiment, target device 3946 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3940 can determine target device 3946 in any technically feasible manner.

[0362] In at least one embodiment, if the target device 3946 is CUDA compatible (e.g., a CUDA-enabled GPU 3994), the HIP compiler driver 3940 generates HIP / NVCC compile commands 3942. In at least one embodiment and in conjunction with Figure 39B As described in more detail, HIP / NVCC compile command 3942 configures CUDA compiler 3950 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3930. In at least one embodiment and in response to HIP / NVCC compile command 3942, CUDA compiler 3950 generates host executable code 3970(1) and CUDA device executable code 3984.

[0363] In at least one embodiment, if the target device 3946 is not CUDA compatible, the HIP compiler driver 3940 generates HIP / HCC compilation commands 3944. In at least one embodiment and as in conjunction with Figure 39C As described in more detail, HIP / HCC compile command 3944 configures HCC 3960 to compile HIP source code 3930 using the HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3944, HCC 3960 generates host executable code 3970(2) and HCC device executable code 3982. In at least one embodiment, HCC device executable code 3982 is a compiled version of the device code contained in HIP source code 3930 that can be executed on GPU 3992. In at least one embodiment, GPU 3992 can be any processor optimized for parallel instruction processing that is not CUDA-compatible and is compatible with HCC. In at least one embodiment, GPU 3992 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, GPU 3992 is a non-CUDA-enabled GPU 3992.

[0364] For illustrative purposes only, Figure 39A39. In at least one embodiment, three different flows that can be implemented to compile CUDA source code 3910 for execution on a CPU 3990 and different devices are depicted. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3910 for execution on the CPU 3990 and a CUDA-enabled GPU 3994 without converting the CUDA source code 3910 into HIP source code 3930. In at least one embodiment, the indirect CUDA flow converts CUDA source code 3910 into HIP source code 3930 and then compiles the HIP source code 3930 for execution on the CPU 3990 and a CUDA-enabled GPU 3994. In at least one embodiment, the CUDA / HCC flow converts CUDA source code 3910 into HIP source code 3930 and then compiles the HIP source code 3930 for execution on the CPU 3990 and a GPU 3992.

[0365] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3950 receives a CUDA source code 3910 and a CUDA compile command 3948 that configures the CUDA compiler 3950 to compile the CUDA source code 3910. In at least one embodiment, the CUDA source code 3910 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3948, the CUDA compiler 3950 generates a host executable code 3970 (1) and a CUDA device executable code 3984 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3970 (1) and the CUDA device executable code 3984 can be executed on a CPU 3990 and a CUDA-enabled GPU 3994, respectively. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0366] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, a CUDA to HIP conversion tool 3920 receives CUDA source code 3910. In at least one embodiment and as indicated by bubble note B2, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 into HIP source code 3930. In at least one embodiment and as indicated by bubble note B3, a HIP compiler driver 3940 receives the HIP source code 3930 and determines whether the target device 3946 is CUDA-enabled.

[0367] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3940 generates HIP / NVCC compile commands 3942 and sends both the HIP / NVCC compile commands 3942 and the HIP source code 3930 to the CUDA compiler 3950. Figure 39B As described in more detail, the HIP / NVCC compile command 3942 configures the CUDA compiler 3950 to compile the HIP source code 3930 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3942, the CUDA compiler 3950 generates a host executable code 3970 (1) and a CUDA device executable code 3984 (indicated by bubble note B5). In at least one embodiment and as indicated by bubble note B6, the host executable code 3970 (1) and the CUDA device executable code 3984 can be executed on a CPU 3990 and a CUDA-enabled GPU 3994, respectively. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0368] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3920 receives CUDA source code 3910. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 into HIP source code 3930. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3940 receives the HIP source code 3930 and determines that the target device 3946 is not CUDA-enabled.

[0369] In at least one embodiment, the HIP compiler driver 3940 generates HIP / HCC compile commands 3944 and sends both the HIP / HCC compile commands 3944 and the HIP source code 3930 to the HCC 3960 (indicated by bubble comment C4). Figure 39C As described in more detail, HIP / HCC compile command 3964 configures HCC 3960 to compile HIP source code 3930 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3944, HCC 3960 generates host executable code 3970(2) and HCC device executable code 3982 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3970(2) and HCC device executable code 3982 can be executed on CPU 3990 and GPU 3992, respectively.

[0370] In at least one embodiment, after converting the CUDA source code 3910 to the HIP source code 3930, the HIP compiler driver 3940 can then be used to generate executable code for the CUDA-enabled GPU 3994 or GPU 3992 without having to re-implement the CUDA to HIP conversion tool 3920. In at least one embodiment, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 to the HIP source code 3930, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3940 then configures the HCC 3960 to generate a host executable code 3970 (2) and an HCC device executable code 3982 based on the HIP source code 3930. In at least one embodiment, the HIP compiler driver 3940 then configures the CUDA compiler 3950 to generate a host executable code 3970 (1) and a CUDA device executable code 3984 based on the stored HIP source code 3930.

[0371] Figure 39B 3990 and a CUDA-enabled GPU 3994 configured to compile and execute Figure 39A In at least one embodiment, the system 3904 includes, but is not limited to, CUDA source code 3910, a CUDA to HIP conversion tool 3920, HIP source code 3930, a HIP compiler driver 3940, a CUDA compiler 3950, a host executable 3970(1), a CUDA device executable 3984, a CPU 3990, and a CUDA-enabled GPU 3994.

[0372] In at least one embodiment and as previously incorporated herein Figure 39A As depicted, CUDA source code 3910 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, CUDA source code 3910 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0373] In at least one embodiment, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 into HIP source code 3930. In at least one embodiment, the CUDA to HIP conversion tool 3920 converts each kernel call in the CUDA source code 3910 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3910 into any number of other functionally similar HIP calls.

[0374] In at least one embodiment, the HIP compiler driver 3940 determines that the target device 3946 is CUDA-enabled and generates HIP / NVCC compile commands 3942. In at least one embodiment, the HIP compiler driver 3940 then configures the CUDA compiler 3950 via the HIP / NVCC compile commands 3942 to compile the HIP source code 3930. In at least one embodiment, as part of configuring the CUDA compiler 3950, the HIP compiler driver 3940 provides access to a HIP to CUDA translation header 3952. In at least one embodiment, the HIP to CUDA translation header 3952 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3950 uses the HIP to CUDA translation header 3952 in conjunction with a CUDA runtime library 3954 corresponding to the CUDA runtime API 3902 to generate host executable code 3970(1) and CUDA device executable code 3984. In at least one embodiment, the host executable code 3970(1) and the CUDA device executable code 3984 can then be executed on the CPU 3990 and the CUDA-enabled GPU 3994, respectively. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0375] Figure 39C A system 3906 is shown that is configured to compile and execute using a CPU 3990 and a non-CUDA enabled GPU 3992, according to at least one embodiment. Figure 39A CUDA source code 3910. In at least one embodiment, system 3906 includes, but is not limited to, CUDA source code 3910, a CUDA to HIP conversion tool 3920, HIP source code 3930, a HIP compiler driver 3940, HCC 3960, a host executable 3970(2), an HCC device executable 3982, a CPU 3990, and a GPU 3992.

[0376] In at least one embodiment, and as previously incorporated herein Figure 39A As depicted, CUDA source code 3910 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, CUDA source code 3910 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0377] In at least one embodiment, CUDA to HIP conversion tool 3920 converts CUDA source code 3910 into HIP source code 3930. In at least one embodiment, CUDA to HIP conversion tool 3920 converts each kernel call in CUDA source code 3910 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3910 into any number of other functionally similar HIP calls.

[0378] In at least one embodiment, the HIP compiler driver 3940 then determines that the target device 3946 is not CUDA-enabled and generates HIP / HCC compile commands 3944. In at least one embodiment, the HIP compiler driver 3940 then configures the HCC 3960 to execute the HIP / HCC compile commands 3944, thereby compiling the HIP source code 3930. In at least one embodiment, the HIP / HCC compile commands 3944 configure the HCC 3960 to use, but are not limited to, the HIP / HCC runtime library 3958 and the HCC header 3956 to generate host executable code 3970(2) and HCC device executable code 3982. In at least one embodiment, the HIP / HCC runtime library 3958 corresponds to the HIP runtime API 3932. In at least one embodiment, the HCC header 3956 includes, but is not limited to, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code 3970 ( 2 ) and HCC device executable code 3982 may execute on CPU 3990 and GPU 3992 , respectively.

[0379] Figure 40 According to at least one embodiment, Figure 39C 39. An exemplary kernel converted by the CUDA to HIP conversion tool 3920. In at least one embodiment, the CUDA source code 3910 divides the overall problem that a given kernel is designed to solve into relatively coarse-grained sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0380] In at least one embodiment, CUDA source code 3910 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0381] In at least one embodiment, a kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 4010 is used to specify the size of the grid on which the kernel is executed and the associated streams for a given kernel call. In at least one embodiment, the CUDA kernel launch syntax 4010 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the bracketed list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 4010 includes, but is not limited to, CUDA launch function syntax rather than execution configuration syntax.

[0382] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID that can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0383] In at least one embodiment, with respect to CUDA kernel launch syntax 4010, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 4010, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 4010, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0384] In at least one embodiment, CUDA source code 3910 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to be executed on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16xN / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 4010, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform one pairwise addition.

[0385] In at least one embodiment, while converting CUDA source code 3910 to HIP source code 3930, CUDA-to-HIP conversion tool 3920 converts each kernel call in CUDA source code 3910 from CUDA kernel launch syntax 4010 to HIP kernel launch syntax 4020, and converts any number of other CUDA calls in source code 3910 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 4020 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 4020 as in CUDA kernel launch syntax 4010 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in HIP kernel launch syntax 4020 and optional in CUDA kernel launch syntax 4010.

[0386] In at least one embodiment, in addition to the kernel call to cause the kernel MatAdd to execute on the device, Figure 40 A portion of the HIP source code 3930 depicted in Figure 40 3910). In at least one embodiment, kernel MatAdd is defined in HIP source code 3930 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3910. In at least one embodiment, the kernel call in HIP source code 3930 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3910 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0387] Figure 41 More details are shown according to at least one embodiment. Figure 39C3992. In at least one embodiment, the GPU 3992 is a non-CUDA-enabled GPU. In at least one embodiment, the GPU 3992 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the GPU 3992 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3992 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3992 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3992 is configured to perform both graphics-related operations and operations unrelated to graphics. In at least one embodiment, the GPU 3992 can be configured to execute device code included in the HIP source code 3930.

[0388] In at least one embodiment, GPU 3992 includes, but is not limited to, any number of programmable processing units 4120, a command processor 4110, an L2 cache 4122, a memory controller 4170, a DMA engine 4180(1), a system memory controller 4182, a DMA engine 4180(2), and a GPU controller 4184. In at least one embodiment, each programmable processing unit 4120 includes, but is not limited to, a workload manager 4130 and any number of compute units 4140. In at least one embodiment, command processor 4110 reads commands from one or more command queues (not shown) and dispatches the commands to workload managers 4130. In at least one embodiment, for each programmable processing unit 4120, the associated workload manager 4130 dispatches work to the compute units 4140 included in the programmable processing unit 4120. In at least one embodiment, each compute unit 4140 can execute any number of thread blocks, but each thread block executes on a single compute unit 4140. In at least one embodiment, a work group is a thread block.

[0389] In at least one embodiment, each compute unit 4140 includes, but is not limited to, any number of SIMD units 4150 and shared memory 4160. In at least one embodiment, each SIMD unit 4150 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 4150 includes, but is not limited to, a vector ALU 4152 and a vector register file 4154. In at least one embodiment, each SIMD unit 4150 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 4160.

[0390] In at least one embodiment, programmable processing units 4120 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 4120 includes, but is not limited to, any number of specialized graphics hardware in addition to compute units 4140. In at least one embodiment, each programmable processing unit 4120 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 4130, and any number of compute units 4140.

[0391] In at least one embodiment, compute units 4140 share L2 cache 4122. In at least one embodiment, L2 cache 4122 is partitioned. In at least one embodiment, all compute units 4140 in GPU 3992 can access GPU memory 4190. In at least one embodiment, memory controller 4170 and system memory controller 4182 facilitate data transfers between GPU 3992 and a host, and DMA engine 4180(1) enables asynchronous memory transfers between GPU 3992 and the host. In at least one embodiment, memory controller 4170 and GPU controller 4184 facilitate data transfers between GPU 3992 and other GPUs 3992, and DMA engine 4180(2) enables asynchronous memory transfers between GPU 3992 and other GPUs 3992.

[0392] In at least one embodiment, GPU 3992 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or external to GPU 3992. In at least one embodiment, GPU 3992 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3992 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3992 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 4170 and system memory controller 4182) and memory devices (e.g., shared memory 4160) that are dedicated to a component or shared between multiple components. In at least one embodiment, GPU 3992 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 4122), each of which can be private or shared among any number of components (e.g., SIMD units 4150, compute units 4140, and programmable processing units 4120).

[0393] Figure 42 shows how threads of an exemplary CUDA grid 4220 are mapped to Figure 41 4140. In at least one embodiment, and for illustration purposes only, the grid 4220 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 4220 includes, but is not limited to, (BX*BY) thread blocks 4230, each of which includes, but is not limited to, (TX*TY) threads 4240. Threads 4240 are Figure 42 Depicted as a curved arrow.

[0394] In at least one embodiment, grid 4220 is mapped to programmable processing units 4120(1), which include, but are not limited to, compute units 4140(1)-4140(C). In at least one embodiment and as shown, (BJ*BY) thread blocks 4230 are mapped to compute unit 4140(1), and the remaining thread blocks 4230 are mapped to compute unit 4140(2). In at least one embodiment, each thread block 4230 may include, but are not limited to, any number of warps, and each warp is mapped to Figure 41 4150 of different SIMD units.

[0395] In at least one embodiment, the warps in a given thread block 4230 may synchronize together and communicate via shared memory 4160 included in the associated compute unit 4140. For example, and in at least one embodiment, the warps in thread block 4230(BJ, 1) may synchronize together and communicate via shared memory 4160(1). For example, and in at least one embodiment, the warps in thread block 4230(BJ+1, 1) may synchronize together and communicate via shared memory 4160(2).

[0396] Figure 43 The present invention illustrates how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based, single-architecture alternative to proprietary languages ​​that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also allows custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs to ISO C++ that developers may be familiar with. DPC++ incorporates the Khronos Group's standard SYCL to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer that builds on the underlying concepts, portability, and efficiency of OpenCL, enabling code for heterogeneous processors to be written in a "single source" style using standard C++. SYCL enables single-source development, where C++ template functions can contain host code and device code to build complex algorithms accelerated using OpenCL, and then reuse them throughout the source code on different types of data.

[0397] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across different hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across different hardware targets, and the DPC++ compatibility tool can be used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ base toolkit includes: a DPC++ compiler for deploying applications across different hardware targets; a DPC++ library for improving productivity and performance for CPUs, GPUs, and FPGAs; a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0398] In at least one embodiment, the DPC++ programming model is used to simplify one or more aspects related to programming CPUs and accelerators by using modern C++ features to express parallelism in a programming language called Data Parallel C++. The DPC++ programming language can be used to reuse code for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single source language and clearly communicate execution and memory dependencies. Mappings in the DPC++ code can be used to transition an application to run on hardware or a set of hardware devices that optimally accelerates the workload. Even on platforms without an available accelerator, the host can be used to simplify the development and debugging of device code.

[0399] In at least one embodiment, CUDA source code 4300 is provided as input to DPC++ compatibility tool 4302 to generate human-readable DPC++ 4304. In at least one embodiment, human-readable DPC++ 4304 includes inline comments generated by DPC++ compatibility tool 4302 that guide the developer on how and / or where to modify the DPC++ code to complete the coding and tuning to the desired performance 4306, thereby generating DPC++ source code 4308.

[0400] In at least one embodiment, the CUDA source code 4300 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA source code 4300 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that is executable on a device (e.g., a GPU or FPGA) after compilation and may include one or more parallelizable workflows that can be executed on one or more processor cores of the device. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, a GPU, or another GPGPU. In at least one embodiment, host code is source code that is compiled and executable on a host. In at least one embodiment, some or all of the host code and device code may be executed in parallel across a CPU and a GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. In combination Figure 43 The CUDA source code 4300 described may be consistent with that discussed elsewhere in this document.

[0401] In at least one embodiment, DPC++ compatibility tool 4302 refers to an executable tool, program, application, or any other suitable type of tool for facilitating the migration of CUDA source code 4300 to DPC++ source code 4308. In at least one embodiment, DPC++ compatibility tool 4302 is a command-line-based code migration tool available as part of the DPC++ toolkit for porting existing CUDA source code to DPC++. In at least one embodiment, DPC++ compatibility tool 4302 converts some or all of a CUDA application's source code from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, referred to as human-readable DPC++ 4304. In at least one embodiment, human-readable DPC++ 4304 includes comments generated by DPC++ compatibility tool 4302 to indicate where user intervention may be necessary. In at least one embodiment, user intervention is required when CUDA source code 4300 calls a CUDA API for which there is no equivalent DPC++ API; other examples of requiring user intervention are discussed in more detail below.

[0402] In at least one embodiment, a workflow for migrating CUDA source code 4300 (e.g., an application or portion thereof) includes creating one or more compilation database files; migrating CUDA to DPC++ using DPC++ compatibility tool 4302; completing the migration and verifying correctness to generate DPC++ source code 4308; and compiling DPC++ source code 4308 using the DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used during Makefile execution and stores them in the compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the intercept-build command converts the Makefile commands into DPC compatibility commands.

[0403] In at least one embodiment, the intercept build is a utility script that intercepts the build process to capture compile options, macro definitions, and include paths, and writes that data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 4302 parses the compile database and applies options when migrating input sources. In at least one embodiment, the use of the intercept build is optional, but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files: commands may include necessary compile flags; directories may include paths to header files; and files may include paths to CUDA files.

[0404] In at least one embodiment, DPC++ compatibility tool 4302 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, DPC++ compatibility tool 4302 can be used as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes an interception build tool. In at least one embodiment, the interception build tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the interception build tool is used by DPC++ compatibility tool 4302 to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool 4302 generates human-readable DPC++ 4304, which can be DPC++ code, such as that generated by DPC++ compatibility tool 4302, which cannot be compiled by the DPC++ compiler and requires additional pipeline to verify the incorrectly migrated code portions, and may involve manual intervention, such as intervention by the developer. In at least one embodiment, DPC++ compatibility tool 4302 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be automatically migrated.In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0405] In at least one embodiment, DPC++ compatibility tool 4302 is capable of successfully migrating all portions of CUDA code to DPC++, and there may simply be an optional step for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, DPC++ compatibility tool 4302 directly generates DPC++ source code 4308 that is compiled by the DPC++ compiler, without requiring or utilizing manual intervention to modify the DPC++ code generated by DPC++ compatibility tool 4302. In at least one embodiment, DPC++ compatibility tool generates compilable DPC++ code that developers can optionally tune for performance, readability, maintainability, and various other considerations, or any combination thereof.

[0406] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using, at least in part, the DPC++ compatibility tool 4302. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source file includes a<cuda.h> header files and<stdio.h> header file. In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as or related to:

[0407]

[0408]

[0409]

[0410] In at least one embodiment, and in conjunction with the CUDA source files described above, DPC++ compatibility tool 4302 parses the CUDA source code and replaces the header files with the appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID, and correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0411] In at least one embodiment, and in conjunction with the CUDA source file described above, there are two vectors A and B that are initialized, and the result of the vector addition is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating CUDA code to DPC++ code, DPC++ compatibility tool 4302 converts the CUDA thread ID used to index work elements to SYCL standard addressing for work elements via local IDs. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 4302 can be optimized—for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0412] In at least one embodiment, and in conjunction with the CUDA source files described above, memory allocations are migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call, malloc_device(), to which the device and context are passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., a host and a GPU device); a device can have multiple queues to which jobs can be submitted; each device can have a context; and a context can have multiple devices and manage shared memory objects.

[0413] In at least one embodiment and in conjunction with the above CUDA source file, the main() function calls or calls VectorAddKernel() to add two vectors A and B and store the result in vector C. In at least one embodiment, the CUDA code that calls VectorAddKernel() is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler cgh passes data submitted to the queue, synchronization, and computation, and parallel_for is called for multiple global elements and multiple work items in the work group that calls VectorAddKernel().

[0414] In at least one embodiment, and in conjunction with the CUDA source files described above, CUDA calls that copy device memory and then release memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated intact without modification by the DPC++ compatibility tool 4302. In at least one embodiment, the DPC++ compatibility tool 4302 modifies the CUDA API for memory setup and / or host calls to execute the kernel on the acceleration device. In at least one embodiment, and in conjunction with the CUDA source files described above, a corresponding human-readable DPC++ 4304 (e.g., compilable) is written as or in association with:

[0415]

[0416]

[0417]

[0418] In at least one embodiment, human-readable DPC++ 4304 refers to the output generated by DPC++ compatibility tool 4302 and can be optimized in one way or another. In at least one embodiment, human-readable DPC++ 4304 generated by DPC++ compatibility tool 4302 can be manually edited by the developer after migration to improve maintainability, performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool 4302, such as the disclosed DPC++, can be optimized by removing duplicate calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by DPC++ compatibility tool 4302 to replace the use of unified shared memory with accessors. In at least one embodiment, DPC++ compatibility tool 4302 has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool 4302 is verbose because it uses generic templates to migrate CUDA code to DPC++ code that is applicable to a wide range of cases.

[0419] In at least one embodiment, the CUDA to DPC++ migration workflow includes the following steps: preparing for migration using an intercept-build script; performing the migration of the CUDA project to DPC++ using the DPC++ compatibility tool 4302; manually reviewing and editing the migrated source files to ensure completeness and correctness; and compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: the migrated API does not return error codes (CUDA code can return error codes that can later be used by the application, but SYCL uses exceptions to report errors, so error codes are not used to expose errors); DPC++ does not support CUDA compute capability-related logic; statements cannot be deleted. In at least one embodiment, scenarios where manual intervention is required in the DPC++ code may include but are not limited to: error code logic replaced with (*,0) code or commented out; equivalent DPC++ APIs are unavailable; CUDA compute capability-dependent logic; hardware-dependent APIs (clock()); missing features of unsupported APIs; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS APIs; and more.

[0420] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0421] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0422] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0423] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0424] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0425] At least one embodiment of the present disclosure may be described in terms of the following:

[0426] 1. A system comprising:

[0427] at least one processor;

[0428] at least one memory comprising instructions that, in response to being executed by the at least one processor, cause the system to at least:

[0429] selecting a set of lights from a plurality of lights associated with the virtual scene, the set of lights selected based at least in part on a first one or more random factors;

[0430] selecting a set of photons from the set of light based at least in part on a second one or more random factors, the set of photons to be used to generate a graphics frame, wherein the set of photons is selected such that data indicative of the set of photons has a total size that is less than a total size of memory predicted to be available in a processor cache; and

[0431] Pixels of the graphics frame are rendered based at least in part on the set of photons.

[0432] 2. The system of clause 1, wherein the at least one memory further comprises instructions that, in response to being executed by the at least one processor, cause the system to at least:

[0433] Additional subsets of light are selected for use in generating additional graphics frames, the additional subsets of light being selected from the plurality of lights associated with the virtual scene.

[0434] 3. The system of clause 1 or 2, wherein the at least one memory further comprises instructions that, in response to being executed by the at least one processor, cause the system to at least:

[0435] A second pixel of the graphics frame is rendered using a second subset of light selected from the set of lights.

[0436] 4. The system of any of clauses 1-3, wherein the pixel is one of a plurality of pixels in a first tile of the graphics frame, and wherein pixels in a second tile are rendered using a different set of photons.

[0437] 5. The system of any of clauses 1-4, the at least one memory further comprising instructions that, in response to being executed by the at least one processor, cause the system to at least:

[0438] A plurality of tiles of the graphics frame are rendered using the set of photons, the plurality of tiles being non-contiguous in the graphics frame, the plurality of tiles being rendered contiguously to keep the set of photons resident in the processor cache.

[0439] 6. The system of any of clauses 1-5, the at least one memory further comprising instructions that, in response to being executed by the at least one processor, cause the system to at least:

[0440] shuffling one or more lights from the set of photons into additional sets of photons; and

[0441] Additional pixels of the graphics frame are rendered using the additional set of photons.

[0442] 7. The system of any of clauses 1-6, wherein the set of photons is selected to have a total size that is less than an amount of processor cache memory available during rendering of the graphics frame.

[0443] 8. The system of any of clauses 1-7, wherein the first one or more random factors are weighted to favor selection of light based at least in part on the intensity of the selected light.

[0444] 9. A method comprising:

[0445] selecting a set of lights from a plurality of lights associated with the virtual scene based at least in part on the first one or more random factors;

[0446] Generating a graphics frame using light from the light set by at least the following steps:

[0447] selecting a set of photons from the set of light based at least in part on a second one or more random factors; and

[0448] Pixels of the graphics frame are rendered based at least in part on the set of photons.

[0449] 10. The method of clause 9, further comprising:

[0450] Additional graphics frames are generated using an additional set of lights selected from the plurality of lights associated with the virtual scene.

[0451] 11. The method according to clause 9 or 10, further comprising:

[0452] A second pixel of the graphics frame is rendered using a second subset of light selected from the set of lights.

[0453] 12. The method according to any of clauses 9-11, further comprising:

[0454] Pixels in different tiles of the graphics frame are rendered using different sets of photons.

[0455] 13. The method according to any of clauses 9 to 12, further comprising:

[0456] A plurality of tiles of the graphics frame are rendered using the set of photons, the plurality of tiles being rendered discontinuously but continuously in the graphics frame.

[0457] 14. The method according to any of clauses 9 to 13, further comprising:

[0458] The set of photons is selected such that its size is smaller than a processor cache size.

[0459] 15. The method according to any of clauses 9 to 14, further comprising:

[0460] generating the additional set of photons based at least in part on randomly selecting at least a portion of the set of photons for inclusion in the additional set of photons; and

[0461] Additional tiles of the graphics frame are generated using the additional sets of photons.

[0462] 16. The method according to any of clauses 9 to 15, further comprising:

[0463] An additional set of light subsets is generated by replacing at least a portion of the set of light subsets with one or more additional lights selected from the set of light subsets.

[0464] 17. A non-transitory computer-readable storage medium comprising instructions that, in response to being executed by at least one processor of a computing device, cause the computing device to at least:

[0465] selecting a set of lights from lights associated with the virtual scene, the set of lights being selected at least in part randomly, wherein a graphics frame is rendered based at least in part on the set of lights; and

[0466] A portion of the graphics frame is generated using a subset of photons from the set of lights, the subset of photons being at least partially randomly selected from the set of lights, wherein pixels of the portion of the graphics frame are rendered based at least in part on the set of photons.

[0467] 18. The non-transitory computer-readable storage medium of clause 17, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least:

[0468] Additional graphics frames are generated using an additional set of lights selected from the lights associated with the virtual scene.

[0469] 19. The non-transitory computer-readable storage medium of clause 17 or 18, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least:

[0470] Different sets of photons are used to render pixels in different portions of the graphics frame.

[0471] 20. The non-transitory computer-readable storage medium of any of clauses 17-19, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least:

[0472] Portions of the graphics frame are rendered using the set of photons, the portions being rendered consecutively.

[0473] 21. The non-transitory computer-readable storage medium of any of clauses 17-20, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least:

[0474] Additional sets of photons are generated based at least in part on selecting one or more lights from the set of photons.

[0475] 22. The non-transitory computer-readable storage medium of any of clauses 17-21, wherein during rendering of one or more portions of the graphics frame, a majority of the lights in the subset of lights remain resident in a processor cache.

[0476] 23. The non-transitory computer-readable storage medium of any of clauses 17-22, wherein the set of lights and subset of lights are selected based at least in part on at least one of an intensity of a selected light or a distance to a selected light.

[0477] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illuminate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0478] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0479] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0480] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “compute,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0481] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As non-limiting examples, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0482] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, a computer system, or a computer-implemented machine. The process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0483] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0484] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A system comprising: at least one processor; at least one memory comprising instructions that, in response to being executed by the at least one processor, cause the system to at least: selecting a set of virtual lighting sources from a plurality of virtual lighting sources associated with the virtual scene, the set of virtual lighting sources selected based at least in part on a first one or more random factors; selecting a subset of virtual illumination sources from the set of virtual illumination sources based at least in part on a second one or more random factors, the subset of virtual illumination sources to be used in generating a graphics frame, wherein the subset of virtual illumination sources is selected such that a total size of data indicative of the subset of virtual illumination sources is less than memory predicted to be available in a processor cache; and Pixels of the graphics frame are rendered based at least in part on the subset of virtual illumination sources.

2. The system of claim 1 , wherein the at least one memory further comprises instructions that, in response to being executed by the at least one processor, cause the system to at least: An additional subset of virtual lighting sources is selected for use in generating additional graphics frames, the additional subset of virtual lighting sources being selected from the plurality of virtual lighting sources associated with the virtual scene.

3. The system of claim 1 , wherein the at least one memory further comprises instructions that, in response to being executed by the at least one processor, cause the system to at least: A second pixel of the graphics frame is rendered using a second subset of virtual illumination sources selected from the set of virtual illumination sources. 4 . The system of claim 1 , wherein the pixel is one of a plurality of pixels in a first tile of the graphics frame, and wherein the pixel in a second tile is rendered using a different subset of virtual illumination sources.

5. The system of claim 1 , wherein the at least one memory further comprises instructions that, in response to being executed by the at least one processor, cause the system to at least: A plurality of tiles of the graphics frame are rendered using the subset of virtual illumination sources, the plurality of tiles being non-contiguous in the graphics frame, the plurality of tiles being rendered contiguously to keep the subset of virtual illumination sources resident in the processor cache.

6. The system of claim 1 , wherein the at least one memory further comprises instructions that, in response to being executed by the at least one processor, cause the system to at least: shuffling one or more virtual illumination sources from the subset of virtual illumination sources into an additional subset of virtual illumination sources; and Additional pixels of the graphics frame are rendered using the additional subset of virtual illumination sources.

7. The system of claim 1, wherein the subset of virtual lighting sources is selected to have a total size that is less than an amount of processor cache memory available during rendering of the graphics frame.

8. The system of claim 1, wherein the first one or more random factors are weighted to favor selecting a virtual lighting source based at least in part on an intensity of the selected virtual lighting source.

9. A method comprising: selecting a set of virtual lighting sources from a plurality of virtual lighting sources associated with the virtual scene based at least in part on the first one or more random factors; Generating a graphics frame using a virtual illumination source from the set of virtual illumination sources by at least the following steps: selecting a subset of virtual illumination sources from the set of virtual illumination sources based at least in part on a second one or more random factors; and Pixels of the graphics frame are rendered based at least in part on the subset of virtual illumination sources.

10. The method according to claim 9, further comprising: Additional graphics frames are generated using an additional set of virtual lighting sources selected from the plurality of virtual lighting sources associated with the virtual scene.

11. The method according to claim 9, further comprising: A second pixel of the graphics frame is rendered using a second subset of virtual illumination sources selected from the set of virtual illumination sources.

12. The method according to claim 9, further comprising: Pixels in different tiles of the graphics frame are rendered using different subsets of virtual lighting sources.

13. The method according to claim 9, further comprising: A plurality of tiles of the graphics frame are rendered using the subset of virtual illumination sources, the plurality of tiles being rendered discontinuously but continuously in the graphics frame.

14. The method according to claim 9, further comprising: A subset of the virtual illumination sources is selected whose size is smaller than a processor cache size.

15. The method according to claim 9, further comprising: generating the additional subset of virtual illumination sources based at least in part on randomly selecting at least a portion of the subset of virtual illumination sources for inclusion in the additional subset of virtual illumination sources; as well as Additional tiles of the graphics frame are generated using the additional subset of virtual illumination sources.

16. The method according to claim 9, further comprising: An additional subset of virtual illumination sources is generated by replacing at least a portion of the subset of virtual illumination sources with one or more additional virtual illumination sources selected from the set of virtual illumination sources.

17. A non-transitory computer-readable storage medium comprising instructions that, in response to being executed by at least one processor of a computing device, cause the computing device to at least: selecting a set of virtual lighting sources from virtual lighting sources associated with the virtual scene, the set of virtual lighting sources being selected at least in part randomly, wherein a graphics frame is to be rendered based at least in part on the set of virtual lighting sources; and A portion of the graphics frame is generated using a subset of virtual illumination sources from the set of virtual illumination sources, the subset of virtual illumination sources being at least partially randomly selected from the set of virtual illumination sources, wherein pixels of the portion of the graphics frame are rendered at least partially based on the subset of virtual illumination sources.

18. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least: Additional graphics frames are generated using an additional set of virtual lighting sources selected from the virtual lighting sources associated with the virtual scene.

19. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least: Pixels in different portions of the graphics frame are rendered using different subsets of virtual lighting sources.

20. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least: Portions of the graphics frame are rendered using the subset of virtual illumination sources, the portions being rendered consecutively.

21. The non-transitory computer-readable storage medium of claim 17, further comprising instructions that, in response to being executed by at least one processor of the computing device, cause the computing device to at least: An additional subset of virtual illumination sources is generated based at least in part on selecting one or more virtual illumination sources from the subset of virtual illumination sources.

22. The non-transitory computer-readable storage medium of claim 17, wherein during rendering of one or more portions of the graphics frame, a majority of the subset of virtual illumination sources remain resident in a processor cache.

23. The non-transitory computer-readable storage medium of claim 17, wherein the set of virtual illumination sources and the subset of virtual illumination sources are selected based at least in part on at least one of an intensity of a selected virtual illumination source or a distance to a selected virtual illumination source.

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