Method and system for generating calibration data for wafer analysis

Abstract

Disclosed herein is a computer-implemented method for generating calibration data usable for sample analysis. The method comprises: (i) identifying a target in an image frame belonging to a scan region of a sample; (ii) calculating a displacement of the target relative to a position of the target as given by or derived from reference data for the scan region; (iii) determining, based at least on the calculated target displacement, a value of a coordinate transformation parameter (CTP) relating coordinates of the image frame to coordinates of the scan region as given by or derived from the reference data; and (iv) using at least the CTP to obtain displacements for a plurality of segments in the image frame, thereby generating a displacement map for the image frame or at least a portion thereof.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Application No. 16 / 990593, filed August 11, 2020. The disclosure of the stated application is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This disclosure generally relates to methods and systems for generating calibration data for wafer analysis. Background Technology

[0004] Process diagnostic tools used in semiconductor manufacturing, such as inspection, metrology, and verification systems, typically feature a large field of view (FOV) to parallelize data acquisition from the sample being analyzed (e.g., a wafer, photomask, or reticle) and achieve high processing speeds (throughput). A movable stage can be used to translate the sample being inspected relative to the imaging device, allowing coverage of large areas of the sample. For example, a mechanical stage can move the wafer along a first direction, while the imaging device collects data points along a second direction perpendicular to the first direction. This enables slice-by-slice coverage of the wafer (or one or more regions of the wafer), facilitating the construction of a two-dimensional image.

[0005] As design rules shrink, analyzing smaller structures on samples becomes increasingly difficult. More stringent performance requirements are placed on analytical systems, particularly on the accuracy of pattern localization on samples. For example, wafer inspection systems will require higher localization accuracy to correlate (e.g., analytical algorithm) parameters, and more generally, the analytical algorithm, with specific locations on the wafer.

[0006] Temporal physics effects and defects exacerbate the challenge, adversely affecting positioning accuracy and playing an increasingly important role as design rules shrink. These temporal physics effects and defects include, for example, mechanical vibration, thermal fluctuations, thermal expansion of the stage, release of mechanical tension in the optical module and stage, mechatronic drift, atmospheric density instability, and jitter and / or acceleration (each configured to allow translation of the stage and / or substages along (different) corresponding directions), which in turn cause additional mechanical vibration.

[0007] Other defects may include misalignment of the stage axis. For example, the scanning wafer may be translated along a direction slightly offset relative to the wafer's y-axis (as defined by the rows of dies on the wafer). And / or, for example, the FOV of the imaging device (imager) may be slightly offset relative to the wafer's x-axis. Summary of the Invention

[0008] Aspects of this disclosure, according to some embodiments thereof, relate to methods and systems for generating calibration data for sample analysis (e.g., analysis of wafers, photomasks, or intermediate masks). More specifically, but not exclusively, aspects of this disclosure, according to some embodiments thereof, relate to methods and systems for generating position calibration data for analyzing patterned wafers.

[0009] Therefore, according to one aspect of some embodiments, a computer-implemented method is provided for generating calibration data that can be used for sample analysis. The method includes:

[0010] - Identify targets in image frames that belong to the scanned area of ​​a sample (e.g., a wafer, photomask, or intermediate mask).

[0011] - Calculate the displacement of the target relative to the position of the target as given (i.e., specified) or derived from the reference data of the scanned area.

[0012] - Determine the value of the coordinate transformation parameter (CTP) that relates the coordinates of the image frame to the coordinates of the scanned area, as given by or derived from the reference data, based at least on the calculated target displacement.

[0013] - At least the CTP is used to obtain the displacement of multiple segments in the image frame, thereby generating a displacement mapping of the image frame or at least a portion of the image frame.

[0014] According to some embodiments of the method, the CTP includes at least three independent parameters.

[0015] According to some embodiments of the method, each of the at least three independent parameters characterizes a corresponding correlation that persists on the image frame.

[0016] According to some embodiments of the method, the CTP includes one or more parameters characterizing global offset, linear scaling, fixed-angle skew, and rotation.

[0017] According to some embodiments of the method, the reference data includes one or more of the following: design data generated from scan data of the sample obtained during formulation setup, CTP and / or displacement mapping, and data obtained from scans of another sample (of the same design as the analyzed sample) or including features of an architecture similar to those in the scanned region.

[0018] According to some embodiments of the method, prior to calculating the displacement of the target, the reference data is calibrated based on the latest system coordinates, which may have already been generated taking into account previously obtained scan data (e.g., from a region scanned along the same slice). According to some such embodiments, the calibration includes rescaling the reference data coordinates.

[0019] According to some embodiments of the method, at least some of the segments have a pixel size.

[0020] According to some embodiments of the method, the sample is a patterned (first) wafer.

[0021] According to some embodiments of the method, the scanning area is located along a slice of a first chip extending through the wafer, and the method further includes repetition of the method relative to other scanning areas located along the slice of the first chip.

[0022] According to some embodiments of the method, the CTP of the scanned region and at least one of the one or more other scanned regions (i.e., at least one region) is determined with reference to one or more previously determined CTPs of the previously scanned regions along the slice.

[0023] According to some embodiments of the method, the method further includes initial operations that include optimizing (i) the height of image frames, which belong to the scan regions along the slice, and (ii) the selection of the CTP, such as to achieve the accuracy required at maximum or substantially maximum throughput.

[0024] According to some embodiments of the method, the method further includes saving the generated CTP and, optionally, displacement mappings of image frames belonging to previously scanned regions along the slice.

[0025] According to some embodiments of the method, the method further includes generating displacement maps of additional image frames belonging to additional scan regions along the slice, the additional scan regions being located in additional chips along a chip column including the first chip. The displacement maps of a first set of image frames in the additional image frames may be generated directly, at least based on a calculated displacement of the target relative to a corresponding position of the target as given by reference data, in which (i.e., in the image frame). The displacement maps of a second set of image frames may be generated, at least based on a calculated displacement of the target relative to a calibration position of a corresponding target in a corresponding image frame belonging to a scan region in a corresponding previously scanned chip (e.g., in an adjacent chip) in the chip column.

[0026] According to some embodiments of the method, the previously scanned chip is the last chip scanned.

[0027] According to some embodiments of the method, the method includes repeating the method slice by slice to generate calibration data for one or more chip columns of the wafer.

[0028] According to some embodiments of the method, the method further includes generating displacement maps of additional regions within the slice along other chips in a chip column including the first chip. For every predetermined number of chips along the chip column, the displacement map of the image frame of the next chip in the chip column is generated directly from reference data. For the remaining chips in the chip column, the displacement map of the image frame of each chip is determined at least based on calibration data of corresponding image frames in adjacent and previously scanned chips in the chip column.

[0029] According to some embodiments of the method, when a given image frame belonging to one of the scan regions or one of the additional scan regions along the slice is characterized by (i) an insufficient number of identifiable targets and / or (ii) an uneven distribution of identifiable targets, such that (i.e., in a sense) the required accuracy of the displacement mapping of the given image frame cannot be achieved solely based on the displacement of the identifiable targets in the given image frame, the displacement mapping of the given image frame is interpolated or extrapolated based on calibration data of image frames belonging to scan regions near the scan region belonging to the given image frame.

[0030] According to some such embodiments of the method, the method further includes scanning the sample.

[0031] According to some embodiments of the method, the method can be implemented during operation while the sample is being scanned.

[0032] According to some embodiments of the method, the method can be implemented without tools using the preserved scan data of the sample.

[0033] According to some embodiments of the method, the reference images have a width of at least about 100 pixels (perpendicular to the mechanical scanning direction).

[0034] According to some embodiments of the method, the (multiple) reference images have a width of at least about 1000 pixels.

[0035] According to one aspect of some embodiments, a computer-implemented method for sample analysis is provided. The method includes: generating calibration data for image frames belonging to regions along slices on a sample by performing the methods disclosed above; and using the calibration data to associate one or more defect detection algorithms with corresponding subframes in the image frames, wherein the calibration data includes CTP and / or displacement mapping of the image frames.

[0036] According to one aspect of some embodiments, a non-transitory computer-readable medium is provided. The computer-readable medium stores instructions executable by a computerized system (such as the computerized system and sample analysis system described below) to implement the method described above for generating calibration data usable for sample analysis.

[0037] According to one aspect of some embodiments, a computerized system for generating calibration data that can be used for sample analysis is provided. The system includes a displacement analysis module. The displacement analysis module is configured to:

[0038] - Calculate the displacement of the target identified in one or more image frames belonging to one or more scanned regions of the sample relative to the position of the target as given by or derived from reference data of the one or more regions.

[0039] - Determine the values ​​of coordinate transformation parameters (CTPs) that relate the coordinates of the one or more image frames to the coordinates of the scanned region, as given by or derived from the reference data of the one or more regions, based at least on the calculated target displacement.

[0040] - At least the CTP is used to determine the displacement of multiple segments in the one or more image frames, thereby generating one or more displacement maps of the one or more image frames or at least one or more portions of the one or more image frames.

[0041] According to some embodiments of the computerized system, the CTP includes at least three independent parameters.

[0042] According to some embodiments of the computerized system, each of the at least three independent parameters characterizes a corresponding correlation that persists in each of the image frames.

[0043] According to some embodiments of the computerized system, the CTP includes one or more parameters characterizing global offset, linear scaling, fixed-angle skew, and rotation.

[0044] According to some embodiments of the computerized system, the reference data includes one or more of the following: design data generated from scan data of the sample obtained during formulation setup, CTP and / or displacement mapping, and data obtained from scans of another sample (of the same design as the analyzed sample) or including features of an architecture similar to those in the one or more scan regions.

[0045] According to some embodiments of the computerized system, prior to calculating the displacement of the target, the reference data is calibrated based on the latest system coordinates, which may have already been generated taking into account previously obtained scan data (e.g., from a region scanned along the same slice). According to some such embodiments, the calibration includes rescaling the reference data coordinates.

[0046] According to some embodiments of the computerized system, at least some of the segments have a pixel size.

[0047] According to some embodiments of the computerized system, the sample is a patterned (first) wafer.

[0048] According to some embodiments of the computerized system, the scanning area is located along a slice of a first chip extending through the wafer, and the displacement analysis module is further configured to generate calibration data relative to image frames of other scanning areas located along the slice, respectively belonging to the first chip.

[0049] According to some embodiments of the computerized system, the CTP of the scan area and at least one of the one or more other scan areas is determined with reference to one or more previously determined CTPs of the previously scanned areas along the slice.

[0050] According to some embodiments of the computerized system, the displacement analysis module is further configured to perform initial operations including optimizing (i) the height of image frames, which belong to the scanned regions along the slice, and (ii) the selection of the CTP, such as to achieve the accuracy required at maximum or substantially maximum throughput.

[0051] According to some embodiments of the computerized system, the computerized system is configured to store the generated CTP and, optionally, displacement maps of image frames belonging to previously scanned regions along the slice.

[0052] According to some embodiments of the computerized system, the computerized system is further configured to generate displacement maps of additional image frames belonging to additional scan regions along the slice, the additional scan regions being located in additional chips along a chip column including the first chip. The displacement maps of a first set of image frames in the additional image frames may be generated directly, at least based on a calculated displacement of the target relative to a corresponding position of the target as given by reference data, whereby (i.e., in the image frame). The displacement maps of a second set of image frames may be generated, at least based on a calculated displacement of the target relative to a calibration position of the corresponding target in a corresponding image frame belonging to a scan region in a corresponding previously scanned chip (e.g., in an adjacent chip) within the chip column.

[0053] According to some embodiments of the computerized system, the previously scanned chip is the last chip scanned.

[0054] According to some embodiments of the computerized system, the displacement analysis module is further configured to generate calibration data belonging to scan areas on the wafer slice by slice, thereby generating calibration data for one or more chip columns of the wafer.

[0055] According to some embodiments of the computerized system, the displacement analysis module is further configured to generate displacement maps of additional regions within the slice along other chips in a chip column including the first chip. For every predetermined number of chips along the chip column, the displacement map of the image frame of the next chip in the chip column is generated directly from reference data. For the remaining chips in the chip column, the displacement map of the image frame of each chip is determined at least based on calibration data of corresponding image frames in adjacent and previously scanned chips in the chip column.

[0056] According to some embodiments of the computerized system, the displacement analysis module is further configured to interpolate or extrapolate the displacement mapping of the image frame based on or also taking into account calibration data of image frames belonging to scan regions near the scan region belonging to the image frame when the image frame is characterized by (i) an insufficient number of identifiable targets and / or (ii) an uneven distribution of identifiable targets, such that the required accuracy of the displacement mapping of the image frame cannot be achieved solely based on the displacement of the identifiable targets in the image frame.

[0057] According to some embodiments of the computerized system, the displacement analysis module is further configured to generate the displacement map during runtime while the wafer is being scanned. According to some such embodiments, the computerized system may be configured to receive scan data of the wafer from a wafer inspection tool scanning the wafer in real-time or near real-time (and generate the displacement map based on the scan data). Alternatively, the computerized system may be configured to scan the wafer.

[0058] According to some embodiments of the computerized system, the imager of the computerized system has a field of view (FOV) of at least about 100 pixels.

[0059] According to some embodiments of the computerized system, the imager of the computerized system has a field of view (FOV) of at least about 1,000 pixels.

[0060] According to some embodiments of the computerized system, the computerized system can be configured to generate (a plurality of) the displacement maps without tools using the stored scan data of the sample.

[0061] According to one aspect of some embodiments, a sample analysis system (e.g., a wafer analysis system) is provided, the sample analysis system including the computerized system described above for generating calibration data.

[0062] According to some embodiments of the sample analysis system, the sample analysis system further includes:

[0063] - A scanning device, the scanning device including an imager and configured to scan a region of a sample.

[0064] - A processing and memory circuitry system, comprising the computerized system and a sample analysis module (e.g., a wafer analysis module). The sample analysis module is configured to detect potential defects in one or more regions of the area, taking into account displacement mappings generated by the displacement analysis module of the computerized system.

[0065] According to some embodiments of the sample analysis system, the imager is or includes an optically based imager.

[0066] According to some embodiments of the sample analysis system, the optical-based imager includes a large field-of-view scanning tool (i.e., corresponding to at least one thousand pixels).

[0067] According to some embodiments of the sample analysis system, the imager includes a scanning electron microscope.

[0068] According to some embodiments of the sample analysis system, the processing and memory circuitry further includes an image processing module. The image processing module is configured to:

[0069] - Receive image frame data of one or more regions imaged by the imager;

[0070] - Identify resolvable targets within the one or more regions.

[0071] - Send the image data of the identified target to the displacement analysis module.

[0072] According to one aspect of some embodiments, a non-transitory computer-readable medium is provided. The computer-readable medium includes instructions executable by a system's processing circuitry to generate calibration data that can be used for sample analysis. The instructions are configured to cause the system to:

[0073] - Identify targets in image frames corresponding to the scanned area of ​​the sample.

[0074] - Calculate the displacement of the target relative to the position of the target as given by or derived from the reference data of the scanned area.

[0075] - Determine the value of the coordinate transformation parameter (CTP) that relates the coordinates of the image frame to the coordinates of the scanned area, as given by or derived from the reference data, based at least on the calculated target displacement.

[0076] - At least the CTP is used to obtain the displacement of multiple segments in the image frame, thereby generating a displacement mapping of the image frame or at least a portion of the image frame.

[0077] According to one aspect of some embodiments, a wafer analysis method incorporating the above-described methods is provided. The wafer analysis method may be a process diagnostic task, which may be any one of wafer inspection, metrology, and / or verification.

[0078] It will be apparent to those skilled in the art that the techniques, systems, methods, and computer program products of this disclosure are applicable not only to wafer analysis but also to the analysis of photomasks and intermediate masks used in semiconductor manufacturing. Therefore, the scope of this disclosure is to be understood to cover not only wafer analysis but also the analysis of photomasks and intermediate masks used in wafer manufacturing.

[0079] Some embodiments of this disclosure may include some, all, or none of the advantages described above. One or more other technical advantages will be apparent to those skilled in the art based on the accompanying drawings, specification, and claims. Furthermore, although specific advantages have been listed above, various embodiments may include all, some, or none of the listed advantages.

[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In case of any conflict, the patent specification (including the definitions) shall prevail. Unless the context clearly specifies otherwise, as used herein, the indefinite articles “a” and “an” mean “at least one” or “one or more”.

[0081] Unless otherwise specifically stated, as will be apparent from this disclosure, it should be understood that, according to some embodiments, terms such as “processing,” “computing,” “calculating,” “determining,” “estimating,” “evaluating,” “measuring,” etc., may refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or transform data representing physical (e.g., electronic) quantities within the registers and / or memory of the computing system into other data similarly representing physical quantities within the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0082] Embodiments of this disclosure may include devices for performing the operations described herein. These devices may be specifically configured for the desired purpose, or they may include (or a plurality of) general-purpose computers selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in a computer-readable storage medium such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, magneto-optical disks), read-only memory (ROM), random access memory (RAM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, or any other type of medium suitable for storing electronic instructions and capable of being coupled to a computer system bus.

[0083] The processes and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems and programs can be used in accordance with the teachings herein, or it may prove convenient to construct more specialized devices to perform the desired methods(s). The desired structures(s) for various such systems(s) emerge from the following description. Furthermore, embodiments of this disclosure are described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0084] The various aspects of this disclosure can be described in the general context of computer-executable instructions (such as program modules) that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The disclosed embodiments can also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules can reside on both local and remote computer storage media (including memory storage devices). Attached Figure Description

[0085] This document describes some embodiments of the present disclosure with reference to the accompanying drawings. The description, together with the drawings, makes it apparent to those skilled in the art how some embodiments can be practiced. The drawings are for illustrative purposes and are not intended to show structural details of embodiments more detailed than necessary for a basic understanding of the present disclosure. For clarity, some objects depicted in the drawings are not drawn to scale. Furthermore, two different objects in the same drawing may be drawn to different scales. In particular, the scale of some objects may be greatly exaggerated compared to other objects in the same drawing.

[0086] In the attached diagram:

[0087] Figure 1A An example displacement mapping according to some embodiments is schematically depicted;

[0088] Figure 1B A chip on a wafer according to some embodiments is schematically depicted;

[0089] Figure 2 Linear coordinate transformations related to wafer analysis are schematically depicted according to some embodiments;

[0090] Figures 3A-3E An example coordinate transformation relating the coordinates of an image frame parameterized to a scanned wafer region and the coordinates of a reference data region parameterized to the wafer region, according to some embodiments, is illustrated.

[0091] Figure 3FAccording to some embodiments, from Figures 3A-3E The graphical representation of the displacement mapping obtained by coordinate transformation;

[0092] Figure 4A This is a block diagram of a computerized system for generating calibration data for wafer inspection, according to some embodiments.

[0093] Figure 4B According to some embodiments Figure 4A A block diagram of the system's displacement analysis module;

[0094] Figure 5A Image frames schematically depicting scanned areas on a (patterned) wafer according to some embodiments;

[0095] Figure 5B and 5C It is based on some embodiments corresponding to Figure 5A A schematic graphical representation of the reference data for the image frame;

[0096] Figure 5D The illustration schematically depicts segments divided into pieces according to some embodiments. Figure 5A Image frames;

[0097] Figure 5E According to some embodiments, from Figure 5B and Figure 5C The graphical representation of the displacement mapping obtained by coordinate transformation;

[0098] Figure 6 A scan slice extending through a chip according to some embodiments is schematically depicted;

[0099] Figure 7 The illustration schematically depicts adjacent slices along a column of chips on a wafer scanned in alternating directions, according to some embodiments.

[0100] Figure 8 A flowchart illustrating a coordinate transformation-based method for generating calibration data for wafer analysis, according to some embodiments, is shown; and

[0101] Figure 9 A flowchart illustrating a computerized system and method using the present disclosure to calibrate system coordinates during wafer scanning at runtime, according to some embodiments, is presented. Detailed Implementation

[0102] The principles, uses, and implementation methods of the teachings herein can be better understood by referring to the accompanying specifications and figures. After carefully reading the specifications and figures presented herein, those skilled in the art will be able to implement the teachings without excessive effort or experimentation. In the figures, the same reference numerals consistently refer to the same parts.

[0103] In the specification and claims of this application, the words "comprising," "having," and their forms are not limited to members of the list that the words can be associated with.

[0104] As used herein, the term "substantially" can be used to specify that a first characteristic, quantity, or parameter is close to or equal to a second or target characteristic, quantity, or parameter. For example, the first object and the second object can be said to have "substantially the same length" when the length of the first object is equivalent to at least 80% (or some other predefined threshold percentage) and no more than 120% (or some other predefined threshold percentage) of the length of the second object. In particular, the case where the first object and the second object have the same length is also covered in statements that the first object and the second object have "substantially the same length".

[0105] According to some embodiments, the target quantity may refer to an optimal parameter, which can in principle be obtained using mathematical optimization software. Therefore, for example, when the value of the parameter is equal to at least 80% of the maximum possible value (or some other predefined threshold percentage), it can be said that the value adopted by the parameter is "substantially equal to" the maximum possible value that the parameter can adopt. In particular, the case where the value of the parameter is equal to the maximum possible value is also covered in the statement that the value adopted by the parameter is "substantially equal to" the maximum possible value that the parameter can adopt.

[0106] As used herein, the term "about" can be used to specify the value of a quantity or parameter (e.g., the length of an element) as a continuous range of values ​​within a neighborhood (and including) a given (statement) value. According to some embodiments, "about" can specify the value of a parameter as between 80% and 120% of a given value. For example, the statement "the length of the element is about 1 m" is equivalent to the statement "the length of the element is between 0.8 m and 1.2 m." According to some embodiments, "about" can specify the value of a parameter as between 90% and 110% of a given value. According to some embodiments, "about" can specify the value of a parameter as between 95% and 105% of a given value.

[0107] As used herein, the terms “substantially” and “about” may be used interchangeably according to some embodiments.

[0108] For ease of description, a three-dimensional Cartesian coordinate system (with orthogonal axes x, y, and z) is introduced in some of the accompanying figures. It should be noted that the orientation of the coordinate system relative to the depicted object may vary in each figure. Additionally, the symbol ⊙ can be used to indicate an axis pointing "outside the page," while the symbol... It can be used to represent an axis pointing "inside the page".

[0109] Referring to the accompanying drawings, in the flowchart, optional operations may appear in boxes depicted by dashed lines.

[0110] introduction

[0111] This document discloses systems and methods for generating displacement maps of (multiple) scan regions on a wafer (both at runtime and "tool-free"). According to some embodiments, the disclosed systems and methods aim to address temporal instabilities that adversely affect runtime wafer analysis (e.g., due to temporal physics effects and defects listed in the background art). Ideally, in the absence of temporal instabilities, data points (collected by an imaging device for scanning the wafer) would form a temporally fixed grid. In contrast, temporal instabilities typically result in a temporally non-rigid grid (of the collected data points). The resulting uncertainty in the (positional) coordinates of each grid point is on the order of tens or even hundreds of nanometers, and thus violates design rules for advanced technology nodes.

[0112] As used herein, a computational task (e.g., the generation of (multiple) displacement maps) can be considered to run "tool-free" when implemented after a scan in which scan data for processing in the computational task has been obtained. Therefore, a computational task implemented relative to the scan data of the sample is tool-free when executed after a sample scan (in which scan data was obtained).

[0113] Figure 1A An example displacement map 10 according to some embodiments is schematically depicted. It shows regions belonging to the scanned wafer area (such as...). Figure 1B Image frame 12 (region 110a) is shown in the image. Frame 12 is shown divided into frame segments 14, as indicated by the dashed grid 16 superimposed on frame 12. Each frame segment 14 may correspond to a single pixel. Also superimposed on frame 12 is a double-dotted grid 26. The double-dotted grid 26 is generated based on reference data (such as a CAD-based simulation image (not shown)) corresponding to the wafer region represented by frame 12. The double-dotted grid 26 is divided into reference data (RD) segments 24. The reference data specifies the expected positions of the segments according to a default coordinate system available before the start of the scan.

[0114] It can be seen that grids 16 and 26 differ from each other due to physical effects and defects, as described above and further detailed below. Each RD segment 24 in the RD segments 24 of the dotted-dashed grid 26 corresponds to a corresponding frame segment from frame segment 14. The superposition of the (dotted-dashed) grid 26 on the (dashed) grid 16 provides a graphical representation of the displacement of each frame segment 14 relative to its corresponding reference data position. For example, the displacement of frame segment 14c relative to its reference data position (indicated by RD segment 24c) is indicated by arrow 32c. Similarly, the displacement of frame segment 14d relative to its reference data position (indicated by RD segment 24d) is indicated by arrow 32d. In particular, it can be seen that arrows 32c and 32d differ from each other in length and orientation, thus reflecting the sensitivity of the disclosed method and system to displacement and deformation of the scanned image (image frame) at the subpixel level.

[0115] Now for reference Figure 1B , Figure 1B Also used to introduce the term. The description refers to a chip 102a on a wafer 100 (wafer 100 is shown only partially) such as a wafer used for manufacturing integrated circuits and other microdevices. As used herein, unless otherwise specified, the term "wafer" will be used to refer to a "processed" or "patterned" wafer (including electronic circuitry fabricated thereon). Wafer 100 includes a plurality of chips 102 (of which only chip 102a is shown in full). Chips 102 may be arranged in rows of chips (columns of chips) on the wafer. Chips 102a are depicted in a widely implemented rectangular form, but it should be understood that other forms may also be applied. Chips 102 may also include partial edge chips residing on the circular wafer boundary. Similar to the term "wafer," unless otherwise specified, the term "chip" will be used to refer to a small piece of semiconductor material on which electronic circuitry has been fabricated.

[0116] Figure 1B The edge 104 of the chip 100 is also indicated.

[0117] The wafer 100 is configured to be diced (“sliced”) into individual chips. Each chip may contain a copy of the same electronic circuitry, or some chips may each contain different electronic circuitry. The scope of this disclosure is to be understood to cover both options.

[0118] Each column of chips to be scanned (chip column) is divided into adjacent (scanning) slices 106, such as adjacent slices 106a and 106b, which extend (along the y-axis) through chip 102a. According to some embodiments, each slice 106 of the slices 106 may correspond in width to or substantially correspond to the x-dimension of the field of view (FOV) of the imaging device. In other words, each slice 106 of the slices 106 may represent a portion of the “coverage” of the wafer 100 due to the corresponding scan path along the wafer 100. It should be noted that, although in Figure 1B In this context, slice 106 is depicted as straight, but the scan path is not limited to a straight line and can follow any curve as needed, such as in the case of a helical scan in an R-θ stage. According to some embodiments ( Figure 1B (Not depicted in the image), adjacent slices may partially overlap to ensure complete (i.e., 100%) coverage of the chip. Different regions 110 on chip 102a are indicated. One region 110, namely region 110a, is shown as divided (divided) into segments 112. Segments 112 are shown as rectangular, but it should be understood that other shapes may also be applied. Each segment 112 may correspond to an image frame (such as...) belonging to region 110a. Figure 1A A group of adjacent pixels or even a single pixel in frame 12.

[0119] Depending on the scanning recipe, the chip can be scanned partially or completely. Furthermore, the dimensions of the chips 102 can vary (due to their design). Specifically, according to some embodiments, the widths of chips along the same chip column can differ. Therefore, the width of a slice can vary along its length. More specifically, according to some embodiments, the imaging device can be configured to adjust its FOV during operation based on the width of the chip currently being scanned. Additionally, the spacing between chips on the wafer (e.g., wafer 100) can also vary. Depending on the scanning recipe, areas between chips, such as… Figure 1B Region 120 in the middle.

[0120] To achieve high throughput, a large field of view (FOV) (e.g., thousands to tens of thousands of pixels) can be used to parallelize data capture and analysis. However, the larger the FOV, the greater the variation in the optical paths traveled by light rays returning from different locations (field points) on the wafer (e.g., reflected, scattered). In particular, the larger the FOV, the greater the variation in the length of the optical paths traveled by different light rays, and therefore, the greater the distortion of image frames due to the temporal physics effects listed above.

[0121] Reliably and efficiently accounting for these distortions is a challenge. That is, being able to reliably and efficiently associate each segment (e.g., each pixel) of an image frame with the reference data location of that segment (i.e., the location determined by the reference data). Additional related challenges arise when the image frame is not densely and / or uniformly filled with resolvable targets or does not contain (multiple) unique patterns: specifically, the image frame may include one or more unresolvable subframes (which do not contain any resolvable targets), each of which may include, for example, hundreds of thousands or even millions of pixels.

[0122] To this end, this disclosure teaches how to obtain a coordinate transformation that relates the coordinates of an image frame belonging to a scanned wafer area to the coordinates of reference data describing the wafer, particularly the scanned wafer area. According to some embodiments, the coordinate transformation allows each pixel of the image frame to be associated with corresponding reference data coordinates (e.g., in micrometers or nanometers), thereby obtaining a displacement map. The displacement map can specify the displacement of each pixel relative to its reference data position, thereby generating calibration data at even single-pixel resolution (in a sense, the calculated displacement of a pixel may differ from that of each of its surrounding pixels).

[0123] Based on the calculated displacement of the (identifiable) target in the image frame relative to its reference data position, a coordinate transformation and thus a displacement map are generated. Advantageously, the generated displacement map can also take into account subframes of the image frame that do not contain any registered targets, such as subframes consisting of unresolved arrays, low-contrast features, saturation features, etc.

[0124] To specify a coordinate transformation, a value for the coordinate transformation parameter {C} should be provided. For example, a two-dimensional global translation (offset) can be specified by two values, representing translation along, for example, the x-axis and y-axis. The selection of the set of coordinate transformation parameters (CTP) can be based on prior knowledge of the architecture and temporal behavior of the analysis system and the characteristics of the wafer.

[0125] For a given set of CTPs (e.g., global displacements and rotations), the value of the CTP can be obtained based on the calculated target displacement (also known as "displacement data"). More precisely, displacement data fitting can be used to obtain the (optimal) value of the CTP. According to some embodiments, high-accuracy displacement mapping can be achieved even when constrained to linear coordinate transformations. Figure 2 The described linear coordinate transformations include global offsets (e.g., along the x and y axes), linear scaling (along the x and y axes), fixed-angle skew (relative to the x and y axes), and rotations.

[0126] For example, global offset may be caused by inaccurate placement of the wafer on the stage (assuming the stage plane is parallel to the xy plane). Linear scaling may be caused by changes in magnification or scan speed. Assuming the stage is intended to translate along the y-axis, x-skew may be caused by a slight (angular) offset in the direction of stage translation or low-frequency jitter parallel to the x-axis (of the stage), and y-skew may be caused by wafer rotation or low-frequency jitter parallel to the y-axis (of the stage). Note that in the first order, rotation and skew are indistinguishable.

[0127] More generally, it will be understood that the CTP set may include any transformation parameters characterizing the correlations that persist on the image frame (i.e., along the height and width of the image frame).

[0128] Figures 3A-3E An example coordinate transformation M is schematically depicted, relating the coordinates of an image frame scanning a wafer region to the coordinates of reference data for the wafer region. More specifically, Figure 3A A rectangular region A (marked by dashed lines) on the chip of the wafer intended to be scanned is schematically depicted (such as region 110a on wafer 100). Targets T1, T2, T3, and T4 within region A are also depicted. The origin O of the coordinate system (i.e., the point whose coordinates are given by x = 0 and y = 0) is also indicated.

[0129] For ease of description and to make the discussion more specific, we assume a constant x-skewness, without other physical effects or defects. (Reference) Figure 3B The dashed arrow g represents the actual direction of movement of the stage on which the scanning wafer is placed, and thus indicates the degree of skew. Due to the skew, region A will only be partially scanned. Figure 3C The scanning region S is schematically depicted; S is the area that is actually scanned. Since the skew is constant in the scanning region S (i.e., it does not change during the "grab" time of the scanning region S), the scanning region S has the shape of a parallelogram.

[0130] Figure 3D A (image) frame I, obtained from an imaging device and corresponding to the scanned region S, is depicted. Frame I is shown as being divided into pixels P. Figure 3D The horizontal and vertical axes are labeled u and v, respectively, to emphasize that frame coordinates can often differ from wafer coordinates (i.e., Figure 3B (x and y in the coordinate system). It also indicates the origin of the frame coordinate system. (That is, the point whose coordinates are given by u=0 and v=0). The target relative to its position Figure 3C The displacement of the position in the middle is obvious.

[0131] Figure 3EA schematic depiction is shown of a “deformed” image I' corresponding to frame I when presented in reference coordinates, or in this example, wafer coordinates equivalent to said reference coordinates. The deformed image I' can be obtained from frame I using a coordinate transformation M (or conversely, depending on how the coordinate transformation M is defined).

[0132] Figure 3E The text also indicates the pixel P corresponding to frame I. A and P B The deformed image I' contains pixels P′A and P′B.

[0133] As detailed below, the coordinate transformation M is obtained using a numerical fitting method based on the calculated displacement of the target within frame I. Figure 3E Zhong also gave instructions Figure 3D The targets T1, T2, T3, and T4 are indicated to illustrate their displacements. More specifically, if in Figure 3D In the vector (u1, v1), the position of target T1 is given by the vector (u1, v1), while... Figure 3E The position of the target T1 is given by the vector (x1, y1), and the displacement of T1 is given by the difference between the two vectors: (u1-x1, v1-y1).

[0134] Figure 3F This is a schematic graphical depiction of the displacement map D obtained from the coordinate transformation M. More specifically, frame I is depicted as being divided into pixels P. Within each pixel P, a corresponding arrow is drawn, indicating the direction and relative magnitude of the pixel's displacement relative to its position in image I'.

[0135] Please refer to this again. Figures 3A-3E The width L of frame I (and region A) may correspond to (i) the full width (i.e., x-dimension) of the FOV of the imaging device used to scan the wafer, or (ii) a fraction (i.e., a portion) of the width of the FOV. As detailed below, the height of frame I (and region A) may be selected, such as to achieve the desired (or desired) accuracy of the displacement mapping D (e.g., such that the displacement of each pixel is determined to the desired accuracy).

[0136] system

[0137] According to one aspect of some embodiments, a computerized system is provided for generating calibration data that can be used to inspect a wafer (such as wafer 100). Figure 4AA block diagram of such a computerized system, namely computerized system 400, is shown according to some embodiments. According to some embodiments, system 400 may be combined with or connected to an inspection machine for inspecting wafers (e.g., during different stages of manufacturing system 400). According to some embodiments, system 400 may be integrated into an inspection system, some or all of the functions and / or features described herein have been incorporated into said inspection system. According to some embodiments, and as... Figure 4A As depicted, the system 400 can be additionally configured to perform process diagnostic tasks, such as wafer inspection, metrology, and / or verification.

[0138] System 400 includes a processing circuitry system 402 (which includes one or more processors) and a memory circuitry system 404 (which includes one or more memories and is functionally associated with the processing circuitry system 402). The processing circuitry system 402 includes at least a displacement analysis module 410. The displacement analysis module 410 is configured to determine the displacement of segments within an image frame belonging to a scanned wafer region.

[0139] As used herein, the term “processing and memory circuitry” may be used together to refer to a processing circuitry and a memory circuitry that is functionally associated with the processing circuitry, such as processing circuitry 402 and memory circuitry 404.

[0140] More specifically, the displacement analysis module 410 is configured to determine the values ​​of coordinate transformation parameters (CTPs) for a specified coordinate transformation that correlates a first coordinate set with a second coordinate set. The first coordinate set parameterizes an image frame of the scanned wafer region. The second coordinate set parameterizes a corresponding region specified by reference data of the wafer (possibly after rescaling according to the latest system coordinates, as described below). The coordinate transformation is configured to take into account temporal physical effects and defects affecting the wafer and setup during wafer scanning, as well as defects that may have already existed in the wafer before scanning (e.g., warpage due to induced stress during manufacturing). As explained above, physical effects and defects “appear” in the image frame. To remove defects, the image frame is calibrated.

[0141] The memory circuit system 404 may include non-volatile and volatile memory components. The memory circuit system 404 may store instructions executable by the displacement analysis module 410 to determine the value of the CTP, as described above. According to some embodiments, the memory circuit system 404 may be configured to serve as a "tracking" database and temporarily store the CTP and, optionally, displacement maps of image frames (generated by the displacement analysis module 410). Specifically, the memory circuit system 404 may be configured to temporarily store displacement maps of image regions densely filled with resolvable targets. The stored displacement maps can be used to generate displacement maps of sparsely filled adjacent image regions, as described below. Figure 6 As explained in the description.

[0142] According to some embodiments, the processing circuit system 402 further includes an image processing module 414. According to some embodiments, the processing circuit system 402 further includes a wafer analysis module 416. The functions of the image processing module 414 and the wafer analysis module 416 are described below.

[0143] Each of the displacement analysis module 410, image processing module 414, and wafer analysis module 416 may be implemented by one or more processors. According to some embodiments, each of the one or more processors may be dedicated to a module and independent of those processors in other modules. Alternatively, according to some embodiments, one or more processors may be “shared” by some modules within the module. The modules listed above may also include software processing modules and / or firmware processing modules.

[0144] According to some embodiments, system 400 further includes a controller 420, a movable stage 422, and an imager 424 (e.g., an imaging device). The controller 420 is functionally associated with the stage 422, the imager 424, and the processing circuitry system 402. More specifically, the controller 420 may be configured to control and synchronize the operation and function of the modules and components listed above during wafer scanning. For example, the stage 422 may be configured to support the sample to be inspected, such as wafer 100, and mechanically translate the sample along a scan path set by the controller 420, which may also control the imager 424. The stage 422 may include a multi-axis sub-stage that allows translation of the wafer along any scan path (including curved scan paths) given by the controller 420.

[0145] Imager 424 is configured to scan a wafer, such as wafer 100. Imager 424 may include scanning, imaging, and / or inspection devices as known in the field of wafer analysis. More specifically, imager 424 may include a light source for generating a light beam configured to strike the wafer, and one or more sensors configured to detect light returning from the wafer. According to some embodiments, the generated light beam may be coherent, for example, when the light source is a laser. According to some embodiments, the light beam may be incoherent. According to some embodiments, imager 424 may have a large FOV (e.g., on the order of thousands to tens of thousands of pixels). As used herein, according to some embodiments, scanning tools such as imager 424 are referred to as having a large FOV when the FOV corresponds to at least one thousand pixels, five thousand pixels, or ten thousand pixels. Each possibility corresponds to a separate embodiment. According to some embodiments, imager 424 may be configured to generate multiple scan points, for example, using diffractive optics.

[0146] According to some embodiments, imager 424 may operate based on multi-point scanning. Alternatively, according to some embodiments, imager 424 may operate based on flood illumination, in which case imager 424 may include a one-dimensional or two-dimensional pixel array camera.

[0147] Alternatively or additionally, imager 424 may include a charged particle source for generating a beam of charged particles configured to impact a wafer, and one or more sensors configured to detect charged particles deflected from the wafer. According to some embodiments, imager 424 may be or include a multi-beam and / or multi-channel charged particle imaging system. According to some embodiments, imager 424 includes a scanning electron microscope (SEM).

[0148] For example, to perform a scan, wafer 100 may be placed on a movable stage such as stage 422. In such embodiments, wafer 100 is translated by stage 422 during scanning of wafer 100. For example, stage 422 may be moved along one or more of the x-axis, y-axis, and z-axis depending on the requirements of the analysis scheme and scanning recipe. (Here, the x-axis and y-axis are defined as “axis lines” parallel to wafer 100, and the z-axis is defined as perpendicular to wafer 100). Alternatively or additionally, imager 424 may be repositioned to image different portions of wafer 100. Scanning may be based on scan instructions sent from (scanning) recipe database 430 to imager 424.

[0149] According to some embodiments, an alignment module (e.g., in controller 420 or a controller different from controller 420) may be used to align the wafer 100 on stage 422, for example, during setup or before the start of scanning (of the wafer). According to some embodiments, alignment may be achieved using anchor points from reference data.

[0150] Imager 424 is configured to transmit the thus obtained scanned image data (image frame data) of wafer 100 to image processing module 414. Image processing module 414 is configured to identify predefined targets (which may be defined by the scan recipe) within the image frame belonging to a scanned wafer region (such as region 110a of wafer 100). More specifically, according to some embodiments, image processing module 414 may be configured, for each target in the image frame, to: (i) calculate the expected position of the target based on the latest system coordinates and the target's reference data position, (ii) generate a cropped image of the target with surrounding boundaries, and (iii) send the cropped image to displacement analysis module 410.

[0151] According to some embodiments, the image processing module 414 may be configured to magnify the surrounding boundaries of the cropped image, such as to ensure that the target will be virtually entirely within the cropped image. The degree of magnification may be determined taking into account the level of inaccuracy of the latest system coordinates (i.e., the system's current coordinate system).

[0152] The displacement analysis module 410 is configured to receive reference data corresponding to the target image from the recipe database 430, and calibrate the reference data according to the latest system coordinates if necessary. Specifically, calibration may include rescaling the reference data coordinates. The displacement analysis module 410 is further configured to (i) calculate a (maximum) matching score between the cropped image and the corresponding (possibly rescaled) reference data using a pattern recognition method (e.g., image correlation), (ii) compare the matching score with a (predefined) threshold, and if the matching score exceeds the threshold, (iii) calculate the displacement of each target in the target based on the cropped image of the target (and its position in terms of the latest system coordinates) received from the image processing module 414 and the corresponding reference data. Therefore, when the calculated matching score is greater than the threshold, the target can be considered to have been "identified".

[0153] According to some embodiments, during scanning, the displacement analysis module 410 can send calibration data to the controller 420 for runtime correction and / or adjustment of scan parameters (at the beginning of scanning a new slice), such as the origin of the chip column, scan path, etc. In particular, the calibration data can be used to update system coordinates.

[0154] According to some embodiments, and as Figure 4BAs depicted, the displacement analysis module 410 may include a target displacement module 410a and a displacement mapping module 410b. The target displacement module 410a is configured to receive a (cropped) image of a target located in the scanned wafer region from the image processing module 414. The target displacement module 410a is further configured to receive reference data corresponding to the target (e.g., from the recipe database 430). The target displacement module 410a can use the received image and reference data to calculate the displacement of the target relative to its reference data position.

[0155] The displacement mapping module 410b is configured to receive the calculated target displacement from the target displacement module 410a. The displacement mapping module 410b is further configured to determine the value of the CTP based on the calculated target displacement. Based on the determined value of the CTP, the displacement mapping module 410b can generate a high (spatial) resolution displacement map.

[0156] As explained below in the Methods section, the calibration data generated by System 400 (belonging to the wafer) can be used to improve the detection of potential defects on the wafer. In particular, the higher positioning accuracy provided by the calibration data allows for better correlation of analytical parameters, and more generally, analytical algorithms, with specific locations on the wafer. The calibration data can also be used to improve the accuracy of reporting the location of detected defects. Additionally, the calibration data may be relevant to tasks beyond defect detection, such as improving the positioning accuracy of defect inspection tools or metrology tools, or other inspection equipment used to inspect wafers (e.g., SEM or multi-beam inspection equipment).

[0157] Without limiting the scope of this disclosure in any way, according to some embodiments, system 400 can be used for process diagnostic tasks. Specifically, according to some embodiments, system 400 can be used for inspection tasks, where a wafer or one or more chips are partially or completely scanned to detect potential defects. Additionally or alternatively, according to some embodiments, system 400 can be used for verification tasks, in which it is determined whether a potential defect is of interest. Verification tasks typically require higher resolution scanning compared to inspection tasks and may therefore utilize electron beam inspection. Such inspection tools typically inspect small portions of a wafer at higher resolution (but lower throughput).

[0158] Whenever the term “inspection” or its derivatives are used in this disclosure, it will be understood that the inspection referred to is not limited in terms of the resolution or size of the inspected area(s). In particular, it will be understood that, according to some embodiments, system 400 may be suitable for inspection tools and lower-resolution wafer inspection tools, etc. It will also be understood that this applies to the term “analysis,” which, according to some embodiments, is used interchangeably with the term “inspection.”

[0159] Figure 5AAn image frame 500 is schematically depicted of a scanned area (such as region 110a) of a (patterned) chip according to some embodiments. Frame 500 may contain any number of pixels between thousands and hundreds of millions of pixels. According to some embodiments, the width of the scanned area may correspond to the full width of the field of view (FOV) of the imager 424. According to some embodiments, the width of the scanned area may correspond to a portion of the width of the FOV of the imager 424.

[0160] Figure 5B The schematic depiction illustrates the corresponding embodiment according to some embodiments. Figure 5A A reference image of the scanned area. As is known in the art, a reference image can be obtained from corresponding reference data (such as design data) by performing mathematical transformations on the reference data to generate its graphical representation. More specifically, Figure 5B The “Reference Data” (RD) region 500’ corresponding to frame 500 is schematically depicted. Compared to frame 500, RD region 500’ is depicted as “reduced” along the x and y axes. RD region 500’ can be generated using the corresponding reference data and the latest system coordinates. The latest system coordinates specify the pixel width and pixel height, as estimated before capturing frame 500.

[0161] The double-headed arrow w and the difference interval Δw indicate the contraction of RD region 500' along the x-axis. The double-headed arrow h and the difference interval Δh indicate the contraction of RD region 500' along the y-axis. Although frame 500 is linearly expanded compared to RD region 500', it should be understood that this particular variant choice (between frame 500 and RD region 500') is intended as a simple and straightforward example to facilitate a more concrete description and presentation of the discussion.

[0162] As used herein, the term "reference data" should be broadly interpreted to encompass any data indicating (patterning) the physical design of a wafer and / or data derived from the physical design (e.g., through simulation, geometry, and Boolean operations). According to some embodiments, the wafer's reference data may include the wafer's "design data," such as CAD data in various formats. Design data may be provided in different formats, such as GDSII format, OASIS format, etc.

[0163] According to some embodiments, the reference data for the wafer may include data obtained by fully or partially scanning the wafer during recipe setup. Furthermore, a first wafer manufactured according to a specific design may be scanned during recipe setup, and the obtained scan data may be processed to generate reference data or additional reference data for use with subsequently manufactured wafers having the same design as the first wafer. Such “self-generated” reference data is essential when design data is unavailable, but it can also be beneficial even when design data is available.

[0164] According to some embodiments, when generating the displacement map of an image frame, reference data of the wafer can be used in conjunction with data obtained at runtime. For example, during runtime, scan data of one chip or multiple chips with the same architecture can be used to generate the displacement map of another chip with the same architecture, as detailed below.

[0165] Furthermore, according to some embodiments, calibration data generated relative to the scanned first region can be used to generate a displacement map of the scanned second region. Specifically, in embodiments where the second region is scanned shortly after (e.g., immediately) the first region and positioned near the first region (e.g., adjacent to the first region along the same slice). For example, values ​​of global offset and constant skew determined relative to the first region can be used to generate the displacement map of the second region. Therefore, the computational load involved in generating the CTP of the second region is reduced (because the number of CTPs that must be calculated is reduced).

[0166] More specifically, reference data or supplementary reference data used to analyze multiple wafers of a particular architecture can be generated, for example, by partially or completely scanning one or more sample wafers among multiple sample wafers. Image processing tools can be applied to the acquired scan data to discover (or find) unique patterns that are “easily” identifiable (detectable) within a corresponding search area around them. The discovered unique patterns (or more precisely, the image and its exact location) can be stored, for example, in a recipe database 430 for future use as reference data. As used herein, a pattern may be referred to as “unique” even if it is singular only along one axis (e.g., the x-axis or y-axis). In particular, a pattern that exhibits uniqueness only along one axis (e.g., the x-axis) can still be used as reference data and can be used for x-axis calibration.

[0167] According to some embodiments, the image processing module 414 and the displacement analysis module 410 may be further configured for “self-generation” of reference data (particularly the discovery of easily identifiable registration targets), as described above, specifically when design data is unavailable.

[0168] According to some embodiments, the reference data may also include reference data belonging to other types of wafers (i.e., wafers with different architectures than the wafer to be analyzed) or obtained from such wafers, but these wafers are known to include patterns commonly shared with the wafer to be analyzed.

[0169] Refer again Figure 5AWithin frame 500, a plurality of frame targets 510 (i.e., targets imaged in frame 500) are schematically depicted and indicated. Each frame target 510 is shown as being enclosed within a corresponding dashed box (e.g., 32×32 pixels) from dashed box 512. For example, frame target 510a (from frame target 510) is enclosed within dashed box 512a. Each frame target 510 may include a pattern that is relatively easily recognizable in the environment of frame target 510, for example, by image processing module 414 (using a suitable image processing algorithm).

[0170] The corresponding RD target in RD region 500' (from RD target 510') can be associated with each frame target 510 in frame target 510. RD target 510' in Figure 5B and 5C The target is shown as being enclosed within a dashed box 512'. For example, target RD 510a' (from target RD 510') is enclosed within a dashed box 512a'. Figure 5C The RD region 500' is schematically depicted with a dashed box 512 superimposed on it (which represents the position of frame target 510). The superposition of the dashed box 512 on the RD region 500' visually illustrates the displacement of frame target 510 relative to RD target 510'.

[0171] As a non-limiting example, and for clarity, all frame targets 510 are shown as rectangles (i.e., dashed box 512 is a rectangle) and have the same dimensions. However, it should be understood that other options are also possible. According to some embodiments, the height and / or width of the frame targets may differ from each other. More generally, any shape composed of pixels is feasible in principle.

[0172] Displacement analysis module 410 (e.g., target displacement module 410a) is configured to calculate the displacement of each frame target 510 in the frame targets 510 relative to the corresponding RD target (from RD target 510'). According to some embodiments, displacement analysis module 410 may employ image registration methods known in the art to calculate the displacement of each frame target 510 (e.g., frame target 510a). For example, by maximizing the cross-correlation coefficient between frame target 510a and RD target 510a' (which corresponds to frame target 510a).

[0173] The calculated displacement of a target (frame) represents the displacement of the target relative to the position in which the target "should already be" according to reference data. In other words, the calculated displacement represents the displacement of the target relative to the position it would already be in the absence of physical effects and defects.

[0174] It should be noted that in implementations where the format of the scanned data (e.g., the format of the image frame) and the format of the reference data are different, intermediate processing of at least one of these formats may be required before performing image registration.

[0175] Additional details and the different ways in which the displacement analysis module 410 can perform image registration are described below. Figure 7 The descriptions are presented in the description and methods section.

[0176] exist Figure 5D In the diagram, as indicated by the dashed grid 522, frame 500 is shown as being segmented (divided) into frame segments 520 (i.e., sub-images of frame 500). According to some embodiments, the size and / or shape of the frame segments 520 may differ from one another to accommodate various image distortions. According to some embodiments, each frame segment 520 may correspond to a pixel. According to some embodiments, at least some or all of the segments may correspond to multiple pixels, such that all pixels in the segment share the same size and shape; in this case, the segmentation of frame 500 into frame segments 520 may be performed by the displacement analysis module 410.

[0177] The displacement analysis module 410 (e.g., displacement mapping module 410b) is further configured to generate a displacement mapping for the displacement of each frame segment 520 (or at least some frame segments 520) in the specified frame segment 520 based on the calculated displacement of the frame target 510. More specifically, the displacement analysis module 410 is configured to use the calculated displacement of the frame target 510 to obtain a coordinate transformation relating the coordinates of the parameterized frames 500 (i.e., u and v) to the coordinates of the parameterized RD region 500' (i.e., x and y). In other words, the displacement analysis module 410 is configured to determine the value of each parameter C in the CTP set {C} of the parameterized coordinate transformation.

[0178] As a non-restrictive example intended to make the discussion more specific, in Figures 5A-5D In this context, u = (1 + α)·x and v = (1 + β)·y, where α > 0 and β > 0. Therefore, the coordinate transformation can be characterized by the values ​​of two parameters α and β (i.e., {C} = {α, β}). Specifically, the scaling of the axes can be different (i.e., α ≠ β). That is, the pixel size along the wafer translation axis (i.e., the y-axis) can be determined by the stage motion, while the pixel size along the other axis (i.e., the x-axis) can be determined by the optical magnification.

[0179] It will be understood that either α or β can typically be negative. Setting α and β to positive values ​​is purely to make the signs of α and β correspond to expansion (rather than contraction), and... Figures 5A-5D Consistent. Using existing wafer analysis systems, α and β are typically less than 10. -3 .

[0180] The Methods section discusses various methods (e.g., fitting methods) for obtaining CTP values.

[0181] Figure 5E The displacement mapping corresponding to the coordinate transformations specified above, according to some embodiments, is schematically depicted. Frame segment 520 is indicated by dashed grid 522. Further indicated are RD segments 520', which correspond to frame segment 520. That is, each RD segment 520' in RD segments 520' can be obtained by applying coordinate transformations to the corresponding segments from frame segment 520. RD segments 520' are indicated by double-dotted grid 522'. Some frame segments 520 are "filled" with a first pattern to facilitate differentiation. Some RD segments 520' are "filled" with a second pattern to facilitate differentiation.

[0182] According to some embodiments, the position of a segment can be specified by the segment's "centroid" coordinates. Therefore, it can be said that frame segment 520... (i，j) (From frame segment 520) is positioned at the intersection of a first horizontal line (not indicated) extending from the middle of the i-th row of frame segment 520 and a first vertical line (not indicated) extending from the middle of the j-th column of frame segment 520. Similarly, it can be said that RD segment 520' (k,i) (From RD fragment 520') Positioned at the intersection of the second horizontal line (not indicated) extending from the middle of the k-th row of RD fragment 520' and the second vertical line (not indicated) extending from the middle of the l-th column of RD fragment 520'. Frame fragment 520 (i,j) The displacement (i.e., relative to the corresponding RD segment 520') (i,j) The displacement of the "center of mass" can be given by: Δx i =u i -x i =α·x i And Δy j =v j –y j =β·y j .

[0183] Displacement arrow A (7,8) and A (10,14) Frame fragment 520 is shown respectively. (7,8) and 520 (10,14) The displacement. Displacement arrow A (7,8) and A (10,14) Each of the points in the graph points from the centroid of the corresponding RD segment to the centroid of its corresponding (frame) segment.

[0184] Figure 6A chip 602 (such as chip 102a) according to some embodiments is depicted. A slice 606 of chip 602 and adjacent regions 610 (such as region 110) along the length of slice 606 are also depicted. A motion arrow m indicates the scanning direction (i.e., the direction of movement of stage 422). A close-up view of region 610a shows its architecture and the target 630a therein. System 400 is configured to achieve the above in Figures 5A-5E The process described in the description is used to generate the displacement mapping of the image frame belonging to region 610.

[0185] Region 610b is also indicated. According to some embodiments, image frames belonging to region 610b cannot generate a displacement map with the required accuracy. According to some embodiments, this may be because region 610b includes an insufficient number of registration targets, in a sense too few to generate a displacement map with the required accuracy. Alternatively, according to some embodiments, this may be because the distribution of registration targets in region 610b may not be uniform enough to generate a displacement map with the required accuracy (i.e., to ensure that the displacement of all frame segments is determined to the required accuracy).

[0186] According to some embodiments, when generating the displacement map corresponding to region 610b, the displacement analysis module 410 may be configured to additionally take into account previously obtained calibration data (e.g., a CTP set) corresponding to regions in slice 606 located near region 610b. In other words, the displacement analysis module 410 may be configured to generate the displacement map corresponding to region 610b using extrapolation techniques based on calibration data from other regions along slice 606.

[0187] According to some embodiments, when generating a displacement map corresponding to region 610b, the displacement analysis module 410 may be configured to additionally take into account calibration data corresponding to all regions scanned along slice 606 and on chip 602 prior to region 610b (or at least all of said regions from which displacement maps can be generated with the desired accuracy from image frames from the regions).

[0188] According to some embodiments, when generating a displacement map corresponding to region 610b, the displacement analysis module 410 may be configured to additionally take into account calibration data corresponding to regions along slices 606 on one or more previously scanned chips located in the same chip array.

[0189] According to some embodiments, calibration data (or at least CTP) corresponding to the scanned area may be temporarily stored in memory circuitry 404 (e.g., in a volatile memory component of memory circuitry 404). Displacement analysis module 410 (more specifically, displacement mapping module 410b) may be configured to request some or all of the stored CTP and / or displacement mappings from memory circuitry 404 when assigned a task to generate displacement mappings corresponding to regions including an insufficient number of registration targets. According to some embodiments, the stored calibration data may be deleted from memory circuitry 404 once it is no longer used for extrapolation and / or interpolation purposes. In particular, according to some embodiments, the stored CTP may be deleted after a time interval greater than the characteristic timescale (coherence time) of the associated time-physical effects (multiple) affecting the wafer or setup (and parameterized by the CTP).

[0190] Optionally, according to some embodiments, the generation of the displacement map of region 610b may be delayed to also take into account calibration data of the region scanned along slice 606 after region 610b (from which the displacement map can be generated with the desired accuracy). In other words, the displacement analysis module 410 may be further configured to use interpolation techniques to generate the displacement map of region 610b based on calibration data from the regions above and below region 610b along slice 606.

[0191] Also refer to Figure 7 During the scanning of chip columns on a wafer, the chip columns can be scanned slices after slicing in alternating directions (e.g., from the “bottom” of the wafer to the “top” of the wafer and from the top to the bottom), as indicated by arrows u and d. Figure 7 In the description, terms such as “top,” “bottom,” “above,” “below,” “right,” and “left” should be referenced from the accompanying drawings (i.e., including the attached images). Figure 7 The orientation of the element (as defined by the page) can be understood as follows: Therefore, when the first element is closer to the top of the page than the second element, it can be said that the first element is above the second element.

[0192] As previously discussed, the displacement analysis module 410 is configured to determine the CTP value associated with a pair of coordinate sets: a first coordinate set in the pair parameterizes an image frame of the scanned wafer region (i.e., an image frame belonging to the scanned wafer region), while a second coordinate set can be used as a "reference". According to some embodiments, the second coordinate set (in the pair of coordinate sets) can also parameterize a second image frame. The second image frame can be a previously scanned wafer region (e.g., region 710") that corresponds to a wafer region (e.g., region 710') in the image frame parameterized by the first coordinate set. In particular, the previously scanned wafer region (depicted in the image frame parameterized by the second coordinate set) can be located in a chip (e.g., chip 702') adjacent to a chip (e.g., chip 702") that includes the wafer region depicted in the image frame parameterized by the first coordinate set.

[0193] For example, chips 702' and 702" are adjacent and positioned along slice 706 of chip column 704 of wafer 700 (such as wafer 100). Depending on defects, chips 702' and 702" share the same architecture. Slice 706 is shown scanned from top to bottom (as indicated by arrow d). Depending on defects, regions 710' and 710" are "corresponding" regions in the sense of sharing the same architecture. Region 710" is scanned before region 710'.

[0194] According to some embodiments, the coordinate transformation is determined by identifying a target in an image frame belonging to region 710' and calculating its displacement relative to the position of the corresponding target in an image frame belonging to region 710' (e.g., by maximizing the correlation coefficient of the target's image, as explained above). Based on the calculated target displacement, the value of CTP is determined. CTP can then be used to obtain the displacements of multiple segments in the image frame belonging to region 710' relative to their corresponding positions in the image frame belonging to region 710', thereby generating a displacement mapping 710' of the image frame belonging to region 710'.

[0195] The obtained coordinate transformation is configured to take into account both temporal and permanent physical effects and defects, which manifest as variations between image frames belonging to regions 710” and 710’. Therefore, image frames belonging to region 710” are used to generate a displacement map corresponding to region 710’. Similarly, image frames belonging to region 710”’ corresponding to region 710” can be used to generate a displacement map corresponding to region 710”. Region 710”’ is located on chip 702”’ (on slice 706), chip 702”’ is located adjacent to chip 702”’ and is situated above chip 702”’ on chip column 704.

[0196] Conversely, in a slice scanned from the bottom to the top of chip column 704, such as slice 706' which is the leftmost slice of chip column 704, image frames belonging to the region on chip 702' can be used to generate a displacement map of the corresponding region on chip 702", and image frames belonging to the region on chip 702" are used to generate a displacement map of the corresponding region on chip 702"'.

[0197] Finally, the coordinate transformation belonging to the "first scan" region along the slice (i.e., the region in the bottom chip when the slice is scanned from bottom to top, or the region in the top chip when the slice is scanned from top to bottom) can associate the coordinates of the image frame of the parameterized (first scan) region with the coordinates of parameterized reference data (such as design data for the first scan region). For example, the CTP of the first scan region 710t (which corresponds to regions 710', 710" and 710"') in the top chip 702t of chip column 704 can associate its image frame with its reference data.

[0198] According to some embodiments, the wafer analysis module 416 is or includes a defect detection module. The wafer analysis module 416 may be configured, for example, as part of a chip-to-chip (D2D) or cell-to-cell (C2C) defect detection scheme, taking into account the generated displacement mapping (correlated with the coordinates of the corresponding region of the image frame). Additionally, the wafer analysis module 416 may be configured to apply a specific defect detection algorithm to the corresponding subframe within the image frame based on the generated displacement mapping.

[0199] Alternatively, according to some embodiments, the displacement analysis module 410 may be configured to determine a set of CTPs relating the coordinates of image frames along all corresponding regions of the slice (e.g., regions 710', 710" and 710"', and along the remainder of the regions along slice 706) to a common (and individual) coordinate set. The common coordinate set may parameterize reference data, such as design data (which is common to all regions because they correspond to each other). The reference data may be stored in a recipe database, such as recipe database 430. According to some such embodiments, where the wafer analysis module 416 is or includes a defect detection module, the wafer analysis module 416 may be configured as part of a chip-to-database (D2DB) defect detection scheme, taking into account the displacement mapping (which has already been generated relative to the common coordinate set). Furthermore, the wafer analysis module 416 may be configured to apply a specific defect detection algorithm to the corresponding subframes within the image frames based on the generated displacement mapping.

[0200] Additionally, according to some embodiments, one or more CTPs associated with non-transient effects, such as a fixed offset in the stage translation direction, can be “transferred” from the scanned slice to the subsequent scanned slice(s), thereby potentially improving accuracy.

[0201] According to some embodiments, the two methods described above for generating displacement maps (i.e., via chip-to-chip or cell-to-cell comparison, or via chip-to-database comparison) can be combined. For example, according to some such embodiments, some CTPs can correlate the coordinates of two image frames, each parameterized at runtime, while other CTPs can correlate corresponding image frames obtained at runtime (in particular, corresponding image frames of regions of intermediate chips in a chip array) with corresponding reference data such as design data.

[0202] As a non-limiting example, assume that the (first) distance between chip 702' and bottom chip 702b is equal to the (second) distance between chip 702" (which is adjacent to 702') and top chip 702t. That is, assume that the number of chips between chip 702' and bottom chip 702b is equal to the number of chips between chip 702" and top chip 702t. Displacement mappings of image frames belonging to regions in chip 702' and bottom chip 702b along a slice (e.g., slice 706') scanned from bottom to top can be generated using reference data (such as design data). Displacement mappings of image frames belonging to regions along these same slices (i.e., scanned from top to bottom) in the remaining parts of the chips in chip column 704 can be generated based on image registration relative to corresponding image frames belonging to previously scanned regions in one or more chips positioned below them.

[0203] For example, the CTP of an image frame along a slice scanned from bottom to top in chip 702” can be generated based on image registration relative to a corresponding image frame of a previously scanned region in chip 702”. Similarly, the CTP of an image frame along a slice scanned from bottom to top in chip 702” can be generated based on image registration relative to a corresponding image frame of a previously scanned region in chip 702”. Likewise, the CTP of an image frame along a slice scanned from bottom to top in each chip located between bottom chip 702b and chip 702’ can be generated based on image registration relative to a corresponding image frame of a previously scanned region in the corresponding adjacent chip located below it.

[0204] It should be noted that for each image frame belonging to the region of the slice scanned from bottom to top in chip 702', the displacement of the (frame) target is calculated relative to the (frame) target position as given by the reference data of the corresponding region (which may be rescaled based on the latest system coordinates). In contrast, for each image frame belonging to the region of a slice scanned from bottom to top in chip 702", the displacement of the (frame) target relative to the calibration position of the corresponding (frame) target in the image frame belonging to the previously scanned region of chip 702' is calculated. However, it is important to emphasize that, not only in the former case but also in the latter case, reference data is taken into account when calculating the target displacement (and therefore the displacement mapping), because in the above example, the calibration position (the target displacement is calculated relative to said calibration position) is calculated (directly) based on the reference data (determined by rescaling). Therefore, the displacement mapping of the image frames belonging to chip 702" (which is generated based on the calculated displacement of the (frame) target (in the image frame) relative to the calibration position of the corresponding (frame) target in the corresponding image frame belonging to chip 702') can be said to be derived from the reference data.

[0205] Similarly, the displacement mapping of the image frame belonging to chip 702”' (which is generated based on the calculated displacement of the (frame) target (in the image frame) relative to the calibrated position of the corresponding (frame) target within the corresponding image frame belonging to chip 702”) can be said to be derived from the reference data. Since the calibrated target position itself is derived from the reference data, the displacement of the target (in the image frame belonging to chip 702”') relative to said position is calculated as explained in the previous paragraph.

[0206] More generally, the target displacement calculated relative to the calibration position of the corresponding target can be said to be derived from reference data. Similarly, the CTP and displacement mapping generated based on the target displacement calculated relative to the calibration position of the corresponding target can be said to be derived from reference data.

[0207] Typically, in any "chain" (i.e., sequence) of displacement maps generated based on registered image frames relative to each other, the displacement map of the "first" image frame in the chain can be generated based on reference data. Therefore, it can be said that all displacement maps are derived from the reference data. It can be said that the displacement map of the first image is generated (obtained) directly from the reference data. It can be said that the displacement maps of the rest of the frame are generated indirectly from the reference data because calculations for inter-image registration are involved.

[0208] continue Figure 7The description suggests that a displacement mapping of image frames belonging to regions along a top-to-bottom scanned slice (e.g., slice 706) in chip 702” and top chip 702t can be generated using reference data (such as design data). The displacement mapping of image frames belonging to regions along these same slices (i.e., top-to-bottom scanned slices) in the remainder of the chips in chip column 704 can be generated based on image registration relative to corresponding image frames belonging to previously scanned regions in one or more chips positioned above them.

[0209] For example, the CTP of an image frame belonging to a region of a slice scanned from top to bottom in chip 702' can be generated based on image registration relative to a corresponding image frame of a previously scanned region in chip 702"". Similarly, the CTP of an image frame belonging to a region of a slice scanned from top to bottom in each chip located between bottom chip 702b and chip 702" can be generated based on image registration relative to a corresponding image frame of a previously scanned region in the corresponding adjacent chip located above it.

[0210] It should be noted that the accuracy of displacement mappings for image frames generated based on displacement mapping chains (where each displacement mapping has been generated using calibration data along the corresponding scanned area of ​​the slice and the previously scanned area) can decrease with the length of the chain. On the other hand, when considering that displacement mappings are generated as part of, for example, a defect inspection scheme, and chip-to-chip or cell-to-cell image registration is implemented by default (i.e., in any case) for defect detection purposes, the computational cost of generating displacement mappings directly from reference data can be relatively high.

[0211] Therefore, according to some embodiments, in order to balance the above considerations (and simultaneously achieve the required or desired accuracy), for a predetermined number of chips, the displacement mapping of the image frames of the next chip (to be scanned) can be generated directly from reference data (such as design data), while the displacement mapping of the image frames of the remaining chips can be generated based on image registration relative to the corresponding image frames from the respective previous (and possibly adjacent) scanned chips.

[0212] method

[0213] Figure 8 A flowchart is shown of a computerized method 800 for generating calibration data that can be used for wafer analysis, according to some embodiments. Method 800 can be implemented using a system configured to generate calibration data that can be used for wafer analysis, such as system 400.

[0214] According to some embodiments, method 800 includes:

[0215] - Operation 810, wherein a target is identified in an image frame (e.g., frame 500) of a first region (e.g., region 110a) on a chip of a wafer (e.g., wafer 100). Corresponding reference data may be used to identify the target.

[0216] - Operation 820, wherein the displacement of the target (i.e., the image of the target in the image frame) relative to the position of the corresponding target as given by or derived from the reference data of the target.

[0217] - Operation 830, wherein the value of CTP relating the coordinates of the image frame to the coordinates of the reference data is determined based at least on the target displacement calculated in operation 820.

[0218] - Operation 840, wherein (at least) determined values ​​of CTP are used to obtain displacements of multiple segments (e.g., pixels) in an image frame, thereby generating a displacement map of the image frame or at least a portion of the image frame.

[0219] - Optional operation 850, in which CTP and optionally other acquired calibration data can be saved.

[0220] - Optional operation 860, in which operations 810 to 850 are repeated continuously for additional regions (image frames). These regions can be located along slices extending through the chip.

[0221] Operation 810 may be implemented by an image processing module such as image processing module 414 or the like. Each of operations 820, 830, and 840 may be implemented by a displacement analysis module such as displacement analysis module 410 or the like. In particular, according to some embodiments, operation 820 may be implemented by a target displacement module such as target displacement module 410a or the like. According to some such embodiments, operations 830 and 840 may be implemented by a displacement mapping module such as displacement mapping module 410b or the like.

[0222] Each target to be identified in operation 810 may (i) form a unique pattern along one or both of the x-axis and y-axis within its environment, and (ii) exhibit high contrast along one or both of the x-axis and y-axis. The targets to be identified may be specified by a scan recipe. The scan recipe may include identification information for each target. The identification information associated with a target may be a cropped image of the target obtained during recipe setup, multiple representative cropped images of the target, a CAD simulation image, or other parametric values ​​of image pattern recognition properties that can be used for identification purposes. The identification information may be stored in a (scanned) recipe database such as recipe database 430.

[0223] On the one hand, the larger the number of registration targets used in operation 810, the greater the resulting noise suppression (i.e., the averaging of time and / or local measurement noise), and therefore the more accurate the corresponding determination of CTP and displacement mapping in operations 830 and 840. On the other hand, the larger the number of registration targets used in operation 810, the greater the computational load, which may cause scan delays, resulting in lower throughput, and / or potentially requiring additional computational resources. Therefore, according to some embodiments, when the chip or one or more regions on the chip are characterized by a high density of registration targets, only a subset of the registration targets may be used in operation 810 (provided that the subset is sufficient to achieve the required accuracy). The number and selection of registration targets (to be used in operation 810) can be determined during recipe setup.

[0224] In operation 820, the reference data can be calibrated based on the latest system coordinates before calculating the displacement. Specifically, the reference data coordinates can be rescaled according to the latest system coordinates.

[0225] According to some embodiments, in operation 820, the displacement of the target (i.e., the image of the target in the image frame) can be calculated to subpixel precision. For example, using image correlation techniques, a correlation coefficient between the target image and its reference image (obtained from reference data describing the target) can be calculated for the relative displacement between two images. The subpixel displacement can then be obtained by interpolating the correlation coefficients and taking the maximum value. If the format of the scan data differs from the format of the reference data, intermediate processing of at least one of them may be required before calculating the correlation coefficient.

[0226] According to some embodiments, in operation 820, the displacement of the target can be obtained by calculating the displacement of the target relative to the corresponding position of the target as specified by reference data (possibly after rescaling). In this case, it can be said that the displacement (and therefore, CTP and displacement mapping) is obtained directly from the reference data. According to some embodiments, the displacement of the target can be obtained by calculating the displacement of the target relative to the calibration position of the corresponding target in the corresponding image frame. In this case, it can be said that the displacement (and therefore, CTP and displacement mapping) is obtained (or derived) indirectly from the reference data, as described above (in... Figure 7 (As described in the description) regarding the displacement mapping chain.

[0227] In operation 830, fitting methods (optimization algorithms) known in the art, such as least squares regression and the Nelder-Mead downhill simplex method, can be used to extract CTP{C} from the calculated target displacement. This minimizes the difference between the calculated target displacement and the corresponding displacement, as specified by the "trial" coordinate transformation. In this regard, it should be noted that fast fitting methods have the advantage of not reducing the throughput of the inspection tool. Different sets of CTPs can be selected before analyzing new types of wafers (e.g., those with different chip geometries and different pattern types) to optimize computation time while simultaneously meeting accuracy requirements. (Typically, accuracy requirements reflect the intricacy of the pattern on the wafer.) Typically, the goal is to achieve a minimum set of important CTPs with associated errors within the required accuracy.

[0228] According to some embodiments, CTP corresponds to the following form of linear coordinate transformation:

[0229] x→u=T x +S x ·(xx c )+Φ x ·y,

[0230] y→v=T y +S y ·(yy c )+Φ y ·x.

[0231] Here, T x and T y Parameterize the global translation along the x-axis and y-axis respectively, S x and S y Parameterize the linear scaling along the x-axis and y-axis respectively, and Φ x and Φ y Parameterize the x and y skews separately. Due to Φ x and Φ y It is a constant (i.e., independent of coordinates within the image region), and the skew described by the above coordinate transformation is uniform (at a fixed angle). When constrained to a sufficiently small angle (i.e., when constrained to first order in x and y), any rotation about an axis parallel to the z-axis can be “absorbed” into Φ. x and / or Φ y Therefore, no rotation coefficients appear in the above equations. Coordinates x and y are reference coordinates, i.e., they parameterize the RD region of the image frame, while coordinates u and v parameterize the image frame. c and y c Mark the center of the RD region.

[0232] It should be noted that the choice of CTP can depend on the size (e.g., height) of the image frame for which the displacement mapping is to be generated. More specifically, the larger the image frame size, the more complex the coordinate transformation (relating the displacement of the frame segment to its reference data position) may be, thus increasing the number of CTPs required to achieve the desired (or expected) accuracy.

[0233] The size of a segment can be determined based on the desired (spatial) resolution of the image frame. Each segment may include multiple pixels. When maximum resolution is required, each segment will correspond to a single pixel. According to some embodiments, the lower the required resolution, the lower the accuracy required for displacement mapping, which means that relatively fewer targets can be displaced and / or fewer CTPs can be used when generating the displacement mapping.

[0234] According to some embodiments, the CTP set may include additional parameters (in addition to the six listed in the equations above). Specifically, according to some embodiments, the CTP set may include any parameters associated with the continuous transformation, which can help account for the displacement of a segment relative to its reference data position throughout the image frame. According to some embodiments, to further reduce residuals, experimental design methods or other methods such as machine learning-based methods can be used to evaluate the importance of a particular CTP. The option of incorporating additional parameters to meet accuracy requirements or further reduce residuals reflects the flexibility of the disclosed methods.

[0235] According to some embodiments, the width of an image frame corresponds to or is included in the field of view (FOV) of an imager (such as imager 424). Specifically, the width of an image frame may correspond only to a portion of the imager's FOV. That is, the image frame may depict a scan region whose width is smaller than the width of a scan slice that includes the scan region. According to some embodiments, each segment of an image frame corresponds to a single pixel.

[0236] According to some embodiments, in operation 860, for a given m (where m is an integer greater than 1), the m-th repetition can be implemented for the (m+1)-th region adjacent to the m-th region where the (m-1)-th repetition can be implemented. According to some embodiments, at least some of the regions in operation 860 may overlap.

[0237] According to some embodiments, such as where method 800 includes operation 860, method 800 may further include operations where the number of slice-related image frames on the chip is predetermined in order to meet desired criteria (e.g., the required accuracy of the displacement mapping). Fixing the number of image frames corresponds to determining the height(s) of the image frames(s). As mentioned above, the higher the required accuracy, the greater the number of CTPs that may be necessary to generate the displacement mapping with the required accuracy. In particular, higher accuracy may require taking into account additional CTPs characterized by shorter coherence times, which may correspondingly limit the height of the image frames (so that the correlation exhibited by the additional CTPs persists across the entire y-axis of each image frame). According to some embodiments, the height(s) of the image frames(s) and the selection of CTPs can be optimized to achieve the required accuracy of the displacement mapping at maximum throughput.

[0238] The additional slice repeat method 800 can be used, such as scanning one or more areas of the wafer or scanning the entire wafer.

[0239] According to one aspect of some embodiments, method 800 can be implemented as part of a process diagnostic task such as wafer inspection, metrology, and / or verification.

[0240] According to one aspect of some embodiments, a wafer analysis method is provided. The wafer analysis method may include, for example, determining the presence of potential defects on the wafer or examining potential defects in a provided list of potential defects. The wafer analysis method is performed with reference to calibration data generated according to method 800. In other words, the method includes method 800. The method may be implemented using a system such as system 400. In particular, a displacement analysis module such as displacement analysis module 410 (and an image processing module such as image processing module 414) may be used to generate calibration data from the acquired scan data. A wafer analysis module such as wafer analysis module 416 may be used to perform the analysis.

[0241] It should be noted that the disclosed method can be applied at any stage of the wafer manufacturing process, where the imager is able to identify patterns on the wafer.

[0242] Figure 9 A flowchart 900 illustrates, according to some embodiments, the calibration (i.e., update) of system coordinates (i.e., the system's coordinate system) during wafer scanning implemented using a system such as system 400. At the start of scanning the wafer or one or more regions of the wafer, a default coordinate system 902 is adopted, which serves as the initial coordinate system for the wafer. The default coordinate system 902 may be stored in a database 906 (such as a recipe database 430).

[0243] A default coordinate system 902 can be sent to the system's alignment module. In operation 910, the alignment module can utilize the default coordinate system 902 to align the wafer relative to the axis of the stage on which the wafer is placed (e.g., stage 422) such that the wafer array is parallel to the direction of stage translation during scanning. A new system coordinate system 914 is generated by modifying the default coordinate system 902 to account for the wafer alignment. As described below, the system coordinate system 914 is repeatedly updated during wafer scanning.

[0244] Before scanning begins, in operation 918, the mechanical scanning parameters, specified by the scanning recipe and initially relative to the default coordinate system 902, can be adjusted according to the latest (i.e., current) system coordinates 914. The mechanical scanning parameters may specify, for example, the scan path. More generally, at the beginning of scanning each slice, operation 918 is performed repeatedly, as detailed below.

[0245] The scanning of each slice can be performed as described above in method 800 and Figure 6 This is implemented as described in the description. For each resolvable capture (image) frame, a target displacement 922 is calculated. According to some embodiments, the target displacement 922 may be calculated by a processing circuitry system such as processing circuitry system 402 using reference data from database 906. That is, by calculating the displacement of each identified target (e.g., frame target 510a) in the capture frame relative to the position of the target as specified by reference data (e.g., RD ​​target 510a') and latest system coordinates 914. In particular, RD regions (e.g., RD ​​region 500') corresponding to the capture frame (e.g., image frame 500) may be positioned and aligned relative to the latest system coordinates 914. Targets may be identified by an image processing module such as image processing module 414. Target displacement 922 may be calculated by a displacement analysis module such as displacement analysis module 410, and more precisely by a target displacement module such as target displacement module 410a.

[0246] According to some alternative embodiments, for a given capture frame of the last scanned region, at least some of the target displacements 922 can be calculated based on the (corresponding) calibration frames of the earlier scanned regions. The earlier scanned regions may have the same design as the last scanned region. In particular, according to some embodiments, the earlier scanned regions may be located along the same slice as the last scanned region, but on a chip adjacent to the chip that includes the last scanned region.

[0247] Next, using a displacement analysis module such as displacement analysis module 410, and more precisely, a displacement mapping module such as displacement mapping module 410b, the target displacement 922 is used to calculate CTP 926. Then, CTP 926 is used to generate the displacement mapping 930 of the captured frame.

[0248] CTP 926 and / or displacement mapping 930 can be used to update system coordinates 914. According to some embodiments, the update may include a short-term correction 934 to system coordinates 914. The short-term correction 934 to system coordinates 914 is temporary and is intended to account for temporal physical effects affecting the wafer and / or setup (e.g., stage 422 and / or imager 424). For example, one or more CTPs from CTP 926 can be used to temporarily update system coordinates 914, characterized by (i) having been determined for the last captured frame (or multiple most recent captured frames), and (ii) being associated with one or more physical effects having a sufficiently long coherence time, such as affecting one or more frames to be captured next. The temporary update associated with each such CTP can be “released” (i.e., removed) after a time interval greater than the corresponding coherence time. These CTPs can then be recalculated based on the latest scan data (i.e., scan data belonging to a newer captured frame, such as the last captured frame).

[0249] When a slice scan is completed, operation 918 can be repeated before starting the scan of the next slice, taking into account long-term physical effects and defects affecting the wafer and / or setup detected during the scan of the last slice. More generally, the estimates of long-term physical effects previously detected during slice scanning can be improved. These updated estimates can be used in operation 918 to adjust the mechanical scanning parameters before starting the scan of the next slice.

[0250] Calibration data and corresponding scan data generated at each stage of the scan can be sent to database 906. For each resolvable capture frame, its associated CTP 926 can be sent to database 906. Calibration data can be analyzed over a long period (i.e., not at runtime) to improve scan recipes and / or correct the default coordinate system 902, potentially resulting in a faster defect coordinate calculation rate.

[0251] As used herein, according to some embodiments, the term "sample" as used with respect to objects analyzed using the methods and / or systems of this disclosure encompasses patterned wafers, photomasks, and intermediate masks.

[0252] As used herein, according to some embodiments, the term "calibration data" as referenced with respect to an image frame may include the calculated CTP and / or the generated displacement map belonging to the image frame. According to some embodiments, calibration data obtained during scanning may be used as reference data in subsequent stages of scanning.

[0253] As used herein, the terms "frame" and "image frame" may be used interchangeably according to some embodiments.

[0254] As used herein, according to some embodiments, the term "frame target" when referring to an image frame will be understood to mean a subframe of the image frame that depicts a sub-region of the wafer region corresponding to the image frame and exhibits the desired image pattern recognition properties (i.e., high-contrast edges, pattern uniqueness, etc.) in the registration target.

[0255] As used herein, according to some embodiments, the term "target" may be used to refer to the image of the target when used relative to a scanned image (e.g., an image frame). In particular, according to some embodiments, the terms "target" and "frame target" may be used interchangeably when used relative to an image frame.

[0256] As used herein, the terms “coordinate transformation” and “coordinate mapping” may be used interchangeably according to some embodiments.

[0257] As used herein, the terms "identifiable target" and "registration target" may be used interchangeably according to some embodiments.

[0258] As used herein, according to some embodiments, an image region (e.g., a subframe of an image frame) may be referred to as "resolvable" when it includes at least one resolvable target (a resolvable image of the target). Similarly, according to some embodiments, an image region may be referred to as "unresolvable" when it does not include a resolvable target (a resolvable image of the target).

[0259] Although this disclosure focuses on the scanning and inspection of wafers, those skilled in the art will understand that the disclosed systems and methods are also applicable to photomasks and intermediate masks used in wafer manufacturing.

[0260] It will be understood that certain features of this disclosure described in the context of a single embodiment for clarity may also be provided in combination in a single embodiment. Conversely, various features of this disclosure described in the context of a single embodiment for brevity may also be provided individually or in any suitable sub-combination or suitably provided in any other described embodiment of this disclosure. Unless expressly indicated so, any feature described in the context of one embodiment should not be considered a fundamental feature of that embodiment.

[0261] Although the operations of a method according to some embodiments may be described in a specific sequence, the methods of this disclosure may include some or all of the operations described in a different order. The methods of this disclosure may include several or all of the operations described. Unless expressly indicated otherwise, no particular operation of the disclosed methods shall be considered a fundamental operation of the method.

[0262] Although this disclosure has been described in conjunction with specific embodiments thereof, it will be apparent that many alternatives, modifications, and variations will be obvious to those skilled in the art. Therefore, this disclosure covers all such alternatives, modifications, and variations that fall within the scope of the appended claims. It should be understood that this disclosure is not necessarily limited in its application to the details of the construction and arrangement of the components and / or methods set forth herein. Other embodiments may be practiced, and embodiments may be performed in various ways.

[0263] The wording and terminology used herein are for descriptive purposes and should not be construed as restrictive. Any references or designations made herein should not be interpreted as an admission that such references are prior art to this disclosure. Section headings are used herein to simplify understanding of the specification and should not be construed as unnecessarily restrictive.

Claims

1. A computer-implemented method for generating calibration data that can be used for sample analysis, the method comprising: Identify targets in image frames that belong to the scanned area of ​​the sample; Calculate the displacement of the target relative to the position of the target, as given by or derived from the reference data of the scanned area; Based at least on the calculated target displacement, determine the value of the coordinate transformation parameter CTP that relates the coordinates of the image frame to the coordinates of the scanned area as given by or derived from the reference data; as well as The CTP is used at least to obtain the displacements of multiple segments in the image frame, thereby generating a displacement mapping of the image frame or at least a portion of the image frame.

2. The method of claim 1, wherein the CTP comprises at least three independent parameters.

3. The method of claim 2, wherein each of the at least three independent parameters characterizes a corresponding correlation that persists on the image frame.

4. The method of claim 2, wherein the CTP includes one or more parameters characterizing global offset, linear scaling, fixed-angle skew, and rotation.

5. The method of claim 1, wherein the reference data includes one or more of the following: design data generated from scan data of the sample obtained during formulation setup, CTP and / or displacement mapping, and data obtained from scans of the same design or of another sample having features similar to those in the scan region.

6. The method of claim 1, wherein prior to calculating the displacement of the target, the reference data is calibrated based on the latest system coordinates, which are generated taking into account previously obtained scan data.

7. The method of claim 1, wherein at least some of the segments have a pixel size.

8. The method of claim 1, wherein the sample is a patterned wafer.

9. The method of claim 8, wherein the scanning area is located along a slice of a first chip extending through the wafer, and wherein the method further comprises repeating the method relative to other scanning areas located along the slice of the first chip.

10. The method of claim 9, wherein the CTP of at least one of the scan regions and the other scan regions is determined with reference to one or more previously determined CTPs of previously scanned regions along the slice.

11. The method of claim 9, further comprising an initial operation including optimizing (i) the height of image frames, each belonging to a scan region along the slice, and (ii) the selection of the CTP, such as to achieve the accuracy required at maximum or substantially maximum throughput.

12. The method of claim 9, further comprising generating displacement maps of additional image frames belonging to additional scan regions along the slice, the additional scan regions being located in additional chips along a chip column including the first chip, wherein the displacement maps of a first set of image frames in the additional image frames are generated directly based at least on a calculated displacement of a target in the first set of image frames relative to a corresponding position of the target as given by reference data; and The displacement mapping of the second set of image frames is generated based at least on the calculated displacement of the target in the second set of image frames relative to the calibration position of the corresponding target in the corresponding image frame of the corresponding scanned region in the corresponding previously scanned chip in the chip column.

13. The method of claim 12, wherein the previously scanned chip is the last scanned chip.

14. The method of claim 12, wherein the method is repeated slice by slice to generate calibration data for one or more chip columns of the wafer.

15. The method of claim 9, wherein when an image frame belonging to one of the other scan regions along the slice is characterized by an insufficient number of identifiable targets and / or an uneven distribution of identifiable targets, such that the required accuracy of the displacement mapping of the image frame cannot be achieved solely based on the displacement of the identifiable targets in the image frame, the displacement mapping of the image frame is interpolated or extrapolated based on or also taking into account calibration data of image frames belonging to scan regions near the scan region belonging to the image frame.

16. The method of claim 1, further comprising scanning the sample and generating the calibration data during runtime while the sample is being scanned.

17. A computerized system for generating calibration data that can be used for sample analysis, the system comprising a displacement analysis module, wherein the displacement analysis module is configured to: Calculate the displacement of the target identified in one or more image frames corresponding to one or more regions of the sample relative to the position of the target as given by or derived from reference data of the one or more regions; Based at least on the calculated target displacement, determine the values ​​of the coordinate transformation parameter CTP, which relates the coordinates of the one or more image frames to the coordinates of the one or more regions as given by or derived from the reference data of the one or more regions; as well as The CTP is used at least to determine the displacement of multiple segments in the one or more image frames, thereby generating one or more displacement maps of the one or more image frames or at least one or more portions of the one or more image frames.

18. A sample analysis system, comprising: A scanning device, the scanning device including an imager and configured to scan a region of a sample; as well as A processing and memory circuitry system, the processing and memory circuitry system comprising: the computerized system of claim 17; And a sample analysis module configured to detect potential defects in one or more regions of the area, taking into account displacement mappings of one or more regions of the area generated by the displacement analysis module of the computerized system.

19. The sample analysis system of claim 18, wherein the imager comprises an optical-based imager, and wherein, Optionally, the imager includes a large field-of-view scanning tool, and / or the imager includes a scanning electron microscope.

20. A non-transitory computer-readable medium comprising instructions executable by a processing circuitry of a system for generating calibration data usable for sample analysis, the instructions being configured to cause the system to: Identify targets in image frames corresponding to the scanned area of ​​the sample; Calculate the displacement of the target relative to the position of the target, as given by or derived from the reference data of the scanned area; Based at least on the calculated target displacement, determine the value of the coordinate transformation parameter CTP that relates the coordinates of the image frame to the coordinates of the scanned area as given by or derived from the reference data; as well as The CTP is used at least to obtain the displacements of multiple segments in the image frame, thereby generating a displacement mapping of the image frame or at least a portion of the image frame.

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