Bit line precharge circuit and method for memory circuits

Abstract

Embodiments of the invention provide systems and methods for controlling wake-up operations of a memory circuit. The memory circuit is configured to sequentially pre-charge bit lines of a memory array during wake-up. A first bit line of a memory cell receives a sleep signal, then a design delay occurs before a second complementary bit line is pre-charged. The sleep signal can then pre-charge a bit line of a second memory cell with a further delay between pre-charges of each bit line. The memory circuit is configured to simultaneously pre-charge both bit lines of the memory cell when an operation associated with the cell is designated.

Description

Technical Field

[0001] The technology described in this application generally relates to semiconductor memory systems, and more specifically, to bit line precharge circuit systems and methods for semiconductor memory systems. Background Technology

[0002] A memory bank is a logical unit of storage. A memory bank typically consists of multiple rows and columns of memory cells (memory units). A sleep signal is wired to the memory bank to precharge the bit cells for wake-up or operation. A wake-up signal can be generated with associated power cost to prepare the memory cells for operation after a low-power or sleep state. Summary of the Invention

[0003] According to one aspect of the present invention, a bit cell precharge circuit is provided, comprising: an operational precharge circuit configured to simultaneously precharge a first bit line and a second bit line of a bit cell associated with operation; and a wake-up precharge circuit configured to sequentially precharge a first bit line of a first bit cell, a second bit line of the first bit cell, a first bit line of a second bit cell, and a second bit line of the second bit cell.

[0004] According to another aspect of the present invention, a bit line precharge circuit is provided, comprising: a first bit line of a first memory cell configured to receive a first precharge signal; and a second complementary bit line of the first memory cell configured to receive a second precharge signal, wherein the first precharge signal and the second precharge signal have different phases.

[0005] According to another aspect of the present invention, a method for precharging a bit cell is provided, comprising: during a wake-up operation: precharging a first bit line of a first bit cell, and then precharging a second bit line of the first bit cell; then precharging a first bit line of a second bit cell, and then precharging a second bit line of the second bit cell; and during an operation associated with one of the first bit cell and the second bit cell: simultaneously precharging a first bit line and a second bit line of the bit cell associated with the operation. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic diagram illustrating a memory circuit configured to receive sleep and wake-up commands in an embodiment.

[0008] Figure 2 This is a block diagram of a memory architecture including sleep signals and delay elements, as described in an embodiment.

[0009] Figure 3 This is a schematic diagram of an example power management circuit for a semiconductor memory (e.g., SRAM) in the embodiment.

[0010] Figure 4 This is an example shown in the embodiment. Figure 3 Timing diagram of an example operation of a power management circuit.

[0011] Figures 5A to 5B The embodiments described can be used, for example, as follows. Figure 3 An instance of a delay element, comprising one or more delay elements.

[0012] Figure 6 This is a schematic diagram of another exemplary power management circuit for a semiconductor memory (e.g., SRAM) in the embodiment.

[0013] Figure 7 This is another example of a power management circuit for a semiconductor memory (e.g., SRAM) in the embodiments.

[0014] Figure 8 This is an additional example of a power management circuit for a semiconductor memory (e.g., SRAM) in the embodiments.

[0015] Figure 9 This is another example of a power management circuit for a semiconductor memory (e.g., SRAM) in the embodiments.

[0016] Figures 10A to 10B This is a flowchart of an example method for controlling the wake-up operation of a memory array in the embodiment.

[0017] Figure 11 This is a flowchart of an example method for controlling the wake-up operation of a memory array in the embodiment. Detailed Implementation

[0018] This invention provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or characters may be repeated in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Power gating is typically used to shut down peripherals and memory arrays in low-power SRAM. High-power gates can be used to increase the internal supply voltage of the memory when it exits sleep mode (e.g., shutdown, deep sleep, and light sleep). Power gating that provides a short wake-up time to the internal supply voltage can result in large inrush currents. Large inrush currents may not be optimal, as they can lead to component failure and excessive power draw in confined devices.

[0020] The word line internal power supply and bit line precharge circuitry of a memory system can be shut down during light sleep mode. Memory design standards may recommend maintaining a wake-up peak current lower than the peak current during task mode (read / write operations), especially during light sleep mode. During light sleep wake-up, when the bit lines are precharged in the memory almost simultaneously, the design may not meet this standard.

[0021] Sequential wake-up is a technique that can be used to reduce wake-up peak current in memory systems. However, it can be difficult to match the bit line precharge and sleep signal delays across all memory macros and PVTs. Without careful management, multiple bit lines may be precharged essentially simultaneously, resulting in undesirable peak current levels.

[0022] This document describes systems and methods for power management in memory systems. In embodiments, delay elements (e.g., a pair of inverters) are used in a semiconductor memory system (e.g., SRAM) to track bit line precharge signals in order to reduce peak current when exiting power management modes (e.g., shutdown, deep sleep, and light sleep). In this way, sequential bit line precharge operation within the memory can be implemented, thus reducing wake-up peak current to prevent high peak power consumption that could lead to component failure in constrained devices. When the wake-up peak current exceeds the task mode peak current, it can cause component failure.

[0023] Figure 1 This is a schematic diagram illustrating a memory circuit configured to receive sleep and array signals in an embodiment. Example SRAM memory 102 includes multiple input pins configured to receive sleep and address signals. Figure 1 In this example, memory 102 is configured to receive a clock (CLK) 115, a chip enable (CEB) signal 117, a shutdown mode (SD) signal 109, a deep sleep mode (DSLP) signal 111, and a light sleep mode (LSLP) signal 113. SRAM memory 102 is also configured to receive an address input (ADR) 118. In this embodiment, the address received at the address input indicates an address within the memory bank. The memory bank consists of two or more memory arrays.

[0024] Figure 2This is a block diagram of a bitline precharge circuit 200 including a sleep signal with sequential delay elements, as described in the embodiments. The example SRAM memory circuit includes a memory array with two memory cells, including a first (bottom) memory cell and a second (top) memory cell. The bottom memory cell includes a first bit line and a second complementary bit line. The top memory cell includes a first bit line and a second complementary bit line. The second bit line is also referred to as an anti-phase line. The memory circuit also includes global control within global inputs / outputs. The global control includes sleep logic circuitry, as well as a clock generator and an address decoder. The sleep logic circuitry has respective input pins for a shutdown mode (SD) signal 109, a deep sleep mode (DSLP) signal 111, and a light sleep mode (LSLP) signal 113. The clock generator and decoder have respective pins for a clock (CLK) signal 115, a chip enable (CEB) signal 117, and an address input (ADR) 118. The sleep logic circuit is configured to generate a sleep signal (SLP) if an off (SD) signal 109, a deep sleep mode (DSLP) signal 111, or a light sleep mode (LSLP) signal 113 is present. The sleep signal or wake-up signal path includes multiple delay elements configured in series. The signal is configured to sequentially precharge each bit line using the delay elements between each connection of the wake-up signal path and the bit line.

[0025] Figure 3 This is a schematic diagram of an example power management circuit 300 for a semiconductor memory (e.g., SRAM) according to an embodiment. The power management circuit 300 is as follows... Figure 2The illustrated bit-line precharge circuit 200 is an example embodiment. The example power management circuit 300 includes a memory array 302 having multiple memory cells controlled by a local input / output (I / O) system 304 and a global I / O system 306. The global I / O system 306 includes logic circuitry 308 that generates a sleep signal 301 (SLP), and a clock generator and address decoder 310 that generate a clock (ICLK) and addressing signals (TOP, BOT) for selecting memory cells in the memory array 302 for read or write operations. Specifically, in the illustrated embodiment, the global I / O system 306 includes an OR gate 308 that generates the sleep signal 301 (SLP) based on power management signals including a shutdown mode (SD) signal 309, a deep sleep mode (DSLP) signal 311, and a light sleep mode (LSLP) signal 313. These three modes (SD, DSLP, and LSLP) control the power management of the memory system. For example, in light sleep mode, the bit line precharge circuit and word line driver may be turned off; in deep sleep mode, the memory logic may be turned off; and in shutdown mode, the entire memory circuitry may be turned off. In the illustrated embodiment, the clock generator and address decoder 310 generate a clock signal (ICLK) based on the global clock signal 315 (CLK) and the chip enable signal 317 (CEB), and generate address signals (TOP, BOT) based on the address word 318 (ADR) and the chip enable signal 317 (CEB).

[0026] In the illustrated embodiment, the memory array 302 includes a first (bottom) memory cell 312 and a second (top) memory cell 314. In the illustrated embodiment, the sleep signal (SLP) from the global I / O system 306 is received in the local I / O system 304 as a first delayed sleep signal 316 (SLP_BOT_BL) and a second delayed sleep signal 319 (SLP_BOT_BLB) from the bottom memory cell 312.

[0027] Local I / O system 304 includes logic circuitry for each memory cell in memory array 302. Based on sleep signal 301 (SLP), clock (ICLK), and address (TOP, BOT) signals, this logic circuitry generates a bit line precharge (BPCHB) signal to control the power of the bit lines of each memory cell. Local I / O system 304 also includes multiple delay elements 307, 324, 334, 337, and 344, which are connected in series within the sleep signal path, causing a delay between the sleep signal 301 (SLP) and the logic circuitry of each bit line of the multiple memory cell bit lines 321, 325, 333, and 335. Sleep signal 301 (SLP) is delayed by first delay element 307 before first logic (OR) gate 322 in bottom memory cell 312. The output of the first delay element is a first delayed sleep signal 316 (SLP_BOT_BL). The first delay element is positioned along the wake-up signal path. Delay elements 307, 324, 334, 337, and 344 may be buffers, each including an even number of inverters. The delay elements are sequentially connected to a sleep signal 301 (SLP), such that a transition in the sleep signal 301 (SLP) indicative of a memory wake-up operation (e.g., exiting shutdown, deep sleep, or light sleep) causes multiple memory cells in the memory array 302 to receive power sequentially. The sleep signal (SLP) is input to the first delay element 307 to generate a first delayed sleep signal 316 (SLP_BOT_BL). The first delayed sleep signal 316 (SLP_BOT_BL) is input to the second delay element 324 to generate a second delayed sleep signal 319 (SLP_BOT_BLB). The second delayed sleep signal 319 (SLP_BOT_BLB) is input to the third delay element 334 to generate a third delayed sleep signal 329 (SLP_TOP_BL). The third delayed sleep signal 329 (SLP_TOP_BL) is input to the fourth delayed element 337 to generate the fourth delayed sleep signal 339 (SLP_TOP_BLB). The fourth delayed sleep signal 339 (SLP_TOP_BLB) is input to the fifth delayed element 344 and then output from the local I / O 304.

[0028] Clock (ICLK) and address (TOP, BOT) signals are input to a first AND gate 320 and a second AND gate 330. A first delayed sleep signal 316 (SLP_BOT_BL), along with the output of the first AND gate 320 as the bit line precharge signal 303 (BPCHB_BOT) for the bottom memory cell 312, is input to a first OR gate 322 for the bottom memory cell 312, wherein the first AND gate 320 receives the clock (ICLK) and address (BOT) signals. The clock (ICLK) and address (TOP) signals are input to the second AND gate 330, which outputs the bit line precharge signal (BPCHB_TOP) for the top memory cell 314.

[0029] The bit line precharge signal 303 (BPCHB_BOT) for the bottom memory cell 312 is input to the first logic (OR) gate 322 and the second logic (OR) gate 327. The first logic (OR) gate 322 and the second logic (OR) gate 327 generate bit line precharge signals (BPCHB_BOT_BL and BCHB_BOT_BLB) for the bottom memory cell 312. Specifically, the bit line precharge signal 323 (BPCHB_BOT_BL) is received at the gate of the first PMOS transistor 326, which includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the bit line 321 (BL_BOT). The anti-phase line precharge signal 331 (BPCHB_BOT_BLB) is received at the gate of the second PMOS transistor 328, which includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the anti-phase line 325 (BLB_BOT). As described above, the bit line precharge signal 303 (BPCHB_BOT) is configured such that the bit lines 321, 325 (BL_BOT and BLB_BOT) of the bottom cell are precharged substantially simultaneously during operation associated with the bottom cell 312.

[0030] The bit line precharge signal 305 (BPCHB_TOP) of the top memory cell 314 is input to the first logic (OR) gate 332 and the second logic (OR) gate 342 of the top memory cell. The first logic (OR) gate 332 and the second logic (OR) gate 342 generate bit line precharge signals (BPCHB_TOP_BL and BCHB_TOP_BLB) for the top memory cell 314. Specifically, the bit line precharge signal 341 (BPCHB_TOP_BL) is received at the gate of the first PMOS transistor 336, which includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the bit line 333 (BL_TOP). The anti-phase line precharge signal 343 (BPCHB_TOP_BLB) is received at the gate of the second PMOS transistor 338, which includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the anti-phase line 335 (BLB_TOP). As described above, the bit line precharge signal 305 (BPCHB_TOP) is configured such that the bit lines 333 and 335 (BL_TOP and BLB_TOP) for the top cell are precharged substantially simultaneously during the operation associated with the top cell 314.

[0031] Clock (ICLK) and address (TOP, BOT) signals are input to a first logic (AND) gate 320. A first delayed sleep signal 316 (SLP_BOT_BL), along with the output of the first logic (AND) gate 320 as the bit line precharge signal 303 (BPCHB_BOT) for the bottom memory cell 312, is input to a first logic (OR) gate 322 for use in the bottom memory cell 312, wherein the first logic (AND) gate 320 receives the clock (ICLK) and address (TOP, BOT) signals. More specifically, as shown, the logic circuit of the bottom memory cell 312 includes a first logic (AND) gate 320 having inputs that receive the address (BOT) signal and the clock (ICLK) signal, and a first logic (OR) gate 322 having inputs that receive the output of the first logic (AND) gate 320 and the first delayed sleep signal 316 (SLP_BOT_BL). The output of the first logic (OR) gate 322 provides a bit line precharge signal 323 (BPCHB_BOT_BL) for switching the memory cell. The output of the second logic (OR) gate 327 provides an anti-phase line precharge signal 331 (BPCHB_BOT_BLB) for the anti-phase line 325 of the bottom memory cell 312. Specifically, the bit line precharge signal 323 (BPCHB_BOT_BL) is received at the gate of the first PMOS transistor 326, which includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the bit line 321 (BL_BOT). The anti-phase line precharge signal 331 (BPCHB_BOT_BLB) is received at the gate of the second PMOS transistor 328, which includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the anti-phase line 325 (BLB_BOT).

[0032] In response to the transition of a first delayed sleep signal 316 (SLP_BOT_BL) indicating a memory wake-up operation, a first logic (OR) gate 322 for the bottom memory cell 312 generates a logic state on a bit line precharge signal 323 (BPCHB_BOT_BL), which causes power to be supplied to precharge the memory cell bit line 321 (BL_BOT). The sleep signal further passes through a delay element 324 to generate a second delayed sleep signal 319 (SLP_BOT_BLB). In response to the transition of the second delayed sleep signal 319 (SLP_BOT_BLB) indicating a memory wake-up operation, a second logic (OR) gate 327 for the bottom memory cell 312 generates a logic state on an anti-phase line precharge signal 331 (BPCHB_BOT_BLB), which causes power to be supplied to precharge the anti-phase line 325 (BLB_BOT) of the memory cell. More specifically, the first PMOS transistor 326 is controlled by a bit line precharge signal 323 (BPCHB_BOT_BL) to power the memory cell bit line 321 (BL_BOT). The second PMOS transistor 328 is controlled by an anti-phase line precharge signal 331 (BPCHB_BOT_BLB) to power the memory cell anti-phase line 325 (BLB_BOT) to initialize the bit line voltages when the memory array 302 is powered on in response to a memory wake-up operation (e.g., waking from shutdown, deep sleep, or light sleep). Figure 4 An example of this operation is shown in timing diagram 400.

[0033] Figure 4 This is a timing diagram 400 of an example power management circuit 300 for a semiconductor memory (e.g., SRAM) according to an embodiment. Reference Figure 4 The wake-up operation is initiated by a logic high-to-logic transition 401 of the sleep signal 113 (LSLP) received by the global I / O system 306. The logic state transition 401 of the sleep signal 113 (LSLP) causes a corresponding logic state transition 403 in the sleep signal 301 (SLP) received by the local I / O system 304. The initial sleep signal 301 (SLP) passes through a first delay element, which generates a first delayed sleep signal 316 (SLP_BOT_BL). (Refer to the above...) Figure 3 In detail, the logic state transition 403 in the first delayed sleep signal 316 (SLP_BOT_BL) causes a high-to-low transition 405 in the logic state of the bit line precharge signal 323 (BPCHB_BOT_BL) of the first logic (OR) gate 322 of the bottom memory cell 312, which allows power to be supplied to precharge the memory cell bit line 321 (BL_BOT). The precharging of the memory cell bit line 321 (BL_BOT) can be... Figure 4 The voltage transitions observed in timing diagram 400 via logic state transition 405 in response to bit line precharge signal 323 (BPCHB_BOT_BL) are shown. This generates a first peak in wake-up current 407i (VDD). This first peak of wake-up current 407i (VDD) is, for example, one-quarter smaller than the wake-up current in the memory circuitry that simultaneously precharges the bit line.

[0034] Refer again Figure 3 The first delayed sleep signal 316 (SLP_BOT_BL) is received as input to the second delay element 324 and a second delayed sleep signal 319 (SLP_BOT_BLB) is generated. The second delayed sleep signal 319 (SLP_BOT_BLB) is received by the third delay element 334 and a third delayed sleep signal 329 (SLP_TOP_BL) is generated. The first logic circuit (OR) gate 332 of the top memory cell 314 generates a bit line precharge signal 341 (BPCHB_TOP_BL), which keeps the logic state of the second delayed sleep signal unchanged (indicating a wake-up operation) until the voltages of the bit lines 321 and 325 (BL_BOT and BLB_BOT) of the bottom memory cell 312 have been initialized.

[0035] like Figure 4 As shown in timing diagram 400, the second delayed sleep signal 319 (SLP_BOT_BLB) only begins its logic state transition 409 after the bit line precharge signal 323 (BPCHB_BOT_BL) has transitioned from logic high to logic low 405. This causes a time delay 410 between the precharge of the bit line 321 (BL_BOT) voltage of the first PMOS transistor 326 in the bottom memory cell 312 and the start-up of the complementary PMOS transistor 328 for bit line 325 (BLB_BOT).

[0036] Refer again Figure 3The third delayed sleep signal 329 (SLP_TOP_BL) is provided as a sleep signal input to the logic circuits 330 and 332 for the top memory cell 314 and also as an input to the fourth delayed element 337. The logic circuitry of the top memory cell 314 includes a first AND gate 330 with inputs for receiving an address (TOP) signal and a clock (ICLK), and a first OR gate 332 with inputs for receiving the output of the first logic gate 330 and the third delayed sleep signal 329 (SLP_TOP_BL). The output of the first AND gate 330 of the top memory cell 314 is a bit line precharge 305 (BPCHB_TOP). The output of the first OR gate 332 provides a bit line precharge signal 341 (BPCHB_TOP_BL) for the switching circuitry in the top memory cell 314. Specifically, the gate of the first PMOS transistor 336 receives a bit line precharge signal 341 (BPCHB_TOP_BL). The first PMOS transistor 336 includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the bit line 333 (BL_TOP) of the top memory cell 314. The output of the second logic gate 342 (OR) provides the top memory cell 314 with an anti-phase line precharge signal 343 (BPCHB_TOP_BLB). The gate of the second PMOS transistor 338 receives the anti-phase line precharge signal 343 (BPCHB_TOP_BLB). The second PMOS transistor 338 includes a source terminal coupled to the power supply voltage and a drain terminal coupled to the anti-phase line 335 (BLB_TOP) of the top memory cell 314.

[0037] In response to the transition of the third delayed sleep signal 329 (SLP_TOP_BL) indicating a memory wake-up operation, the first logic (OR) gate 332 of the top memory cell 314 generates a logic state on the bit line precharge signal 341 (BPCHB_TOP_BL), which powers the first PMOS transistor 336 of the top memory cell 314 to precharge the memory cell bit line 333 (BL_TOP). Subsequently, in response to the transition of the fourth delayed sleep signal 339 (SLP_TOP_BLB) indicating a memory wake-up operation, the second logic (OR) gate 342 of the top memory cell 314 generates a logic state on the anti-phase line precharge signal 343 (BPCHB_TOP_BLB), which causes the second PMOS transistor 338 to be powered to precharge the memory cell anti-phase line 335 (BLB_TOP). Figure 4As shown in the timing diagram, the logic state transition 413 in the third delayed sleep signal 329 (SLP_TOP_BL) causes a logic state transition 415 in the bit line precharge signal 341 (BPCHB_TOP_BL) of the first logic (OR) gate 332 of the top memory cell 314, which causes power to be supplied to precharge the memory cell bit line 333 (BL_TOP). Figure 4 As shown in the timing diagram, the logic state transition 417 in the fourth delayed sleep signal 339 (SLP_TOP_BLB) causes a logic state transition 419 in the anti-phase line precharge signal 343 (BPCHB_TOP_BLB) of the second logic (OR) gate 342 of memory cell 314, which allows power to be supplied to precharge the memory cell anti-phase line 335 (BLB_TOP). The precharge of memory cell bit lines 333 and 335 (BL_TOP and BLB_TOP) can be... Figure 4 The timing diagram 400 shows the voltage transitions 411 and 413 that occur in response to the logic state transitions 415 and 419 of the bit line precharge signals 341 and 343 (BPCHB_TOP_BL and BPCHB_TOP_BLB).

[0038] Refer again Figure 3 The second delayed sleep signal 319 (SLP_BOT_BLB) is received as input to the third delayed element 334, which generates a third delayed sleep signal 329 (SLP_TOP_BL). The third delayed sleep signal 329 (SLP_TOP_BL) generated by the third delayed element 334 is delayed, so that the logic state of the third delayed sleep signal 329 (SLP_TOP_BL) does not change (a change would indicate a wake-up operation) until the voltage of the bit lines 321 and 325 (BL_BOT and BLB_BOT) of the bottom memory cell 312 has been initialized.

[0039] like Figure 4 As shown in timing diagram 400, the third delayed sleep signal 329 (SLP_TOP_BL) only begins after the bit line precharge signal 331 (BPCHB_BOT_BLB) has a logic high to logic low transition 411. This results in a time delay 416 between the precharge of the voltage of the anti-phase line 325 (BLB_BOT) of the bottom memory cell 312 and the initiation of the wake-up operation of the first bit line 333 (BL_TOP) of the top memory cell 314.

[0040] like Figure 4As shown in timing diagram 400, the fourth delayed sleep signal 339 (SLP_TOP_BLB) only begins its high-to-low logic state transition 417 after the bit line precharge signal 341 (BPCHB_TOP_BL) has a high-to-low transition 415. This results in a time delay 418 between the precharge of the bit line 333 (BL_TOP) voltage of the top memory cell 314 and the initiation of the wake-up operation of the anti-phase line 335 (BLB_TOP) of the top memory cell 314.

[0041] In this manner, the bit lines of the two memory cells 312 and 314 in Example Embodiment 300 are precharged sequentially, such as... Figure 4 The example timing diagram 400 is shown. Specifically, the gates of the four PMOS transistors 326, 328, 336, and 338 sequentially receive the precharge signals 323, 331, 341, and 343 for each bit line. Figure 4 As further shown, the sequential wake-up operation causes the resulting wake-up current draw 430 to occur during four separate intervals, which reduces the peak wake-up current compared to a system that performs wake-up operations on multiple memory cells simultaneously.

[0042] Figures 5A to 5B Examples of buffer 500 according to embodiments are described, and buffer 500 can be used, for example, as... Figure 3 One or more of the delay elements 307, 324, 334, 337, and 344. For example... Figure 5A As shown, buffer 500 includes a pair of inverters 502 and 504. First inverter 502 has an output 506 that serves as an input to second inverter 504. The output 506 of first inverter 502 is inverted with the input, such that if the input is logic high, the output is logic low. A sleep signal (e.g., SLP_BOT_BL) is the input to first inverter 502, and the output 506 of first inverter 502 is the input to second inverter 504. The output of second inverter 504 provides a delayed sleep signal (e.g., SLP_BOT_BLB) that matches the logic state of the input sleep signal.

[0043] Figure 5B A logic state table 510 for the example delay element is shown. As shown in Table 510, when the first sleep signal (e.g., SLP_BOT_BL) is in a logic low state, the delayed sleep signal (e.g., SLP_BOT_BLB) will also be in a logic low state. (Refer to the above...) Figure 4 In detail, when the first delayed sleep signal (e.g., SLP_BOT_BL) is in a logic high state, the delayed sleep signal (e.g., SLP_BOT_BLB) will be in a logic high state.

[0044] Figure 6 This is a schematic diagram of another example of a power management circuit 600 for a semiconductor memory (e.g., SRAM) according to an embodiment. Figure 6 Example 600 shown Figure 3 The example power management circuit 300 shown is the same, except that... Figure 6 Example 600 shown utilizes additional delay elements 610, 612, and 614 between sleep signals 316, 319, 329 and subsequent delayed sleep signals 319, 329, 339. A fourth additional delay element 616 is connected in series between the fourth delayed sleep signal 339 (SLP_TOP_BLB) and the bit-line sleep signal output from local I / O 304. Delay elements 610, 612, 614, and 616 can be, for example, buffers, each comprising an even number of inverters. The length of the signal delay caused by each delay element 610, 612, 614, and 616 can be determined, for example, by the number of inverter pairs included in the buffer circuit. Multiple delay elements can be connected in series with delay elements located at the edges of local I / O 304. For example, when line resistance is high, the additional delay elements can provide additional delay in bit-line tracking during pre-charge.

[0045] When a memory wake-up operation is initiated by one or more of the SD 109, DSLP 111, and LSLP 113 signals received by the global I / O system 306, bit line 321 (BL_BOT) is precharged, and then a second delayed sleep signal 319 (SLP_BOT_BLB) is generated by a second delay element, which precharges the anti-phase line 325 (BLB_BOT). Once the bottom memory cell 312 is precharged, a third delayed sleep signal 329 (SLP_TOP_BL) is generated in conjunction with the above reference. Figure 3 The same manner described in the illustrated embodiment is generated by the third delay element 334. The third delayed sleep signal 329 (SLP_TOP_BL) also precharges the first bit line 333 (BL_TOP) of the top memory cell, and then inputs to the fourth delay element 337 to sequentially precharge the second bit line 335 (BLB_TOP) of the top memory cell, as referenced above. Figure 3As described. However, in this embodiment 600, the subsequent delayed sleep signals 319, 329, and 339 (SLP_BOT_BLB, SLP_TOP_BL, and SLP_TOP_BLB) are generated by delay elements 610, 612, and 614, respectively. In this way, the initiation of the memory wake-up operation of the second bit line 325 of the bottom memory cell is delayed by a time amount (D1) compared to the initiation of the memory wake-up operation of the first bit line 321 of the bottom memory cell, and the initiation of the memory wake-up operation of the first bit line 333 (BL_TOP) of the top memory cell is delayed by a time amount (D2) compared to the initiation of the memory wake-up operation of the second bit line 325 of the bottom memory cell, and the initiation of the memory wake-up operation of the second bit line 333 of the top memory cell is delayed by a time amount (D3) compared to the initiation of the memory wake-up operation of the first bit line 333 (BL_TOP) of the top memory cell. The lengths of the time delays (D1, D2, and D3) can be determined by the sizes of the individual delay elements, with delay elements 324 and 610 for D1, delay elements 334 and 612 for D2, and delay elements 337 and 614 for D3 (e.g., by selecting the number of inverter pairs), and can be configured such that the bit lines 321, 325, 333, and 335 of the memory cells 312 and 314 are precharged sequentially, similar to (or identical to) those of the delay elements. Figure 3 The embodiments generate sequential bit-line precharge. In this way, sequential bit-line precharge operations within the memory can be implemented. Therefore, the wake-up peak current can be significantly reduced (e.g., by a quarter) compared to existing SRAM architectures.

[0046] Figure 7 This is another example of a power management circuit 700 for a semiconductor memory (e.g., SRAM) according to an embodiment. Figure 7 Example 700 shown and Figure 3 The power management circuit shown is the same as the example power management circuit 300, except that... Figure 7In the illustrated example 700, the memory cell includes equalizer devices 710 and 712 located between bit lines 321 and 325 (BL_BOT and BLB_BOT), and between bit lines 333 and 335 (BL_TOP and BLB_TOP), respectively. For example, the equalizer devices may include PMOS transistors. The equalizer 710 of the bottom memory cell 312 receives a bit line precharge signal 331 (BPCHB_BOT_BLB) at the gate of a PMOS transistor, which includes a source terminal coupled to the bit line and a drain terminal coupled to a complementary bit line. The bit line precharge signal 331 (BPCHB_BOT_BLB) received at the gate terminal is generated by a second logic (OR) gate 327, which has inputs from a second delayed sleep signal 319 (SLP_BOT_BLB) and a bit line precharge signal 303 (BPCHB_BOT). Figure 4 As shown in timing diagram 400, the second delayed sleep signal 319 (SLP_BOT_BLB) only begins its logic state transition 409 after the bit line precharge signal 323 (BPCHB_BOT_BL) transitions from logic high to logic low. This results in a time delay 410 between the precharge of the bit line 321 (BL_BOT) voltage of the first PMOS transistor 326 and the wake-up start of the complementary PMOS transistor 328 for the bit line 325 (BLB_BOT) of the bottom memory cell. When (BPCHB_BOT_BL) transitions from logic high to logic low during wake-up, an additional equalizer device equalizes the complementary bit lines 321 and 325 (BL_BOT and BLB_BOT) such that the voltage at the source terminal of the first PMOS transistor 326 of the bottom memory cell 312 is substantially the same as the voltage at the source terminal of the second PMOS transistor 328.

[0047] The equalizer 712 of the top memory cell 314 receives a bit line precharge signal 343 (BPCHB_TOP_BLB) at the gate of a PMOS transistor, which includes a source terminal coupled to bit line 333 (BL_TOP) and a drain terminal coupled to the anti-phase line 333 (BLB_TOP). The bit line precharge signal 343 (BPCHB_TOP_BLB) is received at the gate terminal and originates from a second logic (OR) gate 342, which has inputs from a fourth delayed sleep signal 339 (SLP_TOP_BLB) and a bit line precharge signal 305 (BPCHB_TOP). Figure 4As shown in timing diagram 400, the fourth delayed sleep signal 339 (SLP_TOP_BLB) initiates a logic state transition 417 only after the bit line precharge signal 341 (BPCHB_TOP_BL) transitions from logic high to logic low. This results in a time delay between the precharge of the bit line 333 (BL_TOP) voltage of the first PMOS transistor 336 and the wake-up activation of the complementary PMOS transistor 338 for the bit line 335 (BLB_TOP) of the top memory cell 314. When the bit line precharge signal 343 (BPCHB_TOP_BL) transitions from logic high to logic low during wake-up activation, an additional equalizer device equalizes the complementary bit lines 333 and 335 (BL_TOP and BLB_TOP) so that the voltages at the source terminals of the first PMOS transistor 336 and the second PMOS transistor 338 of the top memory cell 314 are substantially the same.

[0048] Figure 8 This is a schematic diagram of an additional example of a power management circuit 800 for a semiconductor memory (e.g., SRAM) according to an embodiment. Figure 8 Example 800 shown Figure 3 The example power management circuit 300 shown is the same, except that... Figure 8 The example 800 shown does not utilize a delay element between the sleep signal 301 (SLP) and the first logic (OR) gate 322. In this embodiment, there is no series-connected delay element between the sleep signal 301 (SLP) and the sleep signal 316 (SLP_BOT_BL) on the first bit line 321 of the bottom memory cell 312.

[0049] Figure 9 This is a schematic diagram of another example of a power management circuit 900 for a semiconductor memory (e.g., SRAM) according to an embodiment. Figure 9 Example 900 shown and Figure 7 The example power management circuit 700 shown is the same, except that... Figure 9Example 900 shown includes additional equalizer delay elements 910, 912, 914, and 916 between sleep signals 316, 319, and 329 and delayed sleep signals 319, 329, and 339. A fourth additional delay element 916 is connected in series between the fourth delayed sleep signal 339 (SLP_TOP_BLB) and the bit-line sleep signal output from local I / O 304. For example, delay elements 910, 912, 914, and 916 may each be a buffer comprising a series of even-numbered inverters. The length of the signal delay caused by each delay element 910, 912, 914, and 916 can be determined, for example, by the number of inverter pairs included in the buffer circuit. Multiple delay elements may be connected in series with delay elements located at the edges of local I / O 304. For example, when line resistance is high, additional delay elements can provide additional delay for pre-charge in bit-line tracking.

[0050] Figure 10A This is a flowchart describing a method 1000 for controlling the wake-up operation of a memory array comprising multiple memory cells. For ease of understanding, reference is made to the previously described structure. Figure 10A The steps are defined, but it should be understood that various structures can be used to perform these steps. Method 1000 can, for example, be performed by... Figure 3 , 6 The example memory circuits 300, 600, 700, 800, and 900 shown in 7, 8, and 9 are used to execute this. In step 1001, a sleep signal 301 (SLP) indicating the initiation of a memory wake-up operation is received by the memory circuit. The sleep signal can be, for example, generated by... Figure 3 , 6 The logic circuits 322, 327, 332, and 342 in 7, 8, and 9 receive the signal. In response to the sleep signal, a first-bit line precharge signal (e.g., BPHB_BOT_BL) is generated for the first memory cell among the multiple memory cells. For example, the first-bit line precharge signal can be generated by… Figure 3 , 6 The logic circuit 322 shown in 7, 8, and 9 is generated. In step 1010, the bit lines of the first memory cell, for example... Figure 3 , 6 Bit line 321, shown in 7, 8, and 9, is precharged in response to a first bit precharge signal. In step 1015, a delayed sleep signal (e.g., SLP_BOT_BLB) is generated in response to a sleep signal transmitted through a series-connected delay element (e.g., 324). In response to the sleep signal, a second bit line precharge signal (e.g., BPHB_BOT_BLB) is generated for a first memory cell among a plurality of memory cells. In step 1020, in response to the second bit line precharge signal, the second bit line of the first memory cell, for example... Figure 3Bit line 325, as shown in 6, 7, 8, or 9, is precharged. In step 1025, the delayed sleep signal is passed through another delay element, thereby delaying the signal again and generating a second delayed sleep signal. In response to the second delayed sleep signal, a third bit line precharge signal is generated for the second memory cell among the plurality of memory cells. For example, the third bit line precharge signal can be generated by... Figure 3 The logic circuit 332 shown in 6, 7, 8, or 9 is generated. In step 1030, in response to the second bit line precharge signal, the bit line of the second memory cell, for example... Figure 3 Bit line 333, as shown in 6, 7, 8, or 9, is precharged. In step 1035, the second delayed sleep signal passes through the third delayed element, thereby delaying the signal again and generating a third delayed sleep signal. In response to the third delayed sleep signal, a fourth bit line precharge signal is generated for the second bit line in the second memory cell among the plurality of memory cells. In step 1040, in response to the fourth bit line precharge signal, the second bit line of the second memory cell, for example... Figure 3 Bit line 335, as shown in 6, 7, 8, or 9, is precharged.

[0051] Figure 10B This is a flowchart of an example method 1000 for pre-charging bit cells during operation associated with memory cells in a memory array comprising multiple memory cells. For ease of understanding, reference is made to the previously described structure. Figure 10B The steps are defined, but it should be understood that various structures can be used to perform these steps. Method 1000 can, for example, be performed by... Figure 3The example memory circuits 300, 600, 700, 800, and 900 shown in 6, 7, 8, and 9 are executed. At step 1002, an operation signal is received from the clock generator and address decoder 310, and the logic circuits 320 and 330 of each of the memory cells 312 and 314 generate a bit line precharge signal 303 (BPCHB_BOT) for the bottom memory cell 312 or a bit line precharge signal 305 (BPCHB_TOP) for the top memory cell 314. For the operation signal associated with the bottom memory cell 312, the bit line precharge signal 303 (BPCHB_BOT) is simultaneously received by logic (OR) gates 322 and 327. At step 1050, the bit line precharge signals 323 and 331 (BPCHB_BOT_BL and BCHB_BOT_BLB) simultaneously precharge the corresponding bit lines 321 and 325 (BL_BOT and BLB_BOT). For the operation signal associated with the top memory cell 314, the bit line precharge signal 305 (BPCHB_TOP) is simultaneously received by logic (OR) gates 332 and 342. In step 1050, the bit line precharge signals 341 and 343 (BPCHB_TOP_BL and BCHB_TOP_BLB) simultaneously precharge the corresponding bit lines 333 and 335 (BL_TOP and BLB_TOP).

[0052] In the example method, based on the previous operation, one of the two bit lines associated with the bit cell is at a high logic level and the complementary bit line is at a low logic level. Global I / O 306 signals that the associated bit cell is the target of the next operation (e.g., a read or write operation), and the precharge circuit precharges both bit lines to a high level (e.g., by setting the low level to a high level and restoring any small drop in the high level to restore it to the appropriate high level). Specifically, in step 1002, clock generation and address decoder 310 are input to logic circuitry that generates the bit line precharge signal associated with the memory cell. In step 1050, the precharge circuit precharges both bit lines to a high level.

[0053] When a memory wake-up operation is initiated by one or more of the SD 109, DSLP 111, and LSLP 113 signals received by the global I / O system, bit lines 321 and 325 (BL_BOT and BLB_BOT) for the bottom memory cell 312 are precharged, and a third delayed sleep signal 329 is generated by a third delayed element 334, as referenced above. Figure 3 As described in the embodiment. The third delayed sleep signal 329 also causes bit lines 333, 335 (BL_TOP and BLB_TOP) to be aligned with the above reference. Figure 3The same method is used for precharging. Thus, the initiation of the memory wake-up operation of the second bit line 325 (BLB_BOT) of the bottom memory cell is delayed by a time amount (D1) compared to the initiation of the memory wake-up operation of the first bit line 321 (BL_BOT) of the bottom memory cell, and the initiation of the memory wake-up operation of the first bit line 333 (BL_TOP) of the top memory cell is delayed by a time amount (D2) compared to the initiation of the memory wake-up operation of the second bit line 325 (BLB_BOT) of the bottom memory cell, and the initiation of the memory wake-up operation of the second bit line 335 (BLB_TOP) of the top memory cell is delayed by a time amount (D3) compared to the initiation of the memory wake-up operation of the first bit line 333 (BL_TOP) of the top memory cell. The lengths of the time delays (D1, D2, and D3) can be determined by the sizes of the corresponding delay elements 324, 334, and 337 (e.g., by selecting the number of inverter pairs) and can be configured such that the bit lines 321, 325, 333, and 335 of the memory cells 312 and 314 are precharged sequentially, similar to (or identical to) those generated by... Figure 3 The bit line precharge sequence generated by the embodiment.

[0054] Figure 11 This is a flowchart describing a method 1100 for controlling a wake-up operation of a memory array comprising multiple memory cells. For ease of understanding, reference is made to the previously described structure. Figure 11 The steps are as follows, but it should be understood that various structures can be used to perform these steps. In step 1110, a wake-up operation is initiated at the memory input (e.g., SD, LSLP, DSLP). A sleep signal propagates along the wake-up signal path to precharge multiple bit cells. In step 1120, the sleep signal precharges the first bit line of the first bit cell, and then precharges the second bit line of the first bit cell. There is a delay between the precharging of the first bit line and the second bit line. In step 1130, the delayed sleep signal (e.g., SLP_TOP_BL) then precharges the first bit line of the second bit cell, and then precharges the second bit line of the second bit cell. Delay elements (e.g., delay elements 307, 324, 334, 337, 344) are used. Figure 3 This results in each bit line being precharged at a different phase. Using this method, all bit lines are not precharged simultaneously, thus reducing peak inrush current.

[0055] According to some embodiments, systems and methods for bit cell precharge circuits are provided. In one example, the precharge circuit includes an operational circuit and a wake-up precharge circuit. The operational circuit is configured to cause the first bit line and the second bit line of the memory cell to operate simultaneously. The wake-up precharge circuit is configured to sequentially precharge the first bit line and the second bit line of the first cell. In this example, both the first bit line and the second bit line are precharged by a bit line precharge signal. Because this signal is delayed between the precharge of the first bit line and the second bit line of the first cell, the bit line precharge signals have different phases. The wake-up circuit can also sequentially precharge the first bit line of the second bit cell and the second bit line of the second bit cell. For example, the circuit can sequentially precharge by positioning delay elements along the wake-up signal path. In one example, the wake-up signal path is configured to begin precharging the next bit line on the wake-up signal path once the previous bit line on the wake-up signal path has completed precharging to maximize the speed of the wake-up operation while limiting peak power. In another example, the signal path is configured with additional delay elements along the wake-up signal path, such that an additional delay occurs between the precharges of each bit line.

[0056] In one embodiment, the precharge circuitry can precharge bit cells via an operating mode or a wake-up mode. The bit line precharging method for bit cells results in interleaved bit line precharging during wake-up mode and simultaneous precharging of bit lines during operating mode. During operating mode, memory cells are precharged for operations associated with addressed memory cells (e.g., R / W operations). During operating mode, controls can simultaneously precharge two bit lines of a memory cell to reduce wake-up time. The wake-up operation of a memory array can include sequentially precharging each bit line by charging one bit line, delaying the event, and then charging a second complementary bit line of the bit cell. The delay time can be determined by the number of buffers, such as inverter pairs. The wake-up signal then charges the first bit line of a second memory cell, delays the event, and then charges the second complementary bit line of the second memory cell. Interleaving the precharging of bit lines during wake-up operation can limit peak power consumption. This can prevent high peak power consumption, reduce power consumption of memory circuitry with maximum current, or allow other memory circuitry components to draw power in a constrained device.

[0057] In another embodiment, the memory circuitry includes a memory array having a plurality of memory cells, a first logic circuit, a delay element, and a second logic circuit. The first logic circuitry can be configured to generate a first bit line precharge signal for a first memory cell, wherein the first bit line precharge signal is generated in response to a sleep signal. The first bit line precharge signal is configured to charge the first bit line, and then cause the sleep signal to propagate through the delay element, which generates a delayed sleep signal. The delayed sleep signal then charges a second complementary bit line. The second logic circuitry can be configured to generate a second bit line precharge signal for a second memory cell, wherein the second bit line precharge signal is generated in response to the delayed sleep signal. The second logic circuitry can be configured to supply power to one or more bit lines of the second memory cell in response to the second bit line precharge signal. The second logic circuitry can be configured to supply power to the first bit line in response to the delayed precharge signal, and then supply power to the second complementary bit line of the second memory cell.

[0058] According to one embodiment of the present invention, a bit cell precharge circuit is provided, comprising: an operational precharge circuit configured to simultaneously precharge a first bit line and a second bit line of a bit cell associated with operation; and a wake-up precharge circuit configured to sequentially precharge a first bit line of a first bit cell, a second bit line of the first bit cell, a first bit line of a second bit cell, and a second bit line of the second bit cell.

[0059] In some embodiments, the wake-up precharge circuit includes: a circuit for detecting a wake-up signal; and a wake-up signal path including a delay element between each of the first bit line of the first bit unit, the second bit line of the first bit unit, the first bit line of the second bit unit, and the second bit line of the second bit unit.

[0060] In some embodiments, each delay element includes an inverter pair.

[0061] In some embodiments, the wake-up precharge circuit further includes: a first equalizer element configured to connect the first bit line of the first bit unit and the second bit line of the first bit unit; and a second equalizer element configured to connect the first bit line of the second bit unit and the second bit line of the second bit unit.

[0062] In some embodiments, after power is supplied to the first bit line of the first bit unit, the wake-up precharge circuit causes a logic state transition in the delayed sleep signal to occur.

[0063] In some embodiments, the time between the pre-charging of the first bit line and the second bit line of the first bit unit is based on a delay associated with one of the delay elements and the length of the wake-up signal path located between the pre-charging circuits of the first bit line and the second bit line of the first bit unit.

[0064] According to an embodiment of the present invention, a bit line precharge circuit is provided, comprising: a first bit line of a first memory cell configured to receive a first precharge signal; and a second complementary bit line of the first memory cell configured to receive a second precharge signal, wherein the first precharge signal and the second precharge signal have different phases.

[0065] In some embodiments, the circuit further includes: a first bit line of a second memory cell configured to receive a third precharge signal; and a second complementary bit line of the second memory cell configured to receive a fourth precharge signal, wherein the third precharge signal and the fourth precharge signal have different phases.

[0066] In some embodiments, the first precharge signal, the second precharge signal, the third precharge signal, and the fourth precharge signal have different phases.

[0067] In some embodiments, the circuit further includes an equalizer device located between the first bit line of the first memory cell and the second complementary bit line of the first memory cell.

[0068] In some embodiments, the circuit further includes: a first equalizer device located between a first bit line of the first memory cell and a second complementary bit line of the first memory cell; and a second equalizer device located between a first bit line of the second memory cell and a second complementary bit line of the second memory cell.

[0069] In some embodiments, the circuit further includes a sleep signal bit line, wherein the sleep signal bit line includes a plurality of delay elements.

[0070] In some embodiments, the delay element includes a pair of inverters.

[0071] According to an embodiment of the present invention, a method for precharging a bit cell is provided, comprising: during a wake-up operation: precharging a first bit line of a first bit cell, and then precharging a second bit line of the first bit cell; then precharging a first bit line of a second bit cell, and then precharging a second bit line of the second bit cell; and during an operation associated with one of the first bit cell and the second bit cell: simultaneously precharging a first bit line and a second bit line of the bit cell associated with the operation.

[0072] In some embodiments, the method further includes: during the wake-up operation: generating a first delayed sleep signal at a delayed element; generating a second delayed sleep signal at a second delayed element; generating a third delayed sleep signal at a third delayed element; and generating a fourth delayed sleep signal at a fourth delayed element.

[0073] In some embodiments, the delayed sleep signal, the second delayed sleep signal, the third delayed sleep signal, and the fourth delayed sleep signal are generated sequentially.

[0074] In some embodiments, the first delayed sleep signal, the second delayed sleep signal, the third delayed sleep signal, and the fourth delayed sleep signal precharge the first bit line of the first unit, the second bit line of the first unit, the first bit line of the second unit, and the second bit line of the second unit, respectively.

[0075] In some embodiments, the delay element includes multiple pairs of inverters.

[0076] In some embodiments, the method further includes: during the wake-up operation: operation of a first equalizer device to equalize the voltage on the first bit line of the first bit cell and the second bit line of the first bit cell.

[0077] In some embodiments, the method further includes: operating the second equalizer device to equalize the voltage on the first bit line of the second bit unit and the second bit line of the second bit unit.

[0078] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A bit cell pre-charge circuit, comprising: An operational precharge circuit is configured to simultaneously precharge the first bit line and the second bit line of the bit cell associated with the operation. The wake-up precharge circuit is configured to sequentially precharge the first bit line of the first bit unit, the second bit line of the first bit unit, the first bit line of the second bit unit, and the second bit line of the second bit unit. The wake-up pre-charge circuit includes: Circuit for detecting wake-up signals; The wake-up signal path includes a delay element between each of the first bit line of the first bit unit, the second bit line of the first bit unit, the first bit line of the second bit unit, and the second bit line of the second bit unit, wherein the delayed sleep signal of the wake-up signal path corresponding to one bit line of the first bit unit, the first bit line of the second bit unit, and the second bit line of the second bit unit uses the delay element to track the change in the logic state of the bit line precharge signal of the previous bit line of the bit line, and the delayed sleep signal and the bit line precharge signal corresponding to the same bit line are different signals.

2. The circuit according to claim 1, wherein, The wake-up signal path of the wake-up pre-charge circuit includes: A delay element connected between the pre-charge circuit of the first bit line of the first bit unit and the pre-charge circuit of the second bit line of the first bit unit.

3. The circuit according to claim 2, wherein, Each delay element includes an inverter pair.

4. The circuit according to claim 2, wherein, The wake-up pre-charge circuit also includes: A first equalizer element is configured to connect the first bit line of the first bit unit and the second bit line of the first bit unit; The second equalizer element is configured to connect the first bit line of the second bit unit and the second bit line of the second bit unit.

5. The circuit according to claim 2, wherein, After power is supplied to the first bit line of the first bit unit, the wake-up precharge circuit causes a logic state transition in the delayed sleep signal.

6. The circuit according to claim 2, wherein, The time between the pre-charge of the first bit line and the pre-charge of the second bit line of the first bit unit is based on a delay, which is associated with one of the delay elements and the length of the wake-up signal path located between the pre-charge circuits of the first bit line and the second bit line of the first bit unit.

7. A bit line pre-charge circuit, comprising: The first line of the first unit is configured to receive a first precharge signal; as well as The second complementary bit line of the first bit unit is configured to receive the second precharge signal. The sleep signal bit line includes multiple delay elements, wherein the delayed sleep signal of the sleep signal bit line corresponding to the second bit line of the first bit unit tracks the change in the logic state of the bit line precharge signal of the first bit line of the first bit unit using the delay elements, and the delayed sleep signal and the bit line precharge signal corresponding to the same bit line are different signals. The first pre-charge signal and the second pre-charge signal have different phases.

8. The circuit according to claim 7, further comprising: The first line of the second bit unit is configured to receive a third precharge signal. as well as The second complementary bit line of the second bit unit is configured to receive the fourth precharge signal. The third pre-charge signal and the fourth pre-charge signal have different phases.

9. The circuit according to claim 8, wherein, The first precharge signal, the second precharge signal, the third precharge signal, and the fourth precharge signal have different phases.

10. The circuit according to claim 7, further comprising: An equalizer device is located between the first bit line of the first bit unit and the second complementary bit line of the first bit unit.

11. The circuit according to claim 8, further comprising: The first equalizer device is located between the first bit line of the first bit unit and the second complementary bit line of the first bit unit. as well as The second equalizer device is located between the first bit line of the second bit unit and the second complementary bit line of the second bit unit.

12. The circuit according to claim 7, wherein, The plurality of delay elements includes a first delay element connected between the pre-charge circuit of the first bit line of the first bit unit and the pre-charge circuit of the second bit line of the first bit unit.

13. The circuit according to claim 12, wherein, The delay element includes a pair of inverters.

14. A method for pre-charging a potential cell, comprising: During the wake-up operation: The first bit line of the first bit unit is pre-charged, and then the second bit line of the first bit unit is pre-charged. Then the first bit line of the second bit unit is pre-charged, and then the second bit line of the second bit unit is pre-charged. A sleep signal is generated at the sleep logic circuit; The sleep signal is delayed by using a delay element to generate a delayed sleep signal; During an operation associated with one of the first bit unit and the second bit unit: Simultaneously, the first and second bit lines of the bit cells associated with the operation are pre-charged. During the wake-up operation, the delayed sleep signal corresponding to the second bit line of the first bit unit, the first bit line of the second bit unit, and one bit line of the second bit line of the second bit unit uses the delay element to track the change in the logic state of the bit line precharge signal of the previous bit line of the bit line, and the delayed sleep signal and the bit line precharge signal corresponding to the same bit line are different signals.

15. The method of claim 14, wherein delaying the sleep signal using the delay element to generate the delayed sleep signal comprises: A first delayed sleep signal is generated at the first delayed element; A second delayed sleep signal is generated at the second delayed element; A third delayed sleep signal is generated at the third delayed element; A fourth delay sleep signal is generated at the fourth delay element.

16. The method according to claim 15, wherein, The first delayed sleep signal, the second delayed sleep signal, the third delayed sleep signal, and the fourth delayed sleep signal are generated sequentially.

17. The method according to claim 15, wherein, The first delayed sleep signal, the second delayed sleep signal, the third delayed sleep signal, and the fourth delayed sleep signal precharge the first bit line of the first bit unit, the second bit line of the first bit unit, the first bit line of the second bit unit, and the second bit line of the second bit unit, respectively.

18. The method according to claim 15, wherein, The delay element includes multiple pairs of inverters.

19. The method of claim 14, further comprising: During the wake-up operation: The first equalizer device operates to equalize the voltage on the first bit line and the second bit line of the first bit unit.

20. The method of claim 19, further comprising: The operation of the second equalizer device is to equalize the voltage on the first bit line of the second bit unit and the second bit line of the second bit unit.

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