Memory device, controller controlling the memory device, memory system including the memory device, and operating method thereof

Abstract

A method of operating a memory device includes receiving a training request for a data lane, detecting at least one mode parameter from the training request, sending the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set configuration information from the external device, and performing communication with the external device according to the set transmission signaling mode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0105217, filed on August 21, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to memory devices, controllers for controlling memory devices, memory systems including memory devices, and methods of operating the same. Background Technology

[0004] Typically, the demand for faster and higher-capacity data transmission is growing with the widespread deployment of mobile devices and the rapid increase in internet traffic. However, using signal modulation schemes based on non-return-to-zero (NRZ) coding to meet this increasing demand can be challenging. In recent years, pulse amplitude modulation (PAM) signaling schemes (e.g., 4-level pulse amplitude modulation (PAM4)) have been actively developed as an alternative for faster and higher-capacity data transmission. Summary of the Invention

[0005] Example embodiments provide a memory device for selecting a transmission signaling mode, a controller for controlling the memory device, a memory system including the memory device, and a method of operating the memory device.

[0006] According to an example embodiment, a memory device includes: memory device processing circuitry configured to send read data to a data channel according to a transmission signaling mode, receive write data from the data channel according to the transmission signaling mode, store the transmission signaling mode, and perform a training operation on the data channel in response to a training request received from an external device, wherein the training operation detects at least one mode parameter, selects one of a first transmission signaling mode and a second transmission signaling mode as the transmission signaling mode using the detected mode parameter, and outputs mode flag information associated with the detected mode parameter to the external device.

[0007] According to an example embodiment, a method of operating a memory device includes: receiving a training request for a data channel; detecting at least one mode parameter according to the training request; sending the detected mode parameter to an external device; setting at least one of a non-return-to-zero (NRZ) mode and a 4-level pulse amplitude modulation (PAM4) mode to a transmission signaling mode based on mode register setting configuration information from the external device; and performing communication with the external device according to the set transmission signaling mode.

[0008] According to an example embodiment, a memory system includes: a memory device configured to receive or transmit data via a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode; and a controller configured to control the memory device and select the transmission signaling mode using at least one mode parameter. The memory device includes: memory device processing circuitry configured to store the transmission signaling mode, receive a training request from the controller, detect at least one mode parameter associated with the data channel in response to the training request, and send flag information associated with the detected at least one mode parameter to the controller.

[0009] According to an example embodiment, a controller for controlling a memory device includes: controller processing circuitry configured to generate a clock and output the clock to the memory device, generate a command address signal to operate the memory device, send the command address signal in response to the clock, and send data to and receive data from the memory device via a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode. During a training period of the memory device, the controller receives flag information associated with at least one mode parameter from the memory device and uses the flag information to determine the transmission signaling mode as one of the first transmission signaling mode and the second transmission signaling mode. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 This is a diagram illustrating a memory system according to an example embodiment.

[0012] Figure 2A and Figure 2B This is a diagram illustrating the transmission signaling according to an example embodiment.

[0013] Figure 3 This is a diagram illustrating a pattern detection circuit according to an example embodiment.

[0014] Figure 4 This is a diagram illustrating a termination voltage detector according to an example embodiment.

[0015] Figure 5 This is a diagram illustrating a current detector according to an example embodiment.

[0016] Figure 6 This is a diagram illustrating a current detector according to an example embodiment.

[0017] Figure 7This is a diagram illustrating a channel loss detector according to an example embodiment.

[0018] Figure 8 This is a diagram illustrating a dual-mode transceiver according to an example embodiment.

[0019] Figure 9 This is a flowchart illustrating a mode selection method for a memory device according to an example embodiment.

[0020] Figure 10 This is a flowchart illustrating a mode selection method for a memory device according to an example embodiment.

[0021] Figure 11 This is a diagram illustrating a memory system according to an example embodiment.

[0022] Figure 12A This is a ladder diagram illustrating the training operation of a memory system according to an example embodiment.

[0023] Figure 12B This is a ladder diagram illustrating the training operation of a memory system according to an example embodiment.

[0024] Figure 13 This is a diagram illustrating a memory system performing at least one command / address calibration according to an example embodiment.

[0025] Figure 14 This is a diagram illustrating a memory system according to an example embodiment.

[0026] Figure 15 This is a diagram illustrating a computing system according to an example embodiment.

[0027] Figure 16 This is a diagram illustrating a computing system according to an example embodiment.

[0028] Figure 17 This is a diagram illustrating a data center application of a memory device according to an example embodiment. Detailed Implementation

[0029] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0030] In the memory system according to the example embodiment, a transmission signaling mode can be selected based on channel environment information in the memory device, and improved or optimal data transmission can be performed under the selected transmission signaling mode.

[0031] Figure 1 This is a diagram illustrating a memory system 10 according to an example embodiment. (Refer to...) Figure 1The memory system 10 may include a memory device 100 and / or a controller 200. The memory system 10 may be implemented as a multi-chip package (MCP) or a system-on-a-chip (SoC).

[0032] The memory device 100 can be configured to store data received from the controller 200 or to output read data to the controller 200. The memory device 100 can be used as operational memory, working memory, or buffer memory in a computing system. In example embodiments, the memory device 100 can be implemented as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FBDIMM), a hierarchically buffered DIMM (RBDIMM), a mini DIMM, a micro DIMM, a register-equipped DIMM (RDIMM), or a low-load DIMM (LRDIMM).

[0033] In an example embodiment, memory device 100 may be implemented as volatile memory. For example, volatile memory may include at least one of the following: Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Low Power Double Data Rate SDRAM (LPDDR SDRAM), Graphics Double Data Rate SDRAM (GDDR SDRAM), Rambus DRAM (RDRAM), and Static RAM (SRAM). In an example embodiment, memory device 100 may be implemented as non-volatile memory. For example, non-volatile memory may include one of NAND flash memory, Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM), and NOR flash memory.

[0034] Although not shown in the accompanying drawings, memory device 100 may include a serial presence detection (SPD) chip. The SPD chip may be configured to store information related to the characteristics of memory device 100. In an example embodiment, the SPD chip may store memory device information, such as the module type, operating environment, column arrangement, module configuration, and storage capacity of memory device 100. In an example embodiment, the SPD chip may include a programmable read-only memory, such as an electrically erasable programmable read-only memory (EEPROM).

[0035] In addition, the memory device 100 may include a mode detection circuit 101, a mode register 102, and / or a dual-mode transceiver (XCVR) 103.

[0036] The pattern detection circuit 101 can be configured to detect an improved or optimal transmission signaling mode based on environmental information of the data channel. The transmission signaling mode can include different multi-level signaling modes. For example, the transmission signaling mode can include non-return-to-zero (NRZ), 4-level pulse amplitude modulation (PAM4), etc. For example, the pattern detection circuit 101 can select either the NRZ mode or the PAM4 mode based on channel loss, current consumption, or termination voltage.

[0037] The mode register 102 can be configured to store the transmission signaling mode selected by the mode detection circuit 101.

[0038] Transceiver (XCVR) 103 can be configured to send and receive data via a data channel (DQ channel) according to a transmission signaling mode stored in mode register 102. In an example embodiment, transceiver 103 can be implemented as a dual-mode transceiver. Hereinafter, for ease of description, transceiver 103 will be referred to as a dual-mode transceiver.

[0039] The dual-mode transceiver 103 may include a transmitter TX and a receiver RX. The transmitter TX of the memory device 100 may be configured to send read data DRD to the controller 200 via a data channel according to the transmission signaling mode PAM4 / NRZ. The receiver RX of the memory device 100 may be configured to receive write data DWR from the controller 200 via a data channel according to the transmission signaling mode PAM4 / NRZ.

[0040] The controller 200 can be configured to control the memory device 100. The controller 200 can indicate a transmission signaling mode stored in the memory device 100. The controller 200 can send data to and receive data from the memory device 100 via a data channel according to the transmission signaling mode.

[0041] Controller 200 may include transceiver 203. Transceiver 203 may include transmitter TX and receiver RX. Transmitter TX of controller 200 may be configured to send write data DWR to memory device 100 via data channel according to transmission signaling mode PAM4 / NRZ. Receiver RX of controller 200 may be configured to receive read data DRD from memory device 100 via data channel according to transmission signaling mode PAM4 / NRZ.

[0042] In example embodiments, controller 200 may be configured as an add-on chip or may be integrated with memory device 100. For example, controller 200 may be implemented on a motherboard. Furthermore, controller 200 may be implemented as an integrated memory controller (IMC) included in a microprocessor. Additionally, controller 200 may be located in an input / output hub. The input / output hub including controller 200 may be referred to as a memory controller hub (MCH).

[0043] Generally, data transmission using PAM4 signals can be advantageous in reducing the impact of channel loss caused by the increased bandwidth of the memory device interface.

[0044] The memory system 10 according to the example embodiment may have an interface including a transceiver XCVR capable of providing NRZ / PAM4 dual-mode operation to perform improved or optimal transmission operations depending on the channel environment.

[0045] Furthermore, the memory system 10 according to the example embodiment may include a memory device 100 that automatically selects the mode by changing the improved or optimal transmission signaling mode NRZ / PAM4 according to the channel environment.

[0046] Figure 2A and Figure 2B This is a diagram illustrating transmission signaling according to an example embodiment. (Reference) Figure 2A It can transmit two-bit data (00, 01, 10, and 11) corresponding to the four voltage levels VR1 to VR4 based on PAM4 transmission signaling. (See reference) Figure 2B It can transmit one bit of data 1 and 0 corresponding to two voltage levels VL and VH based on NRZ transmission signaling.

[0047] What needs to be understood is that, with Figure 2A and Figure 2B The data corresponding to the voltage levels shown are merely examples.

[0048] Figure 3 This is a diagram illustrating a pattern detection circuit 101 according to an example embodiment. (See reference...) Figure 3 The mode detection circuit 101 may include a termination voltage detector 101-1, a current detector 101-2 and / or a channel loss detector 101-3.

[0049] The termination voltage detector 101-1 can be configured to detect the termination voltage corresponding to a channel. In some example embodiments, the detected termination voltage can be used to select a transmission signaling mode. For example, when the termination voltage is higher than a reference voltage, the PAM4 mode can be selected. When the termination voltage is not higher than the reference voltage, the NRZ mode can be selected.

[0050] The current detector 101-2 can be configured to detect the current consumed by the memory device 100. In some example embodiments, the detected current consumption can be used to select a transmission signaling mode. For example, when the consumed current is higher than a reference current, the PAM4 mode can be selected. When the consumed current is not higher than the reference current, the NRZ mode can be selected. As mentioned above, it should be understood that selecting the PAM4 mode and the NRZ mode based on the consumed current is only one example. For example, when the consumed current is higher than a reference current, the NRZ mode can be selected. When the consumed current is not higher than a reference current, the PAM4 mode can be selected.

[0051] The channel loss detector 101-3 can be configured to detect loss in the data channel. In some example embodiments, the detected channel loss can be used to select a transmission signaling mode. For example, when the channel loss is greater than a reference value, the PAM4 mode can be selected. When the channel loss is not greater than the reference value, the NRZ mode can be selected.

[0052] According to the example embodiment, the mode detection circuit 101 can detect at least one of termination voltage, current consumption, and channel loss to change the transmission signaling mode corresponding to the data channel.

[0053] What needs to be understood is that Figure 3 The pattern detection circuit 101 shown is merely an example. The pattern detection circuit according to this disclosure can be implemented as at least one of a termination voltage detector 101-1, a current detector 101-2, and a channel loss detector 101-3.

[0054] Figure 4 This is a diagram illustrating a termination voltage detector 101-1 according to an example embodiment. (Refer to...) Figure 4 The termination voltage detector 101-1 may include a comparator CMP. The comparator CMP can compare the termination voltage Vterm corresponding to the data channel with the reference voltage Vref, and can output mode information MD_term to the mode register 102.

[0055] What needs to be understood is that Figure 4 The termination voltage detector 101-1 shown is just an example.

[0056] Figure 5 This is a diagram illustrating a current detector 101-2 according to an example embodiment. (Refer to...) Figure 5 The current detector 101-2 may include an amplifier OPAMP. The amplifier OPAMP can compare the current corresponding to the power supply Vreg with the load current I. LOAD The comparison can be performed, and the mode information MD_crr can be output to the mode register 102.

[0057] What needs to be understood is that, Figure 5 The current detector 101-2 shown is merely one example of this disclosure.

[0058] Figure 5 The current detector 101-2 shown can be implemented inside the memory device 100. However, this disclosure is not limited thereto. The current detector according to this disclosure can be located outside or externally to the memory device.

[0059] Figure 6 This is a diagram illustrating a current detector CD according to an example embodiment. (Reference) Figure 6 The current detector CD can be located inside the power management circuit PMIC. The current detector CD can sense the current I consumed by the memory device 100. LOAD Furthermore, it can send pattern information MD_crr corresponding to the detection result to the memory device 100.

[0060] Figure 7 This is a diagram illustrating the channel loss detector 101-3 according to an example embodiment. (Refer to...) Figure 7 The channel loss detector 101-3 may include: a comparator configured to compare the comparison voltage V at the front end or back end of the channel. REF，RX and V REF，TX The comparators are compared with each other; a multiplexer is configured to select one output from the outputs of the comparators in response to the selection signal SEL; and a frequency divider is configured to divide the output of the multiplexer. The frequency information output from the frequency divider may include mode information MD_loss and may be input to mode register 102.

[0061] What needs to be understood is that, Figure 7 The channel loss detector 101-3 shown is merely one example of this disclosure. The mode information MD_loss corresponding to the channel loss can be detected simply by comparing the voltages at the channel front end and the channel back end.

[0062] Figure 8 This is a diagram illustrating a dual-mode transceiver 103 according to an example embodiment. (Refer to...) Figure 8 The transmitter TX of the dual-mode transceiver 103 may include a serializer MUX / SER, a first driver 103-1 and / or a second driver 103-2.

[0063] The serializer MUX / SER can convert parallel data DATA1 to DATAn into serial data and output them according to the transmission signaling mode.

[0064] The first driver 103-1 can be activated in response to the first transmission signaling mode signal NRZ. The first driver 103-1 can transmit and receive data signals according to the NRZ signaling scheme.

[0065] The second driver 103-2 can be activated in response to the second transmission signaling mode signal PAM4. The second driver 103-2 can transmit and receive data signals according to the PAM4 signaling scheme. In an example embodiment, the second driver 103-2 may include a low-swing driver LSD configured to generate signals with a low-swing level (…). Figure 2A The signals of VR2 and VR3; and the high-swing driver HSD, are configured to generate signals with high swing levels (VR2 and VR3); Figure 2A The signals of VR1 and VR4). A detailed description of the second driver 103-2 is disclosed in US10,312,896, the disclosure of which is incorporated herein by reference.

[0066] like Figure 8 As shown, each of the first driver 103-1 and the second driver 103-2 may include: at least one pull-up driver between the power supply terminal VDD and the output terminal OUT; and at least one pull-down driver between the output terminal OUT and the ground terminal.

[0067] Figure 9 This is a flowchart illustrating a mode selection method for a memory device 100 according to an example embodiment. In the following text, reference will be made to... Figures 1 to 9 Describes the mode selection method for memory device 100.

[0068] The memory device 100 can communicate with the controller 200 essentially in NRZ mode (S110). It can be determined whether the half-bandwidth value BW / 2 corresponding to the data channel is greater than the reference bandwidth dB_ref (S120). When the half-bandwidth value BW / 2 is not greater than the reference bandwidth dB_ref, it can be determined whether the consumed current I is higher than the reference current I_ref (S130). When the consumed current I is not greater than the reference current I_ref, it can be determined whether the termination voltage V is higher than the reference voltage V_ref (S140). When the termination voltage V is not higher than the reference voltage V_ref, NRZ mode can be maintained (S150).

[0069] When the half-bandwidth value BW / 2 is greater than the reference bandwidth dB_ref, the consumed current I is higher than the reference current I_ref, or the termination voltage V is greater than the reference voltage V_ref, the PAM4 mode (S160) can be selected.

[0070] What needs to be understood is that, Figure 9 The comparison criteria for bandwidth shown are not limited to the half-bandwidth value BW / 2.

[0071] Moreover, it is important to understand that Figure 9 The sequence of operations shown is merely an example of this disclosure.

[0072] exist Figure 9 In the mode selection method described herein, the NRZ mode is set as the default mode, but this disclosure is not limited thereto. In the mode selection method according to this disclosure, the PAM4 mode can be set as the default mode.

[0073] Figure 10 This is a flowchart illustrating a mode selection method for a memory device 100 according to an example embodiment. In the following text, reference will be made to... Figures 1 to 10 Describes the mode selection method for memory device 100.

[0074] The memory device 100 can communicate with the controller 200 in PAM4 mode (S210). It can be determined whether the half-bandwidth value BW / 2 corresponding to the data channel is greater than the reference bandwidth dB_ref (S220). When the half-bandwidth value BW / 2 is greater than the reference bandwidth dB_ref, it can be determined whether the consumed current I is higher than the reference current I_ref (S230). When the consumed current I is higher than the reference current I_ref, it can be determined whether the termination voltage V is higher than the reference voltage V_ref (S240). When the termination voltage V is higher than the reference voltage V_ref, PAM4 mode can be maintained (S250).

[0075] NRZ mode (S260) can be selected when the half-bandwidth value BW / 2 is not greater than the reference bandwidth dB_ref, the consumed current I is not higher than the reference current I_ref, or the termination voltage V is not greater than the reference voltage V_ref.

[0076] Typically, training operations can be performed on the memory device during startup or under specific conditions. Training enables the controller to improve the reliability of data or signal exchange with the memory device. For example, training data under various conditions can be written to or read from the memory device to determine improved or optimal clock timing or reference levels. Mode selection operations of the memory device 100 according to this disclosure can be performed during the training operation period.

[0077] Figure 11 This is a diagram illustrating a memory system 20 according to an example embodiment. (Refer to...) Figure 11 ,and Figure 1Compared to the memory system 10 shown, the memory system 20 may include a controller 200a including training logic 201. The training logic 201 can perform training operations on the data channels of the memory device 100 to communicate with the memory device 100 according to a predetermined or desired scheme. Based on such training operations, the memory device 100 can detect and select the most suitable transmission signaling mode for the data channels.

[0078] According to an example embodiment, the transmission signaling mode can be selected by using the detected mode parameter to set the mode register setting (MRS).

[0079] Figure 12A This is a ladder diagram illustrating the training operation of a memory system according to an example embodiment. In the following text, reference will be made to... Figures 1 to 11 Describe the training operations in the memory device MEM and the controller CNTL.

[0080] Before communication is initiated, the controller CNTL may send a training request (or training command) to the memory device MEM (S10). The memory device MEM may, in response to the training request, perform a training operation corresponding to the data channel. Specifically, the memory device MEM may detect at least one mode parameter to select an improved or optimal transmission signaling mode for the data channel (S11). The at least one mode parameter may include the current consumed, termination voltage, and channel loss associated with the data channel. The memory device MEM may send flag information associated with the detected mode parameter to the controller CNTL (S12). The controller CNTL may select the transmission signaling mode based on the flag information (S13). The controller CNTL may send MRS information for setting the transmission signaling mode to the memory device MEM (S14). The memory device 100 may perform MRS settings associated with the transmission signaling mode PAM4 / NRZ based on the MRS information (S15).

[0081] In the memory system according to this disclosure, the transmission signaling mode setting is not limited to an MRS setting. The memory system according to this disclosure can use mode parameters detected by the memory device to select the transmission signaling mode.

[0082] Figure 12B This is a ladder diagram illustrating the training operation of a memory system according to an example embodiment. In the following text, reference will be made to... Figures 1 to 11 Describe the training operations in the memory device MEM and the controller CNTL.

[0083] Before communication is performed, the controller CNTL may send a training request (or training command) to the memory device MEM (S20). The memory device MEM may respond to the training request by performing a training operation corresponding to the data channel, and may detect at least one mode parameter as a result of the training operation (S11). The memory device MEM may use the detected mode parameter to select the transmission signaling mode PAM4 / NRZ (S22). The memory device MEM may send mode flag information corresponding to the selected transmission signaling mode PAM4 / NRZ to the controller CNTL (S23). The controller CNTL may select the transmission signaling mode PAM4 / NRZ based on the mode flag information (S24).

[0084] What needs to be understood is that Figure 12A and Figure 12B The method for selecting a transmission signaling mode using detected mode parameters described herein is merely an example of this disclosure.

[0085] Figure 13 This is a diagram illustrating a memory system performing at least one command / address calibration according to an example embodiment.

[0086] refer to Figure 13 The memory system 1000 may include a controller 1800 and / or a memory device 1900. The controller 1800 may include a clock generator 1801, a command / address CA generator 1802, a command / address reference generator 1803, a register 1804, a comparator 1806, a phase / timing controller 1808, and / or a data input unit 1810 / data output unit 1812. The controller 1800 may provide the memory device 1900 with a clock signal CK generated by the clock generator 1801 via a clock signal line.

[0087] In an example embodiment, the memory system 1000 may have an additional command / address reference signal CA_Ref line disposed in the interface. In calibration mode, the command / address reference signal CA_Ref line can be used to send and receive a reference signal CA_Ref for the command / address and a reference value for the command / address.

[0088] The calibration results using these command / address reference values ​​can be provided to the phase / timing controller 1808 to adjust the phase / timing of the command / address signal CA. Because of the presence of an additional command / address reference signal CA_Ref line, a calibration operation can be performed to adjust the phase / timing of the command / address signal CA while performing the operation for sending the command / address signal CA.

[0089] The CA generator 1802 can generate a phase- or timing-adjusted command / address signal CA in response to the control signal CTR of the phase / timing controller 1808, and can send the phase- or timing-adjusted command / address signal CA to the memory device 1900.

[0090] Command / address reference generator 1803 may have the same configuration as command / address generator 1802 and may generate the same first command / address reference signal CA_Ref as the command / address signal CA generated by command / address generator 1802.

[0091] The first command / address reference signal CA_Ref1 can be provided to register 1804. Furthermore, the first command / address reference signal CA_Ref1 can be sent to the CA reference bus 16 via data output unit 1812, and can be provided to memory device 1900 via the CA reference bus 16.

[0092] Register 1804 can store the first command / address reference signal CA_Ref1. Comparator 1806 can compare the first command / address reference signal CA_Ref1 stored in register 1804 with the third command / address reference signal CA_Ref3 output from data input unit 1810. Comparator 1804 can compare the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3 to generate a pass or fail signal P / F.

[0093] The phase / timing controller 1808 can generate a control signal CTR indicating the phase offset of the command / address signal CA based on the pass or failure signal P / F from the comparator 1806. The control signal CTR can adjust the phase or timing of the command / address signal CA to generate a phase-adjusted command / address signal CA.

[0094] The data input unit 1810 can receive the second command / address reference signal CA_Ref2 sent by the memory device 1900 through the CA reference bus, and can send the second command / address reference signal CA_Ref2 to the comparator 1806 as the third command / address reference signal CA_Ref3.

[0095] The data output unit 1812 can receive the first command / address reference signal CA_Ref1 generated by the command / address reference generator 1803 and send the first command / address reference signal CA_Ref1 to the CA reference bus 12.

[0096] The memory device 1900 may include a clock buffer 1902, a command / address CA receiver 1904, a command / address reference receiver 1906, and / or a data input unit 1908 / data output unit 1910. The clock buffer 1902 may receive a clock signal CK transmitted via a clock signal line to generate an internal clock signal ICK. The CA receiver 1904 may receive a chip select signal / CS, a clock enable signal CKE, and a command / address signal CA transmitted via the CA bus in response to the internal clock signal ICK.

[0097] The clock enable signal CKE can be used as a pseudo-command, acting as a read command for the command / address signal CA sent via the CA bus. When the clock enable signal CKE is activated, the CA receiver 1904 can receive the command / address signal CA.

[0098] Data input unit 1908 can receive the first command / address reference signal CA_Ref1 sent by controller 1800 via the CA reference bus, and can also send the first command / address reference signal CA_Ref1 to command / address reference receiver 1906. Command / address reference receiver 1906 can have the same configuration as CA receiver 1904. Command / address reference receiver 1906 can receive chip select signal / CS, clock enable signal CKE, and the first command / address reference signal CA_Ref1 sent via the CA reference bus in response to internal clock signal ICK, to generate a second command / address reference signal CA_Ref2.

[0099] The second command / address reference signal CA_Ref2 can be the same signal output by the CA receiver 1904, which receives the chip select signal / CS, clock enable signal CKE, and command / address signal CA transmitted via the CA bus in response to the internal clock signal ICK. The second command / address reference signal CA_Ref2 can be sent to the CA reference bus via the data output unit 1910.

[0100] The CA calibration performed in the memory system 1000 will be described below. The CA generator 1802 of the controller 1800 can adjust the phase or timing of the command / address signal CA in response to the control signal CTR of the phase / timing controller 1808 to send the command / address signal CA to the CA bus. The command / address reference generator 1803 can generate a first command / address reference signal CA_Refl identical to the command / address signal CA, and can send the first command / address reference signal CA_Refl to the CA reference bus.

[0101] The CA reference receiver 1906 of the memory device 1900 can receive the first command / address reference signal CA_Ref1 according to the internal clock signal ICK and the clock enable signal CKE, and generate a second command / address reference signal CA_Ref2. The second command / address reference signal CA_Ref2 of the memory device 1900 can be sent to the CA reference bus.

[0102] The controller 1800 can send a first command / address reference signal CA_Ref1, transmitted via the CA reference bus, to the comparator 1806 as a second command / address reference signal CA_Ref2. The comparator 1806 can compare the data of the first command / address reference signal CA_Ref1 with the data of the second command / address reference signal CA_Ref2 to generate a pass or fail signal P / E. The phase / timing controller 1808 can generate a control signal CTR, indicating the phase offset of the command / address signal CA, based on the pass or fail signal P / F from the comparator 1806. The CA generator 1802 can generate a phase-adjusted command / address signal CA based on the control signal CTR.

[0103] By repeating this CA calibration operation, the phase / timing controller 1808 of the controller 1800 can determine that the middle of the position of (P) is in the middle of the command / address signal CA window, and can generate a command / address signal CA to make the middle of the command / address signal CA window the edge of the clock signal CK, and provide the command / address signal CA to the memory device 1900. Therefore, the memory device 1900 can receive the command / address signal CA at the rising / falling edge of the clock signal CK, in which the middle of the effective window is set at the rising / falling edge of a pair of clock signals (clock signal pair) consisting of CK and CKB (i.e., the inverted clock signal).

[0104] A memory system 1000 according to an example embodiment may include references respectively disposed in a controller 1800 and a memory device 1900. Figures 1 to 12B The dual-mode transceiver 1820 and dual-mode transceiver 1920 are described.

[0105] In the example embodiment, each of the dual-mode transceivers 1820 and 1920 can select one of the NRZ and PAM4 modes in real time through multiple data channels DQ, and can transmit data in the selected mode.

[0106] The memory system according to the example embodiment can be disposed on a single substrate.

[0107] Figure 14 This is a diagram illustrating a memory system 2000 according to an example embodiment. Reference Figure 14The memory system 2000 may include a control chip 2100 and / or a memory chip 2200 mounted on a substrate 2001. In an example embodiment, the control chip 2100 and the memory chip 2200 may be connected to each other via the substrate 2001 having an interposer layer. Each of the control chip 2100 and the memory chip 2200 may include Figures 1 to 12B The dual-mode transceiver (dual-mode XCVR) described in [the document].

[0108] The memory device according to the example embodiment can be applied to a computing system.

[0109] Figure 15 This is a diagram illustrating a computing system 3000 according to an example embodiment. (Reference) Figure 15 The computing system 3000 may include at least one volatile memory module (DIMM) 3100, at least one non-volatile memory module (NVDIMM) 3200 and / or at least one central processing unit (CPU) 3300.

[0110] The computing system 3000 can be used as one of a variety of devices, such as computers, portable computers, ultra-mobile personal computers (UMPCs), workstations, data servers, netbooks, personal data assistants (PDAs), web tablets, cordless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), digital cameras, digital recorders / players, digital picture / video recorders / players, portable game consoles, navigation systems, black boxes, 3D televisions, devices capable of transmitting and receiving information in a wireless environment, wearable devices, various electronic devices constituting a home network, various electronic devices constituting a computer network, various electronic devices constituting a remote information network, radio frequency identification (RFID), and various electronic devices constituting a computing system, etc.

[0111] At least one non-volatile memory module 3200 may include at least one non-volatile memory. In an example embodiment, the at least one non-volatile memory may include NAND flash memory, vertical NAND (VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), thyristor random access memory (TRAM), etc.

[0112] In an example embodiment, at least one of memory module 3100 and memory module 3200 can be changed according to the channel environment. Figures 1 to 1The multi-level transmission signaling mode described in section 2 may include an interface circuit IF that performs data communication with the central processing unit 3300 according to the changed transmission signaling mode.

[0113] In an example embodiment, memory modules 3100 and 3200 can be connected to central processing unit 3300 via a DDRx interface (where x is an integer of 1 or greater).

[0114] At least one central processing unit 3300 may be implemented as controlling a volatile memory module 3100 and a non-volatile memory module 3200. In an example embodiment, the central processing unit 3300 may include a general-purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof.

[0115] According to the example embodiment, the transmission signaling mode change can be performed in the stacked memory package chip.

[0116] Figure 16 This is a diagram illustrating a computing system according to an example embodiment. (Reference) Figure 16 The computing system 4000 may include a host processor 4100 and / or at least one memory package chip 4210 controlled by the host processor 4100.

[0117] In an example embodiment, the host processor 4100 and the memory package chip 4210 can send and receive data through channel 4001.

[0118] The memory package chip 4210 may include stacked memory chips and a controller chip. For example... Figure 16 As shown, the memory package chip 4210 may include a plurality of DRAM chips disposed on the DRAM controller chip. It should be understood that the configuration of the memory package chip according to this disclosure is not limited thereto.

[0119] In an example embodiment, the transmission signaling mode can vary depending on the internal channel environment between the stacked memory chips and the controller chip of the memory package chip 4210.

[0120] In the example embodiment, the transmission signaling mode can change in real time according to the channel environment between the host processor 4100 and the memory package chip 4210.

[0121] The data communication method disclosed herein can be applied to data centers.

[0122] Figure 17 This is a diagram illustrating a data center of a memory device applied according to an example embodiment. (Reference) Figure 17Data center 7000 is a facility that collects various types of data and provides services, and may also be referred to as a data storage center. Data center 7000 may be a system for managing search engines and databases, and may be a computing system used in a company (e.g., a bank) or organization (e.g., a government agency). Data center 7000 may include application servers 7100 to 7100n and / or storage servers 7200 to 7200m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m may be selected differently according to example embodiments, and the number of application servers 7100 to 7100n and storage servers 7200 to 7200m may differ from each other.

[0123] Application server 7100 or storage server 7200 may include at least one of processors 7110 and 7210 and memories 7120 and 7220. To describe storage server 7200 as an example, processor 7210 may control the overall operation of storage server 7200 and may access memory 7220 to execute commands and / or data loaded into memory 7220. Memory 7220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), optane DIMM, or non-volatile DIMM (NVMDIMM). The number of processors 7210 included in storage server 7200 may be selected differently according to the example embodiment.

[0124] In an example embodiment, processor 7210 and memory 7220 may provide a processor-memory pair. In an example embodiment, the number of processors 7210 and memory 7220 may differ from each other. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. According to an example embodiment, application server 7100 may not include storage device 7150. Storage server 7200 may include at least one storage device 7250. Storage device 7250 may be configured to change the transmission signaling mode according to the channel environment, as referenced... Figures 1 to 16 As stated above.

[0125] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300. Network 7300 can be implemented using Fibre Channel (FC), Ethernet, etc. FC can be used as a medium for higher-speed data transmission, and optical switches can be used to provide higher performance / availability. Storage servers 7200 to 7200m can be configured as file storage, block storage, or object storage depending on the access method of network 7300.

[0126] In the example embodiment, network 7300 may be a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to a TCP / IP-based SCSI or Internet SCSI (iSCSI) protocol. In the example embodiment, network 7300 may be a general-purpose network such as a TCP / IP network. For example, network 7300 may be implemented according to protocols such as Ethernet-based FC (FCoE), network attached storage (NAS), fabrics-based NVMe (NVMe-oF), etc.

[0127] The following description will focus on application server 7100 and storage server 7200. The description of application server 7100 can be applied to another application server 7100n, and the description of storage server 7200 can be applied to another storage server 7200m.

[0128] Application server 7100 can store data requested by users or clients in one of storage servers 7200 to 7200m via network 7300. Furthermore, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server, a database management system (DBMS), etc.

[0129] Application server 7100 can access memory 7120n or storage device 7150n included in another application server 7100n via network 7300, or access storage servers 7200 to 7200m or storage devices 7250 to 7250m or memory 7220 to 7220m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n and / or storage servers 7200 to 7200m. For example, application server 7100 can execute commands to move or copy data between application servers 7100 to 7100n and / or storage servers 7200 to 7200m. In some example embodiments, data can be moved from storage servers 7200 to 7200m to storage devices 7250 to 7250m via storage devices 7220 to 7220m, thereby moving to storage servers 7200 to 7200m, or it can be directly moved to storage devices 7120 to 7120n of application servers 7100 to 7100n. Data moved via network 7300 may be encrypted for security or privacy purposes.

[0130] To describe the storage server 7200 as an example, interface 7254 can provide physical connections between processor 7210 and controller 7251, as well as between NIC 7240 and controller 7251. For example, interface 7254 can be implemented using a direct-attached storage (DAS) method, where storage device 7250 is directly connected to a dedicated cable. Furthermore, interface 7254 can be implemented in various interface configurations such as: Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral PCI Component Interconnect (PCI Fast), PCIe (NV Fast), NVMe (NVM Fast), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Memory (UFS), Embedded Universal Flash Memory (eUFS), Compact Flash Memory (CF) card interface, etc.

[0131] The storage server 7200 may also include a switch 7230 and a NIC 7240. The switch 7230 may selectively connect the processor 7210 and the storage device 7250 to each other, or selectively connect the NIC 7240 and the storage device 7250 to each other, under the control of the processor 7210.

[0132] In an example embodiment, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 can connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, DSP, host bus interface, etc., and can connect to processor 7210 and / or switch 7230 via the host bus interface. The host bus interface can be implemented as one of the above examples of interface 7254. In an example embodiment, NIC 7240 can be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0133] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send data to storage devices 7150 to 7150n and 7250 to 7250m, or send commands to memories 7120 to 7120n and 7220 to 7220m to program or read data. In some example embodiments, the data may be error-corrected data that has been corrected by an error-correcting code (ECC) engine. This data is data that has undergone data bus inversion (DBI) or data masking (DM) and may include cyclic redundancy code (CRC) information. This data may be encrypted for security or privacy purposes.

[0134] Storage devices 7150 to 7150m and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 7252 to 7252m, the read enable signal RE can be input as a data output control signal for outputting data to the DQ bus. The read enable signal RE can be used to generate a data strobe DQS. Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable signal WE.

[0135] Controller 7251 can control the overall operation of storage device 7250. In an example embodiment, controller 7251 may include static random access memory (SRAM). Controller 7251 can write data to NAND flash memory 7252 in response to a write command, or read data from NAND flash memory 7252 in response to a read command. For example, write and / or read commands may be provided by processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100n. DRAM 7253 can temporarily store (buffer) data to be written to or read from NAND flash memory 7252. Furthermore, DRAM 7253 can store metadata. Metadata is user data or data generated by controller 7251 for managing NAND flash memory 7252. Storage device 7250 may include a security element (SE) for security or privacy.

[0136] As described above, the example embodiments provide a memory device for selecting a transmission signaling mode, a controller for controlling the memory device, a memory system including the memory device, and a method for operating the same. The memory device can select a transmission signaling mode according to the channel environment, and can send and receive data according to the selected transmission signaling mode to automatically perform communication in an improved or optimal environment.

[0137] Furthermore, the memory device can detect and select improved or optimal transmission signaling patterns during the training period to operate adaptively according to the channel environment.

[0138] One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuitry; hardware / software combinations such as processors executing software; or combinations of both. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0139] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: The memory device processing circuitry is configured as follows: Send read data to the data channel according to the transmission signaling mode; Receive write data from the data channel according to the transmission signaling mode; Store the transmission signaling mode; as well as In response to a training request received from an external device, a training operation is performed on the data channel to detect at least one mode parameter, select one of a first transmission signaling mode and a second transmission signaling mode as the transmission signaling mode using the detected mode parameter, and output mode flag information associated with the detected mode parameter to the external device. The at least one mode parameter includes at least one of the following: the termination voltage corresponding to the data channel, and the current consumed by the memory device.

2. The memory device according to claim 1, wherein, The first transmission signaling mode is non-return-to-zero (NRZ) mode, and The second transmission signaling mode is 4-level pulse amplitude modulation (PAM4) mode.

3. The memory device according to claim 1, wherein, The memory device processing circuitry includes a pattern detection circuitry, which includes a termination voltage detector configured to detect the transmission signaling pattern by comparing the termination voltage with a reference voltage.

4. The memory device according to claim 1, wherein, The memory device processing circuitry includes a pattern detection circuitry, which includes a current detector configured to detect the transmission signaling pattern by comparing the current consumed by the memory device with a reference current.

5. The memory device according to claim 1, wherein, The memory device processing circuitry further includes a transmitter, the transmitter comprising: A serializer is configured to convert received parallel data into serial data according to the transmission signaling mode; A first driver is configured to output converted serial data according to the first transmission signaling mode; and The second driver is configured to output converted serial data according to the second transmission signaling mode.

6. The memory device according to claim 1, wherein, The transmission signaling mode is the NRZ mode, which is the default mode, and The transmission signaling mode is selected from the NRZ mode to the PAM4 mode based on the at least one mode parameter.

7. The memory device according to claim 1, wherein, The memory device processing circuitry includes a mode detection circuit configured to send mode selection information associated with a selected transmission signaling mode to the external device.

8. The memory device according to claim 1, wherein, The transmission signaling mode is stored in the memory device processing circuit using the mode register settings received from the external device.

9. A method of operating a memory device, the method comprising: Receive training requests for the data channel; Detect at least one mode parameter based on the training request; Send the detected pattern parameters to external devices; Based on the configuration information set from the mode register of the external device, at least one of the non-return-to-zero NRZ mode and 4-level pulse amplitude modulation PAM4 mode is set to the transmission signaling mode. as well as Communication is performed with the external device according to the pre-set transmission signaling mode. Detecting the at least one mode parameter includes: Determine whether the current consumed by the memory device is higher than a reference current; or Determine whether the termination voltage corresponding to the data channel is higher than the reference voltage.

10. The method of claim 9, further comprising: Communication is performed using the NRZ mode as the default mode.

11. The method according to claim 10, wherein, Setting the transmission signaling mode includes selecting the PAM4 mode when the consumed current is higher than the reference current or when the termination voltage is higher than the reference voltage.

12. The method according to claim 9, further comprising: Communication is performed using the PAM4 mode as the default mode. The setting of the transmission signaling mode includes selecting the NRZ mode when the consumed current is not higher than the reference current or when the termination voltage is not higher than the reference voltage.

13. A memory system, comprising: The memory device is configured to receive or transmit data via a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode; as well as A controller is configured to control the memory device and select the transmission signaling mode using at least one mode parameter, wherein the at least one mode parameter includes at least one of the following: a termination voltage corresponding to the data channel, and a current consumed by the memory device. The memory device includes: The memory device processing circuitry is configured as follows: Store the transmission signaling mode; and The system receives a training request from the controller to detect at least one mode parameter associated with the data channel in response to the training request, and sends flag information associated with the detected at least one mode parameter to the controller.

14. The memory system according to claim 13, wherein, The controller includes: The controller processing circuit corresponding to the data channel, and The controller processing circuit is configured to make a training request for the data channel, and The transmission signaling pattern is detected by the memory device processing circuit according to the training request.

15. The memory system according to claim 13, wherein, The controller is configured to communicate with the memory device according to the transmission signaling mode stored in the mode register.

16. The memory system according to claim 13, wherein, According to the first transmission signaling mode, one bit of data corresponding to each of the first voltage level and the second voltage level which is higher than the first voltage level is transmitted through the data channel.

17. The memory system according to claim 13, wherein, According to the second transmission signaling mode, two bits of data corresponding to each of the following voltage levels are transmitted through the data channel: a first voltage level, a second voltage level higher than the first voltage level, a third voltage level higher than the second voltage level, and a fourth voltage level higher than the third voltage level.

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