Merge buffer and memory device including the same

Abstract

The present application relates to a merge buffer and a memory device including the same. A memory device according to the present technology includes: a memory cell array configured to include a plane having a plurality of memory cells; a page buffer connected to at least one memory cell among the plurality of memory cells through a bit line and configured to perform a sensing operation of reading data stored in the at least one memory cell connected to the bit line; a common reference voltage generator configured to generate a common reference voltage; a plurality of merge buffers configured to generate a reference signal using the common reference voltage; and control logic configured to control operations of the common reference voltage generator and the merge buffers such that a page buffer control signal generated based on the reference signal is provided to the page buffer.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a merge buffer, and more particularly to a merge buffer and a memory device including the same. BACKGROUND

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device can include a memory device in which data is stored and a memory controller that controls the memory device. The memory device is classified into a volatile memory device and a non-volatile memory device.

[0003] The volatile memory device is a device that stores data only when power is supplied and loses the stored data when power is cut off. The volatile memory device includes a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0004] The non-volatile memory device is a device that does not lose data even if power is cut off. The non-volatile memory device includes a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, etc. SUMMARY

[0005] The memory device according to an embodiment can include a memory cell array configured to include a plane having a plurality of memory cells, a page buffer connected to at least one memory cell among the memory cells through a bit line and configured to perform a sensing operation of reading data in the at least one memory cell connected to the bit line, a common reference voltage generator configured to generate a common reference voltage, a plurality of merge buffers configured to generate a reference signal using the common reference voltage, and a control logic configured to control operations of the common reference voltage generator and the merge buffers such that a page buffer control signal generated based on the reference signal is provided to the page buffer.

[0006] The merge buffer according to an embodiment can include an input circuit configured to receive a common reference voltage, at least one constant current generator configured to generate a constant current having a constant magnitude, at least one current mirror component configured to generate a current and a mirror current having magnitudes corresponding to each other, at least one current sensing component configured to output a current in response to the mirror current, an output circuit configured to generate a reference signal based on the current output from the current sensing component and the mirror current, and a feedback component configured to generate a current in response to a voltage fed back from the output circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1is a diagram illustrating a memory system according to an embodiment.

[0008] Figure 2 is a diagram illustrating a signal exchanged between a memory controller and a memory device according to Figure 1

[0009] Figure 3 is a diagram for describing a memory device according to Figure 1

[0010] Figure 4 is a diagram illustrating an embodiment of a memory cell array of Figure 3

[0011] Figure 5 is a diagram illustrating a memory block of Figure 4

[0012] Figure 6 is a diagram illustrating an embodiment in which memory blocks of Figure 4

[0013] Figure 7 is a diagram illustrating another embodiment in which memory blocks of Figure 4

[0014] Figure 8 is a diagram illustrating a multi-plane structure in a memory device according to Figure 1

[0015] Figure 9 is a diagram illustrating an embodiment of a page buffer of Figure 3

[0016] Figure 10 is an example of a diagram illustrating a reference signal of a first to third sense signals according to Figure 9

[0017] Figure 11 is an example of a chart illustrating that a first reference sense signal is generated independently for each plane among reference signals according to Figure 10

[0018] Figure 12 is an example of a diagram illustrating a method for generating a reference signal separately for each plane.

[0019] Figure 13 is an example of a diagram illustrating another method for generating a reference signal separately for each plane.

[0020] Figure 14 is an example of a circuit diagram of a common reference voltage generator according to Figure 13

[0021] ​​​​​​​​​​​Figure 15 is an example illustrating a graph of generating a common reference voltage differently according to temperature.

[0022] Figure 16 is an example illustrating a circuit diagram of a merge buffer according to Figure 13

[0023] Figure 17 is an example illustrating a circuit diagram of an operation of a merge buffer according to Figure 16

[0024] Figure 18 is an example illustrating a circuit diagram of another embodiment of a merge buffer according to Figure 16

[0025] Figure 19 is an example illustrating a circuit diagram of still another embodiment of a merge buffer according to Figure 16

[0026] Figure 20 is an example of a circuit diagram for generating a bias voltage according to Figure 16

[0027] Figure 21 is a diagram illustrating a memory card to which a memory system according to Figure 1

[0028] Figure 22 is a block diagram illustrating a solid state drive (SSD) system to which a memory system according to Figure 1 DETAILED DESCRIPTION

[0029] The specific structural or functional descriptions disclosed in the detailed description or claims of the present specification are only examples to describe the embodiments of the present concept according to the present disclosure. The embodiments of the present concept according to the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in the present specification.

[0030] Embodiments of the present disclosure provide a merge buffer that quickly stabilizes a reference signal and supports overdrive and underdrive functions, and a memory device including the same.

[0031] The present technology can provide a merge buffer that quickly stabilizes a reference signal and supports overdrive and underdrive functions, and a memory device including the same.

[0032] Figure 1 is a diagram illustrating a memory system according to an embodiment.

[0033] Referring to Figure 1 ​​​​​​​The memory system 1000 can include a memory device 1100 in which data is stored, and / or a memory controller 1200 that controls the memory device 1100 according to a request of the host 2000.

[0034] The host 2000 can communicate with the memory system 1000 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multi-Media Card (MMC), Embedded MMC (eMMC), Dual In-Line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-reduced DIMM (LRDIMM).

[0035] The memory device 1100 can be implemented as a volatile memory device in which data is lost when power is cut off, or a non-volatile memory device in which data is maintained even if power is cut off. The memory device 1100 can perform a program operation, a read operation, or an erase operation under the control of the memory controller 1200. For example, during a program operation, the memory device 1100 can receive a command, an address, and data from the memory controller 1200 and perform a program operation. During a read operation, the memory device 1100 can receive a command and an address from the memory controller 1200 and output data stored in a location (e.g., a physical address) corresponding to the received address to the memory controller 1200. The memory device 1100 can be referred to as a chip or a die as an individual integrated chip (IC) processed as a final element.

[0036] The memory system 1000 can include a plurality of memory devices 1100 and can group the plurality of memory devices into a plurality of memory device groups 1300 according to channels connected to the memory controller 1200. For example, among the memory devices, a memory device connected to the memory controller 1200 through a first channel CH1 can be referred to as a first group GR1. Among the memory devices, a memory device connected to the memory controller 1200 through a second channel CH2 can be referred to as a second group GR2. Figure 1 A group is exemplified to include a plurality of memory devices. However, a group can include a single memory device 1100.

[0037] The memory controller 1200 can control the overall operation of the memory system 1000 and control the exchange of data between the host 2000 and the memory device 1100. For example, when a command is received from the host 2000, the memory controller 1200 can control the memory device group 1300 connected with the corresponding channel CH1 to CHk according to the received command. The memory controller 1200 can control the memory device group 1300 connected to the corresponding channel to program, read, or erase data according to the request of the host 2000.

[0038] Figure 2 is a diagram illustrating signals exchanged between a memory controller and a memory device according to Figure 1

[0039] Referring to Figure 2 , the memory controller 1200 and the memory device 1100 can exchange commands, data, and / or addresses with each other through input / output pads DQ. For example, the input / output pads DQ can be composed of eight lines to transmit and receive 8-bit data, and each line can transmit and receive 1-bit data.

[0040] The memory device 1100 can receive a chip enable signal through a CE# pad, a write enable signal through a WE# pad, a read enable signal through a RE# pad, an address latch enable signal through an ALE pad, a command latch enable signal through a CLE pad, and a write protect signal through a WP# pad.

[0041] The address latch enable signal can be a signal that instructs the memory device 1100 by the memory controller 1200 to load an address provided to the memory device 1100 through the input / output pads DQ into an address register. The chip enable signal can be a signal that instructs the memory device 1100 by the memory controller 1200 to enable or disable one or more memory devices. The command latch enable signal can be a signal that instructs the memory device 1100 by the memory controller 1200 to load a command provided to the memory device 1100 through the input / output pads DQ into a command register. The read enable signal can be a signal that instructs the memory device 1100 by the memory controller 1200 to transmit data to the memory controller 1200. The write enable signal can be a signal that informs that a command, an address, and data are transferred.

[0042] The memory device 1100 can output a ready-busy signal to the memory controller 1200 through an RB pad RB. The ready-busy signal can indicate whether a memory array of the memory device 1100 is in a busy state or an idle state.​

[0043] Figure 2 A connection relationship between a memory device 1100 and a memory controller 1200 is exemplified. However, the input / output pads DQ, the CE# pad, the WE# pad, the RE# pad, the ALE pad, the CLE pad, and the WP# pad can form channels CH1 to CHk, and one of the memory controller 1200 and the memory device group 1300 can be connected through the formed channels CH1 to CHk.

[0044] Accordingly, when the memory controller 1200 transmits a command, data, and / or an address through the input / output pads DQ included in one channel, all of the memory devices 1100 belonging to a group connected to the corresponding channel or the memory devices 1100 selected by the memory controller 1200 among the groups connected to the corresponding channel can receive the command, data, and / or address. For example, the memory controller 1200 can transmit a status read command to the memory devices 1100 through the input / output pads DQ corresponding to the first channel CH1, and at least one memory device in the first group GR1 connected with the first channel CH1 can transmit status information to the input / output pads DQ in response to the status read command.

[0045] Figure 3 is a diagram for describing Figure 1 a memory device.

[0046] The memory device 1100 can be implemented as a volatile memory device or a non-volatile memory device. For example, the memory device 1100 can be one of a volatile memory device such as a dynamic random access memory (DRAM) and a static RAM (SRAM), and a non-volatile memory device such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a flash memory. Figure 3 A non-volatile memory device is exemplified as an example.

[0047] The memory device 1100 can include a memory cell array 100 in which data is stored. The memory device 1100 can include a peripheral circuit 200 configured to perform a program operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 can include a control logic 300 that controls the peripheral circuit 200 under the control of a memory controller 1200. The control logic 300 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 300 can be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0048] The memory cell array 100 includes a plurality of memory cells in which data is stored. For example, the memory cell array 100 can include at least one plane, which can include one or more memory blocks. In an embodiment, a plane can be a unit of a memory region accessed when a program operation, a read operation, or an erase operation is performed. Each memory block can include a plurality of memory cells. A structure including a plurality of planes can be referred to as a multi-plane structure. Information necessary for the operation of the memory device 1100 and user data can be stored in the memory blocks. The memory blocks can be implemented in a two-dimensional structure or a three-dimensional structure. The memory blocks having a two-dimensional structure can include memory cells arranged in parallel to a substrate, and the memory blocks having a three-dimensional structure can include memory cells vertically stacked on a substrate.

[0049] The peripheral circuit 200 can be configured to perform the program operation, the read operation, and the erase operation according to the control of the control logic 300. For example, the peripheral circuit 200 can include a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, and a current sensing circuit 260.

[0050] The voltage generation circuit 210 can generate various operation voltages Vop for the program operation, the read operation, and the erase operation in response to an operation signal OP_CMD output from the control logic 300. For example, the voltage generation circuit 210 can generate various voltages such as a program voltage, a verify voltage, a pass voltage, a read voltage, and an erase voltage under the control of the control logic 300.

[0051] The row decoder 220 can provide the operation voltage Vop to a local line LL connected to a selected memory block among the memory blocks of the memory cell array 100 in response to a row address RADD output from the control logic 300. The local line LL can include a local word line, a local drain select line, and / or a local source select line. In addition, the local line LL can include various lines such as a source line connected to the memory block.

[0052] The page buffer group 230 can be connected to the bit lines BL1 to BLI connected to the memory blocks of the memory cell array 100. The page buffer group 230 can include a plurality of page buffers PB1 to PBI connected to the bit lines BL1 to BLI. The page buffers PB1 to PBI can operate in response to a page buffer control signal PBSIGALS output from the control logic 300. For example, the page buffers PB1 to PBI can temporarily store data received through the bit lines BL1 to BLI, or can sense a current or a voltage of the bit lines BL1 to BLI during a read operation or a verify operation.

[0053] The column decoder 240 can transfer data between the input / output circuit 250 and the page buffer group 230 in response to a column address CADD output from the control logic 300. For example, the column decoder 240 can exchange data with the page buffers PB1 to PBI through data lines DL, or exchange data with the input / output circuit 250 through column lines CL.

[0054] The input / output circuit 250 can receive a command CMD, an address ADD, and data from the memory controller 1200 through input / output pads DQ, and output data read from the memory cell array 100 to the memory controller 1200 through the input / output pads DQ. For example, the input / output circuit 250 can transfer the command CMD and the address ADD received from the memory controller 1200 to the control logic 300 or exchange data DATA with the column decoder 240.

[0055] During a read operation or a verify operation, the current sensing circuit 260 can generate a reference current in response to an enable bit VRY_BIT<#>, compare a sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current, and output a pass signal PASS or a fail signal FAIL.

[0056] The control logic 300 can receive a command CMD and an address ADD in response to signals received through the CE# pad, the WE# pad, the RE# pad, the ALE pad, the CLE pad, and the WP# pad. The control logic 300 can generate control signals for controlling the peripheral circuit 200 in response to the received command CMD and the address ADD, and output the generated control signals to the peripheral circuit 200. For example, the control signals can include at least one of an operation signal OP_CMD, a row address RADD, a column address CADD, page buffer control signals PBSIGNALS, and enable bits VRY_BIT<#>. The control logic 300 can output the operation signal OP_CMD to the voltage generation circuit 210, output the row address RADD to the row decoder 220, output the column address CADD to the column decoder 240, output the page buffer control signals PBSIGNALS to the page buffer group 230, and output the enable bits VRY_BIT<#> to the current sense circuit 260. In addition, the control logic 300 can determine whether a verification operation is passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0057] Further, at least some of the page buffer control signals PBSIGNALS can not be directly output by the control logic 300, and there can be a separate circuit that outputs the page buffer control signals PBSIGNALS according to the control of the control logic 300.

[0058] For example, the memory device 1100 can further include a common reference voltage generator 500 that generates a common reference voltage CRV, a merge buffer 510 that generates a reference signal RSIG for at least one of the page buffer control signals PBSIGNALS using the common reference voltage CRV, and a buffer circuit OPBF that receives the reference signal RSIG and outputs at least one of the page buffer control signals PBSIGNALS.

[0059] At least one of the page buffer control signals PBSIGNALS output from the buffer circuit OPBF can include at least one of a first sense signal PB_SENSE, a second sense signal SA_CSOC, and a third sense signal SA_SENSE for controlling a sensing operation of the page buffers PB1 to PBI.

[0060] The reference signal RSIG can include a first reference sense signal VPB_SENSE for generating the first sense signal PB_SENSE, a second reference sense signal VSA_CSOC for generating the second sense signal SA_CSOC, and a third reference sense signal VSA_SENSE for generating the third sense signal SA_SENSE.

[0061] The merge buffer 510 can be included in the memory device 1100 by a number corresponding to a plane of the memory cell array 100. For example, when the memory cell array 100 includes first to fourth planes P1 to P4 (refer to Figure 8 ), the memory device 1100 can include a merge buffer 510 generating a reference signal for the first plane P1, a merge buffer 510 generating a reference signal for the second plane P2, a merge buffer 510 generating a reference signal for the third plane P3, and a merge buffer 510 generating a reference signal for the fourth plane P4.

[0062] The control logic 300 can control the operation of the common reference voltage generator 500 and the merge buffer 510 so that the page buffer control signals PBSIGNALS generated based on the reference signal RSIG are provided to the page buffers PB1 to PBI. The control logic 300 can provide a first control signal CSIG1 for controlling the operation of the common reference voltage generator 500 to the common reference voltage generator 500, and can provide a second control signal CSIG2 for controlling the operation of the merge buffer 510 to the merge buffer 510. The first control signal CSIG1 can include a signal for enabling or disabling the operation of the common reference voltage generator 500 and a signal for determining the resistance value of the variable resistor Rx (refer to Figure 14 ) included in the common reference voltage generator 500. The second control signal CSIG2 can include a signal for enabling or disabling the operation of the merge buffer 510 and a drive control signal for determining the resistance values of the variable resistors VR1, VR2, and VR3 included in the merge buffer 510. The merge buffer 510 can output the reference signal RSIG having a voltage level corresponding to one of a reference level corresponding to a preset voltage level, an overdrive level higher than the reference level, and an underdrive level lower than the reference level, based on the drive control signal.

[0063] The common reference voltage generator 500, the merge buffer 510, and the buffer circuit OPBF are described below with reference to Figure 10 to Figure 20 .

[0064] Figure 4 is a diagram illustrating an embodiment of a memory cell array. Figure 3 .

[0065] Referring to Figure 4 , the memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. Each memory block can have a three-dimensional structure. Each memory block can include a plurality of memory cells stacked on a substrate. The plurality of memory cells can be arranged along the +X direction, the +Y direction, and the +Z direction.

[0066] Figure 5 This is an example Figure 4 A diagram of the storage blocks.

[0067] Reference Figure 5 An example is shown Figure 4 The first storage block BLK1 is shown among the multiple storage blocks BLK1 to BLKz. The remaining storage blocks BLK2 to BLKz may have the same shape as the first storage block BLK1.

[0068] The first memory block BLK1 may include multiple cell strings ST connected between bit lines BL1 to BLI and the source line SL. For example, cell strings ST may be connected to bit lines BL1 to BLI individually, and may be connected together to the source line SL. Since the cell strings ST are configured similarly to each other, the string ST connected to the first bit line BL1 is described as an example below.

[0069] The cell string ST may include a source selection transistor SST connected in series between the source line SL and the first bit line BL1, first memory cells F1 to the nth memory cell Fn (n is a positive integer), and a drain selection transistor DST. The number of source selection transistors SST and drain selection transistors DST is not limited to... Figure 5 The quantities shown are as follows. The source selection transistor SST can be connected between the source line SL and the first memory cell F1. The first memory cells F1 to the nth memory cell Fn can be connected in series between the source selection transistor SST and the drain selection transistor DST. The drain selection transistor DST can be connected between the nth memory cell Fn and the first bit line BL1. Although not shown in the figure, dummy cells can be further connected between memory cells F1 to Fn or between the source selection transistor SST and the drain selection transistor DST.

[0070] The gates of the source selection transistors SST, which are included in different cell strings ST, can be connected to the source selection line SSL. The gates of the first memory cells F1 to the nth memory cell Fn can be connected to the first word lines WL1 to the nth word lines WLn, respectively, and the gate of the drain selection transistor DST can be connected to the drain selection line DSL. Here, a group of memory cells connected to word lines WL1 to WLn is called a page PG. For example, a group of first memory cells F1 connected to the first word line WL1 among the memory cells F1 to Fn included in different cell strings ST can be a physical page PPG. Programming and reading operations can be performed on a physical page PPG basis.

[0071] Figure 6 This is an example of one of them. Figure 4 The diagram shows an implementation of the storage blocks in a three-dimensional configuration.

[0072] ReferenceFigure 6 For example, a first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz shown in FIG. 10 is illustrated. Figure 4 The remaining memory blocks BLK2 to BLKz can have the same shape as the first memory block BLK1.

[0073] The memory block BLK1 implemented in a three-dimensional structure can be formed in a vertical (Z-direction) I shape on a substrate, and can include a plurality of cell strings ST arranged between a bit line BL and a source line SL. Alternatively, a well can be formed instead of the source line SL. Such a structure is also referred to as bit cost scalable (BiCS). For example, when the source line SL is formed horizontally on a substrate, the cell string ST having a BiCS structure can be formed in a vertical direction (Z-direction) on the source line SL.

[0074] For example, the cell string ST can be arranged in each of a first direction (X-direction) and a second direction (Y-direction). The cell string ST can include a source select line SSL, a word line WL, and a drain select line DSL stacked on each other and spaced apart from each other. The number of the source select line SSL, the word line WL, and the drain select line DSL is not limited to the number shown in the drawing, and can differ according to the memory device 1100. The cell string ST can include a vertical channel film vertically passing through the source select line SSL, the word line WL, and the drain select line DSL, and a bit line BL contacting an upper portion of the vertical channel film CH protruding to an upper portion of the drain select line DSL and extending in the second direction (Y-direction). A memory cell can be formed between the word line WL and the vertical channel film CH. A contact plug CT can also be formed between the bit line BL and the vertical channel film CH.

[0075] Figure 7 is an example illustrating another embodiment in which Figure 4 is a diagram of another embodiment in which a memory block is configured in three dimensions.

[0076] Referring to Figure 7 For example, a first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz shown in FIG. 10 is illustrated. Figure 4 The remaining memory blocks BLK2 to BLKz can have the same shape as the first memory block BLK1.

[0077] A first storage block BLK1 implemented in a three-dimensional structure can be formed in a U shape in a vertical direction (Z direction) on a substrate, and can include a pair of source strings ST_S and drain strings ST_D connected between a bit line BL and a source line SL. The source strings ST_S and the drain strings ST_D can be connected to each other by a pipe gate PG to form a U-shaped structure. The pipe gate PG can be formed in a pipe line PL. For example, the source strings ST_S can be formed vertically between the source line SL and the pipe line PL, and the drain strings ST_D can be formed vertically between the bit line BL and the pipe line PL. Such a structure is also referred to as a pipe-shaped bit cost scalable (P-BiCS).

[0078] For example, the drain strings ST_D and the source strings ST_S can be arranged along a first direction (X direction) and a second direction (Y direction), respectively, and the drain strings ST_D and the source strings ST_S can be alternately arranged along the second direction (Y direction). The drain strings ST_D can include word lines WL and drain selection lines DSL stacked and spaced apart from each other, and a drain vertical channel film D_CH vertically passing through the word lines WL and the drain selection lines DSL. The source strings ST_S can include word lines WL and source selection lines SSL stacked and spaced apart from each other, and a source vertical channel film S_CH vertically passing through the word lines WL and the source selection lines SSL. The drain vertical channel film D_CH and the source vertical channel film S_CH can be connected to each other by a pipe gate PG in a pipe line PL. The bit line BL can contact an upper portion of the drain vertical channel film D_CH protruding to an upper portion of the drain selection line DSL and can extend in the second direction (Y direction).

[0079] Figure 8 is a diagram illustrating a multi-plane structure in a memory device according to Figure 1

[0080] Referring to Figure 8 The memory cell array 100 of the memory device 1100 can include a plurality of planes P1 to P4. For example, the first to fourth planes P1 to P4 can be included in the memory cell array 100 in one memory device 1100.

[0081] The respective first to fourth planes P1 to P4 can be connected to row decoders RD1 to RD4 and page buffer groups PBG1 to PBG4, and can be independently operated. For example, the first plane P1 can be connected to the first row decoder RD1 and the first page buffer group PBG1 to operate, the second plane P2 can be connected to the second row decoder RD2 and the second page buffer group PBG2 to operate, and the third plane P3 can be connected to the third row decoder RD3 and the third page buffer group PBG3 to operate.

[0082] ​For example, during a read operation, in response to a received row address, the respective first to fourth row decoders RD1 to RD4 can apply a read voltage to selected memory blocks from the respective first to fourth planes P1 to P4. The first to fourth page buffer groups PBG1 to PBG4 can temporarily store read data by sensing a voltage or current connected to bit lines of the first to fourth planes P1 to P4. When all sensing operations of the first to fourth planes P1 to P4 are completed, the read data temporarily stored in the first to fourth page buffer groups PBG1 to PBG4 can be sequentially output through the input / output circuit 250. For example, after read data of the first page buffer group PBG1 is first output, read data of the second to fourth page buffer groups PBG2 to PBG4 can be sequentially output.

[0083] As shown in FIG. 1, the memory device 1100 can include a plurality of planes P1 to P4. For example, the memory device 1100 can include a first plane P1, a second plane P2, a third plane P3, and a fourth plane P4. The first to fourth planes P1 to P4 can be independently controlled by the control logic 300. For example, the first to fourth planes P1 to P4 can be independently controlled by the first to fourth control logics CL1 to CL4. Figure 8 As shown, the memory device 1100 including the plurality of planes P1 to P4 can simultaneously (or in parallel) perform a read operation, a program operation, or an erase operation on pages or blocks located in different planes. For example, the memory controller 1200 can send a command indicating a plane interleaved operation to the control logic 300. For example, the memory controller 1200 can send a command indicating a plane interleaved read operation to the control logic 300 to simultaneously read pages or blocks located in different planes. As used herein with respect to occurrences, the words "simultaneously" and "simultaneously" mean occurring on overlapping time segments. For example, if a first occurrence occurs on a first time segment and a second occurrence occurs simultaneously on a second time segment, the first segment and the second segment at least partially overlap each other, such that there is a time in which both the first occurrence and the second occurrence occur.

[0084] Further, to perform the plane interleaved operation, the control logic 300 can include independent control logics CL1 to CL4 corresponding to the respective planes P1 to P4. For example, the first control logic CL1 can control operations of the first plane P1, the second control logic CL2 can control operations of the second plane P2, the third control logic CL3 can control operations of the third plane P3, and the fourth control logic CL4 can control operations of the fourth plane P4. Accordingly, the first to fourth row decoders RD1 to RD4 and the first to fourth page buffers PBG1 to PBG4 can be independently controlled by the first to fourth control logics CL1 to CL4. In addition, at least some of the control logics CL1 to CL4 can be integrated such that one control logic controls two or more planes.

[0085] Figure 9 is a diagram illustrating an embodiment of a page buffer. Figure 3

[0086] Referring to FIG. 2, the memory device 1100 can include a plurality of planes P1 to P4. For example, the memory device 1100 can include a first plane P1, a second plane P2, a third plane P3, and a fourth plane P4. The first to fourth planes P1 to P4 can be independently controlled by the control logic 300. For example, the first to fourth planes P1 to P4 can be independently controlled by the first to fourth control logics CL1 to CL4.​Figure 9 It is described that, for example Figure 3 The first page buffer PB1 among the plurality of page buffers PB1 to PBI shown can be configured identically or similarly to the first page buffer PB1, but the remaining page buffers can also be configured identically or similarly to the first page buffer PB1.

[0087] The first page buffer PB1 can operate in response to signals output from the control logic 300. The signals PB_SENSE, SA_PRECH, SA_SENSE, SA_CSOC, and SA_DISCH described below can be included in the page buffer control signals PBSIGNALS output from the control logic 140.

[0088] Referring to Figure 9 The first page buffer PB1 can include a bit line connection component 231 that electrically connects the first bit line BL1 and a common sensing node CSO in response to a first sensing signal PB_SENSE, a pre-charge-sense component 232 connected between the common sensing node CSO and a sensing node SEN and performing a pre-charge operation of charging a charge provided from a power source V_CORE to the first bit line BL1 and / or a sensing operation of sensing a current of the first bit line BL1, a sense data output circuit 233 that outputs data corresponding to a potential level of the sensing node SEN to a latch node QS, and a sense latch SLATS that latches (or stores) data output to the latch node QS. Here, a voltage of the common sensing node CSO can be determined based on a threshold voltage of a memory cell connected to the first bit line BL1, and a voltage of the sensing node SEN electrically connected to the common sensing node CSO through the pre-charge-sense component 232 can also be determined based on the threshold voltage of the memory cell connected to the first bit line BL1.

[0089] For example, the bit line connection component 231 can include a first NMOS transistor N1 connected between the first bit line BL1 and the common sensing node CSO and having a gate electrode that receives the first sensing signal PB_SENSE. Accordingly, the first NMOS transistor N1 can be turned on or off in response to the first sensing signal PB_SENSE.

[0090] The pre-charge-sense component 232 can pre-charge the first bit line BL1 in response to a pre-charge signal SA_PRECH. In addition, the pre-charge-sense component 232 can electrically connect the common sensing node CSO and a sense amplifier node SAN in response to a second sensing signal SA_CSOC, or can electrically connect the common sensing node CSO and the sensing node SEN to perform a sensing operation in response to a third sensing signal SA_SENSE.

[0091] For example, the precharge-sense component 232 can include a second NMOS transistor N2 connected between the common sense node CSO and a sense amplifier node SAN and having a gate electrode that receives a second sense signal SA CSOC, a third NMOS transistor N3 connected between the common sense node CSO and a sense node SEN and having a gate electrode that receives a third sense signal SA_SENSE, a fourth NMOS transistor N4 connected between the sense amplifier node SAN and the sense node SEN and having a gate electrode that receives a precharge signal SA_PRECH, and a first PMOS transistor PT1 connected between a power supply V_CORE and the sense amplifier node SAN and having a gate electrode that is connected to a latch node QS.

[0092] The second NMOS transistor N2 can electrically connect the sense amplifier node SAN and the common sense node CSO to each other in response to the second sense signal SA CSOC. The third NMOS transistor N3 can electrically connect the common sense node CSO and the sense node SEN to each other in response to the third sense signal SA_SENSE. The fourth NMOS transistor N4 can electrically connect the sense amplifier node SAN and the sense node SEN to each other in response to the precharge signal SA_PRECH. The first PMOS transistor PT1 can transfer charge provided from the power supply V_CORE to the sense amplifier node SAN based on a voltage level of the latch node QS.

[0093] The sense data output circuit 233 can include a second PMOS transistor PT2 including a gate electrode connected to the sense node SEN and connected between the power supply V_CORE and the latch node QS. The second PMOS transistor PT2 can electrically connect the power supply V_CORE and the latch node QS based on a voltage level applied to the sense node SEN.

[0094] The first page buffer PB1 can also include a discharge component 234 connected between the common sense node CSO and ground to discharge charge charged in the first bit line BL1 to ground. The discharge component 234 can include a fifth NMOS transistor N5 including a gate electrode to which a discharge signal SA_DISCH is provided and electrically connected between the common sense node CSO and a discharge node DN, and a sixth NMOS transistor N6 connected between the discharge node DN and ground and having a gate electrode connected to the latch node QS. In response to the discharge signal SA_DISCH, the discharge component 234 can discharge the charge charged in the first bit line BL1 by electrically connecting the common sense node CSO to ground.

[0095] Additionally, the first page buffer PB1 may also include: a seventh NMOS transistor N7, which electrically connects the common sensing node CSO and the main latch sensing node SO in response to the transmission signal TRANSO; and a main latch MLATS, which latches the voltage level of the main latch sensing node SO.

[0096] For example, the first sensing signal PB_SENSE, the second sensing signal SA_CSOC, and the third sensing signal SA_SENSE can have a constant voltage level interval between them.

[0097] Figure 10 This is an example based on Figure 9 An example of a graph of the reference signals from the first sensing signal to the third sensing signal. Figure 11 This is an example based on Figure 10 An example of a graph in which a first reference sensing signal is generated independently for each plane in the reference signal.

[0098] Reference Figure 10 The first sensing signal PB_SENSE can be generated from the first reference sensing signal VPB_SENSE, the second sensing signal SA_CSOC can be generated from the second reference sensing signal VSA_CSOC, and the third sensing signal SA_SENSE can be generated from the third reference sensing signal VSA_SENSE.

[0099] For example, the first sensing signal PB_SENSE can be a signal output from the buffer circuit OPBF after the first reference sensing signal VPB_SENSE is input to the buffer circuit OPBF. Similarly, the second sensing signal SA_CSOC can be a signal output from the buffer circuit OPBF after the second reference sensing signal VSA_CSOC is input to the buffer circuit OPBF, and the third sensing signal SA_SENSE can be a signal output from the buffer circuit OPBF after the third reference sensing signal VSA_SENSE is input to the buffer circuit OPBF.

[0100] The buffer circuit OPBF can be implemented as a single operational amplifier including a first input terminal, a second input terminal connected to the output terminal, and an output terminal, but is not limited thereto, and can be implemented as various types of buffers.

[0101] In addition, reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE need to be generated separately for each plane to generate the first sensing signal PB_SENSE, the second sensing signal SA_CSOC, and the third sensing signal SA_SENSE.

[0102] For example, the control logic 300 can support an overdrive function and an underdrive function, the overdrive function providing the first to third sense signals PB_SENSE, SA_SENSE, and SA_CSOC generated using the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE higher than the reference level to the page buffers PB1 to PBI in order to increase the sensing operation speed of the first bit line BL1, and the underdrive function providing the first to third sense signals PB_SENSE, SA_SENSE, and SA_CSOC generated using the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE lower than the reference level to the page buffers PB1 to PBI in order to prevent peak current from flowing in the first bit line BL1.

[0103] At this time, as shown in Figure 8 , for a plane interleaved operation in which a plurality of planes P1 to P4 constituting the memory cell array 100 are simultaneously operated at timings overlapping each other in time, it can be necessary to support an overdrive function or an underdrive function for each plane at independent timings.

[0104] In Figure 11 , for example, an overdrive function and an underdrive function according to a plane interleaved operation are shown for a first reference sense signal VPB_SENSE among the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE.

[0105] Referring to Figure 11 , as an example, a voltage level change of the first reference sense signals VPB_SENSE_P1, VPB_SENSE_P2, VPB_SENSE_P3, and VPB_SENSE_P4 can be examined in a case where the memory cell array 100 includes four planes P1 to P4.

[0106] For example, for a plane interleaved operation, a timing at which the first reference sense signal VPB_SENSE_P1 for the first plane P1 reaches the reference level, a timing at which the first reference sense signal VPB_SENSE_P2 for the second plane P2 reaches the reference level, a timing at which the first reference sense signal VPB_SENSE_P3 for the third plane P3 reaches the reference level, and a timing at which the first reference sense signal VPB_SENSE_P4 for the fourth plane P4 reaches the reference level can be different from each other.

[0107] For example, for the planar interleaving operation, the timing at which the first reference sense signal VPB_SENSE_P1 for the first plane P1 reaches the overdrive level OVD higher than the reference level, the timing at which the first reference sense signal VPB_SENSE_P2 for the second plane P2 reaches the overdrive level OVD higher than the reference level, the timing at which the first reference sense signal VPB_SENSE_P3 for the third plane P3 reaches the overdrive level OVD higher than the reference level, and the timing at which the first reference sense signal VPB_SENSE_P4 for the fourth plane P4 reaches the overdrive level OVD higher than the reference level can be different from each other.

[0108] In addition, for the planar interleaving operation, the timing at which the first reference sense signal VPB_SENSE_P1 for the first plane P1 reaches the undrive level UND lower than the reference level, the timing at which the first reference sense signal VPB_SENSE_P2 for the second plane P2 reaches the undrive level UND lower than the reference level, the timing at which the first reference sense signal VPB_SENSE_P3 for the third plane P3 reaches the undrive level UND lower than the reference level, and the timing at which the first reference sense signal VPB_SENSE_P4 for the fourth plane P4 reaches the undrive level UND lower than the reference level can be different from each other.

[0109] Therefore, it can be necessary to generate the first reference sense signal VPB_SENSE to have the overdrive level OVD and the undrive level UND independently for each plane. In addition, similar to the first reference sense signal VPB_SENSE, it can be necessary to generate the second reference sense signal VSA_CSOC and the third reference sense signal VSA_SENSE to have the overdrive level OVD and the undrive level UND independently for each plane.

[0110] Figure 12 is an example of a diagram illustrating a method for generating reference signals separately for each plane.

[0111] One of the methods for causing the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE to have the overdrive level OVD and the undrive level UND independently for each plane can be to generate the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE separately for each plane.

[0112] Referring to Figure 12 , the memory device 1100 can include the plane reference voltage generator 400 in order to generate the reference signals VPB_SENSE_P1, VSA_SENSE_P1, and VSA_CSOC_P1 for the first plane P1. In addition, although not illustrated in FIG. 11, the memory device 1100 can include the plane reference voltage generator 400 in order to generate the reference signals VPB_SENSE_P2, VSA_SENSE_P2, and VSA_CSOC_P2 for the second plane P2, the reference signals VPB_SENSE_P3, VSA_SENSE_P3, and VSA_CSOC_P3 for the third plane P3, and the reference signals VPB_SENSE_P4, VSA_SENSE_P4, and VSA_CSOC_P4 for the fourth plane P4. Figure 12As shown, however, the memory device 1100 may include a separate plane reference voltage generator 400 for each plane to generate reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE independently for each plane.

[0113] The planar reference voltage generator 400 can generate an output voltage (not shown) by receiving a constant voltage VBG0 that mitigates the effects of temperature changes, and divides the generated output voltage into three voltage levels to generate a first output voltage v1, a second output voltage v2, and a third output voltage v3. The first output voltage v1 can be input to a buffer circuit OPBF to generate a third reference sensing signal VSA_SENSE_P1 for the first plane P1, the second output voltage v2 can also be input to the buffer circuit OPBF to generate a second reference sensing signal VSA_CSOC_P1 for the first plane P1, and the third output voltage v3 can be input to the buffer circuit OPBF to generate a first reference sensing signal VPB_SENSE_P1 for the first plane P1.

[0114] The planar reference voltage generator 400 can generate voltages corresponding to overdrive and underdrive levels for the first output voltage v1 to the third output voltage v3, respectively, to support overdrive and underdrive functions.

[0115] like Figure 12 As shown, when a plane reference voltage generator 400 is provided for each plane, there is an advantage that the voltage levels required for plane interleaving operation can be generated individually for each plane. However, since an independent plane reference voltage generator 400 needs to be provided for each plane, the circuit area of ​​the memory device 1100 is greatly increased, and mismatch may occur between the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE generated for each plane because the characteristics of the plane reference voltage generator 400 are slightly different for each plane.

[0116] Figure 13 This is an example of a diagram illustrating another method for generating reference signals individually for each plane.

[0117] Reference Figure 13, the memory device 1100 can include a common reference voltage generator 500 that generates a common reference voltage CRV by receiving a constant voltage VBG0 mitigating an effect from a temperature change, and generates reference signals for one plane (e.g., VPB_SENSE_P1, VSA_SENSE_P1, and VSA_CSOC_P1 as reference signals for the first plane P1) using the common reference voltage CRV. For example, one merge buffer can correspond to one plane. That is, since the merge buffer 510 generates reference signals for one plane, the memory device 1100 including a plurality of planes can include as many merge buffers 510 as the number corresponding to the number of planes.

[0118] Unlike the plane reference voltage generator 400 according to Figure 12 , since only one common reference voltage generator 500 is included in the memory device 1100, it has an advantage in that, compared to the case of Figure 12 , a circuit area can be greatly reduced.

[0119] In addition, even if one single common reference voltage generator 500 is used, reference signals for an overdrive level and an underdrive level used for a plane interleaving operation will be needed. For this, in Figure 13 , the merge buffer 510 can generate reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE corresponding to the overdrive level and the underdrive level using the common reference voltage CRV.

[0120] Figure 14 is an example of a circuit diagram of a common reference voltage generator according to Figure 13 . Figure 15 is an example of a graph illustrating generation of a common reference voltage according to a temperature difference.

[0121] Referring to Figure 14 , the common reference voltage generator 500 can include an operational amplifier 501, a first initial current generator 502 that generates a first initial current Ia based on an output of the operational amplifier 501, an initial current mirror assembly 503 that generates a second initial current Ib corresponding to the first initial current Ia, and a temperature compensator 504 that outputs a common reference voltage CRV compensating for a temperature change of a bit line based on the second initial current Ib generated by the initial current mirror assembly 503.

[0122] The operational amplifier 501 can include a first input terminal to which a constant voltage VBG0 applied to mitigate an influence from a temperature change is applied, a second input terminal electrically connected to an output node OUTN of the common reference voltage generator 500 through a feedback output node OUTN, and an output terminal that amplifies and outputs a difference between signals applied to the first input terminal and the second input terminal.

[0123] The first initial current generator 502 can include a first transistor T1 including a gate electrode connected to the output terminal of the operational amplifier 501 and connected between a first node ND1 and a second power source VSSI. The first transistor T1 can be turned on in response to the output of the operational amplifier 501 to conduct a first initial current Ia between the first node ND1 and the second power source VSSI.

[0124] The initial current mirror assembly 503 can include a first resistor R1 connected between the first node ND1 and a second node ND2, a second transistor T2 connected between a first power source VCCE and a third transistor T3 and having a gate electrode connected to the second node ND2, the third transistor T3 connected between the second transistor T2 and the second node ND2 and having a gate electrode connected to the first node ND1, a fourth transistor T4 connected between the first power source VCCE and a fifth transistor T5 and having a gate electrode connected to the second node ND2, and the fifth transistor T5 connected between the fourth transistor T4 and the output node OUTN and having a gate electrode connected to the first node ND1.

[0125] The temperature compensator 504 can include a sixth transistor T6 connected between the output node OUTN and a third node ND3 and having a gate electrode connected to the output node OUTN, and a variable resistor Rx connected between the third node ND3 and a fourth node ND4. Here, the variable resistor Rx can be a resistance determined by the control logic 300 so that a preset voltage (for example, a voltage between 0.2 and 0.65) is applied to the third node ND3. For example, the resistance value of the variable resistor Rx can be determined based on a first control signal CSIG1 provided from the control logic 300.

[0126] Figure 14 The illustrated first transistor T1 and sixth transistor T6 can be NMOS transistors, and the second transistor T2 to the fifth transistor T5 can be PMOS transistors, but are not limited thereto. It should be construed to include application of the PMOS transistors and the NMOS transistors in reverse, and the connection relationship between the transistors is replaced accordingly (the connection relationship between the transistors is replaced in reverse so that the current direction is reversed). In an embodiment, the second resistor R2 can be connected between the fourth node ND4 and the second power source VSSI.

[0127] Further, the sixth transistor T6 can have a characteristic corresponding to a transistor (at least one of the first to third NMOS transistors N1 to N3) receiving one of the first to third sense signals PB_SENSE, SA_CSOC, and SA_SENSE in the page buffer (e.g., the first page buffer PB1) according to Figure 9 Further, the sixth transistor T6 can have a characteristic corresponding to a transistor (at least one of the first to third NMOS transistors N1 to N3) receiving one of the first to third sense signals PB_SENSE, SA_CSOC, and SA_SENSE in the page buffer (e.g., the first page buffer PB1) according to Figure 9 Further, the sixth transistor T6 can have a characteristic corresponding to a transistor (at least one of the first to third NMOS transistors N1 to N3) receiving one of the first to third sense signals PB_SENSE, SA_CSOC, and SA_SENSE in the page buffer (e.g., the first page buffer PB1) according to

[0128] A change in threshold voltage of at least one transistor (e.g., the first NMOS transistor N1 receiving the first sense signal PB_SENSE) connected to the bit line can cause a change in voltage applied to the bit line. At this time, since the temperature compensator 504 generates the common reference voltage CRV at the output node OUTN in consideration of a change in characteristic (e.g., threshold voltage characteristic) according to the temperature of at least one transistor connected to the bit line, the voltage of the bit line can always be kept constant (to minimize a change in voltage according to temperature). In other words, the common reference voltage CRV can be generated differently according to temperature to compensate for a change in voltage according to the temperature of the bit line.

[0129] Referring to Figure 15 , a graph in which the common reference voltage CRV is generated differently as the temperature TEMP changes is shown. That is, as Figure 15 indicated, the common reference voltage CRV can be generated to have a higher voltage as the temperature decreases, and a lower voltage as the temperature increases.

[0130] Figure 16 is an example illustrating a circuit diagram of the merge buffer according to Figure 13 .

[0131] Referring to Figure 16The merging buffer 510 can include an input circuit 511 receiving a common reference voltage CRV, at least one current mirror component 514, 515 and 517 generating a current and a mirror current having a magnitude corresponding to each other, at least one current sensing component 516 and 518 outputting a current in response to the mirror current, an output circuit 519 generating a reference signal VPB_SENSE, VSA_CSOC and VSA_SENSE for one plane based on the current and the mirror current output from the current sensing component 516 and 518, a feedback component 512 generating a current in response to a voltage fed back from the output circuit 519, and at least one constant current generator 513 and 520 generating a constant current having a constant magnitude.

[0132] In addition, the merging buffer 510 can further include at least one mirror current receiver 521 and 522 receiving the mirror current.

[0133] The input circuit 511 can be electrically connected to the first power source VCCE through the first current mirror component 514, and can generate the first current I1 in response to the common reference voltage CRV.

[0134] The feedback component 512 can be electrically connected to the first power source VCCE through the second current mirror component 515, and can generate the second current I2 in response to the voltage fed back from the output circuit 519.

[0135] The at least one constant current generator 513 and 520 can include a first constant current generator 513 connected between a first node D1 which is a common node of the input circuit 511 and the feedback component 512 and a second power source VSSI and outputting a first constant current Ic1 having a constant magnitude, and a second constant current generator 520 connected between the output circuit 519 and the second power source VSSI and outputting a second constant current Ic2 having a constant magnitude. The first constant current generator 513 and the second constant current generator 520 can be respectively implemented as a current source generating the first constant current Ic1 and a current source generating the second constant current Ic2.

[0136] For example, the input circuit 511 can include a first transistor TR1 connected between the first node D1 and a second node D2 and having a gate electrode receiving the common reference voltage CRV.

[0137] The at least one current mirror component 514, 515 and 517 can include a first current mirror component 514 generating a first mirror current I1' corresponding to the first current I1 and a second current mirror component 515 generating a second mirror current I2' corresponding to the second current I2.

[0138] For example, the first current mirror assembly 514 can include a second transistor TR2 connected between the first supply VCCE and a second node D2 and having a gate electrode connected to the second node D2, and a third transistor TR3 connected between the first supply VCCE and a third node D3 and having a gate electrode connected to the second node D2.

[0139] For example, the second current mirror assembly 515 can include a fourth transistor TR4 connected between the first supply VCCE and a fourth node D4 and having a gate electrode connected to the fourth node D4, and a fifth transistor TR5 connected between the first supply VCCE and a fifth node D5 and having a gate electrode connected to the fourth node D4.

[0140] The at least one current sensing assembly 516 and 518 can include a first current sensing assembly 516 that outputs a third current I3 in response to a first mirror current I1', and a second current sensing assembly 518 that outputs a fourth current I4 in response to a second mirror current I2'.

[0141] For example, the first current sensing assembly 516 can include a sixth transistor TR6 connected between a sixth node D6 and the second supply VSSI and having a gate electrode connected to the third node D3. The second current sensing assembly 518 can include a seventh transistor TR7 connected between the first output node O1 and the second supply VSSI and having a gate electrode connected to the fifth node D5.

[0142] The at least one current mirror assembly 514, 515, and 517 can further include a third current mirror assembly 517 that generates a third mirror current I3' corresponding to the third current I3. For example, the third current mirror assembly 517 can include an eighth transistor TR8 connected between the first supply VCCE and the sixth node D6 and having a gate electrode connected to the sixth node D6, and a ninth transistor TR9 connected between the first supply VCCE and the first output node O1 and having a gate electrode connected to the sixth node D6.

[0143] The output circuit 519 can be connected between the first output node O1 commonly connected to the third current mirror assembly 517 and the second current sensing assembly 518 and a seventh node D7 of the second constant current generator 520, and can receive a difference current between the third mirror current I3' and the fourth current I4 through the first output node O1.

[0144] The output circuit 519 can output the third reference sensing signal VSA_SENSE through the first output node O1, distribute a voltage applied to the first output node O1, output the second reference sensing signal VSA_CSOC through the second output node O2, and output the first reference sensing signal VPB_SENSE through the third output node O3. For example, the output circuit 519 can include a first variable resistor VR1 connected between the first output node O1 and the second output node O2, a second variable resistor VR2 connected between the second output node O2 and the third output node O3, and a third variable resistor VR3 connected between the third output node O3 and the seventh node D7 of the second constant current generator 520.

[0145] The resistance value of at least one of the first to third variable resistors VR1, VR2, and VR3 can be determined based on a drive control signal provided from the control logic 300. Here, the resistance value is changed according to the drive control signal, and when the resistance value is changed, the voltage level of the reference signal can become a reference level, can increase from the reference level to an overdrive level, or can decrease from the reference level to an underdrive level. In more detail, for example, at least one of the first to third variable resistors VR1, VR2, VR3 can include a plurality of resistors and a switching transistor connected in parallel to at least some of the plurality of resistors and receiving the drive control signal.

[0146] For example, the feedback component 512 can include a tenth transistor TR10 connected between the first node D1 and the fourth node D4 and having a gate electrode connected to the seventh node D7.

[0147] For example, the first constant current generator 513 can include an eleventh transistor TR11 connected between the first node D1 and the second power supply VSSI and having a gate electrode to which a first bias voltage NBIAS1 is applied. The second constant current generator 520 can include a twelfth transistor T12 connected between the seventh node D7 and a thirteenth transistor TR13 and having a gate electrode to which a second bias voltage NBIAS2 is applied, and the thirteenth transistor T13 connected between the twelfth transistor T12 and the second power supply VSSI and having a gate electrode to which the first bias voltage NBIAS1 is applied.

[0148] The at least one mirror current receiver 521 and 522 can include a first mirror current receiver 521 receiving a first mirror current I1' and a second mirror current receiver 522 receiving a second mirror current I2'.

[0149] The first mirror current receiver 521 can include a fourteenth transistor TR14 connected between the third node D3 and a fifteenth transistor TR15 and having a gate electrode to which the second bias voltage NBIAS2 is applied, and the fifteenth transistor TR15 connected between the fourteenth transistor TR14 and the second power source VSSI and having a gate electrode connected to the third node D3.

[0150] The second mirror current receiver 522 can include a sixteenth transistor TR16 connected between the fifth node D5 and a seventeenth transistor TR17 and having a gate electrode to which the second bias voltage NBIAS2 is applied, and the seventeenth transistor TR17 connected between the sixteenth transistor TR16 and the second power source VSSI and having a gate electrode connected to the third node D3.

[0151] In Figure 16 , the first transistor TR1 and the tenth to seventeenth transistors TR10 to TR17 can be NMOS transistors, and the second to ninth transistors TR2 to TR9 can be PMOS transistors. In Figure 16 , the first power source VCCE can provide a high-level voltage higher than a voltage of the second power source VSSI, and the second power source VSSI can provide a low-level voltage or a ground voltage relatively lower than a voltage of the first power source VCCE.

[0152] Figure 17 is an example of a circuit diagram illustrating an operation of the merge buffer according to Figure 16 .

[0153] The merge buffer 510 according to Figure 16 can generate and output the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE through the output circuit 519. At this time, a case in which the first reference sense signal VPB_SENSE is suddenly reduced among the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE can be considered.

[0154] In this case, as the voltage applied to the gate electrode of the tenth transistor TR10 of the feedback assembly 512 is reduced, the magnitude of the second current I2 can be reduced. Also, since the total current of the first current I1 and the second current I2 passing through the first constant current generator 513 is the same as the first constant current Ic1 of the constant magnitude, the magnitude of the first current I1 can be increased with respect to the magnitude of the second current I2. The magnitude of the third current I3 generated through the first current sensing assembly 516 can also be increased according to the first mirror current I1' corresponding to the increased first current I1. Also, the magnitude of the third mirror current I3' can also be increased to have a magnitude corresponding to the magnitude of the third current I3.

[0155] On the other hand, when the magnitude of the second current I2 decreases, the magnitude of the second mirror current I2' also decreases, and thus the magnitude of the fourth current I4 generated by the second current sensing component 518 can also decrease. Since the magnitude of the third mirror current I3' increases and the magnitude of the fourth current I4 decreases, the current input through the output circuit 519 (the difference current between the third mirror current I3' and the fourth current I4) can increase, and the magnitude of the first reference sense signal VPB_SENSE can increase. In the same manner, when the magnitude of the first reference sense signal VPB_SENSE suddenly increases, the magnitude of the first reference sense signal VPB_SENSE can decrease as the current fluctuates in the opposite direction to the increase and decrease of the current described above (or as shown in FIG. 6B). Figure 17 In the same manner, when the magnitude of the first reference sense signal VPB_SENSE suddenly decreases, the magnitude of the first reference sense signal VPB_SENSE can increase as the current fluctuates in the opposite direction to the increase and decrease of the current described above (or as shown in FIG. 6B).

[0156] In the same manner as the increase and decrease of the first reference sense signal VPB_SENSE, the merge buffer 510 can operate in the direction of canceling the increase and decrease of the second reference sense signal VSA_CSOC and the third reference sense signal VSA_SENSE.

[0157] As described above, since the merge buffer 510 quickly cancels the increase and decrease of the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE, the merge buffer 510 can reduce the setup time and stably output the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE.

[0158] In addition, Figure 16 The merge buffer 510 shown in FIGS. 6A and 6B is not necessarily used only to generate the reference signals of the memory device 1100, but can be used as an independent regulator that stabilizes the output signals corresponding to the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE based on the stable operation described above.

[0159] Figure 18 is an example of a circuit diagram illustrating another embodiment of a merge buffer according to Figure 16 Figure 19 is an example of a circuit diagram illustrating yet another embodiment of a merge buffer according to Figure 16

[0160] Referring to Figure 18 In the merge buffer 610 according to another embodiment, the positions of the input circuit 511 and the feedback component 512 of the merge buffer 510 according to Figure 16

[0161] Referring to Figure 19 In the merge buffer 710 according to yet another embodiment, the positions of the input circuit 711 and the feedback component 712 of the merge buffer 510 according to Figure 16 ​​​The NMOS transistors included in the merging buffer 510 can be replaced with PMOS transistors and can be adjusted according to... Figure 16 The PMOS transistors included in the merge buffer 510 are replaced with NMOS transistors, and the wiring order of each component can be replaced in reverse order. Besides the transistor types being reversed, Figure 19 The transistors TR1 to TR17 shown are Figure 16 The transistors TR1 to TR17 are identical, therefore, transistors TR1 to TR17 are represented by the same reference numerals.

[0162] Furthermore, when such Figure 19 When replacing the transistor type as shown, Figure 16 The first bias voltage NBIAS1 and the second bias voltage NBIAS2 can be replaced by the first PMOS voltage PBIAS1 and the second PMOS voltage PBIAS2, respectively, and the connection relationship between the first power supply VCCE and the second power supply VSSI can be interchanged.

[0163] Alternatively, it can be replaced Figure 16 The connection relationship between the sixth transistor TR6 and the seventh transistor TR7 in the merging buffer 510. For example, as... Figure 19 As shown, the sixth transistor TR6 can be connected between the first output node O1 and the second power supply VSSI, and the seventh transistor TR7 can be connected to the sixth node D6 and the second power supply VSSI.

[0164] In addition, such as Figure 19 As shown, it can be changed according to Figure 16 The merging buffer 510 is configured to output one of the reference signals VPB_SENSE, VSA_CSOC, and VSA_SENSE through the seventh node D7 instead of the first output node O1.

[0165] In addition, such as Figure 19 As shown, the information provided can be omitted. Figure 16 The fourteenth transistor TR14 and the sixteenth transistor TR16 in the merge buffer 510.

[0166] Figure 20 It is used to generate based on Figure 16 An example of a circuit diagram for the bias voltage.

[0167] The memory device 1100 according to the embodiment may include a bias voltage generator 800, which generates a bias voltage according to... Figure 16 The bias voltages NBIAS1 and NBIAS2.

[0168] For example, the bias voltage generator 800 can include a current source RCT generating a constant current regardless of a change in temperature or threshold voltage, a first transistor Tr1 having a gate electrode receiving an enable signal EN and connected between the current source RCT and a first bias output terminal OT1, a resistor r connected between the first bias output terminal OT1 and a second bias output terminal OT2, a second transistor Tr2 connected between the second bias output terminal OT2 and a third transistor Tr3 and having a gate electrode connected to the first bias output terminal OT1, and the third transistor Tr3 connected between the second transistor Tr2 and a second power supply VSSI and having a gate electrode connected to the second bias output terminal OT2.

[0169] Here, the resistor r can convert the current generated by the current source RCT into a voltage. The second bias voltage NBIAS2 can be output through the first bias output terminal OT1, and the first bias voltage NBIAS1 can be output through the second bias output terminal OT2.

[0170] The first transistor Tr1 can be turned on in response to the enable signal EN to transfer the current generated by the current source RCT to the resistor r.

[0171] The above-described enable signal EN can be included in page buffer control signals PBSIGNALS provided from the control logic 300.

[0172] Therefore, since the bias voltage generator 800 generates constant bias voltages NBIAS1 and NBIAS2 regardless of temperature, etc., and supplies the constant bias voltages NBIAS1 and NBIAS2 to the merge buffer 510, the merge buffer 510 can generate constant currents Ic1 and Ic2 that are not affected by temperature, etc., based on the bias voltages.

[0173] Figure 21 is a diagram illustrating a memory card to which a memory system is applied. Figure 1

[0174] Referring to Figure 21 , the memory system can include a host 2000 and a memory card 70000.

[0175] The memory card 70000 can be implemented as a smart card. The memory card 70000 can include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0176] The memory controller 1200 can control exchange of data between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 can be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.​

[0177] The card interface 7100 can interface data exchange between the host 2000 and the memory controller 1200 according to a protocol of the host 2000. According to an embodiment, the card interface 7100 can support a Universal Serial Bus (USB) protocol and an Inter-Chip (IC)-USB protocol. Here, the card interface 7100 can refer to hardware capable of supporting a protocol used by the host 2000, software installed in the hardware, or a signal transmission method.

[0178] Figure 22 is a block diagram of a Solid State Drive (SSD) system exemplifying a memory system according to Figure 1

[0179] Referring to Figure 22 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 through a signal connector 3001 and receives a power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 through 322n, an auxiliary power supply device 3230, and a buffer memory 3240.

[0180] In an embodiment, the SSD 3200 can be a component corresponding to the memory device 1100, and can further include at least one of the buffer circuit OPBF, the plane reference voltage generator 400, the common reference voltage generator 500, the merge buffer 510, and the bias voltage generator 800 described with reference to Figure 10 to 20

[0181] The SSD controller 3210 can control the plurality of flash memories 3221 through 322n in response to a signal SIG received from the host 3100. For example, the signal SIG can be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG can be by such as a Universal Serial Bus (USB), a Multimedia Card (MMC), an Embedded MMC (eMMC), a Peripheral Component Interconnect (PCI), a PCI Express (PCI-E), an Advanced Technology Attachment (ATA), a Serial ATA, a Parallel ATA, a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), a FireWire, a Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0182] ​​The auxiliary power supply device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power supply device 3230 can receive the power PWR from the host 3100 and can charge the power. The auxiliary power supply device 3230 can supply power of the SSD 3200 when the power supply from the host 3100 is not smooth. For example, the auxiliary power supply device 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply device 3230 can be located on a main board and can supply auxiliary power to the SSD 3200.

[0183] The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 through 322n, or can temporarily store metadata (for example, a mapping table) of the flash memories 3221 through 322n. The buffer memory 3240 can include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0184] CROSS-REFERENCE TO RELATED APPLICATIONS

[0185] This application claims priority to Korean Patent Application No. 10-2020-0100167, filed on August 10, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A memory device, the memory device comprising: an array of memory cells including a plurality of planes having a plurality of memory cells; a plurality of page buffers connected to the plurality of planes respectively through a plurality of bit lines and performing a sensing operation independently for each of the plurality of planes; a common reference voltage generator generating a common reference voltage; a plurality of merge buffers generating a plurality of reference signals using the common reference voltage; and control logic controlling operations of the plurality of page buffers using a plurality of page buffer control signals generated based on the plurality of reference signals, wherein each of the plurality of merge buffers generates a reference signal corresponding to each of the plurality of planes. The reference signal corresponds to one of an overdrive level higher than a preset reference level and an underdrive level lower than the preset reference level.

2. The memory device of claim 1, wherein, The plurality of page buffer control signals include a first sensing signal, a second sensing signal, and a third sensing signal for controlling the sensing operation, and 3. The memory device of claim 1, wherein, wherein the reference signal includes at least one of a first reference sensing signal for generating the first sensing signal, a second reference sensing signal for generating the second sensing signal, and a third reference sensing signal for generating the third sensing signal. Each of the plurality of page buffers includes:

4. The memory device of claim 3, wherein, a bit line connection component electrically connecting the plurality of bit lines and a common sensing node in response to the first sensing signal; a pre-charge-sense component including a sense amplifier node, the pre-charge-sense component electrically connecting the common sensing node and the sense amplifier node in response to the second sensing signal and electrically connecting the common sensing node and a sense node in response to the third sensing signal; and a sense data output circuit outputting data corresponding to a potential level of the sense node. The bit line connection component includes a first NMOS transistor connected between each of the plurality of bit lines and the common sensing node and having a gate electrode receiving the first sensing signal, 5. The memory device of claim 4, wherein, wherein the pre-charge-sense component includes: a second NMOS transistor connected between the common sensing node and the sense amplifier node and having a gate electrode receiving the second sensing signal; a third NMOS transistor connected between the common sensing node and the sense node and having a gate electrode receiving the third sensing signal; a fourth NMOS transistor connected between the sense amplifier node and the sense node and having a gate electrode receiving a pre-charge signal; and a first PMOS transistor connected between a power source and the sense amplifier node and having a gate electrode connected to a latch node. The common reference voltage generator includes:

6. The memory device of claim 1, wherein, an operational amplifier; ​ a first initial current generator generating a first initial current based on an output of the operational amplifier; an initial current mirror assembly generating a second initial current corresponding to the first initial current; and a temperature compensator outputting the common reference voltage compensating for a temperature change of each of the plurality of bit lines based on the second initial current.

7. The memory device of claim 6, wherein, The operational amplifier includes: a first input terminal receiving a constant voltage mitigating an effect from a temperature change; a second input terminal electrically connected to an output node of the common reference voltage generator to receive a feedback of a voltage of the output node; and an output terminal amplifying and outputting a difference between signals applied to the first input terminal and the second input terminal.

8. The memory device of claim 6, wherein, The temperature compensator includes a transistor having a threshold voltage characteristic corresponding to a threshold voltage characteristic of a transistor from the plurality of page buffers receiving at least one of the plurality of page buffer control signals.

9. The memory device of claim 3, wherein, Each of the plurality of merge buffers includes: an input circuit receiving the common reference voltage; at least one constant current generator generating a constant current having a constant magnitude; at least one current mirror assembly generating a current and a mirror current having magnitudes corresponding to each other; at least one current sensing assembly outputting a current in response to the mirror current; an output circuit generating the reference signal based on the current output from the at least one current sensing assembly and the mirror current; and a feedback assembly generating a current in response to a voltage fed back from the output circuit.

10. The memory device of claim 9, wherein, The input circuit is electrically connected to a first power source through the at least one current mirror assembly and generates a first current in response to the common reference voltage, and The feedback assembly is electrically connected to the first power source through the at least one current mirror assembly and generates a second current in response to the fed back voltage.

11. The memory device of claim 10, wherein, The at least one constant current generator includes: a first constant current generator connected between a first node which is a common node of the input circuit and the feedback assembly and a second power source to output a first constant current having a constant magnitude; and a second constant current generator connected between the output circuit and the second power source to output a second constant current having a constant magnitude.

12. The memory device of claim 11, wherein, The at least one current mirror assembly includes: a first current mirror assembly generating a first mirror current corresponding to the first current; and a second current mirror assembly generating a second mirror current corresponding to the second current.

13. The memory device of claim 12, wherein, The at least one current sensing assembly includes: a first current sensing assembly outputting a third current in response to the first mirror current; and a second current sensing assembly outputting a fourth current in response to the second mirror current. a second current sensing component that outputs a fourth current in response to the second mirror current, and the at least one current mirror component further includes a third current mirror component that generates a third mirror current corresponding to the third current.

14. The memory device of claim 13, wherein, the output circuit is connected between a first output node that is commonly connected to the third current mirror component and the second current sensing component and the second constant current generator, and receives a difference current between the third mirror current and the fourth current through the first output node.

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