Non-volatile memory device

Abstract

The present invention provides a non-volatile memory device, comprising a first memory cell array, a first error correction code (ECC) decoder, and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array and performs an ECC operation on read data from the first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder and adjusts the first address boundary according to the number of first ECC failure bits.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory device, and in particular to a hybrid non-volatile memory device. Background Art

[0002] In order to meet various requirements of electronic devices, multiple individual memory devices are usually provided in the electronic devices. In order to reduce the cost of electronic devices and reduce the complexity of design, a single-chip non-volatile memory device is required to provide mixed functions. Summary of the invention

[0003] A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder, and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array and performs an ECC operation on read data from the first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder and adjusts the first address boundary according to the number of first ECC failure bits.

[0004] Based on the above, an address boundary is generated according to the number of ECC failure bits, and the address boundary is used to divide a memory cell array into a first sub-array and a second sub-array. The first sub-array and the second sub-array can be used to store data and code respectively to implement a mixed data and code storage macro.

[0005] In order to better understand the above features and advantages of the present disclosure, several embodiments accompanied by the drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0007] Figure 1 A schematic diagram showing a nonvolatile memory device according to an embodiment of the present disclosure;

[0008] Figure 2 A block diagram showing a nonvolatile memory device according to an embodiment of the present disclosure;

[0009] Figure 3 A block diagram showing a nonvolatile memory device according to another embodiment of the present disclosure;

[0010] Figure 4 A partitioning scheme for a memory cell array according to an embodiment of the present disclosure is shown.

[0011] Description of Figure Numbers

[0012] 100, 200, 300: non-volatile memory device;

[0013] 110, 210, 400, 410, 3110, 3210: memory cell array;

[0014] 111, 211, 411, 3111: first subarray;

[0015] 112, 212, 412, 3112: second subarray;

[0016] 120, 220, 3120, 3220: ECC decoder;

[0017] 130, 230, 3130, 3230: controller;

[0018] 240, 3140, 3240: ECC encoder;

[0019] 250, 3150, 3250: Source line multiplexer;

[0020] 260, 3160, 3260: sense amplifier and write driver;

[0021] 270, 3170, 3270: bit line multiplexer;

[0022] 280, 3180, 3280: X detector;

[0023] 413, 3211: third subarray;

[0024] 3212: fourth subarray;

[0025] BA1, BA2: address boundaries;

[0026] BA1': adjusted address boundary;

[0027] BA41: first address boundary;

[0028] BA42: second address boundary;

[0029] BUS1: first data bus;

[0030] BUS2: second data bus;

[0031] FBN1: Number of ECC failure bits;

[0032] RDATA, RDATA1, RDATA2: read data;

[0033] WDATA, WDATA1, WDATA2: write data;

[0034] WINF: Write information. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to the presently preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Please refer to Figure 1 The nonvolatile memory device 100 includes a memory cell array 110, an error correction code (ECC) decoder 120, and a controller 130. The memory cell array 110 may be divided into a first sub-array 111 and a second sub-array 112 by an address boundary BA1. The ECC decoder 120 is coupled to the memory cell array 110, and is used to perform an ECC operation on the read data RDATA from the memory cell array 110. The controller 130 is coupled to the ECC decoder 120 and the memory cell array 110. The controller 130 may obtain information of an ECC failure bit number FBN1 from the ECC decoder 120, and adjust the address boundary BA1 according to the ECC failure bit number FBN1.

[0037] In this embodiment, the first sub-array 111 may be configured for data storage, and the second sub-array 112 may be configured for code storage. Here, the first sub-array 111 is used to store normal data, such as information of images, pictures, music or text. The second sub-array 112 is used to store codes such as identification codes or startup codes, which may be more important than the data stored in the first sub-array 111.

[0038] On the other hand, the write cycle endurance of the cells in the first sub-array 111 may be higher than the write cycle endurance of the cells in the second sub-array 112. For example, the write cycle endurance of the cells in the first sub-array 111 may be 1M cycles, and the write cycle endurance of the cells in the second sub-array 112 may be 10K cycles. As an example, each of the cells in the memory cell array 110 is a resistive random access memory (ReRAM) cell. Each of the cells in the second sub-array 112 may be constructed by a one transistor and one resistor (1T1R) structure, and each of the cells in the first sub-array 111 may be constructed by an n transistor and n resistor (nTnR) structure, where n is a positive integer greater than 1.

[0039] The ECC decoder 120 is used to decode the read data RDATA when performing a read operation. The ECC decoder 120 can obtain the ECC failure bit number FBN1 and transmit information about the ECC failure bit number FBN1 to the controller 130. The controller 130 can preset a predefined number and compare the ECC failure bit number FBN1 with the predefined number. If the ECC failure bit number FBN1 is greater than the predefined number, the controller 130 can adjust the address boundary BA1 to the adjusted address boundary BA1'.

[0040] In this embodiment, when the ECC failure bit number FBN1 is greater than a predefined number, the controller 130 may adjust the address boundary BA1 to an adjusted address boundary BA1' to increase the size of the subarray 111. As described above, the size of the subarray 112 is reduced. That is, the reliability of the memory cell array 110 can be improved.

[0041] In detail, when it is determined that the number of ECC failure bits FBN1 is greater than a predefined number, the data retention capability of the memory cells in the first sub-array 111 may be reduced. As described, the controller 130 inserts some memory cells in the second sub-array 112 into the first sub-array 111 by adjusting the address boundary BA1 to the adjusted address boundary BA1′. The memory cells with higher data retention capability from the second sub-array 112 may be added to the first sub-array 111 to increase the reliability of the first sub-array 111.

[0042] In practical applications, in one embodiment of the present disclosure, the controller 130 may adjust the address boundary BA1 by adjusting the memory mapping table of the nonvolatile memory device 100. Alternatively, in another embodiment of the present disclosure, the controller 130 may calibrate the fuse table of the nonvolatile memory device 100.

[0043] In the present embodiment, the nonvolatile memory device 100 can provide a read while read function and also provide a read while write function. When a read operation is performed on the first sub-array 111, another read operation can be performed on the second sub-array 112 and vice versa. In addition, when a write operation is performed on the first sub-array 111, a read operation can be performed on the second sub-array 112 and vice versa.

[0044] Furthermore, in this embodiment, different write algorithms may be used to perform a write operation on the first sub-array 111 and a second write operation on the second sub-array 112 according to different reliability and specification requirements. In addition, the first sub-array 111 and the second sub-array 112 may respectively use a first operation clock signal and a second operation clock signal for access operations, wherein the frequency of the first operation clock signal and the frequency of the second operation clock signal may be the same or different.

[0045] In addition, the memory cells in the memory cell array 110 are not limited to the ReRAM cells in the present disclosure. The memory cells in the memory cell array 110 may also be magnetoresistive random access memory (MRAM) cells, ferroelectric random access memory cells (FRAM) cells, or phase change random access memory (PCRAM) cells.

[0046] Please refer to Figure 2 The non-volatile memory device 200 includes a memory cell array 210, an ECC decoder 220, a controller 230, an ECC encoder 240, a source line (SL) multiplexer (MUX) 250, a sense amplifier (SA) and a write driver 260, a bit line (BL) multiplexer 270, and an X detector 280.

[0047] The memory cell array 210 may be divided into a first sub-array 211 and a second sub-array 212 by an address boundary BA1. Figure 1 Similar to the embodiment in FIG. 2 , the address boundary BA1 can also be adjusted by the controller 230. In addition, the first sub-array 211 and the second sub-array 212 are disposed on the same chip.

[0048] In this embodiment, the memory cell array 210 is coupled to the source line multiplexer 250 via a plurality of source lines. The source line multiplexer 250 is configured to select a plurality of selected source lines among the source lines. The memory cell array 210 is also coupled to the bit line multiplexer 270 via a plurality of bit lines. The bit line multiplexer is configured to select a plurality of selected bit lines among the bit lines. The X detector 280 is coupled to the memory cell array 210 via a plurality of word lines. The X detector 280 is configured to select the detected word line of the memory cell array 210.

[0049] The sense amplifier and write driver 260 includes a plurality of sense amplifiers and a plurality of write drivers. The sense amplifier and write driver 260 is coupled to the source line multiplexer 250. If a read operation is performed, the sense amplifiers in the sense amplifier and write driver 260 may sense data via the selected source line and may generate read data RDATA accordingly. If a write operation is performed, the write driver in the sense amplifier and write driver 260 may write write information WINF to the first sub-array 211 or the second sub-array 212 via the selected source line.

[0050] The ECC decoder 220 is coupled to the sense amplifier and the write driver 260. When performing a read operation, the ECC decoder 220 receives the sensed data from the sense amplifier and the write driver 260, and performs an ECC scheme on the sensed data to generate read data RDATA. The sensed data includes a codeword and an ECC code corresponding to the codeword. The ECC decoder 220 can perform an ECC scheme on the codeword according to the ECC code to correct at least one error of the codeword. In this embodiment, the ECC decoder 220 can be a 2-bit ECC decoder or a 3-bit ECC decoder. The ECC scheme performed by the ECC decoder 220 can be a Hamming code or a BCH code.

[0051] The ECC encoder 240 is coupled to the sense amplifier and the write driver 260. The ECC encoder 240 may receive the write data WDATA and perform an ECC scheme on the write data WDATA to generate an ECC code corresponding to the write data WDATA. In addition, the ECC encoder 240 transmits write information WINF including the write data WDATA and the corresponding ECC code. The sense amplifier and the write driver 260 may write the write information WINF to the memory cell array 210 via the selected source line. The ECC decoder 220 and the ECC encoder 240 may perform the same ECC scheme for decoding and encoding operations.

[0052] It should be noted here that in the present embodiment, the controller 230 may receive information about the number of ECC failure bits FBN1, and adjust the address boundary BA1 according to the number of ECC failure bits FBN1. The controller 230 may compare the number of ECC failure bits FBN1 with a predefined number, and when it is detected that the number of ECC failure bits FBN1 is greater than the predefined number, the controller 230 may adjust the original address boundary BA1 to a newly generated adjusted address boundary BA1'. According to the adjusted address boundary BA1', the size of the first sub-array 211 may be increased and the size of the second sub-array 212 may be correspondingly reduced.

[0053] On the other hand, the first sub-array 211 can be coupled to the first data bus BUS1 via the sense amplifier and the write driver 260, and the second sub-array 212 can be coupled to the second data bus BUS2 via the sense amplifier and the write driver 260. The first data bus BUS1 and the second data bus BUS2 are both input and output (I / O) buses, and the access interfaces of the first data bus and the second data bus can be different. For example, each of the first data bus BUS1 and the second data bus BUS2 can be a serial peripheral interface (SPI) bus, an internal integrated circuit (I 2 C) bus, parallel bus. The controller 230 can be implemented by a logic circuit. The logic circuit can be designed by hardware description language (HDL).

[0054] Please refer to Figure 3 The nonvolatile memory device 300 includes a memory cell array 3110 and a memory cell array 3210, an ECC decoder 3120 and an ECC decoder 3220, a controller 3130 and a controller 3230, an ECC encoder 3140 and an ECC encoder 3240, a source line multiplexer 3150 and a source line multiplexer 3250, a sense amplifier and a write driver 3160 and a sense amplifier and a write driver 3260, a bit line multiplexer 3170 and a bit line multiplexer 3270, and an X detector 3180 and an X detector 3280.

[0055] The memory cell array 3110 and the memory cell array 3210 are disposed on the same chip. The memory cell array 3110 can be divided into a first sub-array 3111 and a second sub-array 3112 by an address boundary BA1, and the memory cell array 3210 can be divided into a third sub-array 3211 and a fourth sub-array 3212 by another address boundary BA2.

[0056] The controller 3130 and the controller 3230 may adjust the address boundary BA1 and the address boundary BA2 according to the number of ECC fail bits corresponding to the memory cell array 3110 and the memory cell array 3210 , respectively.

[0057] The detailed operations for adjusting the address boundary BA1 and the address boundary BA2 can be seen in the above embodiments, and will not be repeated here.

[0058] The ECC decoder 3120 is used to generate read data RDATA1 by performing a first ECC decoding operation on the sensed data from the sense amplifier and write driver 3160. The ECC encoder 3140 performs a first ECC encoding operation on the write data WDATA1 to generate write information to the sense amplifier and write driver 3160. The first ECC decoding operation and the first ECC encoding operation may be based on the same first ECC scheme. In addition, the ECC decoder 3220 is used to generate read data RDATA2 by performing a second ECC decoding operation on the sensed data from the sense amplifier and write driver 3260. The ECC encoder 3240 performs a second ECC encoding operation on the write data WDATA2 to generate write information to the sense amplifier and write driver 3260. The second ECC decoding operation and the second ECC encoding operation may also be based on the same second ECC scheme. In addition, the first ECC scheme and the second ECC scheme may be the same or may be different.

[0059] Please refer to Figure 4 , the memory cell array 400 in this embodiment can be divided into 3 or more parts. For example, the memory cell array 400 can be divided into a first sub-array 411, a second sub-array 412, and a third sub-array 413 according to a first address boundary BA41 and a second address boundary BA42. In this embodiment, the memory cells in the first sub-array 411 can have a first cycle endurance; the memory cells in the second sub-array 412 can have a second cycle endurance; and the memory cells in the third sub-array 413 can have a third cycle endurance. The first cycle endurance can be greater than the second cycle endurance, and the second cycle endurance can be greater than the third cycle endurance. Taking resistive random access memory cells as an example, each of the memory cells in the first sub-array 411 may be a 3T3R (3 transistors and 3 resistors) structure; each of the memory cells in the second sub-array 412 may be a 2T2R (2 transistors and 2 resistors) structure; and each of the memory cells in the third sub-array 413 may be a 1T1R (1 transistor and 1 resistor) structure.

[0060] In this embodiment, one of the first address boundary BA41 and the second address boundary BA42 can be adjusted according to the number of ECC failure bits of the memory cell array 410. The boundary adjustment of the first address boundary BA41 and the second address boundary BA42 depends on the reliability data throughout the life cycle of the device to meet the optimized bit error rate requirements. The detailed operation for adjusting one of the first address boundary BA41 and the second address boundary BA42 can refer to the above embodiment, and will not be repeated here.

[0061] In summary, the nonvolatile memory device disclosed in the present invention provides an adjustable address boundary for dividing a memory cell array into at least two sub-arrays according to the number of ECC failure bits. As described above, the reliability of the memory cell array can be improved.

[0062] It will be apparent to those skilled in the art that various modifications and changes may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, it is desired that the present invention covers modifications and changes to the present invention, provided that the modifications and changes fall within the scope of the appended claims and their equivalents.

Claims

1. A non-volatile memory device, comprising: A first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary; a first ECC decoder coupled to the first memory cell array and performing an ECC operation on read data from the first memory cell array; as well as a controller coupled to the first memory cell array and the first error correction code decoder, and adjusting the first address boundary according to the number of failed bits of the first error correction code, wherein the first subarray is configured for data storage, and the second subarray is configured for code storage, If the number of failed bits of the first error correction code is greater than a predefined number, the controller adjusts the first address boundary to an adjusted first address boundary to increase the size of the first sub-array. 2 . The nonvolatile memory device according to claim 1 , wherein a cycle endurance of the first sub-array is higher than a cycle endurance of the second sub-array.

3. The nonvolatile memory device according to claim 1, wherein each cell of the second sub-array is constructed by one transistor and one resistor structure, and each cell of the first sub-array is constructed by n transistors and n resistor structures, wherein n is a positive integer greater than 1.

4. The nonvolatile memory device according to claim 1, further comprising: A source line multiplexer coupled to a plurality of source lines of the first memory cell array, selecting a plurality of selected source lines among the source lines a sense amplifier and a write driver coupled to the source line and to the first error correction code decoder, sensing read data on the selected source line or transmitting write information to the selected source line; as well as A first error correction code encoder, coupled to the sense amplifier and the write driver, encodes write data to generate the write information.

5. The nonvolatile memory device according to claim 4, further comprising: a bit line multiplexer coupled to a plurality of bit lines of the first memory cell array, and selecting a plurality of selected bit lines among the bit lines; The X detector is used to select the detected word line of the first memory cell array.

6. The nonvolatile memory device according to claim 4, further comprising a first data bus and a second data bus, The first data bus is coupled to the first sub-array via the sense amplifier, the write driver and the source line multiplexer, and the second data bus is coupled to the second sub-array via the sense amplifier, the write driver and the source line multiplexer.

7. The nonvolatile memory device according to claim 6, wherein access interfaces of the first data bus and the second data bus are different.

8. The nonvolatile memory device according to claim 1, wherein: When a read operation is performed on one of the first sub-array and the second sub-array, another read operation is performed on the other of the first sub-array and the second sub-array, or, when a write operation is performed on one of the first sub-array and the second sub-array, a read operation is performed on the other of the first sub-array and the second sub-array.

9. The nonvolatile memory device according to claim 1, wherein the first sub-array and the second sub-array adopt a first operation clock signal and a second operation clock signal, respectively, wherein the frequency of the first operation clock signal and the frequency of the second operation clock signal are different.

10. The nonvolatile memory device according to claim 1, further comprising: A second memory cell array is divided into a third sub-array and a fourth sub-array by a second address boundary; as well as a second ECC decoder, coupled to the second memory cell array, for performing the ECC operation on the read data from the second memory cell array, The controller is further coupled to the second memory cell array and the second ECC decoder and adjusts the second address boundary according to the number of second ECC failure bits.

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