Semiconductor structure

Abstract

The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, the semiconductor structure comprising: a plurality of first patterns arranged along a first direction and a plurality of second patterns arranged along a second direction in a photoresist layer having a thickness greater than 1.2um, the first direction and the second direction having an angle; the first pattern having a first arrangement length in the first direction, the second pattern having a second arrangement length in the second direction, and the sum of the areas of the first pattern and the second pattern being less than 1 / 2 of the product of the first arrangement length and the second arrangement length. In the present application, the photoresist provides good support for the first pattern and the second pattern, avoiding deformation or overlapping of part of the marking pattern during high-energy exposure, thereby reducing the measurement efficiency and accuracy, thereby improving the yield rate of the manufactured semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, which puts higher requirements on the alignment and measurement accuracy of different layers in the manufacturing process.

[0003] However, the ions of some layers in the manufacture of semiconductor devices are implanted deeply, and high-energy exposure is required during exposure, which can easily cause deformation or overlapping of the mark pattern, resulting in poor morphology of the mark pattern, seriously affecting the measurement accuracy and reducing the yield rate of semiconductor devices. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure to solve the technical problem of deformation or overlapping of mark patterns caused by high energy exposure in the background art, so as to improve the efficiency and accuracy of measurement and thus improve the yield rate of semiconductor devices.

[0005] In order to achieve the above objectives and other objectives, the present application provides a semiconductor structure, including:

[0006] A plurality of first patterns arranged along a first direction and a plurality of second patterns arranged along a second direction in a photoresist layer having a thickness greater than 1.2 um, wherein the first direction and the second direction have an angle;

[0007] The first pattern has a first arrangement length in the first direction, the second pattern has a second arrangement length in the second direction, and the sum of the areas of the first patterns and the second patterns is less than 1 / 2 of the product of the first arrangement length and the second arrangement length.

[0008] In one embodiment, both the first pattern and the second pattern are gap patterns.

[0009] In one embodiment, the first pattern is a gap pattern, the width of the gap pattern is 0.5um-1.5um, and / or the distance between two adjacent gap patterns is 0.5um-1.5um.

[0010] In one embodiment, the second pattern is a photoresist pattern, the width of the photoresist pattern is 1.5um-3.5um, and the distance between two adjacent photoresist patterns is 0.5um-1.5um.

[0011] In one embodiment, both the first pattern and the second pattern are photoresist patterns, the width of the photoresist pattern is 2um-3um, the distance between two adjacent first patterns is 1um-1.5um, and the distance between two adjacent second patterns is 1um-1.5um.

[0012] In one embodiment, the first patterns are arranged at equal intervals along a first direction, and the second patterns are arranged at equal intervals along the second direction.

[0013] In one embodiment, the angle between the first direction and the second direction is 90°.

[0014] In one of the embodiments, a plurality of first graphics and a plurality of second graphics are formed in the photoresist layer, the arrangement direction of the first graphics is parallel to the first direction, and the arrangement direction of the second graphics is parallel to the second direction.

[0015] In one embodiment, the first pattern is a gap pattern, and the second pattern is a photoresist pattern.

[0016] In one embodiment, the width of the first pattern is 0.5um-1.5um; the width of the second pattern is 1.5um-3.5um.

[0017] In one embodiment, the distance between the first pattern and the second pattern is greater than the sum of the spacing between the first patterns and the spacing between the second patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic top view of a semiconductor structure provided in the first embodiment of the present application;

[0020] Figure 2 A schematic top view of a semiconductor structure provided in the second embodiment of the present application;

[0021] Figure 3 A schematic top view of a semiconductor structure provided in the third embodiment of the present application;

[0022] Figure 4 A schematic top view of a semiconductor structure provided in a fourth embodiment of the present application;

[0023] Figure 5 A schematic top view of a semiconductor structure provided in a fifth embodiment of the present application;

[0024] Figure 6 A schematic top view of a semiconductor structure provided in a sixth embodiment of the present application;

[0025] Figure 7a This is the Qmerit measurement result of the traditional marking graphic;

[0026] Figure 7b The Qmerit measurement result of the marking pattern provided in Example 2;

[0027] Figure 7c This is the Qmerit measurement result of the marking pattern provided in Example 4.

[0028] Description of reference numerals:

[0029] 100, photoresist layer; 10, first pattern; 20, second pattern; 11, first rectangular through hole; 12, first rectangular photoresist pattern; 21, second rectangular through hole; 22, second rectangular photoresist pattern; 30, first pattern; 40, second pattern. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. In addition, certain terms used throughout the specification and the claims that follow refer to specific elements. It will be understood by those skilled in the art that manufacturers may refer to elements by different names. This document does not intend to distinguish between elements with different names but the same functions. In the following description and embodiments, the terms "include" and "include" are open-ended and should therefore be interpreted as "include, but not limited to...". Similarly, the term "connection" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be completed by a direct electrical connection or by an indirect electrical connection through other devices and connectors.

[0032] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0033] "A plurality of" in the present application means one or more.

[0034] Please refer to Figure 1 , in a semiconductor structure provided in an embodiment of the present application, it includes a plurality of first patterns 10 arranged along a first direction Ox and a plurality of second patterns 20 arranged along a second direction Oy in a photoresist layer 100 with a thickness greater than 1.2 um. The first direction Ox and the second direction Oy have an included angle a, where 0 degrees < a < 180 degrees; the first patterns 10 have a first arrangement length L1 in the first direction Ox, and the second patterns 20 have a second arrangement length L2 in the second direction Oy. Denote the total area of all the first patterns 10 as S1, and denote the area of all the second patterns 20 as S2, then S1 + S2 < 0.5L1 * L2.

[0035] Specifically, please continue to refer to Figure 1 , by arranging a plurality of first patterns 10 along the first direction Ox and a plurality of second patterns 20 along the second direction Oy on a photoresist layer 100 with a thickness greater than 1.2 um, wherein the first direction Ox and the second direction Oy have an included angle a, 0 degrees < a < 180 degrees, the first patterns 10 have a first arrangement length L1 in the first direction Ox, and the second patterns 20 have a second arrangement length L2 in the second direction Oy, it is convenient to achieve precise measurement between different layers in the semiconductor structure through the first patterns 10 and the second patterns 20; since both the first patterns 10 and the second patterns 20 are formed on the photoresist layer 100 with a thickness greater than 1.2 um, the photoresist provides good support for the first patterns 10 and the second patterns 20, avoiding the situation that some marked patterns are deformed or have double images during high-energy exposure, which would reduce the measurement efficiency and accuracy; by setting the sum of the areas of all the first patterns 10 and all the second patterns 20 to be less than 1 / 2 of the product of the first arrangement length L1 and the second arrangement length L2, it is convenient to set a plurality of first patterns and a plurality of second patterns to further improve the measurement accuracy, thereby improving the yield of the manufactured semiconductor devices.

[0036] Furthermore, please refer to Figure 2In one embodiment of the present application, both the first pattern and the second pattern are gap patterns. The first pattern is set to be a first rectangular through hole 11, and a plurality of first rectangular through holes 11 arranged at intervals are arranged along a first direction Ox, and each first rectangular through hole 11 has a first arrangement length L1 in the first direction Ox; the second pattern is set to be a second rectangular through hole 21, and a plurality of second rectangular through holes 21 arranged at intervals are arranged along a second direction Oy, and each second rectangular through hole 21 has a second arrangement length L2 in the second direction Oy. The area of ​​the orthographic projection of each first rectangular through hole 11 on the surface of the photoresist layer 100 and the sum of the area of ​​the orthographic projection of each second rectangular through hole 21 on the surface of the photoresist layer 100 are less than 1 / 2 of the product of the first arrangement length L1 and the second arrangement length L2. Since a plurality of first rectangular through holes 11 and a plurality of second rectangular through holes 21 are provided as marking patterns, accurate measurement can be achieved through the marking patterns; since the photoresist layer 100 provides good support for the marking patterns, deformation or overlapping of part of the marking patterns during high-energy exposure can be avoided, thereby reducing the measurement efficiency and accuracy; by setting the sum of the areas of the first pattern 10 and the second pattern 20 to be less than 1 / 2 of the product of the first arrangement length L1 and the second arrangement length L2, it is convenient to set a plurality of first patterns and a plurality of second patterns to further improve the measurement accuracy, thereby improving the yield rate of the manufactured semiconductor devices.

[0037] Further, in one embodiment of the present application, please refer to Figure 3 , the first pattern is set to be a first rectangular through hole 11, a plurality of first rectangular through holes 11 are arranged at intervals along the first direction Ox, the width w1 of the first rectangular through hole 11 is 0.5um-1.5um, and / or the spacing d1 between adjacent first rectangular through holes 11 is 0.5um-1.5um, the size of the first rectangular through hole 11 is set to ensure that the photoresist at the position of the first rectangular through hole 11 can be exposed and developed during high energy exposure; at the same time, the spacing of the first rectangular through holes 11 is set to ensure that the photoresist between the first rectangular through holes 11 will not be destroyed during high energy exposure. The formed marking pattern has excellent morphology, which is conducive to the accurate measurement of the marking pattern. Figure 7a and Figure 7b As shown, compared with the traditional marking pattern, the Qmerit value in the measurement result obtained by using the marking pattern in this embodiment is smaller and more convergent, indicating that the marking pattern in this embodiment has better quality, and the obtained measurement result is more reliable and has better accuracy.

[0038] In other embodiments of the present application, the gaps in the first pattern may be one or more of circular, elliptical, triangular or polygonal shapes.

[0039] Further, in one embodiment of the present application, please continue to refer to Figure 3The second pattern is set to be a second rectangular photoresist pattern 22, a plurality of second rectangular photoresist patterns 22 are arranged at intervals along the second direction Oy, and each second rectangular photoresist pattern 22 has a second arrangement length L2 in the second direction Oy; the first pattern is set to be a first rectangular through hole 11, a plurality of first rectangular through holes 11 are arranged at intervals along the first direction Ox, and each first rectangular through hole 11 has a first arrangement length L1 in the first direction Ox; the sum of the areas of each first rectangular through hole 11 and each second rectangular photoresist pattern 22 is less than 1 / 2 of the product of the first arrangement length L1 and the second arrangement length L2. The width w2 of each second rectangular photoresist pattern 22 is 1.5um-3.5um, and the spacing d2 between adjacent second rectangular photoresist patterns 22 is 0.5um-1.5um. When the second pattern is a photoresist pattern, specifically, the width of the second rectangular photoresist pattern 22 is greater than the spacing between adjacent second rectangular photoresist patterns 22, so as to prevent the second rectangular photoresist pattern 22 from collapsing when the photoresist layer is too thick, which is conducive to accurate measurement of the marking pattern. At the same time, the first pattern of the gap pattern and the second pattern of the photoresist pattern can simultaneously detect different types of patterns in the marking pattern in the same layer or in the same marking pattern in the same layer.

[0040] Further, in one embodiment of the present application, the distance between the first pattern and the second pattern is greater than the sum of the spacing between the first patterns and the spacing between the second patterns. Figure 3 The first pattern is a first rectangular through hole 11, and the spacing d1 between adjacent first rectangular through holes 11 is 0.5um-1.5um. The second pattern is a second rectangular photoresist pattern 22, and the spacing d2 between adjacent second rectangular photoresist patterns 22 is 0.5um-1.5um. The distance between the first rectangular through hole 11 and the second rectangular photoresist pattern 22 is greater than the sum of the spacing d1 between adjacent first rectangular through holes 11 and the spacing d2 between adjacent second rectangular photoresist patterns 22, so as to ensure a clear boundary between the first rectangular through hole 11 and the second rectangular photoresist pattern 22 to prevent affecting the measurement results.

[0041] Further, in one embodiment of the present application, please refer to Figure 4, the first pattern is set to be a first rectangular photoresist pattern 12, and the second pattern is set to be a second rectangular photoresist pattern 22. A plurality of first rectangular photoresist patterns 12 are arranged at intervals along the first direction Ox, a width w12 of each first rectangular photoresist pattern 12 is 2um-3um, and a spacing d12 of each first rectangular photoresist pattern 12 is 1um-1.5um; a plurality of second rectangular photoresist patterns 22 are arranged at intervals along the second direction Oy, a width w2 of each second rectangular photoresist pattern 22 is 2um-3um, and a spacing d2 of each second rectangular photoresist pattern 22 is 1um-1.5um. When the first pattern and the second pattern of this embodiment are photoresist patterns, specifically, the width of the first rectangular photoresist pattern 12 is greater than the spacing between adjacent first rectangular photoresist patterns 12; the width of the second rectangular photoresist pattern 22 is greater than the spacing between adjacent second rectangular photoresist patterns 22, to prevent the first rectangular photoresist pattern 12 or the second rectangular photoresist pattern 22 from collapsing when the photoresist layer is too thick, especially when the photoresist thickness is greater than 1.2um, the width and spacing of the aforementioned photoresist pattern are more conducive to ensuring the quality of the marking pattern and to achieving accurate measurement of the marking pattern. Figure 7a and Figure 7c As shown, compared with the traditional marking pattern, the Qmerit value in the measurement result obtained by using the marking pattern in this embodiment is smaller and more convergent, indicating that the marking pattern in this embodiment has better quality, the obtained measurement result is more reliable, and the accuracy is better. In other embodiments of the present application, the photoresist pattern in the first pattern 10 and the second pattern 20 can be one or more of a circle, an ellipse, a triangle or a polygon.

[0042] For further information, please refer to Figure 4 The first rectangular photoresist patterns 12 are arranged at equal intervals along the first direction Ox, and the second rectangular photoresist patterns 22 are arranged at equal intervals along the second direction Oy, thereby reducing the complexity of mark pattern preparation while ensuring the measurement accuracy of the mark pattern.

[0043] Further, in one embodiment of the present application, please refer to Figure 5 The angle between the first direction Ox and the second direction Oy is 90°, which can easily realize the detection results of the X direction and the Y direction in the rectangular coordinate system.

[0044] Further, in one embodiment of the present application, please refer to Figure 6The photoresist layer 100 also includes a first pattern 30 and a second pattern 40. The arrangement direction of the first pattern 30 is parallel to that of the first pattern 10, and the arrangement direction of the second pattern 40 is parallel to that of the second pattern 20. The first pattern 30 and the second pattern 40 are used to define the position and shape of the semiconductor device structure in the chip region. The arrangement direction of the first pattern 30 is parallel to that of the first pattern 10, and the arrangement direction of the second pattern 40 is parallel to that of the second pattern 20, which can reduce the influence of the photolithography conditions on the measurement results, so that the measurement results of the mark pattern can better reflect the real situation of the first pattern 30 and the second pattern 40 of the chip removal area.

[0045] For further information, please refer to Figure 6 , the first pattern 30 is a gap pattern, the second pattern 40 is a photoresist pattern, the first pattern 30 is a gap pattern, which is consistent with the type of the first pattern 10, that is, the first pattern 10 is also a gap pattern; the second pattern 40 is a photoresist pattern, which is consistent with the type of the second pattern 20, that is, the second pattern 20 is also a photoresist pattern; specifically, please continue to refer to Figure 6 , the first pattern 30 is set as a third rectangular through hole, and the arrangement direction of the plurality of third rectangular through holes is parallel to the arrangement direction of the first pattern 10; the second pattern 40 is set as a fourth rectangular photoresist pattern, and the arrangement direction of the plurality of fourth rectangular photoresist patterns is parallel to the arrangement direction of the second pattern. Ensure that the pattern type of the chip area and the marking pattern are consistent, so that the measurement result of the marking pattern can better reflect the actual situation of the pattern in the chip area.

[0046] In one embodiment of the present application, please continue to refer to Figure 6 The width w3 of the first graphic 30 is 0.5um-1.5um; the width w4 of the second graphic 40 is 1.5um-3.5um, so as to ensure the quality of the first graphic 30 and the second graphic 40, so that the position and shape of the semiconductor device structure in the chip area can be accurately defined.

[0047] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0048] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0049] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of first patterns arranged along a first direction and a plurality of first patterns arranged along a first direction in a photoresist layer having a thickness greater than 1.2 um A plurality of second patterns arranged in a second direction, wherein the first direction and the second direction have an included angle; The first pattern has a first arrangement length in the first direction, and the second pattern has a first arrangement length in the first direction. The second direction has a second arrangement length, and the sum of the areas of each of the first patterns and each of the second patterns Less than 1 / 2 of the product of the first arrangement length and the second arrangement length; The second pattern is a photoresist pattern, the photoresist pattern is a rectangular photoresist pattern, and the width of the second pattern is greater than the distance between two adjacent second patterns.

2. The semiconductor structure according to claim 1, characterized in that: The first pattern is a gap pattern, the width of the gap pattern is 0.5um-1.5um, and / or the adjacent The distance between the two gap patterns is 0.5um-1.5um.

3. The semiconductor structure according to claim 2, characterized in that: The width of the photoresist pattern is 1.5um-3.5um, and the adjacent The distance between the two photoresist patterns is 0.5um-1.5um.

4. The semiconductor structure according to claim 1, wherein: The first pattern and the second pattern are both photoresist patterns, and the width of the photoresist pattern is 2um-3um, the distance between two adjacent first patterns is 1um-1.5um, and the distance between two adjacent second patterns is The pattern spacing is 1um-1.5um.

5. The semiconductor structure according to claim 1, characterized in that: The first pattern is along a first direction The first and second patterns are arranged at equal intervals along the second direction, and the second patterns are arranged at equal intervals along the second direction.

6. The semiconductor structure according to claim 1, characterized in that: The first direction and the The angle between the two directions is 90°.

7. The semiconductor structure according to claim 3, characterized in that: The photoresist layer also forms There are a plurality of first graphics and a plurality of second graphics, and the arrangement direction of the first graphics is the same as that of the first direction. The arrangement direction of the second graphics is parallel to the second direction.

8. The semiconductor structure according to claim 7, characterized in that: The first graph is a gap graph shape, and the second pattern is a photoresist pattern.

9. The semiconductor structure according to claim 8, characterized in that: The width of the first graphic The width of the second pattern is 0.5um-1.5um; the width of the second pattern is 1.5um-3.5um.

10. The semiconductor structure according to claim 3, characterized in that: The first pattern and the The distance between the second patterns is greater than the distance between the first patterns and the distance between the second patterns. sum.

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