Chip assembly system and chip assembly method

Abstract

The present invention relates to a chip matching system and a chip matching method, which include first defining a plurality of first electronic components in a first wafer as chips of different grades, and defining a plurality of second electronic components in a second wafer as chips of different grades, then performing grade matching on the first electronic components and the second electronic components to generate target information, and then integrating the first and second electronic components at the same place according to the target information. Therefore, the chips of the highest grade can be configured in a multi-chip module to optimize the quality of the multi-chip module.

Description

Technical Field

[0001] The present invention relates to a packaging process, and particularly to a chip assembly system and a chip assembly method for a multi-chip module packaging process. Background Art

[0002] In the existing semiconductor manufacturing process, after the wafer is manufactured, processes such as thinning, packaging, and singulation are carried out. Among them, when carrying out each process, the wafer or chip needs to be carried by a carrier plate (such as a packaging substrate, a temporary glass carrier plate, or others).

[0003] On the production line, defective chips need to be selected first, and then good chips are rearranged on the carrier plate. As Figure 1 shown, first, the wafer 1a is subjected to quality inspection to determine good (accept) chips and defective (reject) chips X. Then, the good chips are classified according to the quality of their functionality performance. According to the level of functionality performance in sequence, the first-level chips 1, the second-level chips 7, the third-level chips 8, and the fourth-level chips 9 are defined. Among them, the functionality performance of the first level is the best, and the fourth level is the worst. After that, the good chips (the first-level chips 1, the second-level chips 7, the third-level chips 8, and the fourth-level chips 9) are picked one by one along the S-shaped continuous turning path L onto the carrier plate, and then the subsequent packaging operation is carried out.

[0004] Early packaging structures usually only required a single chip to meet the functional requirements, so only one chip packaging process (such as a flip-chip process or a wire-bonding process) needed to be carried out on the production line.

[0005] However, due to the demand for multi-functional development and high-frequency and high-speed operations, the product demand has been towards the development of multi-chip modules (MCMs).

[0006] As Figure 1 shown in ', in the existing multi-chip module 1', a plurality of chips 11, 12 need to be bonded to a packaging substrate 10 via a plurality of solder bumps 13, and then a packaging material 14 covering the plurality of chips 11, 12 is formed. After that, a ball mounting process or other processes can be carried out. Therefore, on the production line, multiple chips 11, 12 need to be arranged on a single packaging substrate 10, that is, multiple chip pick and place processes need to be carried out on the production line.

[0007] However, on the production line, these chips 11, 12 are obtained from different wafers, and the grading statuses (such as positions, quantities, etc.) of the chips 11, 12 on each wafer are inconsistent. Therefore, if good chips (first-grade chips 1, second-grade chips 7, third-grade chips 8, and fourth-grade chips 9) are picked one by one along the S-shaped continuous turning path L onto a carrier plate (such as a packaging substrate 10), the grading of each chip 11, 12 in a single multi-chip module 1' cannot be controlled, resulting in the inability to control the functional status of each multi-chip module 1', so that a large number of multi-chip modules 1' with poor functional status (such as all or most of these chips 11, 12 being fourth-grade chips 9) need to be eliminated in subsequent quality control operations.

[0008] Therefore, how to overcome the defects of the above-mentioned prior art has become an urgent issue to be solved at present. Summary of the Invention

[0009] To solve the above problems, the present invention provides a chip matching system and a chip matching method to optimize the quality of multi-chip modules.

[0010] The chip matching system of the present invention includes: a first actuating device for displacing a plurality of first electronic components of different grades defined by a first wafer; a second actuating device for displacing a plurality of second electronic components of different grades defined by a second wafer; and an operation module communicatively connected to the first actuating device and the second actuating device to perform grade matching on the first electronic components and the second electronic components to generate target information, so that the first actuating device and the second actuating device integrate at least one of the first electronic components and at least one of the second electronic components at one place according to the target information.

[0011] In the above-mentioned chip matching system, the first actuating device transmits first status information to the operation module, and the second actuating device transmits second status information to the operation module, so that the operation module performs grade matching according to the first status information and the second status information to generate the target information, wherein the first status information is information on the plurality of first electronic components in cooperation with their grades, and the second status information is information on the plurality of second electronic components in cooperation with their grades.

[0012] The present invention also provides a chip matching method, including: defining a plurality of first electronic components and a plurality of second electronic components of different grades in a first wafer and a second wafer respectively; performing grade matching on the plurality of first electronic components and the plurality of second electronic components to generate target information; and integrating at least one of the first and at least one of the second electronic components at the same place according to the target information.

[0013] In the above-mentioned chip matching system and method, the plurality of first electronic components are at least classified into three grades.

[0014] In the foregoing chip assembly system and method, the multiple second electronic components are at least classified into three grades.

[0015] In the foregoing chip assembly system and method, the operation module matches the first electronic components of the highest grade with the second electronic components of the highest grade at the same place. For example, the number of the matching situations is maximized.

[0016] As can be seen from the above, in the chip assembly system and method of the present invention, the first electronic components and the second electronic components are mainly paired by grade through the operation module to generate target information, so that the first electronic components and the second electronic components of higher grades can be integrated at the same place according to the target information. Therefore, compared with the prior art, the present invention can pair the qualities of the chips of each grade of different wafers according to the quality requirements of the multi-chip module, so as to achieve high-efficiency chip quality pairing operation, optimize the quality of the multi-chip module, and improve the production capacity and efficiency of the production line. Description of the Drawings

[0017] Figure 1 It is a schematic top view of an existing wafer.

[0018] Figure 1 ’ is a schematic perspective view of an existing multi-chip module.

[0019] Figure 2 It is a schematic diagram of the architecture configuration of the chip assembly system of the present invention.

[0020] Figure 2 ’ is a schematic cross-sectional view of an electronic package manufactured by the production line of the chip assembly system of the present invention.

[0021] Figure 2A It is a schematic top view of the first wafer used in the production line of the chip assembly system of the present invention.

[0022] Figure 2A ’ is a schematic top view of the carrier plate used in the production line of the chip assembly system of the present invention.

[0023] Figure 2B It is a schematic top view of the second wafer used in the production line of the chip assembly system of the present invention.

[0024] Figure 2C and Figure 2C ’ is a chart of the target information generated by the operation module of the chip assembly system of the present invention.

[0025] Figure 2D It is a schematic top view of the full-page package structure manufactured by the production line of the chip assembly system of the present invention.

[0026] Figure 3Flow block diagram of the first embodiment of the chip assembly method of the present invention.

[0027] Figure 3 ’ is Figure 3 Schematic diagram of the illustrated process.

[0028] Figure 4 Flow block diagram of the second embodiment of the chip assembly method of the present invention.

[0029] Figure 4 ’ is Figure 4 Schematic diagram of the illustrated process.

[0030] Figure 4 ” is Figure 4 Top view plane schematic diagram of the carrier board of

[0031] Figure 5 is Figure 2D Another embodiment of

[0032] Explanation of reference numerals in the drawings

[0033] 1: First-level chip

[0034] 1’: Multi-chip module

[0035] 1a: Wafer

[0036] 10: Package substrate

[0037] 11, 12: Chips

[0038] 13: Solder bump

[0039] 14: Encapsulation material

[0040] 2: Chip assembly system

[0041] 2’: Electronic package

[0042] 2”, 5: Full-panel packaging structure

[0043] 2a: First electronic component

[0044] 2a’: First wafer

[0045] 2a”: Carrier board

[0046] 2b: Second electronic component

[0047] 2b’: Second wafer

[0048] 2c: Third electronic component

[0049] 2d: Fourth electronic component

[0050] 20a: First detection device

[0051] 20b: Second detection device

[0052] 21: First actuating device

[0053] 22: Second actuator

[0054] 23: Operation module

[0055] 24: Encapsulation layer

[0056] 25:Metal layer

[0057] 3: Electronic devices

[0058] 7: Second level chip

[0059] 8: Third level chip

[0060] 9: Fourth level chip

[0061] L: Continuous turning path

[0062] N: imaginary array

[0063] P: Chip pairing combination

[0064] S30~S36: Steps

[0065] S40~S44: Steps

[0066] X: Defective chip. DETAILED DESCRIPTION

[0067] The following describes the implementation of the present invention through specific embodiments. Those having ordinary knowledge in the technical field can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0068] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "first", "second", "third", "fourth" and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0069] Figure 2 FIG. 2 is a schematic diagram of the architecture configuration of the chip configuration system 2 of the present invention. Figure 2As shown, the chip assembly system 2 includes a first detection device 20a, a first actuating device 21, a second detection device 20b, a second actuating device 22, and an operation module 23 communicatively connected to the first actuating device 21, the second actuating device 22, the first detection device 20a, and the second detection device 20b.

[0070] In this embodiment, the chip assembly system 2 arranges a plurality of electronic components on a carrier board 2a", as Figure 2 shown, to perform a packaging process to obtain the required electronic package 2'. For example, the electronic package 2' is coated with these electronic components via a packaging layer 24, and a metal layer 25 can be formed on the packaging layer 24 according to requirements.

[0071] The carrier board 2a" is a circuit structure with a core layer or a coreless structure, such as a packaging substrate. It should be understood that the carrier board 2a" can also be other components for carrying electronic components such as chips, such as a lead frame, a silicon interposer, or a consumable temporary carrier board, and is not limited to the above.

[0072] The electronic components include a first electronic component 2a, a second electronic component 2b, a third electronic component 2c, and a plurality of fourth electronic components 2d. They are arranged on the carrier board 2a" and electrically connected to the carrier board 2a". Among them, the first electronic component 2a, the second electronic component 2b, and the third electronic component 2c are semiconductor chips, and the fourth electronic components 2d are passive components such as resistors, capacitors, or inductors. For example, the first electronic component 2a, the second electronic component 2b, and the third electronic component 2c are arranged on the carrier board 2a" in a flip-chip manner via a plurality of conductive bumps such as solder materials and electrically connected to the carrier board 2a"; alternatively, the first electronic component 2a, the second electronic component 2b, and the third electronic component 2c can also be arranged on the carrier board 2a" in a wire bonding manner (figure omitted) via a plurality of bonding wires and electrically connected to the carrier board 2a". However, the setting method of the electronic components is not limited to the above.

[0073] The packaging layer 24 is formed on the carrier board 2a" and covers each of the electronic components. Among them, the material for forming the packaging layer 24 is an insulating material such as polyimide (PI for short), dry film, epoxy resin, or molding compound, but is not limited to the above.

[0074] The described metal layer 25 is formed on the outer surface of the encapsulation layer 24 for shielding purposes, and the metal layer 25 is made of a material selected from copper (Cu), nickel (Ni), iron (Fe), aluminum (Al), or stainless steel (Sus). For example, the metal layer 25 is formed by means such as electroplating, chemical coating, physical vapor deposition, sputtering, or other suitable methods.

[0075] The described first detection device 20a is used to detect these electronic components, and the described first actuating device 21 is used to displace these electronic components, and has functions such as picking and resetting these electronic components, so as to configure related equipment (such as robotic arms, conveyor belts, etc.) according to these functions.

[0076] In this embodiment, the first detection device 20a transmits the result information of detecting these electronic components to the first actuating device 21 via the arithmetic module 23 for the first actuating device 21 to displace the first electronic component 2a. For example, the first detection device 20a performs quality inspections on each chip defined in the first wafer 2a', such as Figure 2A shown, to determine good (accept) chips and bad (reject) chips X, and then performs quality classification of the functionality performance of each good chip. According to the level of functionality performance in sequence, the first-level chip 1, the second-level chip 7, the third-level chip 8, and the fourth-level chip 9 are defined, where the functionality performance is the best for the first level and the worst for the fourth level. Specifically, the good chips (the first-level chip 1, the second-level chip 7, the third-level chip 8, and the fourth-level chip 9) in the first wafer 2a' are used as the first electronic component 2a.

[0077] In addition, the first actuating device 21 picks good chips (the first-level chip 1, the second-level chip 7, the third-level chip 8, and the fourth-level chip 9) one by one according to a continuous turning path L in the shape of an S (such as a serpentine) to a carrier plate 2a” (such as a temporary glass carrier plate / or an encapsulation substrate (substrate)), as Figure 2A shown, that is, the bad chips X are eliminated, and these good chips are reset (such as filling the positions of the bad chips X in sequence), so that these good chips are re-arrayed on the carrier plate 2a”.

[0078] The described second detection device 20b is used to detect these electronic components, and the described second actuating device 22 is used to displace these electronic components, and has functions such as picking and resetting these electronic components, so as to configure related devices (such as robotic arms, conveyor belts, etc.) according to these functions.

[0079] In this embodiment, the second detection device 20b transmits the result information of detecting these electronic components to the second actuating device 22 via the operation module 23 for the second actuating device 22 to displace the second electronic component 2b. For example, the second detection device 20b performs quality inspection on each chip defined in the second wafer 2b’, such as Figure 2B as shown, to determine good (accept) chips and defective (reject) chips X, and then classifies the quality of the functionality performance of each of the good chips, and defines a first-grade chip 1, a second-grade chip 7, and a third-grade chip 8 in order of the level of functionality performance, where the functionality performance is the best for the first grade and the worst for the third grade. Specifically, the good chips (the first-grade chip 1, the second-grade chip 7, and the third-grade chip 8) in the second wafer 2b’ serve as the second electronic component 2b. It should be understood that the good chips in the second wafer 2b’ can also be divided into a first-grade chip 1, a second-grade chip 7, a third-grade chip 8, and a fourth-grade chip 9.

[0080] The operation module 23 is used to pair the first electronic component 2a and the second electronic component 2b by grade.

[0081] In this embodiment, the operation module 23 runs via an electronic device 3 (such as Figure 3 as shown), such as various computers, servers, clouds, or other computing devices, to perform data transmission for the first actuating device 21 and the second actuating device 22 in a wired or wireless manner. For example, based on the grade status (first grade, second grade, third grade, and fourth grade) of the chips, the operation module 23 matches the first electronic component 2a and the second electronic component 2b on the carrier plate 2a”. Specifically, the first actuating device 21 transmits the first status information (such as the arrangement status on the carrier plate 2a” as shown in Figure 2A ) of the chip processing result to the operation module 23, and the second actuating device 22 takes the second wafer 2b’ that has been classified by quality as the second status information (such as shown in Figure 2B ) and transmits it to the operation module 23, so that the operation module 23 performs an optimal match for the first status information and the second status information to obtain target information, which includes a hypothetical array N as shown in Figure 2C and a chip pairing combination P as shown in Figure 2C . It should be understood that the first status information and the second status information include the grades, positions, quantities, or others of these good chips (such as the first electronic component 2a and the second electronic component 2b).

[0082] In addition, the chip pairing combination P includes the matching conditions of various grades of chips. For example, the first-grade chips 1 of the first wafer 2a' and the first-grade chips 1 of the second wafer 2b' can be arranged in the same electronic package 2' (such as the "◎" pattern shown in Figure 2C '), and other available matching conditions are represented by the "○" pattern; or, the matching conditions of the fourth-grade chips 9 of the first wafer 2a' and the second- and third-grade chips 7, 8 of the second wafer 2b' are excluded (such as the "─" pattern shown in Figure 2C ' indicates not to be adopted).

[0083] Furthermore, the imaginary array N reorganizes the good chips (second state information) of the second wafer 2b' according to the matching conditions of the chip pairing combination P, that is, based on the available matching conditions (such as the "◎" pattern and the "○" pattern shown in Figure 2C ') in the chip pairing combination P for reorganization, while the non-adopted matching conditions (such as the "─" pattern shown in Figure 2C ') of the chip pairing combination P need to be excluded. For example, the chips of each grade provided by the second state information are subjected to a position redistribution operation according to the chips of each grade of the corresponding first state information, so that the positions of the chips of each grade of the imaginary array N correspond (or align) to the positions of the chips of each grade on the carrier plate 2a" (as shown in Figure 2A '). Specifically, during the picking process, the second actuating device 22 can pick the required grade of chips from the second wafer 2b' to the corresponding carrier plate 2a" (which is already configured with the first electronic component 2a) on the production line according to the order of the imaginary array N along the continuous turning path L. It should be understood that due to the on-site tool configuration of the production line, considering the smooth picking operation of the second actuating device 22 (such as considering the shortest running path of the robotic arm), the picking order of the second actuating device 22 for the imaginary array N is not limited to the above-mentioned continuous turning path L.

[0084] Therefore, the second actuating device 22 picks (pick) the required good chips on the second wafer 2b' according to the target information of the arithmetic module 23 (such as Figure 2BThe first-level chip 1, the second-level chip 7 and the third-level chip 8 shown in the figure are placed on the carrier board 2a' to optimize the functional performance of the electronic package 2'. It should be understood that in a single electronic package 2', if the first electronic component 2a and the second electronic component 2b are both first-level chips 1, the functional performance is best, so the target information needs to present the maximum number of matching combinations of the first-level chips 1 of the two wafers (such as the positions of the first-level chips 1 presented by the imaginary array N correspond as much as possible to the first-level chips 1 of the first electronic component 2a on the carrier board 2a'), that is, to enable the production line to produce the maximum output (such as Figure 2D The full-page packaging structure shown is 2").

[0085] Figure 3 FIG. 1 is a flow block diagram of a first embodiment of a chip matching method of the present invention. In this embodiment, the chip matching system 2 is used to run, such as Figure 3 'shown.

[0086] In step S30, in a production process Figure 2 A plurality of wafers are provided on a production line of the electronic package 2 shown in FIG. 1 . In this embodiment, the plurality of wafers are a first wafer 2a′ and a second wafer 2b′.

[0087] In step S31 , the first inspection device 20 a and the second inspection device 20 b perform quality inspection and classification operations on the first wafer 2 a ′ and the second wafer 2 b ′.

[0088] In this embodiment, the first detection device 20a performs quality detection on each chip defined in the first wafer 2a' to determine good chips and bad chips X, and then classifies the quality of each good chip according to its functional performance to define first-level chip 1, second-level chip 7, third-level chip 8 and fourth-level chip 9, such as Figure 2A and Figure 3 'shown.

[0089] In addition, the second inspection device 20b performs quality inspection on each chip defined in the second wafer 2b' to determine good chips and bad chips X, and then classifies the quality of each good chip according to its functional performance to define first-level chips 1, second-level chips 7 and third-level chips 8, such as Figure 2B and Figure 3 'shown.

[0090] In step S32 , the first actuating device 21 performs a first punching (resetting) operation.

[0091] In this embodiment, the first actuating device 21 rearranges the good chips (the first-grade chips 1, the second-grade chips 7, the third-grade chips 8, and the fourth-grade chips 9) onto the carrier plate 2a", and eliminates the defective chips X, as Figure 2A ’ and Figure 3 ’ shown.

[0092] In step S33, the first actuating device 21 generates first status information according to the actuation (classification) result.

[0093] In this embodiment, the first actuating device 21 transmits the first status information to the electronic device 3, so that the operation module 23 accesses the first status information, as Figure 3 ’ shown.

[0094] In step S34, second status information is collected via the operation module 23.

[0095] In this embodiment, the second actuating device 22 transmits the second wafer 2b’ that has undergone quality classification as second status information (as Figure 2B shown) to the electronic device 3, as Figure 3 ’ shown, so that the operation module 23 accesses the second status information.

[0096] In step S35, target information is generated via the operation module 23.

[0097] In this embodiment, the operation module 23 performs an optimization match for the first status information and the second status information to obtain the target information, as Figure 2C and Figure 3 ’ shown.

[0098] In step S36, a second die bonding operation is performed via the second actuating device 22.

[0099] In this embodiment, the second actuating device 22 picks the good chips on the second wafer 2b’ (the first-grade chips 1, the second-grade chips 7, and the third-grade chips 8 as shown in Figure 2B ) as the second electronic components 2b and respectively displaces them onto the corresponding carrier plates 2a", as Figure 2D and Figure 3 ’ shown.

[0100] Therefore, the first actuation device 21 and the second actuation device 22 transmit the required first status information and second status information to the computing module 23, enabling the computing module 23 to pair the first electronic component 2a and the second electronic component 2b by grade to generate target information, so that the first actuation device 21 and the second actuation device 22 can integrate the first electronic component 2a and the second electronic component 2b at one place according to the target information. Therefore, in the packaging process of a multi-chip module (such as the electronic package 2'), chip pairing of a better grade can be performed according to the quality requirements of the electronic package 2'. Thus, not only can the pairing efficiency of the chip quality of the electronic package 2' be accelerated, but also the quality of the electronic package 2' can be optimized to improve the production capacity and efficiency of the production line.

[0101] Figure 4 FIG. is a schematic flowchart of a second embodiment of the chip integration method of the present invention. The difference between this embodiment and the first embodiment lies in the generation method of the first status information, and the other processes are roughly the same, so the same parts will not be described in detail below.

[0102] In step S40, a first wafer 2a' and a second wafer 2b' are provided on a production line for manufacturing an electronic package 2' as shown in Figure 2 ' to perform quality inspection and classification operations on the first wafer 2a' and the second wafer 2b' through the first detection device 20a and the second detection device 20b.

[0103] In this embodiment, the first detection device 20a performs quality inspection on each chip defined in the first wafer 2a' to determine good chips and defective chips X, and then classifies the quality of the function performance of each good chip to define a first-grade chip 1, a second-grade chip 7, a third-grade chip 8, and a fourth-grade chip 9, as shown in Figure 4 '.

[0104] In addition, the second detection device 20b performs quality inspection on each chip defined in the second wafer 2b' to determine good chips and defective chips X, and then classifies the quality of the function performance of each good chip to define a first-grade chip 1, a second-grade chip 7, and a third-grade chip 8, as shown in Figure 4 '.

[0105] In step S41, the computing module 23 collects the first status information and the second status information, as shown in Figure 4 '.

[0106] In this embodiment, the first actuation device 21 transmits the first wafer 2a' that has been quality-classified as the first status information (as shown in Figure 2A ) to the electronic device 3, as shown in Figure 4As shown in ’, the operation module 23 is enabled to access the first status information, and the second actuating device 22 transfers the second wafer 2b’ that has undergone quality classification as the second status information (as Figure 2B shown) to the electronic device 3, as Figure 4 shown in ’, so that the operation module 23 can access the second status information.

[0107] In step S42, target information is generated via the operation module 23, as Figure 4 shown in ’.

[0108] In this embodiment, the operation module 23 performs an optimization match for the first status information and the second status information to obtain the target information.

[0109] In step S43, a first component placement operation is performed via the first actuating device 21, as Figure 4 shown in ’.

[0110] In this embodiment, the first actuating device 21 picks and places the good chips (first - grade chip 1, second - grade chip 7, third - grade chip 8, and fourth - grade chip 9) on the first wafer 2a’ according to the indication of the target information of the operation module 23, rearranges them on the carrier plate 2a”, and eliminates the defective chips X. For example, the first actuating device 21 does not pick and place according to the sequential L - shaped path of continuous turning, but arranges the good chips (first - grade chip 1, second - grade chip 7, third - grade chip 8, and fourth - grade chip 9) on the first wafer 2a’ according to the grade positions of the target information, and rearranges them (as Figure 4 shown in the arrangement on the carrier plate 2a” shown in ”).

[0111] In step S44, a second component placement operation is performed via the second actuating device 22, as Figure 4 shown in ’.

[0112] In this embodiment, the second actuating device 22 picks and places the good chips (first - grade chip 1, second - grade chip 7, and third - grade chip 8 as Figure 2B shown) on the second wafer 2b’ according to the indication of the target information of the operation module 23 as the second electronic components 2b and respectively displaces them to the corresponding carrier plate 2a”.

[0113] In summary, in the chip matching system 2 and the chip matching method of the present invention, mainly through the operation module 23, chips of different grades on multiple wafers are matched, so as to configure multiple higher-grade electronic components (such as the first-grade chips 1) in the same electronic package 2', so that there will be no excessive lowest-grade electronic components (such as the third-grade chips 8 or the fourth-grade chips 9) in the electronic package 2'. Therefore, compared with the prior art, the chip matching system 2 of the present invention can effectively control the grades of various electronic components (such as the first electronic component 2a and the second electronic component 2b) in a single multi-chip module through the chip matching method, so that the functional states of each multi-chip module (such as Figure 2D as shown) can be effectively controlled, and thus subsequent quality control operations do not need to eliminate multi-chip modules with poor functional states.

[0114] It should be understood that the chip matching system 2 and the chip matching method of the present invention can be applied to the matching of more than three groups of wafers. For example, wafers with Figure 2 the third electronic component 2c as shown in '' are paired to produce a full-page package structure 5 as shown in Figure 5 as shown.

[0115] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person with ordinary knowledge in the technical field can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the present invention should be as listed in the claims.

Claims

1. A chip assembly system, characterized in that, Comprising: A first detection device for performing quality detection on a plurality of first electronic components in a first wafer to classify the plurality of first electronic components into a plurality of different grades; A second detection device for performing quality detection on a plurality of second electronic components in a second wafer to classify the plurality of second electronic components into the plurality of different grades; A first actuating device for displacing the plurality of first electronic components that have been classified into the plurality of different grades; A second actuating device for displacing the plurality of second electronic components that have been classified into the plurality of different grades; And An operation module communicatively connected to the first actuating device and the second actuating device to perform grade pairing on the plurality of first electronic components and the plurality of second electronic components to generate target information, so that the first actuating device and the second actuating device integrate at least one of the first electronic components and at least one of the second electronic components at one place according to the target information, and the integration only integrates the electronic components that have undergone the quality detection. Wherein, the operation module matches the first electronic components of the highest grade with the second electronic components of the highest grade at the same place and maximizes the number of such matching situations.

2. The chip assembly system according to claim 1, wherein The plurality of first electronic components are classified into at least three grades.

3. The chip assembly system according to claim 1, wherein The plurality of second electronic components are classified into at least three grades.

4. The chip assembly system according to claim 1, characterized in that, The first actuating device transmits first status information to the operation module, and the second actuating device transmits second status information to the operation module, enabling the operation module to perform grade pairing according to the first status information and the second status information to generate the target information. Wherein, the first status information is information of the plurality of first electronic components in accordance with their grades, and the second status information is information of the plurality of second electronic components in accordance with their grades.

5. A chip matching method, characterized in that, Comprising: Respectively performing quality detection on a plurality of first electronic components in a first wafer and a plurality of second electronic components in a second wafer to classify the plurality of first electronic components and the plurality of second electronic components into a plurality of different grades; Performing grade pairing on the plurality of first electronic components and the plurality of second electronic components to generate target information; And Integrating at least one of the first electronic components and at least one of the second electronic components at the same place according to the target information, and the integration only integrates the electronic components that have undergone the quality detection. Wherein, the first electronic components of the highest grade are matched with the second electronic components of the highest grade at the same place, and the number of such matching situations is required to be maximized.

6. The chip assembly method according to claim 5, wherein The plurality of first electronic components are classified into at least three grades.

7. The chip assembly method according to claim 5, wherein The plurality of second electronic components are classified into at least three grades.

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