Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate, a gate structure and a sidewall located on the sidewall of the gate structure, the top of the sidewall being higher than the top of the gate structure; a source and a drain located in the substrate on both sides of the gate structure, the top of the source and the drain being higher than or flush with the top of the substrate; a conductive layer located on the source and the drain; a protective layer located on the top of the gate structure and between the sidewalls, the top surface of the protective layer being higher than the top surface of the sidewall; a covering layer located on the top of the conductive layer and the sidewalls, the top of the covering layer being flush with the top of the protective layer; a dielectric layer located on the protective layer and the covering layer; a first interconnection layer located in the protective layer at the top of the gate structure; and a second interconnection layer located in the covering layer at the top of the conductive layer. The semiconductor structure provided by the embodiment of the present invention avoids the short circuit problem between the first interconnection layer and the conductive layer, and between the second interconnection layer and the gate structure, and improves the electrical performance and stability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Over the past several decades, the scaling of feature sizes in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller feature sizes enables increased density of functional units on the limited substrate area of ​​a semiconductor chip. For example, reducing transistor size allows an increased number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. But the drive for greater capacity is not without its problems. The necessity to optimize the performance of each device becomes increasingly apparent.

[0003] In the manufacture of integrated circuit devices, multi-gate transistors become more common as device dimensions continue to shrink. In conventional processes, multi-gate transistors are usually manufactured on a silicon substrate or a silicon-on-insulator substrate.

[0004] But shrinking the size of multi-gate transistors is not without its problems. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks manufactured in a given area increases, the constraints of the photolithography process used to form the building block patterns become difficult to overcome. The electrical performance of multi-gate transistors in the prior art still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a sidewall located on the sidewall of the gate structure, and the top surface of the sidewall is higher than the top surface of the gate structure; a source and a drain located in the substrate on both sides of the gate structure, and the top surface of the source and the drain is higher than or flush with the top surface of the substrate; a conductive layer located on the source and the drain; a protective layer located on the top of the gate structure and between the sidewalls, and the top surface of the protective layer is higher than the top surface of the sidewall; a covering layer located on the conductive layer and the top of the sidewall, and the top surface of the covering layer is flush with the top surface of the protective layer; a dielectric layer located on the protective layer and the covering layer; a first interconnection layer located in the protective layer and on the top of the gate structure; and a second interconnection layer located in the covering layer and on the top of the conductive layer.

[0007] Optionally, the protective layer and the covering layer are made of different materials.

[0008] Optionally, the material of the protective layer includes silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0009] Optionally, the material of the covering layer includes silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0010] Optionally, the covering layer includes: a first covering layer located on the top of the conductive layer, and a second covering layer located on the top of the first covering layer and the top of the sidewall; the top surface of the first covering layer is flush with the top surface of the sidewall, and the top surface of the second covering layer is flush with the top surface of the protective layer.

[0011] Optionally, the method further includes: an etch stop layer, wherein the etch stop layer is located on the protection layer and the cover layer, and the dielectric layer is located on the etch stop layer.

[0012] Optionally, a material of the etch stop layer is different from a material of the cover layer, and the material of the etch stop layer includes silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0013] Accordingly, an embodiment of the present invention further provides a method for forming the above-mentioned semiconductor structure, comprising: providing a substrate, the substrate having a gate structure, an initial sidewall located on the sidewall of the gate structure, and a source and drain located in the substrate on both sides of the gate structure; forming a protective layer on the gate structure, the top surface of the protective layer being flush with the top surface of the initial sidewall; forming a conductive layer on the source and drain, the top surface of the conductive layer being lower than the top surface of the initial sidewall; forming a first covering layer on the conductive layer, the top surface of the first covering layer being lower than the top surface of the initial sidewall; etching the initial sidewall to the top of the initial sidewall The surface of the first covering layer is flush with the top surface of the first covering layer to form a side wall; a second covering layer is formed on the side wall and the first covering layer, the top surface of the second covering layer is flush with the top surface of the protective layer, and the first covering layer and the second covering layer constitute a covering layer; a dielectric layer is formed on the protective layer and the covering layer; the dielectric layer and a part of the protective layer are etched to expose the top surface of the gate structure to form a first opening; the dielectric layer and a part of the covering layer are etched to expose the top surface of the conductive layer to form a second opening; a first interconnection layer is formed in the first opening; and a second interconnection layer is formed in the second opening.

[0014] Optionally, before forming the dielectric layer on the protective layer and the covering layer, the method further includes: forming an etch stop layer on the protective layer and the covering layer.

[0015] Optionally, after forming the first opening and before forming the second opening, the method further includes: forming a sacrificial layer in the first opening, wherein the sacrificial layer also covers the surface of the dielectric layer; and performing a planarization process on the sacrificial layer.

[0016] Optionally, the step of forming the conductive layer includes: forming an initial conductive layer on the source and drain, wherein the top surface of the initial conductive layer is flush with the top surface of the initial spacer; etching the initial conductive layer until the top surface of the initial conductive layer is lower than the top surface of the initial spacer, thereby forming a conductive layer.

[0017] Optionally, the step of forming the first covering layer includes: forming an initial first covering layer on the conductive layer, wherein the top surface of the initial first covering layer is flush with the top surface of the initial side wall; etching the initial first covering layer until the top surface of the initial first covering layer is lower than the top surface of the initial side wall, thereby forming a first covering layer.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] After forming a first covering layer on the conductive layer whose top surface is lower than the top surface of the initial sidewall, the initial sidewall is etched to form a sidewall whose top surface is flush with the top surface of the first covering layer, and then a second covering layer is formed on the sidewall and the first covering layer. On the one hand, when etching the protective layer on the gate structure, the second covering layer on the top of the sidewall can protect the sidewall from etching damage, so that the bottom of the first interconnection layer subsequently formed in the protective layer is limited between the sidewalls, avoiding short circuit between the first interconnection layer and the conductive layer due to the close distance; on the other hand, the top surface of the conductive layer is lower than the top surface of the sidewall, the first covering layer formed on the conductive layer is located between the sidewalls, and the bottom of the second interconnection layer subsequently formed in the first covering layer is limited between the sidewalls, avoiding short circuit between the second interconnection layer and the gate structure due to the close distance, which is beneficial to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure in one embodiment;

[0021] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure in another embodiment;

[0022] Figures 3 to 22 It is a structural schematic diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The electrical performance of the COAG structure MOSFET in the prior art still needs to be improved.

[0024] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor structure in one embodiment.

[0025] refer to Figure 1 The semiconductor structure includes: a substrate 100; a fin 101, located on the substrate 100; a gate structure 102, spanning the fin 101; a sidewall 103, located on the sidewall of the gate structure 102; a source and drain 104, located in the fin 101 on both sides of the gate structure 102; a conductive layer 105, located on the top of the source and drain 104; a first hard mask layer 106, located on the top surface of the gate structure 102; a second hard mask layer 107, located on the top of the conductive layer 105, and also covering the top surface of the sidewall 103; a dielectric layer 108, located on the first hard mask layer 106 and the second hard mask layer 107; a second interconnect layer 109, located in the second hard mask layer 107, and located on the top of the conductive layer 105.

[0026] The inventors found that in the above embodiment, after the second interconnection layer 109 is formed, since the distance between the second interconnection layer 109 and the gate structure 102 is small (refer to Figure 1 As a result, a short circuit between the second interconnect layer 109 and the gate structure 102 may occur easily during the electrical connection process, thereby affecting the performance of the semiconductor structure.

[0027] Another method for forming a semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0028] Figure 2 FIG. 4 is a schematic cross-sectional structural diagram of a semiconductor structure in another embodiment.

[0029] refer to Figure 2 The semiconductor structure includes: a substrate 200; a fin 201, located on the substrate 200; a gate structure 202, spanning the fin 201; a sidewall 203, located on the sidewall of the gate structure 202, and the top of the sidewall 203 is higher than the top of the gate structure 202; a source and a drain 204, located in the fin 201 on both sides of the gate structure 202; a conductive layer 205, located on the top of the source and drain 204; a first hard mask layer 206, located on the top surface of the gate structure 202; a second hard mask layer 207, located on the top surface of the conductive layer 205; a dielectric layer 208, located on the first hard mask layer 206, the second hard mask layer 207 and the sidewall 203; a first interconnect layer 209, located in the first hard mask layer 206, and located on the top of the gate structure 202 between the source and drain 204.

[0030] The inventors found that in the above embodiment, after the first interconnection layer 209 is formed, due to the small distance between the first interconnection layer 209 and the conductive layer 205, a short circuit is easily generated between the first interconnection layer 209 and the conductive layer 205 during the electrical connection process (refer to Figure 2 The dotted circle part in the middle), thereby affecting the performance of the semiconductor structure.

[0031] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. After forming a first covering layer whose top surface is lower than the top surface of an initial sidewall on a conductive layer, the initial sidewall is etched to form a sidewall whose top surface is flush with the top surface of the first covering layer, and then a second covering layer is formed on the sidewall and the first covering layer. On the one hand, the second covering layer plays a role in protecting the sidewall. When the protective layer on the gate structure is subsequently etched to form a first opening, etching of the sidewall is avoided, and the bottom of the first opening is blocked by the sidewall. On the other hand, the top of the conductive layer is lower than the top of the sidewall. When the second covering layer and the first covering layer are subsequently etched to form a second opening, the bottom of the second opening is restricted by the sidewall, and the sidewall is also blocked between the gate structure, thereby avoiding short circuit between the first interconnection layer subsequently formed in the first opening and the conductive layer, and short circuit between the second interconnection layer subsequently formed in the second opening and the gate structure, which is beneficial to improving the electrical performance of the semiconductor structure.

[0032] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] Figures 3 to 22 It is a structural schematic diagram corresponding to each step of a semiconductor structure forming process in one embodiment of the present invention.

[0034] refer to Figure 3 , providing a substrate.

[0035] In this embodiment, the base includes a substrate (not shown) and a plurality of discretely arranged fins 300 located on the substrate, and the fins 300 extend along a first direction X.

[0036] In other embodiments, the fin may not be formed on the substrate.

[0037] In this embodiment, the material of the substrate is silicon.

[0038] In other embodiments, the material of the substrate may also be semiconductor materials such as germanium, silicon germanium, gallium arsenide, silicon on insulator (SOI), and germanium on insulator (GOI).

[0039] In this embodiment, the material of the fin 300 is silicon; in other embodiments, the material of the fin 300 may also be a semiconductor material such as silicon germanium.

[0040] In this embodiment, the method for forming the fin 300 includes: forming a fin material film (not shown) on the substrate; forming a patterned layer (not shown) on the fin material film; and etching the fin material film using the patterned layer as a mask until the substrate surface is exposed to form the fin 300.

[0041] In this embodiment, an isolation structure (not shown) is further formed on the substrate, and the isolation structure covers a portion of the sidewall of the fin 300 .

[0042] In this embodiment, the material of the isolation structure is silicon oxide; in other embodiments, the material of the isolation structure may also include one or more combinations of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0043] In this embodiment, the method for forming the isolation structure includes: forming an isolation structure film (not shown) covering the fin 300 on the substrate; and etching back the isolation structure film to form the isolation structure.

[0044] The process for forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by the fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.

[0045] After the isolation structure is formed, a gate structure, an initial spacer on the sidewall of the gate structure, and a source and drain in the fin 300 on both sides of the gate structure are formed on the substrate.

[0046] The specific steps of forming the gate structure, the initial sidewall spacer and the source and drain include:

[0047] refer to Figure 4 , a dummy gate structure 310 is formed on the substrate.

[0048] In this embodiment, a dummy gate structure 310 is formed on the substrate and spans across the fin 300 .

[0049] In this embodiment, the dummy gate structure 310 includes: a dummy gate dielectric layer 311 located on the fin 300 , a dummy gate layer 312 located on the dummy gate dielectric layer 311 , and a gate protection layer 313 located on the dummy gate layer 312 .

[0050] In this embodiment, the material of the dummy gate dielectric layer 311 is silicon oxide.

[0051] In this embodiment, the material of the dummy gate layer 312 is polysilicon.

[0052] In this embodiment, the material of the gate protection layer 313 includes: silicon nitride or silicon oxide; in other embodiments, the material of the gate protection layer 313 can also be one or more combinations of materials such as silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0053] In this embodiment, the gate protection layer 313 protects the dummy gate layer 312 in the subsequent process of forming the source and drain, and also serves as a stop layer for the subsequent planarization of the interlayer dielectric layer.

[0054] Continue to refer Figure 4 After the dummy gate structure 310 is formed, an initial spacer 320 is formed on the sidewall of the dummy gate structure 310 , and the top surface of the initial spacer 320 is flush with the top surface of the dummy gate structure 310 .

[0055] In this embodiment, the material of the initial side wall 320 is a low-k dielectric material, and the low-k dielectric material is silicon oxycarbide (SiOC); in other embodiments, the material of the initial side wall 320 can also be one or more combinations of materials such as silicon nitride, silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0056] The initial spacer 320 is used to define the position of the subsequently formed source and drain, and the initial spacer 320 is used to protect the sidewall of the dummy gate layer 312 to prevent the subsequently formed gate layer from having morphological defects that affect the electrical performance of the semiconductor structure.

[0057] refer to Figure 5 The source and drain 330 are formed in the substrate on both sides of the dummy gate structure 310 , and the top surface of the source and drain 330 is higher than or flush with the top surface of the substrate.

[0058] In this embodiment, the fins 300 on both sides of the dummy gate structure 310 are etched to form source and drain 330 in the fins 300 .

[0059] In this embodiment, the bottom of the source drain 330 is located in the fin 300, and the top surface of the source drain 330 is higher than the top surface of the fin 300; in other embodiments, the bottom of the source drain 330 is located in the fin 300, and the top surface of the source drain 330 is flush with the top surface of the fin 300.

[0060] The source and drain 330 have source and drain doping ions.

[0061] The process of forming the source and drain 330 includes an epitaxial growth process; the process of doping source and drain doping ions in the source and drain is an in-situ doping process.

[0062] When the semiconductor device is a P-type device, the material of the source and drain 330 includes: silicon, germanium or silicon germanium; the source and drain doping ions are P-type ions, including boron ions, BF 2- ions or indium ions; when the semiconductor device is an N-type device, the material of the source and drain 300 includes: silicon, gallium arsenide or indium gallium arsenide; the source and drain doping ions are N-type ions, including phosphorus ions or arsenic ions.

[0063] In this embodiment, the semiconductor device is a P-type device, the source and drain 330 is made of silicon, and the source and drain doping ions are boron ions. In other embodiments, the semiconductor device is an N-type device, the source and drain 330 is made of silicon, and the source and drain doping ions are phosphorus ions.

[0064] refer to Figure 6 After the source and drain 330 are formed, an interlayer dielectric layer 340 is further formed on the substrate and the source and drain 330 , and the interlayer dielectric layer 340 exposes the top surface of the dummy gate structure 310 .

[0065] In this embodiment, the interlayer dielectric layer 340 is formed on the substrate and the source and drain 330 , and the interlayer dielectric layer 340 covers the sidewalls of the dummy gate structure 310 and exposes the top surface of the gate protection layer 313 .

[0066] In this embodiment, the method for forming the interlayer dielectric layer 340 includes: forming an interlayer dielectric material layer (not shown) on the substrate and the source and drain 330, wherein the interlayer dielectric material layer covers the top surface of the pseudo gate structure 310; and planarizing the interlayer dielectric material layer until the top surface of the gate protection layer 313 is exposed to form the interlayer dielectric layer 340.

[0067] In this embodiment, the material of the interlayer dielectric layer 340 is silicon oxide; in other embodiments, the material of the interlayer dielectric layer 340 can also be a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0068] In this embodiment, the formation process of the interlayer dielectric layer 340 is a chemical vapor deposition process; in other embodiments, the formation process of the interlayer dielectric layer 340 can also be one or more combinations of chemical vapor deposition processes, physical vapor deposition processes or atomic layer deposition processes.

[0069] refer to Figure 7 , the dummy gate structure 310 is removed by etching until the substrate surface is exposed to form a gate opening 301 .

[0070] In this embodiment, the gate protection layer 313 , the dummy gate layer 312 and the dummy gate dielectric layer 311 are removed, and the gate opening 301 is formed between the sidewalls 320 .

[0071] The process of removing the dummy gate structure 310 includes a dry etching process or a wet etching process.

[0072] refer to Figure 8 , an initial gate structure 350 is formed in the gate opening 301 , and a top surface of the initial gate structure 350 is flush with a top surface of the initial spacer 320 .

[0073] In this embodiment, the initial gate structure 350 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0074] In this embodiment, the material of the gate dielectric layer includes a high-K dielectric material, such as oxides - Al2O3, HfO2, Ta2O5, TiO2, ZrO2, etc.

[0075] In other embodiments, the material of the gate dielectric layer may further include other dielectric materials with a dielectric constant higher than 3.9.

[0076] In this embodiment, the material of the gate layer is metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

[0077] In this embodiment, the method for forming the initial gate structure 350 includes: forming the gate dielectric layer on the sidewalls and bottom of the gate opening 301, forming an initial gate material layer on the gate dielectric layer, and planarizing the initial gate material layer until the top surface of the gate material layer is flush with the top of the initial sidewall 320 to form the initial gate structure 350.

[0078] refer to Fig. 9 , etching the initial gate structure 350 until the top surface of the initial gate structure 350 is lower than the top surface of the initial spacer 320 , to form a gate structure 351 .

[0079] In this embodiment, the method of etching the initial gate structure 350 is dry etching.

[0080] refer to Fig.10 After the gate structure 351 is formed, a protection layer 360 is formed on the gate structure, and the top surface of the protection layer 360 is flush with the top surface of the initial spacer 320 .

[0081] In this embodiment, the material of the protection layer 360 is silicon nitride.

[0082] In other embodiments, the material of the protection layer 360 may also be aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0083] In this embodiment, the step of forming the protective layer 360 includes: forming an initial protective material layer (not shown) on the gate structure 351, the initial sidewall 320 and the interlayer dielectric layer 340; planarizing the initial protective material layer until the top surface of the interlayer dielectric layer 340 is exposed, and forming a protective layer 360 on the top surface of the gate structure 351.

[0084] In this embodiment, the protective layer 360 is formed by a chemical vapor deposition process; in other embodiments, the protective layer 360 may be formed by a physical vapor deposition process or an atomic layer deposition process.

[0085] The thickness of the protective layer 360 is 10-50 nm. If the protective layer 360 is too thin, it cannot protect the top of the gate structure well; if the protective layer 360 is too thick, the height of the gate structure 351 is too short, which will increase the resistance.

[0086] After forming the protection layer 360, a conductive layer is formed on the source and drain 330. Specifically, the steps of forming the conductive layer include:

[0087] refer to Fig.11 , the interlayer dielectric layer 340 on the source and drain 330 is etched until the top surface of the source and drain 330 is exposed, thereby forming a conductive opening 331 .

[0088] In this embodiment, the conductive opening 331 provides space for subsequently forming a conductive layer on the source and drain 330 .

[0089] refer to Fig.12 A conductive layer 370 is formed in the conductive opening 331 , and a top surface of the conductive layer 370 is lower than a top surface of the initial spacer 320 .

[0090] In this embodiment, the method for forming the conductive layer 370 includes: forming an initial conductive layer (not shown) in the conductive opening 331, and the top surface of the initial conductive layer is flush with the top surface of the initial side wall 320; etching the initial conductive layer until the top surface of the initial conductive layer is lower than the top surface of the initial side wall 320, so as to form the conductive layer 370.

[0091] In this embodiment, the conductive layer 370 is made of metal, including copper, tungsten or aluminum.

[0092] In this embodiment, the conductive layer 370 is formed by electrochemical plating; in other embodiments, the conductive layer 370 may be formed by physical vapor deposition.

[0093] The method of etching the initial conductive layer includes one of dry etching and wet etching processes or a combination of the two.

[0094] In this embodiment, the conductive layer 370 serves to subsequently realize electrical connection between the source and drain 330 and the outside.

[0095] refer to Fig.13 , a first covering layer 380 is formed on the conductive layer 370 , and a top surface of the first covering layer 380 is lower than a top surface of the initial spacer 320 .

[0096] In this embodiment, the method for forming the first covering layer 380 includes: forming an initial first covering layer (not shown) on the conductive layer 370, wherein the top surface of the initial first covering layer is flush with the top surface of the initial side wall 320; etching the initial first covering layer until the top surface of the initial first covering layer is lower than the top surface of the initial side wall 320, thereby forming the first covering layer 380.

[0097] In this embodiment, the material of the first covering layer 380 is silicon oxide.

[0098] In other embodiments, the material of the first covering layer 380 may also be silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0099] In this embodiment, the material of the first covering layer 380 is different from the material of the protective layer 360. By utilizing the etching selectivity ratio of the material of the first covering layer and the material of the protective layer, damage to the first covering layer 380 can be avoided when the protective layer 360 is subsequently etched; or etching damage to the protective layer 360 can be avoided when the first covering layer 380 is etched.

[0100] In other embodiments, the materials of the first covering layer 380 and the protective layer 360 may also be the same. When the materials of the two are the same, when etching the protective layer 360, it is necessary to add a mask plate covering the first covering layer 380 to avoid etching damage to the first covering layer 380; similarly, when etching the first covering layer 380, it is necessary to add a mask plate covering the protective layer 360 to avoid etching damage to the protective layer 360.

[0101] In this embodiment, the process of forming the first covering layer 380 is a chemical vapor deposition process; in other embodiments, the first covering layer 380 may also be formed by a physical vapor deposition process or an atomic layer deposition process.

[0102] In this embodiment, the thickness of the initial first covering layer is 10-50 nm. If the thickness of the initial first covering layer is too thin, the space provided for the subsequent formation of the second covering layer is too small, and the formed second covering layer is too thin to play a role in protecting the sidewall; if the thickness of the initial first covering layer is too thick, the height of the conductive layer 370 is too short, which will increase the resistance.

[0103] In this embodiment, the method of etching the initial first covering layer is dry etching.

[0104] refer to Fig.14 , etching the initial sidewall spacer 320 until the top surface of the initial sidewall spacer 320 is flush with the top surface of the first covering layer 380 , to form a sidewall spacer 321 .

[0105] In this embodiment, the method of etching the initial sidewall spacer 320 is dry etching.

[0106] In this embodiment, the initial sidewall spacer 320 is etched until the top surface is flush with the top surface of the first cover layer 380 , so as to facilitate the subsequent formation of the second cover layer on the sidewall spacer 321 and the first cover layer 380 .

[0107] In this embodiment, the top surface of the side wall 321 is flush with the top surface of the first covering layer 380, and the first covering layer 380 is formed between the side walls 321. When the first covering layer 380 is subsequently etched to form a second opening on the conductive layer 370, the bottom of the second opening can be confined between the side walls 321, so that the formed second interconnect layer and the gate structure 351 are blocked by the side wall 321, thereby avoiding a short circuit between the second interconnect layer and the gate structure 351.

[0108] refer to Fig.15A second covering layer 400 is formed on the sidewall 321 and the first covering layer 380 , the top surface of the second covering layer 400 is flush with the top surface of the protection layer 360 , and the first covering layer 380 and the second covering layer 400 constitute a covering layer.

[0109] In this embodiment, the material of the second covering layer 400 is the same as that of the first covering layer 380 , that is, silicon oxide, which facilitates subsequent etching of the second covering layer 400 and the first covering layer 380 to form a second opening on the conductive layer 370 .

[0110] In other embodiments, the material of the second covering layer 400 may also be silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0111] In this embodiment, the material of the second covering layer 400 is different from that of the protective layer 360 and that of the sidewall 321. When the protective layer 360 is subsequently etched, the second covering layer 400 covers the surface of the sidewall 321, which can protect the sidewall 321 from etching damage, so that the bottom of the first opening subsequently formed on the gate structure 351 is confined within the sidewall 321, so that the formed first interconnect layer and the conductive layer are blocked by the sidewall 321 to avoid short circuit. At the same time, since the materials of the second covering layer 400 and the protective layer 360 are different, there is an etching selectivity ratio, which is beneficial to increase the process window and reduce the process difficulty when the protective layer 360 or the second covering layer 400 is subsequently etched.

[0112] In other embodiments, the materials of the second covering layer 400 and the protective layer 360 may also be the same. When the materials of the two are the same, when etching the protective layer 360, it is necessary to add a mask plate covering the second covering layer 400 to avoid etching damage to the second covering layer 400; similarly, when etching the second covering layer 400, it is necessary to add a mask plate covering the protective layer 360 to avoid etching damage to the protective layer 360.

[0113] refer to Fig.16 , an etch stop layer 500 is formed on the second covering layer 400 and the protection layer 360 .

[0114] In this embodiment, the material of the etch stop layer 500 is silicon nitride.

[0115] In other embodiments, the material of the etch stop layer 500 may also be aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0116] In this embodiment, the process for forming the etch stop layer 500 is a chemical vapor deposition process; in other embodiments, the etch stop layer 500 may also be formed by a physical vapor deposition process or an atomic layer deposition process.

[0117] In this embodiment, the material of the etch stop layer 500 is different from that of the second cover layer 400. When the first opening on the gate structure 351 is subsequently formed, the etch stop layer 500 can protect the second cover layer from being damaged, thereby ensuring that the conductive layer 370 is not damaged.

[0118] The thickness of the etch stop layer 500 is 3-10 nm. If the thickness of the etch stop layer 500 is less than 3 nm, it is too thin to provide good protection; if the thickness of the etch stop layer 500 is greater than 10 nm, the capacitance of the semiconductor structure will increase.

[0119] Continue to refer Fig.16 A dielectric layer 600 is formed on the etch stop layer 500 , and the dielectric layer 600 is used to subsequently form a first interconnection layer and a second interconnection layer connected to the outside in the dielectric layer 600 .

[0120] In this embodiment, the material of the dielectric layer 600 is the same as that of the second covering layer 400, which is silicon oxide; in other embodiments, the material of the dielectric layer 600 may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant lower than 2.5).

[0121] The material of the dielectric layer 600 is different from the material of the etching stop layer 500. When the dielectric layer 600 and the protective layer 360 are subsequently etched to form the first opening, the presence of the etching stop layer 500 can avoid over-etching that causes etching damage to the second covering layer 400 on the conductive layer 370, thereby protecting the sidewalls 321 and the conductive layer 370 from being in good shape, which is beneficial to the performance of the semiconductor structure.

[0122] The thickness of the dielectric layer 600 is 10-100 nm. If the dielectric layer 600 is too thin, the capacitance will be high; if the dielectric layer 600 is too thick, the difficulty of the etching process will increase when the dielectric layer 600 is subsequently etched to form the first opening and the second opening.

[0123] After forming the dielectric layer 600, a first opening is formed on the gate structure 351, and a second opening is formed on the conductive layer 370. Specifically, the steps of forming the first opening and the second opening include:

[0124] refer to Fig.17, a first patterned layer 601 is formed on the dielectric layer 600 , wherein the first patterned layer 601 defines the position and size of a first opening to be formed.

[0125] In this embodiment, the first patterned layer 601 is a photoresist layer.

[0126] refer to Fig.18 , using the first patterned layer 601 as a mask, the dielectric layer 600 , the etch stop layer 500 and the protection layer 360 are etched until the top surface of the gate structure 351 is exposed, thereby forming a first opening 610 .

[0127] In this embodiment, the first opening 610 provides space for subsequently forming a first interconnection layer.

[0128] In this embodiment, the process of forming the first opening 610 is a dry etching process; in other embodiments, the first opening 610 may also be formed by a wet etching process.

[0129] In this embodiment, during the process of forming the first opening 610, due to the presence of the etching stop layer 500, the second covering layer 400 will not be damaged by etching. When the protection layer 360 is etched, the second covering layer 400 covers the top of the side wall 321 to protect the side wall 321 from etching damage. The side walls 321 on both sides of the first opening 610 can limit the bottom of the first opening 610 to avoid the distance between the first interconnection layer and the conductive layer 370 subsequently formed in the first opening 610 being too close, thereby avoiding a short circuit between the first interconnection layer and the conductive layer 370.

[0130] After forming the first opening 610 , the first patterned layer 601 is removed.

[0131] refer to Fig.19 , a sacrificial layer 602 is formed in the first opening 610 , and the sacrificial layer 602 fills the first opening 610 and also covers the surface of the dielectric layer 600 .

[0132] After the sacrificial layer 602 is formed, a planarization process is performed on the sacrificial layer 602 .

[0133] In this embodiment, the planarization process is a chemical mechanical polishing process.

[0134] In this embodiment, the purpose of forming the sacrificial layer 602 and performing a planarization treatment is to facilitate forming a second patterned layer on the sacrificial layer 602 to define the position and size of the second opening when the dielectric layer 600 is subsequently etched to form the second opening.

[0135] In this embodiment, the material of the sacrificial layer 602 is an organic coating.

[0136] refer to Fig. 20 , a second patterned layer 603 is formed on the sacrificial layer 602, wherein the second patterned layer 603 defines the position and size of the second opening to be formed.

[0137] In this embodiment, the second patterned layer 603 is a photoresist layer.

[0138] refer to Fig.21 , using the second patterned layer 603 as a mask, the sacrificial layer 602 , the dielectric layer 600 , the etch stop layer 500 , the second covering layer 400 and the first covering layer 380 are etched until the top surface of the conductive layer 370 is exposed to form a second opening 620 .

[0139] In this embodiment, the second opening 620 provides space for subsequently forming a second interconnection layer.

[0140] In this embodiment, the process of forming the second opening 620 is a dry etching process; in other embodiments, the second opening 620 may also be formed by a wet etching process.

[0141] In this embodiment, during the process of forming the second opening 620, since the first covering layer 380 is located between the side walls 321, the bottom of the second opening 620 is also located between the side walls 321. Subsequently, the side walls 321 are present between the second interconnect layer formed in the second opening 620 and the gate structure 351, thereby avoiding a short circuit between the second interconnect layer and the gate structure 351.

[0142] After forming the second opening 620 , the second patterned layer 603 and the sacrificial layer 602 are removed.

[0143] refer to Fig. 22 , a first interconnection layer 611 is formed in the first opening 610 ; and a second interconnection layer 621 is formed in the second opening 620 .

[0144] In this embodiment, the material of the first interconnection layer 611 is metal, including aluminum, copper, nickel, etc.

[0145] In this embodiment, the function of the first interconnection layer 611 is to connect different devices together to form a circuit, and can also transmit external electrical signals to different parts inside the semiconductor device, thereby forming a semiconductor device with certain functions.

[0146] In this embodiment, the process for forming the first interconnection layer 611 is an electrochemical plating process, because the electroplating process can form the first interconnection layer 611 with good density and high uniformity.

[0147] In this embodiment, the material of the second interconnection layer 621 is metal, including aluminum, copper, nickel, etc.

[0148] In this embodiment, the second interconnect layer 621 is used to connect different devices together to form a circuit, and can also transmit external electrical signals to different parts inside the semiconductor device, thereby forming a semiconductor device with certain functions.

[0149] In this embodiment, the process for forming the second interconnection layer 621 is an electrochemical plating process, because the electroplating process can form the second interconnection layer 621 with good density and high uniformity.

[0150] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method.

[0151] refer to Fig. 22 The semiconductor structure includes: a substrate; a gate structure 351, located on the substrate; a sidewall 321, located on the sidewall of the gate structure 351, and the top surface of the sidewall 321 is higher than the top surface of the gate structure 351; a source and drain 330, located in the substrate on both sides of the gate structure 351, and the top surface of the source and drain is higher than or flush with the top surface of the substrate; a conductive layer 370, located on the source and drain 330; a protective layer 360, located on the top of the gate structure 351 and on the sidewall The top surface of the protective layer 360 is higher than the top surface of the side wall 321; the covering layer is located on the top of the conductive layer 370 and the side wall 321, and the top surface of the covering layer is flush with the top surface of the protective layer 360; the dielectric layer 600 is located on the protective layer 360 and the covering layer; the first interconnection layer 611 is located in the protective layer 360 and on the top of the gate structure 351; the second interconnection layer 621 is located in the covering layer and on the top of the conductive layer 370.

[0152] In this embodiment, the base includes a substrate (not shown) and a plurality of discretely arranged fins 300 located on the substrate, and the fins 300 extend along a first direction X.

[0153] In this embodiment, the material of the side wall 321 is a low-k dielectric material, and the low-k dielectric material is silicon oxycarbide (SiOC); in other embodiments, the material of the initial side wall 320 can also be one or more combinations of materials such as silicon nitride, silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon boron carbonitride (SiCBN).

[0154] In this embodiment, the material of the protective layer 360 is silicon nitride; in other embodiments, the material of the protective layer 360 may also be aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0155] In this embodiment, the covering layer includes: a first covering layer 380 located on the top of the conductive layer 370, and a second covering layer 400 located on the top of the first covering layer 380 and the top of the side wall 321; the top surface of the first covering layer 380 is flush with the top surface of the side wall 321, and the top surface of the second covering layer 400 is flush with the top surface of the protective layer 360.

[0156] In this embodiment, the material of the first covering layer 380 is silicon oxide; in other embodiments, the material of the first covering layer 380 may also be silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0157] In this embodiment, the material of the second covering layer 400 is the same as that of the first covering layer 380, that is, silicon oxide; in other embodiments, the material of the second covering layer 400 may also be silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0158] In this embodiment, the materials of the second covering layer 400 and the first covering layer 380 are different from the material of the protective layer 360 and the material of the sidewall 321. When etching the protective layer 360, the second covering layer 400 covers the surface of the sidewall 321, which can protect the sidewall 321 from etching damage, so that the bottom of the first opening subsequently formed on the gate structure 351 is confined within the sidewall 321, so that the formed first interconnection layer 611 and the conductive layer are blocked by the sidewall 321 to avoid short circuit; when etching the first covering layer 380 and the second covering layer 400, the protective layer 360 and the sidewall 321 can be prevented from being damaged by etching, thereby avoiding short circuit between the second interconnection layer 621 and the gate structure 351.

[0159] In this embodiment, the top surface of the conductive layer 370 is lower than the top surface of the sidewall 321, and the bottom of the second interconnect layer 621 formed on the conductive layer 370 is confined between the sidewalls 321, so that the sidewall 321 blocks the second interconnect layer and the gate structure 351, thereby preventing the second interconnect layer 621 and the gate structure 351 from short-circuiting.

[0160] In other embodiments, the material of the first covering layer 380 and the second covering layer 400 may also be the same as the material of the protective layer 360. When the material of the first covering layer 380 and the second covering layer 400 is the same as the material of the protective layer 360, when etching the protective layer 360, it is necessary to add a mask that completely covers the second covering layer 400 to prevent the second covering layer 400 and the first covering layer 380 and the side wall 321 thereunder from being etched damage; similarly, when etching the second covering layer 400 and the first covering layer 380, it is necessary to add a mask that completely covers the protective layer 360 to prevent the protective layer 360 from being etched damage.

[0161] In this embodiment, the material of the first interconnection layer 611 is metal, including aluminum, copper, nickel, etc.

[0162] In this embodiment, the material of the second interconnection layer 621 is metal, including aluminum, copper, nickel, etc.

[0163] refer to Fig. 22 The semiconductor structure further includes: an etch stop layer 500 located on the protection layer 360 and the second cover layer 400 , and the dielectric layer 600 is located on the etch stop layer 500 .

[0164] In this embodiment, the material of the etch stop layer 500 is silicon nitride; in other embodiments, the material of the etch stop layer 500 may also be aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

[0165] In this embodiment, the material of the etch stop layer 500 is different from the materials of the second cover layer 400 and the dielectric layer 600. When etching the dielectric layer 600, etching will first stop at the etch stop layer 500 to avoid over-etching and causing etching damage to the second cover layer 400.

[0166] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A gate structure, located on the substrate; A sidewall spacer is located on the sidewall of the gate structure, and a top surface of the sidewall spacer is higher than a top surface of the gate structure; Sources and drains are located in the substrate at both sides of the gate structure, and the top surfaces of the sources and drains are higher than or flush with the top surface of the substrate; A conductive layer, located on the source and drain; A protection layer, located on the top of the gate structure and between the sidewalls, wherein the top surface of the protection layer is higher than the top surface of the sidewalls; A covering layer, located on top of the conductive layer and the sidewalls, wherein a top surface of the covering layer is flush with a top surface of the protective layer; A dielectric layer, located on the protective layer and the cover layer; A first interconnect layer, located in the protection layer and on top of the gate structure; A second interconnect layer is located within the cover layer and on top of the conductive layer.

2. The semiconductor structure according to claim 1, wherein: The protective layer and the covering layer are made of different materials.

3. The semiconductor structure according to claim 2, wherein: The material of the protection layer includes silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

4. The semiconductor structure according to claim 2, characterized in that The material of the cover layer includes silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

5. The semiconductor structure according to claim 1, wherein: The covering layer includes: a first covering layer located on the top of the conductive layer, and a second covering layer located on the top of the first covering layer and the top of the sidewall; the top surface of the first covering layer is flush with the top surface of the sidewall, and the top surface of the second covering layer is flush with the top surface of the protective layer.

6. The semiconductor structure according to claim 1, wherein: Also includes: An etch stop layer is located on the protection layer and the cover layer, and the dielectric layer is located on the etch stop layer.

7. The semiconductor structure according to claim 6, wherein: The material of the etch stop layer is different from that of the cover layer, and the material of the etch stop layer includes silicon nitride, aluminum oxide, aluminum nitride, boron nitride, silicon carbide or amorphous silicon.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a gate structure, an initial spacer located on the sidewall of the gate structure, and a source and drain located in the substrate on both sides of the gate structure; forming a protection layer on the gate structure, wherein a top surface of the protection layer is flush with a top surface of the initial spacer; forming a conductive layer on the source and drain, wherein a top surface of the conductive layer is lower than a top surface of the initial spacer; forming a first covering layer on the conductive layer, wherein a top surface of the first covering layer is lower than a top surface of the initial spacer; Etching the initial sidewall spacer until the top surface of the initial sidewall spacer is flush with the top surface of the first covering layer to form a sidewall spacer; forming a second covering layer on the sidewall and the first covering layer, wherein the top surface of the second covering layer is flush with the top surface of the protection layer, and the first covering layer and the second covering layer constitute a covering layer; forming a dielectric layer on the protective layer and the cover layer; Etching the dielectric layer and a portion of the protective layer until the top surface of the gate structure is exposed to form a first opening; Etching the dielectric layer and a portion of the cover layer until the top surface of the conductive layer is exposed to form a second opening; forming a first interconnect layer in the first opening; A second interconnect layer is formed in the second opening.

9. The method for forming a semiconductor structure according to claim 8, wherein: Before forming the dielectric layer on the protection layer and the cover layer, the method further includes: forming an etching stop layer on the protection layer and the cover layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: After forming the first opening and before forming the second opening, the method further includes: forming a sacrificial layer in the first opening, wherein the sacrificial layer also covers a surface of the dielectric layer; The sacrificial layer is planarized.

11. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the conductive layer comprises: Forming an initial conductive layer on the source and drain, wherein the top surface of the initial conductive layer is flush with the top surface of the initial spacer; The initial conductive layer is etched until a top surface of the initial conductive layer is lower than a top surface of the initial sidewall spacer to form a conductive layer.

12. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the first covering layer comprises: forming an initial first covering layer on the conductive layer, wherein a top surface of the initial first covering layer is flush with a top surface of the initial spacer; The initial first covering layer is etched until a top surface of the initial first covering layer is lower than a top surface of the initial spacer to form a first covering layer.

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