Microelectronic devices including semiconductive pillar structures, and related methods and electronic systems

Abstract

This application relates to microelectronic devices including semiconductive pillar structures, and related methods and electronic systems. A microelectronic device includes semiconductive pillar structures each individually including a digit line contact region laterally disposed between two storage node contact regions. At least one of the semiconductive pillar structures includes a first end portion including a first storage node contact region, a second end portion including a second storage node contact region, and an intermediate portion between the first and second end portions and including a digit line contact region, a longitudinal axis of the first end portion being angularly oriented relative to a longitudinal axis of the intermediate portion. Related microelectronic devices, electronic systems, and methods are also described.

Description

[0001] Priority requirements

[0002] This application claims the filing date benefit of U.S. Patent Application No. 16 / 992,615, entitled “Microelectronic Devices Including Semiconductive Pillar Structures, and Related Methods and Electronic Systems,” filed August 13, 2020.

[0003] Cross-references to related applications

[0004] This application relates to U.S. Patent Application No. 16 / 992,589, filed August 13, 2020, entitled “Microelectronic Devices Including Semiconductive Pillar Structures, and Related Methods and Electronic Systems.” Technical Field

[0005] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices including semiconductor pillar structures, and to related microelectronic devices and electronic systems. Background Technology

[0006] Semiconductor device designers typically aim to increase the integration or density of features within a semiconductor device by reducing the size of individual features and by decreasing the spacing between adjacent features. Furthermore, semiconductor device designers often seek architectures that are not only compact but also offer performance advantages and simplify the design process.

[0007] A relatively common type of semiconductor device is the memory device. A memory device can comprise a memory array having several memory cells arranged in a grid pattern. One type of memory cell is Dynamic Random Access Memory (DRAM). In its simplest design configuration, a DRAM cell contains an access device, such as a transistor, and a storage device, such as a capacitor. Modern applications of memory devices utilize large numbers of DRAM cells arranged in row and column arrays. DRAM cells can be electrically accessed via digital lines and word lines arranged along the rows and columns of the array.

[0008] The decreasing size and spacing of memory device features creates an increasing demand for methods used to form these features. For example, one limiting factor in the continued shrinking of memory devices is the unintentional shorting between contacts associated with the various components of a DRAM cell. As used herein, "contact" refers to a connection that facilitates a conductive path between at least two structures. For instance, in a DRAM device exhibiting a two-bit memory cell structure, digital line contacts are provided between digital lines and access devices (e.g., transistors) formed in or above a substrate, and memory node contacts are formed between access devices and memory nodes (e.g., capacitors) capable of storing charge. As the size of memory device (e.g., DRAM device) features decreases, the packing density of the associated contacts increases, leading to an increased likelihood of unintentional shorting between various components, which can adversely affect memory device performance. In some instances, digital line contacts can unintentionally contact memory node contacts, electrically shorting the digital line to the memory node and causing a failure of the memory cell associated with the memory node. Summary of the Invention

[0009] In some embodiments, a microelectronic device includes: a semiconducting pillar structure, each individually including a digital line contact area laterally disposed between two memory node contact areas, at least one of the semiconducting pillar structures including: a first end portion including a first memory node contact area; a second end portion including a second memory node contact area; and an intermediate portion between the first end portion and the second end portion and including the digital line contact area, wherein the longitudinal axis of the first end portion is oriented at an angle relative to the longitudinal axis of the intermediate portion.

[0010] In other embodiments, a method of forming a microelectronic device includes: forming a pattern of first lines of a first sacrificial material over a substrate material and forming a nitride material in the space between adjacent first lines; forming a second line of a second sacrificial material over the first lines, the second line of the second sacrificial material being oriented relative to the first lines at a first angle in the range of about 30° to about 60°; forming an oxide material on the side surface of the second lines; selectively removing portions of each of the first sacrificial material, the second sacrificial material, and the nitride material relative to the oxide material; forming a pattern of third lines including an underlayer material over the remaining portion of the first sacrificial material, the pattern of the third lines being oriented relative to the remaining portion of the first lines at a second angle; and removing portions of the nitride material selectively applied to the first sacrificial material through the pattern of the third lines to form a columnar structure pattern.

[0011] In another embodiment, a method of forming a microelectronic device includes: forming a first line comprising silicon in a first direction; forming a nitride material between the first lines; forming a second line comprising silicon in a second direction at a first angle relative to the first direction; forming spacers on the second lines; removing portions of the first lines and portions of the nitride material through the spacers; forming lines of a mask extending at a second angle relative to the first direction; removing portions of the nitride material between the lines of the mask; and removing portions of a semiconductive material adjacent to the remaining portions of the first lines and the nitride material to form a semiconductive pillar structure.

[0012] In another embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input and output devices; and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes semiconducting pillar structures spaced apart from each other. Each semiconducting pillar structure includes a central portion between a first end portion and a second end portion, and a first memory node contact electrically connected to the first end portion and a second memory node contact electrically connected to the second end portion. The at least one microelectronic device also includes a digital line electrically connected to the central portion, the digital line being oriented at an angle from about 30° to about 60° relative to the first and second end portions. Attached Figure Description

[0013] Figures 1A to 1X This is a simplified partial cross-sectional view of a method for forming a microelectronic device structure according to embodiments of the present disclosure. Figure 1A , Figure 1C , Figure 1E , Figure 1H , Figure 1J , Figure 1L , Figure 1N , Figure 1S , Figure 1T and Figures 1V to 1X ) and simplified top view ( Figure 1B , Figure 1D , Figure 1F , Figure 1G , Figure 1I , Figure 1K , Figure 1M , Figures 10 to 1R and Figure 1U );

[0014] Figure 2 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0015] Figure 3 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0016] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations for describing the embodiments herein. Elements and features shared between the figures may retain the same numerical designations, but for ease of description below, the reference numerals begin with the designation of the figure on which the element is introduced or most fully described.

[0017] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a full description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as DRAM memory devices, 3D NAND flash memory devices) or a complete microelectronic device. The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions used to form a complete microelectronic device from the structures can be performed using conventional techniques.

[0018] The materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by those skilled in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including but not limited to etching, planarization (e.g., chemical-mechanical planarization), or other known methods.

[0019] As used herein, the term “configuration” refers to the size, shape, material composition, material distribution, orientation, and arrangement of one or more of at least one structure and at least one device in order to facilitate the operation of one or more of the structure and device in a predetermined manner.

[0020] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) on which one or more structures and / or features are formed, and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction generally parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction generally perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by the surface of the substrate, which has a relatively large area compared to the other surfaces of the substrate.

[0021] As used herein, the term "generally" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition conforms to deviations (such as within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the specific parameter, property, or condition being generally satisfied, the parameter, property, or condition may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0022] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes the value, and a deviation from the value that will be understood by one of ordinary skill in the art to be within acceptable tolerances of the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0023] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and similar spatial relative terms are used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures were reversed, then an element described as being “below,” “under,” “below,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped, etc.), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0024] As used herein, features described as “proximate” to each other (e.g., areas, materials, structures, devices) refer to and include features of the disclosed identity (or multiple identities) that are most closely positioned (e.g., closest to, adjacent to) each other. Additional features (e.g., additional areas, additional materials, additional structures, additional devices) of a disclosed identity (or multiple identities) that do not match a “proximate” feature may be positioned between said “proximate” features. In other words, “proximate” features may be positioned directly adjacent to each other such that no other features intervene between “proximate” features; or “proximate” features may be positioned indirectly adjacent to each other such that at least one feature having an identity other than the identity associated with at least one “proximate” feature is positioned between “proximate” features. Therefore, features described as “vertically proximate” to each other refer to and include features of the disclosed identity (or multiple identities) that are most vertically close to each other (e.g., vertically closest to, vertically adjacent to). Furthermore, features described as “horizontally proximate” to each other refer to and include features of the disclosed identity (or multiple identities) that are horizontally closest to each other (e.g., horizontally closest to, horizontally adjacent to).

[0025] As used herein, the term "memory device" means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, and by way of example only, the term "memory device" refers to microelectronic devices that include not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory, and graphics processing units (GPUs) incorporating memory.

[0026] As used herein, “conductive material” means and includes one or more of the following conductive materials: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Fe-based alloys) The term "conductive structure" refers to and includes structures formed from and containing conductive materials. It encompasses gold, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni, and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, and stainless steel. It also includes conductive metal materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, and conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), and conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" refers to and includes structures formed from and containing conductive materials.

[0027] As used herein, “insulating material” means and includes electrically insulating materials, such as at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z N y One or more of the chemical formulas “x”, “y”, and “z” are included in this document (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiOx N y SiO x C z N y A chemical formula represents a material containing “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating materials can include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and “z” (if present) can be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and includes compounds having an elemental composition that cannot be expressed by a well-defined ratio of natural numbers and violates the law of definite proportions. Furthermore, “insulating structure” means and includes structures formed of and containing insulating materials.

[0028] As used herein, “selectively removable” material means and includes materials that exhibit a greater removal rate in response to the same treatment conditions relative to another material exposed to treatment conditions (e.g., exposure to radiation (e.g., heat)). A material selectively removable relative to another material is substantially completely removable without substantially removing said other material (e.g., without removing either substantially of the other material).

[0029] As used herein, "selectively etchable" material means and includes materials that exhibit a greater etching rate in response to exposure to the same etching chemicals and / or processing conditions compared to another material exposed to a given etching chemical and / or processing condition. For example, the material may exhibit an etching rate at least about five times greater than that of another material, such as about ten times, about twenty times, or about forty times greater. Those skilled in the art can select the etching chemicals and etching conditions used to selectively etch the desired material.

[0030] According to the embodiments described herein, a microelectronic device includes a semiconducting pillar structure (e.g., an elongated semiconducting pillar structure with a length greater than its width), the elongated semiconducting pillar structure including a bit line contact region laterally disposed between two memory node contact regions. The bit line contact region is electrically connected to a bit line contact, which in turn is electrically connected to a bit line extending in a first lateral direction. Each of the memory node contact regions is individually electrically connected to a memory node contact, and each of the memory node contacts is electrically connected to a memory node (e.g., a capacitor, which may also be referred to herein as a unit capacitor). Each semiconducting pillar structure may include a central portion comprising a bit line contact region, a first end portion at a first end of the central portion, and a second end portion at a second opposite end of the central portion. The first end portion comprises a first memory node contact region and the second end portion comprises a second memory node contact region. The central portion may extend in the first lateral direction and includes a longitudinal axis substantially parallel to the bit line. In other words, the central portion may be elongated in the direction in which the bit line extends. Each of the first and second end portions includes a longitudinal axis oriented at an angle relative to the longitudinal axis of the central portion. In other words, each of the first and second end portions extends at an angle relative to the central portion. In some embodiments, the semiconducting pillar structure exhibits a so-called "S" shape.

[0031] Orienting the first and second end portions at an angle relative to the central portion helps increase the distance between the memory node contact area and the bit line contact area of ​​the semiconducting pillar structure, thereby reducing the possibility of unintentional short circuits between such features compared to conventional microelectronic devices. Additionally, orienting the first and second end portions at an angle relative to the central portion helps increase the functional area of ​​the semiconducting pillar structure (e.g., an increased functional area for each of the bit line contact area and memory node contact). Furthermore, forming the end portions at an angle relative to the central portion facilitates an increase (e.g., a larger margin) in the area for forming bit line contacts on the bit line contact area and spacers along the bit lines, which can reduce capacitive coupling between bit lines. In some embodiments, the shape of the semiconducting pillar structure can reduce (e.g., eliminate) the overlap between the word line structure and the bit line contact area compared to a conventional pillar structure. In some embodiments, forming the first and second end portions at an angle relative to the central portion can promote increased mechanical stability (and reduced tipping) of the semiconducting pillar structure compared to a conventional pillar structure exhibiting a linear shape. Furthermore, the distance between the so-called through word line structures that are vertically overlaid on the semiconducting pillar structure but not electrically coupled to it can be increased, thereby reducing unintentional coupling between adjacent word lines and so-called "line hammering".

[0032] Microelectronic devices can be formed by patterning a first group of lines, the first group of lines including a first sacrificial material extending in a first lateral direction adjacent to (e.g., on, above, or vertically over) a substrate material to which one or more features are to be formed. In some embodiments, the first group of lines is formed by a pitch quadruple process or a spacer-assisted double patterning (SAPD) process, such that the lines in the first group exhibit desired dimensions and spacing that cannot be achieved by conventional photolithography processes. The spaces between the lines in the first group may be filled with a nitride material exhibiting etch selectivity relative to the first sacrificial material. A first dielectric antireflective coating (DARC) material is formed adjacent to (e.g., on, above, or vertically over) the first group of lines and the nitride material, and a second group of lines including a second sacrificial material is formed adjacent to (e.g., on, above, or vertically over) the first DARC material. In some embodiments, the lines in the second group are formed by a pitch doubling process. The lines in the second group may be oriented at an angle relative to one or more features (e.g., word line structures) extending in a second lateral direction to be formed on the microelectronic device, for example, at an angle ranging from about 30° to about 60°. In some embodiments, the angle is about 41°. In some embodiments, the lines in the second group are oriented at another angle relative to the lines in the first group, for example, from about 30° to about 60°.

[0033] Spacers, including oxide materials, may be formed on the lines in the second group of lines. A first etching process (e.g., a first shaving etching) may pattern a portion of the nitride material and the lines in the first group of lines. The first etching process may remove exposed portions of the first DARC material by means of oxide material, and selectively remove exposed portions of the nitride material, the lines in the second group of lines, and the exposed portions of the lines in the first group. A second etching process (e.g., a second shaving etching) may remove the portions of the first DARC material exposed by the first etching, and may selectively remove the exposed portions of the nitride material that are selective to the first sacrificial material and oxide material. After performing the second etching process, the remaining portions of the oxide material and the first DARC material may be removed (e.g., stripped) to expose the remaining portions of the first sacrificial material and the nitride material. An underlayer material may be formed adjacent to (e.g., on, above, or vertically over) the first sacrificial material and the nitride material, and the second DARC material may be patterned on the underlayer material by a so-called reverse spacing doubling process. The microelectronic device structure can be exposed to a third etching (e.g., a third dicing etching) process by removing portions of the second DARC material and exposed portions of the underlayer material and nitride material, selectively using the first sacrificial material. Removal of portions of the second DARC material and the underlayer material can form lines of the underlayer material extending at an angle relative to a first lateral direction. After removing the nitride material, the underlayer material can be removed, and the remaining portions of the nitride material and the first sacrificial material can be used as a mask to transfer their pattern into an etch-stopping material above the substrate material. The pattern can be transferred from the etch-stopping material to the substrate material to form a semiconductive pillar structure.

[0034] Figures 1A to 1X This is a simplified cross-sectional view. Figure 1A , Figure 1C , Figure 1E , Figure 1H , Figure 1J , Figure 1L , Figure 1N , Figure 1S , Figure 1T and Figures 1V to 1X ) and simplified top view ( Figure 1B , Figure 1D , Figure 1F , Figure 1G , Figure 1I , Figure 1K , Figure 1M , Figures 10 to 1R and Figure 1UThis document illustrates a method for forming a microelectronic device structure (e.g., a memory device structure, such as a DRAM device structure) for a microelectronic device (e.g., a memory device, such as a DRAM device) according to embodiments of the present disclosure. Those skilled in the art will appreciate, in conjunction with the description provided below, that the methods described herein can be used with respect to various devices. In other words, the methods of this disclosure can be used whenever it is desired to form a microelectronic device comprising a pillar structure.

[0035] See Figure 1A and Figure 1B The microelectronic device structure 100 may include a substrate material 102, an etch stop material 104 adjacent to (e.g., on, above, or vertically over) the substrate material 102, and a first line 106 adjacent to (e.g., on, above, or vertically over) the etch stop material 104 and a first sacrificial material 108. Figure 1A Is it through Figure 1B The cross-sectional view of the microelectronic device structure 100 is taken by the cross-section line AA.

[0036] The substrate material 102 may comprise a semiconductor substrate, a substrate semiconductor material on a supporting substrate, metal electrodes, or a semiconductor substrate on which one or more materials, structures, or regions are formed. The substrate material 102 may include a semiconducting material, such as a conventional silicon substrate or other bulk substrate containing semiconductor material. As used herein, the term "bulk substrate" refers to and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates or silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a substrate semiconductor, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si-Germanium). 1-x Ge x Where x is, for example, a mole fraction between 0.2 and 0.8, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when referred to as “substrate” or “base material” in the following description, previous process stages may have been used to form materials, regions, or junctions in the substrate semiconductor structure or base. The substrate material 102 may comprise one or more materials associated with integrated circuit manufacturing. Such materials may comprise, for example, one or more of refractory metals, barrier materials, diffusion materials, and insulating materials. The substrate material 102 may comprise, for example, a complementary metal-oxide-semiconductor (CMOS) structure or other semiconductor structures. Different portions of the substrate material 102 may be electrically isolated from each other by one or more dielectric materials.

[0037] The etch stop material 104 may be formed of and comprise one or more materials exhibiting etch selectivity to various mask materials (e.g., shredded masks), as will be described herein. By way of non-limiting examples, the etch stop material 104 may exhibit etch selectivity relative to various materials, such as sacrificial materials (e.g., amorphous carbon), dielectric materials (e.g., silicon dioxide, silicon nitride), dielectric antireflective coating (DARC) materials, and bottom antireflective coating (BARC) materials. The etch stop material 104 may be formed of and comprise one or more of metal nitrides (e.g., titanium nitride, tungsten nitride, tantalum nitride, aluminum nitride), metal oxides (e.g., aluminum oxide, titanium oxide, tungsten oxide, tantalum oxide, hafnium oxide, zirconium oxide), oxynitride materials, silicon oxycarbonate, silicon oxycarbonate, amorphous carbon, or another material. In some embodiments, the etch stop material 104 comprises titanium nitride.

[0038] The first sacrificial material 108 may be formed and comprise a material that exhibits etch selectivity relative to one or more oxide materials (e.g., silicon dioxide), one or more nitride materials (e.g., silicon nitride, titanium nitride), and one or more DARC materials. In some embodiments, the first sacrificial material 108 is formed and comprises amorphous silicon, such as hydrogenated amorphous silicon.

[0039] Each of the first lines 106 of the first sacrificial material 108 may have a substantially identical width W (e.g., a small lateral dimension) and may be regularly spaced apart by substantially the same distance D1. Therefore, the spacing d between the centerlines of adjacent first lines 106 may be substantially uniform throughout the first sacrificial material 108. The dimensions and spacing of the first lines 106 may be selected to provide the desired lateral dimensions and transverse spacing for features subsequently formed from the base material 102, as will be further described below.

[0040] In some embodiments, the width W of each line in the first line 106 may be in the range of about 10 nm to about 20 nm, for example, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not so limited, and the width W of the lines in the first line 106 may differ from those described above.

[0041] The distance D1 between adjacent lines in the first line 106 may be in the range of about 20 nm to about 40 nm, for example, from about 20 nm to about 25 nm, from about 25 nm to about 30 nm, from about 30 nm to about 35 nm, or from about 35 nm to about 40 nm. However, this disclosure is not so limited, and the distance D1 between adjacent lines in the first line 106 may differ from those described above.

[0042] The first line 106 can be formed through a so-called "spacing quadruple" process to create the desired width W and distance D1. In other embodiments, the first line 106 is formed through a spacer-assisted double patterning (SAPD) process. The first line 106 can be formed using conventional techniques. By means of a non-limiting example, a line of the first material (which may also be referred to as a "mandrel") can be formed adjacent to (e.g., on, above, or vertically over) an etch-stop material 104. A first spacer material can be formed on the line of the first material, and the line of the first material can be removed (e.g., peeled off, etched) to leave the first spacer. A second spacer material can be formed on the side of the first spacer, and the first spacer can be removed (e.g., peeled off, etched) to leave the pattern of the second spacer. The pattern of the second spacer can correspond to the first line 106 of the first sacrificial material 108.

[0043] See Figure 1C and Figure 1D Nitride material 110 may be formed in the space between the first sacrificial material 108 and the first line 106, and first DARC material 112 may be formed adjacent to (e.g., on, above, or vertically over) the nitride material 110 and the first line 106 of the first sacrificial material 108. Line 114 of second sacrificial material 116 may be formed adjacent to (e.g., on, above, or vertically over) the first DARC material 112, and oxide material 118 may be formed adjacent to (e.g., on the side) the line 114 of second sacrificial material 116. The line 114 of second sacrificial material 116 may be referred to herein as the "second line". Oxide material 118 may be configured adjacent to (e.g., on the side).

[0044] The spacer is positioned by the second line 114 of the second sacrificial material 116. The oxide material 118 may extend as a line 120 that is generally parallel to and generally extends together with the second line 114 of the second sacrificial material 116.

[0045] The nitride material 110 can be formed by one or more of CVD, ALD, PVD, LPCVD, PECVD, spin coating, blanket coating, or other methods. In some embodiments, after the nitride material 110 is formed, a portion of the nitride material 110 above the upper surface of the first line 106 of the first sacrificial material 108 can be removed. For example, the microelectronic device structure 100 can be exposed to a chemical mechanical planarization (CMP) process to remove a portion of the nitride material 110 from the upper surface of the first sacrificial material 108 such that the upper surface of the nitride material 110 is substantially coplanar with the upper surface of the first sacrificial material 108.

[0046] The nitride material 110 may be formed of and comprise a dielectric nitride, such as one or more of silicon nitride, aluminum nitride, oxide nitride, or another material. In some embodiments, the nitride material 110 comprises silicon nitride. In some embodiments, the nitride material 110 exhibits etch selectivity relative to the first sacrificial material 108 and the oxide material 118.

[0047] The first DARC material 112 may be formed of and contain silicon oxynitride material, such as Si. x O y N z Where x is between about 10 and about 60, y is between about 20 and about 50, and z is between about 10 and about 20. In some embodiments, the first DARC material 112 comprises silicon-rich silicon oxynitride. However, this disclosure is not so limited and the first DARC material 112 may comprise other suitable DARC materials known in the art. The first DARC material 112 may be formulated and configured to substantially prevent reflection of electromagnetic radiation (e.g., light sources) during patterning of various materials.

[0048] After the first DARC material 112 is formed, a second line 114 of the second sacrificial material 116 may be formed adjacent to (e.g., on, above, or vertically over) the first DARC material 112. In some embodiments, the second line 114 is formed by one or more of CVD, ALD, PVD, LPCVD, PECVD, spin coating, blanket coating, or other methods. By means of a non-limiting example, the second line 114 may be formed by a so-called “spacing doubling” process. In some such embodiments, lines of the first material may be patterned and the second sacrificial material 116 may be formed adjacent to (e.g., on the side) the lines of the first material. After the second sacrificial material 116 adjacent to the lines of the first material is formed, the lines of the first material may be removed.

[0049] The second sacrificial material 116 may be formed from and comprise one or more of the materials described above with reference to the first sacrificial material 108. In some embodiments, the second sacrificial material 116 comprises amorphous silicon. In some embodiments, the second sacrificial material 116 comprises the same material composition as the first sacrificial material 108.

[0050] After the second line 114 of the second sacrificial material 116 is formed, oxide material 118 may be formed on the side of the second line 114 of the second sacrificial material 116. The oxide material 118 may be formed by one or more of CVD, ALD, PVD, LPCVD, PECVD, spin coating, blanket coating or other methods.

[0051] The oxide material 118 may be formed and comprise an oxide material that exhibits etching selectivity relative to the second sacrificial material 116, the first sacrificial material 108, and the nitride material 110. For example, the oxide material 118 may be formed and comprise a dielectric material, such as silicon dioxide.

[0052] Reference Figure 1D The second line 114 of the second sacrificial material 116 may be formed at a first angle α relative to a first lateral direction (e.g., the Y direction) extending laterally from the first line 106 of the first sacrificial material 108 and at a second angle β relative to a second lateral direction (e.g., the X direction) extending laterally from one or more subsequently formed structures (e.g., access lines, such as word lines). The first angle α of the second line 114 and line 120 relative to the first lateral direction may be greater than about 0 degrees and less than about 90 degrees, for example, in the range of about 20 degrees to about 70 degrees, about 30 degrees to about 60 degrees, or about 40 degrees to about 50 degrees. The first angle α may be selected at least in part by the desired architecture of the microelectronic device structure 100 and the desired dimensions of the features to be formed from the substrate material 102, as will be described below. In some embodiments, the first angle α is about 49 degrees.

[0053] The second angle β between the second line 114 of the second sacrificial material 116 and the second transverse direction (e.g., the X direction) may be greater than about zero (0) degrees and less than about ninety (90) degrees, for example, within the range of about (20) degrees to about seventy (70) degrees, about thirty (30) degrees to about sixty (60) degrees, or about forty (40) degrees to about fifty (50) degrees. In some embodiments, the second angle β may be about forty-one (41) degrees. In some embodiments, the sum of the first angle α and the second angle β may be about ninety (90) degrees.

[0054] It should be understood that since the line 120 of the oxide material 118 and the second line 114 of the additional sacrificial material 116 generally extend together, the angle between the line 120 of the oxide material 118 and the first transverse direction can be the same as the first angle α, and the angle between the line 120 of the oxide material 118 and the second transverse direction can be the same as the second angle β.

[0055] Continue to refer to Figure 1D It should be understood that the first lines 106 of the first sacrificial material 108 will not be visible from the top view because they are located below the first DARC material 112. Therefore, Figure 1D The first line 106 is shown in dashed lines to illustrate that it is located below the first DARC material 112. It should be understood that the structure shown in dashed lines here is located below one or more materials.

[0056] Figure 1E Is it through Figure 1F The section line EE cuts Figure 1F A simplified cross-sectional view of the microelectronic device structure 100. (Reference) Figure 1E and Figure 1F The microelectronic device structure 100 may be exposed to a first removal process (e.g., an etching process, such as a first shredding etching process). For example, exposed portions of the first DARC material 112 may be removed (e.g., punched through) and exposed portions of the second sacrificial material 116, nitride material 110, and first sacrificial material 108 may be selectively removed from the oxide material 118 to form a first trench 122 through which the etch stop material 104 may be exposed. In other words, portions of the first DARC material 112, second sacrificial material 116, nitride material 110, and first sacrificial material 108 may be removed without substantially removing portions of the oxide material 118. In some embodiments, the height of the oxide material 118 may be selected (e.g., in the Z direction) such that the height of the oxide material 118 remains substantially the same after portions of the first DARC material 112, second sacrificial material 116, nitride material 110, and first sacrificial material 108 are removed. It will be understood that when a material is etched at a rate substantially greater than or about 2 to 3 times to at least about 40 times the etch rate of a neighboring material exposed to the same etchant, the material is considered to be selectively or preferentially etched.

[0057] By way of non-limiting examples, the microelectronic device structure 100 may be exposed to plasma comprising one or more of methane (CH4), trifluoromethane (CHF3) (also known as chloroform), difluoromethane (CH2F2), sulfur hexafluoride (SF6), or another material to remove portions of the first DARC material 112, the second sacrificial material 116, the nitride material 110, and the first sacrificial material 108 without substantially removing portions of the oxide material 118. Of course, this disclosure is not so limited and portions of the first DARC material 112, the second sacrificial material 116, the nitride material 110, and the first sacrificial material 108 may be removed by other etchants without substantially removing portions of the oxide material 118.

[0058] As described above, in some embodiments, removing portions of the first DARC material 112, the second sacrificial material 116, and the nitride material 110 may expose portions of the etch stop material 104. For example, the etch stop material 104 may be exposed at the lower portion of a first trench 122 that may extend generally parallel to line 120 of the oxide material 118.

[0059] Figure 1G Is it through Figure 1E The cross-section line GG cut Figure 1E A simplified top view of the microelectronic device structure is shown, illustrating a microelectronic device structure 100 without oxide material 118 or first DARC material 112. (See attached image.) Figure 1G As illustrated, a portion of the first sacrificial material 108 is removed through an opening in the first DARC material 112 to expose the etch stop material 104 and to separate (e.g., divide) the first line 106 of the first sacrificial material 108 into different isolated portions.

[0060] Now for reference Figure 1H and Figure 1I The microelectronic device structure 100 may be exposed to a second removal process (e.g., a second etching process, such as a second shredding etching process). Figure 1H Is it through Figure 1I The cross-section line HH intercepted Figure 1I A cross-sectional view of the microelectronic device structure 100. (Reference) Figure 1H and Figure 1I This allows for the removal of a portion of the first DARC material 112 (e.g., the portion of the first DARC material 112 exposed between oxide materials 118). This can be described in relation to the above. Figure 1E and Figure 1F The first DARC material 112 was removed in a substantially similar manner to the removal of a portion of the first DARC material 112. (Refer to...) Figure 1I The removal of a portion of the first DARC material 112 exposes a portion of the first sacrificial material 108 between adjacent lines 120 of the oxide material 118.

[0061] After removing the additional portion of the first DARC material 112, the exposed portion of the nitride material 110 can be selectively removed relative to the oxide material 118 and the first sacrificial material 108. By means of a non-limiting example, the exposed portion of the nitride material 110 can be exposed to a plasma comprising one or more of CH4, CHF3, CH2F2, SF6, or another material to selectively remove the exposed portion of the nitride material 110. Removing a portion of the nitride material 110 can expose the underlying portion of the etch stop material 104.

[0062] Removing a portion of the nitride material 110 can form a second trench 125 spaced from the first trench 122 by lines 120 of the oxide material 118. In some embodiments, the length (e.g., a major dimension) of the second trench 125 may be smaller than the corresponding length of the first trench 122. In other words, the second trench 125 may intersperse portions of the first sacrificial material 108 that remained and were not removed during the formation of the first trench 122. In some embodiments, the second trench 125 is positioned between the first lines 106 of the first sacrificial material 108 at a first angle α. Figure 1GAnd it extends at a second angle β relative to the second lateral direction (e.g., the X direction).

[0063] Reference Figures 1E to 1I In some embodiments, selective removal (e.g., a first removal process) of portions of the first DARC material 112, nitride material 110, second sacrificial material 116, and first sacrificial material 108 may be referenced. Figure 1H and Figure 1I The removal of additional portions of the first DARC material 112 and nitride material 110 (e.g., a second shredding etching) is performed separately. In some such embodiments, the microelectronic device structure 100 may be exposed to one or more cleaning processes between such removal processes. In other embodiments, the removal of additional portions of the first DARC material 112 and nitride material 110 may be performed in the same etching chamber as the selective removal of portions of the first DARC material 112, nitride material 110, second sacrificial material 116, and first sacrificial material 108, without the need for a cleaning process between removal processes. Additionally, although... Figures 1E to 1I The first etching process has been described and shown to be performed prior to the second etching process, but this disclosure is not so limited. In other embodiments, reference is made to... Figure 1H and Figure 1I Additional portions of the first DARC material 112 and nitride material 110 described herein may be found in reference to [reference needed]. Figure 1E and Figure 1F The first DARC material 112, nitride material 110, second sacrificial material 116, and first sacrificial material 108 are removed before removal.

[0064] See Figure 1J and Figure 1K Oxide material 118 and DARC material 112 can be removed from the surface of the microelectronic device structure 100 to expose additional portions of nitride material 110 and first sacrificial material 108. In some embodiments, oxide material 118 is removed by exposing the microelectronic device structure 100 to a wet etching process, such as hydrofluoric acid, nitric acid, ammonium fluoride (a mixture of ammonium fluoride and hydrofluoric acid), or one or more of another material. In some embodiments, oxide material 118 is removed by exposing the microelectronic device structure 100 to a mixture of hydrofluoric acid and ammonium fluoride.

[0065] Figure 1L and Figure 1M This describes the microelectronic device structure 100 after the formation of a mask 124 adjacent to (e.g., on, above, or vertically over) the nitride material 110 and the first sacrificial material 108. Figure 1L Is it through Figure 1M The section line LL intercepts Figure 1MA cross-sectional view of the microelectronic device structure 100.

[0066] Mask 124 may include an underlayer material 126 adjacent to (e.g., on, above, or vertically over) the nitride material 110 and the first sacrificial material 108, and a second DARC material 128 adjacent to (e.g., on, above, or vertically over) the underlayer material 126. Mask 124 may be used to perform a third etching process (e.g., a third dicing etching process) on the microelectronic device structure 100.

[0067] The underlayer material 126 can fill the space between adjacent portions of the nitride material 110 and the first sacrificial material 108, and can contact the etching stop material 104 at the lower portions of the first trench 122 and the second trench 125. After the underlayer material 126 is formed, the microelectronic device structure 100 can be exposed to a planarization process, such as CMP, to substantially planarize the upper surface of the underlayer material 126.

[0068] The underlayer material 126 may be formed of and contain organic materials, such as one or more of a bottom antireflective coating (BARC) material, an extreme ultraviolet (EUV) underlayer material, a polymeric material, or another material. In some embodiments, the underlayer material 126 includes a BARC material.

[0069] The second DARC material 128 may be formed from and comprise one or more of the materials described above with reference to the first DARC material 112. In some embodiments, the second DARC material 128 comprises the same material composition as the first DARC material 112. The second DARC material 128 may be formulated and configured to exhibit etch selectivity relative to each of the etch stop material 104, the first sacrificial material 108, and the nitride material 110.

[0070] The second DARC material 128 can be patterned using conventional techniques to include an opening 130. Figure 1L With the aid of a non-limiting example, the second DARC material 128 can be patterned via a so-called “reverse self-aligned double patterning” (also known as “reverse spacing doubling”) process. In some embodiments, the second DARC material 128 may be formed and patterned to include recesses corresponding to the locations of the openings 130. The recesses may be removed (e.g., punched through) to expose the underlying material 126 and form lines 132 of the second DARC material 128 spaced apart by the openings 130.

[0071] For the sake of clarity and ease of understanding of this disclosure, Figure 1M The underlying material 126 is not shown in the top view. It should be understood that... Figure 1MThe material shown between lines 132 of the additional DARC material 128 (i.e., within opening 130) is vertically positioned below the underlying material 126.

[0072] The line 132 of the second DARC material 128 may extend at a third angle θ relative to one or more subsequently formed structures (e.g., access lines, such as word lines) in a first lateral direction (e.g., the X direction) in which they may extend laterally. In some embodiments, the third angle θ of the line 132 of the second DARC material 128 is greater than about 0 (0) degrees and less than about 90 (90) degrees relative to the first lateral direction, for example, in the range of about 20 (20) degrees to about 70 (70) degrees, about 30 (30) degrees to about 60 (60) degrees, or about 40 (40) degrees to about 50 (50) degrees. The third angle θ may be selected at least in part based on the desired architecture of the microelectronic device structure 100 and the desired dimensions of the features to be formed from the substrate material 102, as will be described below.

[0073] In some embodiments, the third angle θ is in the opposite direction to the first angle α relative to the first lateral direction. In other words, in some embodiments, the first angle α is in one of a clockwise and a counterclockwise direction relative to the first lateral direction, and the third angle θ is in the other of a clockwise and a counterclockwise direction relative to the first lateral direction. In some such embodiments, the angle between the line 132 of the second DARC material 128 and the first groove 122 may be equal to the difference between 180 degrees and the sum of the second angle β and the third angle θ (e.g., 180-β-θ). In some embodiments, the angle between the line 132 and the first groove 122 may be approximately 98 degrees.

[0074] In some embodiments, the third angle θ is approximately equal to the first angle α, wherein the line 132 of the second DARC material 128 is oriented at the third angle θ relative to the first transverse direction in one of the clockwise and counterclockwise directions, and the first groove 122 is oriented at the first angle α relative to the first transverse direction in the other of the clockwise and counterclockwise directions. Therefore, Figure 1M The first angle α and the third angle θ shown in the figure can be approximately the same.

[0075] For reference Figure 1N and Figure 10 After forming line 132 of the second DARC material 128, opening 130 ( Figure 1L , Figure 1MThe material can be transferred to the underlayer 126 to expose portions of the nitride material 110 and the first sacrificial material 108. The nitride material 110 can be selectively removed relative to the first sacrificial material 108 and the etch stop material 104. In some embodiments, the nitride material 110 can be selectively removed relative to the first sacrificial material 108 and the etch stop material 104 by exposing the microelectronic device structure 100 to phosphoric acid. However, this disclosure is not so limited and the nitride material 110 can be selectively removed by other methods.

[0076] The removal of nitride material 110 relative to the first sacrificial material 108 and the etch stop material 104 can form a third trench 135 between adjacent lines 132 of the second DARC material 128, which extend along the microelectronic device structure 100 in the same direction as the lines 132 of the second DARC material 128. In other words, the third trench 135 can be oriented at a third angle θ relative to a second lateral direction (e.g., the X direction).

[0077] For reference Figure 1P In the second DARC material 128 ( Figure 1N , Figure 10 Opening 130 in ) Figure 1L , Figure 1M )Removal of nitride material 110 ( Figure 1N After that, the mask 124 containing the second DARC material 128 and the underlying material 126 can be removed. Figure 1N This leaves the patterned first sacrificial material 108 and nitride material 110 adjacent to (e.g., on, above, or vertically over) the etching stop material 104. By means of non-limiting examples, one or more of, such as hydrofluoric acid, ammonium fluoride, amines (e.g., organic amines, such as ethyleneamine, trimethylhydroxyethyl ethylenediamine (TMAEEA), trimethylhydroxypropyl ethylenediamine (TMAPEA)), or another material, can be used to remove the second DARC material 128 and the underlayer material 126.

[0078] Removing the nitride material 110 can form a pillar structure 140 (e.g., an elongated pillar structure) comprising a portion of the first sacrificial material 108 and a portion of the nitride material 110. In some embodiments, the pillar structure 140 may exhibit an "S" shape. The pillar structure 140 may each individually include a central portion 142 comprising the first sacrificial material 108 and an end portion 144 comprising the nitride material 110. The end portion 144 may also be referred to herein as the "top portion".

[0079] Each of the column structures 140 may individually include an end portion 144 at a first end (e.g., a first longitudinal end) of the central portion 142 and an additional end portion 144 at a second end (e.g., a second longitudinal end) of the central portion 142.

[0080] The end portion 144 may include a longitudinal axis L2 relative to the central portion 142. Figure 1Q The longitudinal axis L1 extending at the first angle α Figure 1Q The longitudinal axis L2 of the central portion 142 may extend in a first lateral direction (e.g., the Y direction).

[0081] See Figure 1Q Column structure 140 ( Figure 1P The etch stop material 104 can be used as a mask to transfer the pattern of the pillar structure 140 onto the etch stop material 104 and subsequently onto the substrate material 102. For example, the microelectronic device structure 100 may be exposed to one or more etchants formulated and configured to selectively remove the etch stop material 104 without substantially removing the first sacrificial material 108 or the nitride material 110. By way of non-limiting examples, the etch stop material 104 may be exposed to one or more of ammonium hydroxide, hydrogen peroxide, or another material. However, this disclosure is not so limited and the etch stop material 104 may be removed by methods other than those described above.

[0082] The patterned etch-stop material 104 can be used to transfer the pattern of the pillar structure 140 onto the substrate material 102 to form isolated semiconducting pillar structures 150 (e.g., elongated semiconducting pillar structures), each individually including a central portion 142 and an end portion 144, as referenced above in the pillar structure 140. Figure 1P As described in ), therefore, in the column structure 140 ( Figure 1P After the pattern is transferred to the etch stop material 104, the patterned etch stop material 104 can be used to transfer the pattern to the underlying substrate material 102 to form a semiconducting pillar structure 150. The semiconducting pillar structure 150 may include rounded edges and correspond to the functional area of ​​the microelectronic device structure 100. By means of a non-limiting example, a portion of the substrate material 102 exposed by the patterned etch stop material 104 can be removed (e.g., partially removed) to form a pattern of the semiconducting pillar structure 150 separated by trenches (e.g., first trench 122, second trench 125, and third trench 135).

[0083] The semiconducting pillar structure 150 may exhibit an elongated shape, with its length (e.g., along the longitudinal axis of the central portion 142 and the longitudinal axis of the end portion 144) greater than the width of the semiconducting pillar structure 150 in a direction substantially perpendicular to said length. The semiconducting pillar structure 150 may include curved (e.g., bow-shaped) sides. The orientation of the semiconducting pillar structure 150 may be non-linear, because the end portion 144 is angled relative to the central portion 142.

[0084] Adjacent semiconducting pillar structures 150 may be spaced apart from each other by a first trench 122 and a second trench 125 oriented at a first angle α relative to the longitudinal axis L2 of the central portion 142. In some embodiments, the first trench 122 may extend substantially along the microelectronic device structure 100 without intersecting the semiconducting pillar structure 150, and the second trench 125 may be interspersed with the central portion of the semiconducting pillar structure 150. In other words, the second trench 125 may be located between the central portions 142 of the semiconducting pillar structures 150. Additionally, the semiconducting pillar structures 150 may be separated from each other by a third trench 135 extending at a third angle θ relative to a second lateral direction (e.g., the X direction). The third trench 135 may intersect the first trench 122 and may separate the central portions 142 of adjacent semiconducting pillar structures 150 from each other. In some embodiments, the first trench 122, the second trench 125, and the third trench 135 are filled with a dielectric material.

[0085] In some embodiments, the first trench 122 may separate the end portions 144 of the semiconducting pillar structures 150 from each other. For example, the upper portion 144 of the first semiconducting pillar structure 150 may be spaced apart from the lower portion 144 of a laterally adjacent second semiconducting pillar structure 150 via the first trench 122. Additionally, the upper portion 144 of the first semiconducting pillar structure 150 may be separated from the lower portion 144 of a laterally adjacent third semiconducting pillar structure 150 via the second trench 125. Similarly, the lower portion 144 of the first semiconducting pillar structure 150 may be spaced apart from the upper portion 144 of a laterally adjacent fourth semiconducting pillar structure 150 via another trench in the first trench 122, and spaced apart from the upper portion 144 of a laterally adjacent fifth semiconducting pillar structure 150 via another trench in the second trench 125.

[0086] Continue to refer to Figure 1Q Each of the semiconductor pillar structures 150 may include a digital line (e.g., bit line) contact area and a memory node (e.g., memory cell) contact area 162. Although the digital line contact area 160 and the memory node contact area 162 are in... Figure 1QThe diagram shows that the digital line contact area 160 and the memory node contact area 162 have the same lateral dimensions as the semiconducting pillar structure 150, but it should be understood that the lateral dimensions of the digital line contact area 160 and the memory node contact area 162 may be smaller than the lateral dimensions of the semiconducting pillar structure 150.

[0087] Storage node contact area 162 may be located on the end portion 144 of the semiconducting pillar structure 150 (e.g., above). Digital line contact area 160 may be located on the central portion 142 of the semiconducting pillar structure 150 (e.g., above). In some embodiments, the digital line contact area 160 of the first semiconducting pillar structure is laterally aligned with the storage node contact areas 162 adjacent to the second and third semiconducting pillar structures 150.

[0088] Continue to refer to Figure 1Q The distance D2 (corresponding to the length of the central portion 142 of the semiconducting pillar structure 150) may be in the range of about 20 nm to about 40 nm, for example, from about 20 nm to about 25 nm, from about 25 nm to about 30 nm, from about 30 nm to about 35 nm, or from about 35 nm to about 40 nm. However, this disclosure is not so limited and the distance D2 may differ from those described.

[0089] The distance D3 between the end portion 144 of the first semiconducting pillar structure 150 and the adjacent central portion 142 of the second semiconducting pillar structure 150 (e.g., the distance between the memory node contact region 162 and the bit line contact region 160 of the first semiconducting pillar structure 150) may be in the range of about 10 nm to about 20 nm, for example, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not so limited and the distance D3 may differ from those described.

[0090] The distance D4 between the end portion 144 of the semiconducting pillar structure 150 and the central portion 142 of the adjacent semiconducting pillar structure 150 can be in the range of about 5 nm to about 20 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not so limited and the distance D4 may differ from those described.

[0091] The distance D5 between opposite sides of the central portion 142 may be in the range of about 5 nm to about 15 nm, for example, from about 5 nm to about 10 nm, or from about 10 nm to about 15 nm. However, this disclosure is not so limited and the distance D5 may differ from those described.

[0092] The distance D6 between the upper portion 144 of the semiconducting pillar structure 150 and the lower portion 144 of the semiconducting pillar structure 150, which is vertically adjacent to it in a direction substantially parallel to the longitudinal axis L4 of the central portion 142, can be in the range of about 10 nm to about 30 nm, for example, from about 10 nm to about 15 nm, from about 15 nm to about 20 nm, from about 20 nm to about 25 nm, or from about 25 nm to about 30 nm. In some embodiments, the distance D6 is about 26 nm. However, this disclosure is not so limited and the distance D6 may differ from those described.

[0093] The distance D7 between the upper portion 144 of the semiconducting pillar structure 150 and the adjacent lower portion 144 of the semiconducting pillar structure 150 in a direction perpendicular to the sides of the upper and lower portions 144 can be in the range of about 5 nm and about 20 nm, for example, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not so limited and the distance D7 may differ from those described.

[0094] The distance D9 between the opposing sidewalls of the end portion 144 may be in the range of about 5 nm to about 15 nm, for example, from about 5 nm to about 10 nm, or from about 10 nm to about 15 nm. In some embodiments, the distance D9 is substantially the same as the distance D5.

[0095] After the formation of the semiconducting pillar structure 150, the microelectronic device structure 100 may undergo additional processing. In some embodiments, the microelectronic device structure 100 may be exposed to one or more ion implantation processes to form so-called source, drain, and channel regions of a transistor structure at least partially formed by the semiconducting pillar structure 150. In some embodiments, the semiconducting pillar structure 150 is exposed to ion implantation to dope at least the upper portion of the patterned substrate material 102'.

[0096] See Figure 1R , Figure 1S and Figure 1T The word line 164 can be formed in the isolation trench between the storage node contact area 162 and the digital line contact area 160. Figure 1R This is a top view of the microelectronic device structure 100 after it has undergone additional processing. Figure 1S Is it through Figure 1R The section line SS cuts Figure 1R A simplified cross-sectional view of the microelectronic device structure 100, and Figure 1T Is it through Figure 1R The section line TT cuts Figure 1R A simplified cross-sectional view of the microelectronic device structure 100.

[0097] Reference Figure 1R and Figure 1S Insulation material 180 ( Figure 1R (For clarity and ease of understanding, not shown) may be formed above the microelectronic device structure 100 and may fill the area between adjacent semiconducting pillar structures 150 (e.g., first trench 122, second trench 125, and third trench 135). The insulating material 180 may be formed of and contain a dielectric material. In some embodiments, the insulating material 180 comprises silicon dioxide.

[0098] After the insulating material 180 is formed, portions of the insulating material 180 and the semiconducting pillar structure 150 between the central portion 142 and the end portion 144 can be removed. For example, a mask material can be formed over the microelectronic device structure 100 with openings (e.g., trenches) extending in a first lateral direction (e.g., the X direction), and portions of the insulating material 180 and the semiconducting pillar structure 150 can be removed through the openings in the mask material.

[0099] In some embodiments, after the opening is formed, the exposed portion of the patterned substrate material 102' may be exposed to the ion implantation process to form the channel region 181 of the transistor structure. A dielectric material 182 (e.g., a gate dielectric material) may be formed within the opening and a conductive material 184 may be formed over the dielectric material 182 to form a word line 164. The dielectric material 182 may be formed from one or more of the following: phosphosilicate glass, borosilicate glass, borosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride material (e.g., silicon nitride (Si3N4)), oxynitride (e.g., silicon oxynitride), another gate dielectric material, dielectric carbon nitride material (e.g., silicon carbon nitride (SiCN)), dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiOCN)), or combinations thereof.

[0100] The conductive material 184 may be formed from one or more of the following and includes one or more of the following: titanium nitride, tantalum nitride, aluminum titanium nitride, elemental titanium, elemental platinum, elemental rhodium, elemental iridium, iridium oxide, elemental ruthenium, elemental ruthenium oxide, elemental molybdenum, elemental tungsten, elemental cobalt, polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, the conductive material 184 includes one or more of elemental molybdenum, elemental tungsten, and elemental cobalt, and one or more of polycrystalline silicon, germanium, and silicon-germanium.

[0101] In some embodiments, and with reference to Figure 1RThe word line 164 can separate the central portion 142 from the end portion 144. In other words, in some embodiments, the word line 164 can be inserted between the central portion 142 and the end portion 144. Therefore, the word line 164 can be located in an isolation trench (e.g., containing insulating material 180) that contains the word line 164 and separates the digital line contact area 160 from the storage node contact area 162 of each of the semiconducting pillar structures 150. Thus, each of the semiconducting pillar structures 150 as described herein may include a central portion 142 spaced apart from the end portions 144 (e.g., first end portion 144 and second end portion 144) by the word line 164 (e.g., first word line 164 and second word line 164). After the word line 164 is formed, the remaining portion of the opening may be filled with an insulating material 186, which may comprise one or more of the materials described above with reference to insulating material 180. In some embodiments, the insulating material 186 comprises the same material composition as insulating material 180.

[0102] Reference Figure 1S and Figure 1T After the word line 164 is formed, an opening 185 may be formed through portions of insulating material 186 and insulating material 180 to expose the surface of the digital line contact area 160 of the semiconducting pillar structure 150. The opening 185 may be formed, for example, by forming and patterning a mask over the microelectronic device structure 100 and exposing the microelectronic device structure 100 to a suitable etchant.

[0103] For reference Figure 1U , Figure 1V and Figure 1W The microelectronic device structure 100 can be subjected to additional processing to form the microelectronic device 190. Figure 1U This is a top view of the microelectronic device 190. Figure 1V Is it through Figure 1U A cross-sectional view taken by the cross-section line VV; and Figure 1W Is it through Figure 1U The cross-sectional view taken by the WW section line. (Refer to...) Figure 1U to Figure 1WA digital line contact 160' may be formed within the opening 185 and on the digital line contact area 160. The digital line contact 160' may be formed of and comprise at least one conductive material. In some embodiments, the digital line contact 160' comprises one or more of the following: titanium nitride, tantalum nitride, aluminum titanium nitride, elemental titanium, elemental platinum, elemental rhodium, elemental iridium, iridium oxide, elemental ruthenium, elemental ruthenium oxide, elemental molybdenum, elemental tungsten, elemental cobalt, polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, the digital line contact 160' comprises one or more of elemental molybdenum, elemental tungsten, and elemental cobalt, and one or more of polycrystalline silicon, germanium, and silicon-germanium. In some embodiments, the digital line contact 160' comprises doped polycrystalline silicon. By way of a non-limiting example, the digital line contact 160' may comprise at least about 10 20 atoms / cm 3 , or even at least about 10 21 atoms / cm 3 .

[0104] In some embodiments, the digital line contact 160' is recessed within the opening 185. Figure 1T After forming the digital line contact 160', conductive material 188 may be formed above the microelectronic device structure 100 and in contact with the digital line contact 160' to form a digital line 166. The conductive material 188 of the digital line 166 may be formed from and include one or more of the materials described above with reference to the word line 164.

[0105] After forming the digital line contact 160' and the digital line 166, an insulating material 192 may be formed over the digital line 166. In some embodiments, a spacer 165 (e.g., a "bit line spacer", "digital line spacer") may be formed on the side of the digital line 166. The insulating material 192 and the spacer 165 may be individually formed of and comprise one or more of the materials described above with reference to insulating materials 180 and 186. In some embodiments, the digital line 166 does not completely fill the opening 185 ( Figure 1T ), and the spacer 165 may be located on the side of the digital line 166 within the opening 185.

[0106] The width of the spacer 165 (e.g., in a direction generally perpendicular to the longitudinal axis L4 of the digital line 166, e.g., the X direction) may be in the range of about 5 nm to about 20 nm, such as from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. However, this disclosure is not so limited and the width may differ from those described.

[0107] Reference Figure 1XStorage node contact 162' may be formed above storage node contact area 162 of semiconducting pillar structure 150. Storage node contact 162' may be formed of and comprise one or more of the materials described above with reference to digital line contact 160'.

[0108] Storage node contact 162' may be electrically connected to storage node contact region 162 of semiconducting pillar structure 140. Storage node contact 162' may be located between adjacent portions of insulating material 186 and insulating material 192. Storage node contact 162' may be formed of and comprise one or more of the materials described above with reference to digital line contact 160'. In some embodiments, storage node contact 162' comprises doped polysilicon. By way of a non-limiting example, storage node contact 162' may comprise at least about 10 20 atoms / cm 3 , or even at least about 10 21 atoms / cm 3 In some embodiments, the microelectronic device structure 190 is exposed to annealing conditions to diffuse dopant from digital line contacts 160' and memory node contacts 162' to form source, drain, and channel regions 181, for example, transistor structures.

[0109] Continue to refer to Figure 1U to Figure 1X In some embodiments, the digital line contact 160' may be aligned in the Y direction and may be offset from the storage node contact 162' in the X direction. In some embodiments, the digital line contact 160' may not be aligned with any of the storage node contacts 162' in the direction in which the digital line 166 extends. Additionally, the storage node contacts 162' may be aligned with each other in the Y direction.

[0110] The microelectronic device 190 may include memory cells, each of which includes an access transistor (e.g., a transistor with a gate along word line 164) coupled to a memory node structure 194 (e.g., a capacitor structure). Figure 1X The diagram shows only one storage node structure 194, but it should be understood that all storage node contacts 162' can be coupled to storage node structure 194.

[0111] Continue to refer to Figure 1X The storage node structure 194 may be formed above and electrically connected to the storage node contact 162'. For the sake of clarity and ease of understanding of this disclosure, Figure 1U The storage node structure is not shown in Figure 194.

[0112] In some embodiments, a re-fabricated material (RDM) structure 196 (also referred to as a "re-fabricated layer (RDL) structure") may be formed on or above the storage node contact 162', and the storage node structure 194 may be electrically connected to the storage node structure 194 and the storage node contact 162'.

[0113] RDM structure 196 can be configured to effectively shift (e.g., interleave, adjust, modify) the lateral position (e.g., in the X direction, in the Y direction) of memory node contact 162′ to accommodate a desired arrangement (e.g., close-packed hexagonal arrangement) of memory node structure 194 above and electrically connected to memory node contact 162′. RDM structure 196 can each be individually formed of and contain conductive materials, including but not limited to metals (e.g., tungsten, titanium, nickel, platinum, gold), metal alloys, metal-containing materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), and conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium). By way of non-limiting examples, RDM structure 196 can individually include W, TiN, TaN, WN, TiAlN, Ti, Pt, Rh, Ir, IrO. x 、Ru、RuO x One or more of its alloys.

[0114] Storage node structure 194 may be configured to store charges representing programmable logic states. For example, a charged state of storage node structure 194 may represent a first logic state (e.g., logic 1), and a de-charged state of storage node structure 170 may represent a second logic state (e.g., logic 0). In some embodiments, storage node structure 194 includes a dielectric material configured to store charges associated with logic states. The dielectric material may include, for example, one or more of the following: silicon dioxide, silicon nitride, polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium dioxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (e.g., ferroelectric hafnium dioxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT), etc.), and high-k dielectric materials. In some embodiments, the storage node structure 170 includes zirconium oxide.

[0115] The RDM structure 196 and the storage node structure 194 can be formed using conventional processes (e.g., conventional deposition processes such as in-situ growth, spin coating, blanket coating, CVD, ALD and PVD; conventional patterning and material removal processes such as conventional alignment, conventional photolithography, conventional development and etching) and conventional processing equipment that are not described in detail herein.

[0116] Return to reference Figure 1U to Figure 1X In an additional embodiment, by modifying oxide material 118 ( Figure 1C , Figure 1D ) and corresponding first groove 122 ( Figure 1E , Figure 1F The first angle α and the second groove 125 () Figure 1H , Figure 1I The second angle β and the second DARC material 128 () Figure 1J , Figure 1M ) line 132 ( Figure 1J , Figure 1M The microelectronic device 190 is formed to exhibit different lateral geometric configurations (e.g., different lateral shapes, different lateral dimensions) of the semiconducting pillar structure 150, in one or more of the third angles θ.

[0117] Compared to conventional microelectronic devices, forming the semiconducting pillar structure 150 to include a central portion 142 and an end portion 144 extending relative to the central portion 142 at a first angle α promotes an increase in the effective area for the digital line contacts 160' on the central portion 142. Additionally, compared to conventional microelectronic device structures, the size and shape of the semiconducting pillar structure 150 promote an increase in the landing area for the storage node contacts 162' from the lateral edge of the spacer 165 (e.g., from about 4 nm to about 5 nm more). Furthermore, the spacing of the semiconducting pillar structure 150 promotes an increase in the width of the spacer 165 (e.g., in the X direction), which promotes a reduction in capacitive coupling of the digital lines 166 compared to conventional microelectronic devices.

[0118] Therefore, according to embodiments of this disclosure, a microelectronic device includes a semiconducting pillar structure, each of the semiconducting pillar structures individually including a digital line contact area laterally disposed between two memory node contact areas. At least one semiconducting pillar structure includes: a first end portion including a first memory node contact area, a second end portion including a second memory node contact area, and an intermediate portion between the first end portion and the second end portion and including the digital line contact area, wherein the longitudinal axis of the first end portion is oriented at an angle relative to the longitudinal axis of the intermediate portion.

[0119] Therefore, according to an additional embodiment of the present disclosure, a method of forming a microelectronic device includes: forming a pattern of a first line of a first sacrificial material over a substrate material and forming a nitride material in the space between adjacent first lines; forming a second line of a second sacrificial material over the first lines, the second line of the second sacrificial material being oriented relative to the first lines at a first angle in the range of about 30° to about 60°; forming an oxide material on the side of the second line; selectively removing portions of each of the first sacrificial material, the second sacrificial material, and the nitride material relative to the oxide material; forming a pattern of a third line including an underlayer material over the remaining portion of the first sacrificial material, the third line being oriented relative to the remaining portion of the first line at a second angle; and removing portions of the nitride material selectively chosen for the first sacrificial material through the pattern of the third line to form a pattern of pillar structures.

[0120] Therefore, according to other embodiments of this disclosure, a method of forming a microelectronic device includes: forming a first line including silicon in a first direction; forming a nitride material between the first lines; forming a second line including silicon in a second direction at a first angle relative to the first direction; forming spacers on the second lines; removing portions of the first lines and portions of the nitride material through the space between the spacers; forming lines of a mask extending at a second angle relative to the first direction; removing portions of the nitride material between the lines of the mask; and removing portions of the semiconductive material adjacent to the remaining portions of the first lines and the nitride material to form a semiconductive pillar structure.

[0121] Microelectronic devices comprising microelectronic devices (e.g., microelectronic device 190) and microelectronic device structures (e.g., microelectronic device structure 100) formed according to embodiments described herein may be used in embodiments of the electronic systems disclosed herein. For example, Figure 2 This is a block diagram of an electronic system 203 according to an embodiment of the present disclosure. The electronic system 203 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 203 includes at least one memory device 205. Memory device 205 may include, for example, the microelectronic device architecture previously described herein (e.g., microelectronic device architecture 100) or previously referenced... Figures 1A to 1T An embodiment of the microelectronic device described (e.g., microelectronic device 100).

[0122] The electronic system 203 may further include at least one electronic signal processor device 207 (often referred to as a “microprocessor”). The electronic signal processor device 207 may optionally include the microelectronic devices or microelectronic device structures previously described herein (e.g., previously referenced...). Figures 1A to 1T Embodiments of the described microelectronic device 190 or one or more of the microelectronic device architecture 100. The electronic system 203 may further include one or more input devices 209 for inputting information into the electronic system 203 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 203 may further include one or more output devices 211 for outputting information to the user (e.g., visual or audio output), such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 209 and output device 211 may include a single touchscreen device, which can be used to input information into the electronic system 203 and output visual information to the user. The input device 209 and output device 211 may be in electrical communication with one or more of the memory device 205 and the electronic signal processor device 207.

[0123] Reference Figure 3 The present invention describes a processor-based system 300. The processor-based system 300 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., including one or more of microelectronic devices and microelectronic device structures 190 or 100). The processor-based system 300 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 300 may include one or more processors 302 (e.g., microprocessors) to control system functions and request processing within the processor-based system 300. The processor 302 and other sub-components of the processor-based system 300 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., including one or more of microelectronic devices 190 or 100).

[0124] The processor-based system 300 may include a power supply 304 operatively connected to the processor 302. For example, if the processor-based system 300 is a portable system, the power supply 304 may include one or more of a fuel cell, an energy purification device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 304 may also include an AC adapter; thus, the processor-based system 300 can be plugged into a wall outlet. For example, the power supply 304 may also include a DC adapter, allowing the processor-based system 300 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0125] Various other devices may be coupled to processor 302 depending on the functions performed by processor-based system 300. For example, user interface 306 may be coupled to processor 302. User interface 306 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 308 may also be coupled to processor 302. Display 308 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 310 may also be coupled to processor 302. RF subsystem / baseband processor 310 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 312 or more may also be coupled to processor 302. The communication port 312 may be adapted to be coupled to one or more peripheral devices 314, such as a modem, printer, computer, scanner or camera, or coupled to a network, such as a local area network, remote local area network, intranet or Internet.

[0126] Processor 302 can control processor-based system 300 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 302 to store and facilitate the execution of various programs. For example, processor 302 may be coupled to system memory 316, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. System memory 316 may include volatile memory, non-volatile memory, or combinations thereof. System memory 316 is typically large enough to dynamically store loaded application programs and data. In some embodiments, system memory 316 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 190 and microelectronic device structure 100), or combinations thereof.

[0127] Processor 302 may also be coupled to non-volatile memory 318, which does not imply that system memory 316 is necessarily volatile. Non-volatile memory 318 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 316. The size of non-volatile memory 318 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Furthermore, for example, non-volatile memory 318 may include large-capacity memory such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 318 may include microelectronic devices, such as the microelectronic devices and microelectronic device architectures described above (e.g., microelectronic device 190 and microelectronic device architecture 100), or combinations thereof.

[0128] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input and output devices, and a memory device operatively coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes semiconducting pillar structures spaced apart from each other. At least one of the semiconducting pillar structures includes a central portion between a first end portion and a second end portion, and a first memory node contact electrically connected to the first end portion and a second memory node contact electrically connected to the second end portion. The at least one microelectronic device also includes a digital line electrically connected to the central portion, the digital line being oriented at an angle from about 30° to about 60° relative to the first and second end portions.

[0129] Additional non-limiting example embodiments of this disclosure are described below.

[0130] Example 1: A microelectronic device comprising: a semiconducting pillar structure, each individually including a digital line contact area laterally disposed between two memory node contact areas, at least one of the semiconducting pillar structures comprising: a first end portion including a first memory node contact area; a second end portion including a second memory node contact area; and an intermediate portion between the first end portion and the second end portion and including the digital line contact area, wherein the longitudinal axis of the first end portion is oriented at an angle relative to the longitudinal axis of the intermediate portion.

[0131] Example 2: The microelectronic device according to Example 1, wherein the longitudinal axis of the second end portion is oriented at an angle relative to the longitudinal axis of the middle portion.

[0132] Example 3: The microelectronic device according to Example 1 or Example 2, wherein the longitudinal axis of the first end portion is substantially parallel to the longitudinal axis of the second end portion.

[0133] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the angle is in the range of about 30° to about 60°.

[0134] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the angle is in the range of about 40° to about 50°.

[0135] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the first memory node contact area is offset longitudinally and laterally from the second memory node contact area.

[0136] Example 7: The microelectronic device according to any one of Examples 1 to 6 further includes: a storage node contact at the two storage node contact areas of each of the semiconducting pillar structures; a digital line contact at the digital line contact area of ​​each of the semiconducting pillar structures; a digital line individually electrically connected to the digital line contact of each of the semiconducting pillar structures; a word line extending laterally in a direction different from the digital line, the word line spacing out the middle portion from each of the first end portion and the second end portion; and a storage node structure individually electrically connected to the storage node contact and located near the intersection of the digital line and the word line.

[0137] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the digital line contact area of ​​the first semiconducting pillar structure is laterally adjacent to the storage node contact area of ​​the second semiconducting pillar structure.

[0138] Example 9: The microelectronic device according to any of Example 8, wherein the digital line contact area of ​​the first semiconducting pillar is laterally located between the storage node contact area of ​​the second semiconducting pillar and the storage node contact area of ​​the third semiconducting pillar.

[0139] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein the middle portion of each half of the conductive pillar structure is laterally aligned with the digital line.

[0140] Example 11: A method of forming a microelectronic device, the method comprising: forming a pattern of a first line of a first sacrificial material over a substrate material and forming a nitride material in the space between adjacent first lines; forming a second line of a second sacrificial material over the first lines, the second line of the second sacrificial material being oriented relative to the first lines at a first angle in the range of about 30° to about 60°; forming an oxide material on the side surface of the second line; selectively removing portions of each of the first sacrificial material, the second sacrificial material, and the nitride material relative to the oxide material; forming a pattern of a third line including an underlayer material over the remaining portion of the first sacrificial material, the pattern of the third line being oriented relative to the remaining portion of the first line at a second angle; and removing portions of the nitride material selectively attached to the first sacrificial material through the pattern of the third line to form a columnar structure pattern.

[0141] Example 12: The method according to Example 11 further includes transferring the pattern of the pillar structure onto the substrate material to form a pattern of the semiconductive pillar structure.

[0142] Example 13: According to the method of Example 12, the pattern of forming the semiconducting pillar structure includes forming a pattern of semiconducting pillar structures each including a digital line contact area at its central portion, the digital line contact area being laterally located between storage node contact areas on the end portions of the semiconducting pillar structure.

[0143] Example 14: The method according to any one of Examples 11 to 13, wherein the oxide material forming the side of the second line includes forming the oxide material comprising silicon dioxide.

[0144] Example 15: The method according to any one of Examples 11 to 14, wherein forming a pattern of a third line including an underlayer material over the remaining portion of the first sacrificial material and the line of the remaining portion of the first line oriented at a second angle relative to the first line includes forming the pattern of the third line at a second angle in the range of about 30° to about 60° relative to the first line.

[0145] Example 16: According to the method of Example 15, wherein: the pattern of forming the third line at a second angle in the range of about 30° to about 60° relative to the remaining portion of the first line includes forming the pattern of the third line at the second angle in one of a clockwise and counterclockwise direction from the first lateral direction; and forming the second line includes forming the second line at the first angle in the other of the clockwise and counterclockwise directions from the first lateral direction.

[0146] Example 17: The method according to any one of Examples 11 to 16, wherein forming the pattern of the first line includes forming the pattern of the first line by a spacing quadruple process or a spacer-assisted double patterning process.

[0147] Example 18: The method according to any one of Examples 11 to 17, wherein forming the pattern of the first line includes spacing the first lines apart by a distance from about 20 nm to about 40 nm.

[0148] Example 19: A method of forming a microelectronic device, the method comprising: forming a first line comprising silicon in a first direction; forming a nitride material between the first lines; forming a second line comprising silicon in a second direction at a first angle relative to the first direction; forming spacers on the second lines; removing portions of the first lines and portions of the nitride material through the spacers; forming lines of a mask extending at a second angle relative to the first direction; removing portions of the nitride material between the lines of the mask; and removing portions of a semiconductive material adjacent to the remaining portions of the first lines and the nitride material to form a semiconductive pillar structure.

[0149] Example 20: According to the method of Example 19, forming a second line including silicon in a second direction at a first angle relative to the first direction includes forming the second line at a first angle relative to the first direction in the range of about 40° to about 50°.

[0150] Example 21: The method according to Example 19 or Example 20 further includes: forming a first storage node contact on a first end portion of the semiconducting pillar structure; forming a second storage node contact on a second end portion of the semiconducting pillar structure; and forming a digital line contact on a central portion of the semiconducting pillar structure.

[0151] Example 22: The method according to any one of Examples 19 to 21, wherein forming the line of the mask extending at a second angle relative to the first direction includes forming the line of the mask to extend at a second angle in a direction opposite to the first direction compared to the first angle.

[0152] Example 23: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: semiconducting pillar structures spaced apart from each other, the at least one semiconducting pillar structure comprising: a central portion between a first end portion and a second end portion; a first memory node contact electrically connected to the first end portion and a second memory node contact electrically connected to the second end portion; and a digital line electrically connected to the central portion, the digital line being oriented at an angle from about 30° to about 60° relative to the first end portion and the second end portion.

[0153] Example 24: The electronic system according to Example 23, wherein the angle is approximately 49°.

[0154] Example 25: The electronic system according to Example 23 or Example 24 further includes a word line extending between the digital line and each of the first memory node contact and the second memory node contact.

[0155] Example 26: An electronic system according to any one of Examples 23 to 25, wherein the longitudinal axis of the first end portion is substantially parallel to the longitudinal axis of the second end portion.

[0156] Example 27: An electronic system according to any one of Examples 23 to 26, wherein the digital line is parallel to the longitudinal axis of the central portion.

[0157] Example 28: An electronic system according to any one of Examples 23 to 27, wherein the semiconducting pillar structure comprises silicon.

[0158] While certain illustrative embodiments have been described in conjunction with the accompanying drawings, those skilled in the art will recognize and understand that the embodiments included in this disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

1. A microelectronic device comprising: Each of the semiconductor pillar structures individually includes a digital line contact area laterally disposed between two memory node contact areas, and at least one of the semiconductor pillar structures includes: A first end portion includes a first storage node contact area and a first end portion longitudinal axis, the first end portion longitudinal axis extending generally parallel to the opposite side defining the first end portion; The second end portion includes a second storage node contact area and a second end portion longitudinal axis, the second end portion longitudinal axis extending generally parallel to the opposite side defining the second end portion; A middle portion, located between the first end portion and the second end portion and including the digital line contact area and a longitudinal axis of the middle portion, the longitudinal axis of the middle portion extending generally parallel to opposite sides defining the middle portion, wherein the longitudinal axis of the first end portion is oriented at an angle relative to the longitudinal axis of the middle portion; and A digital line, which is perpendicularly adjacent to the semiconducting pillar structure, wherein the middle portion of each semiconducting pillar structure is generally laterally aligned with one of the digital lines along the longitudinal axis of the middle portion.

2. The microelectronic device of claim 1, wherein the longitudinal axis of the second end portion is oriented at an angle relative to the longitudinal axis of the middle portion.

3. The microelectronic device according to claim 2, wherein the longitudinal axis of the first end portion is substantially parallel to the longitudinal axis of the second end portion.

4. The microelectronic device according to claim 1, wherein the angle is in the range of 30° to 60°.

5. The microelectronic device of claim 1, wherein the angle is in the range of 40° to 50°.

6. The microelectronic device of claim 1, wherein the first memory node contact area is offset longitudinally and laterally from the second memory node contact area.

7. The microelectronic device according to any one of claims 1 to 6, further comprising: Storage node contacts, located at the contact areas of the two storage nodes in each of the semiconducting pillar structures; A digital line contact, wherein at the digital line contact area of ​​each of the semiconducting pillar structures, the digital line is individually electrically connected to the digital line contact of each of the semiconducting pillar structures; Word lines that extend laterally in a direction different from the number lines, the word lines separating the middle portion from each of the first end portion and the second end portion; as well as The storage node structure is individually electrically connected to the storage node contacts and is located close to the intersection of the digital line and the word line.

8. The microelectronic device according to any one of claims 1 to 6, wherein the digital line contact area of ​​the first semiconducting pillar structure is laterally adjacent to the storage node contact area of ​​the second semiconducting pillar structure.

9. The microelectronic device of claim 8, wherein the digital line contact area of ​​the first semiconducting pillar is laterally located between the storage node contact area of ​​the second semiconducting pillar and the storage node contact area of ​​the third semiconducting pillar.

10. A method of forming a microelectronic device, the method comprising: A pattern of a first line of a first sacrificial material is formed above the base material, and a nitride material is formed in the space between adjacent first lines; A second line of second sacrificial material is formed above the first line, the second line of the second sacrificial material being oriented relative to the first line at a first angle in the range of 30° to 60°; An oxide material is formed on the side surface of the second line; A portion of each of the first sacrificial material, the second sacrificial material, and the nitride material is selectively removed relative to the oxide material; A pattern of a third line including an underlying material is formed over the remaining portion of the first sacrificial material, the pattern of the third line being oriented at a second angle relative to the remaining portion of the first line; as well as The pattern of the third line removes portions of the nitride material that is selective for the first sacrificial material to form a columnar structure pattern.

11. The method of claim 10, further comprising transferring the pattern of the pillar structure onto the substrate material to form a pattern of the semiconductive pillar structure.

12. The method of claim 11, wherein forming the pattern of the semiconducting pillar structure comprises forming the pattern of the semiconducting pillar structure, each including a digital line contact area at its central portion, the digital line contact area being laterally located between storage node contact areas located at the end portions of the semiconducting pillar structure.

13. The method of claim 10, wherein the oxide material forming the side of the second line comprises forming the oxide material comprising silicon dioxide.

14. The method of claim 10, wherein forming a pattern of a third line comprising an underlying material oriented at a second angle relative to the remaining portion of the first sacrificial material over the remaining portion of the first line comprises forming the pattern of the third line at a second angle relative to the first line in the range of 30° to 60°.

15. The method of claim 14, wherein: The pattern of forming the third line at a second angle in the range of 30° to 60° relative to the remaining portion of the first line includes forming the third line at the second angle in one of the clockwise and counterclockwise directions from the first lateral direction; as well as Forming the second line includes forming the second line at the first angle in another direction, either clockwise or counterclockwise, from the first lateral direction.

16. The method according to any one of claims 10 to 15, wherein forming the pattern of the first line comprises forming the pattern of the first line by a quadruple spacing process or a spacer-assisted double patterning process.

17. The method according to any one of claims 10 to 15, wherein forming the pattern of the first lines comprises spacing the first lines apart by a distance from 20 nm to 40 nm.

18. A method of forming a microelectronic device, the method comprising: A first line comprising silicon is formed in a first direction; Nitride material is formed between the first lines; A second line comprising silicon is formed in a second direction at a first angle relative to the first direction; Spacers are formed on the second line; A portion of the first line and a portion of the nitride material are removed through the space between the spacers; Forming a mask line that extends at a second angle relative to the first direction; Remove portions of the nitride material between the lines of the mask; as well as A portion of the semiconductive material adjacent to the first line and the remaining portion of the nitride material is removed to form a semiconductive pillar structure.

19. The method of claim 18, wherein forming a second line comprising silicon in a second direction at a first angle relative to the first direction comprises forming the second line at a first angle in the range of 40° to 50° relative to the first direction.

20. The method of claim 18, further comprising: A first storage node contact is formed on the first end portion of the semiconducting pillar structure; A second storage node contact is formed on the second end portion of the semiconducting pillar structure; as well as A digital line contact is formed on the central portion of the semiconducting pillar structure.

21. The method according to any one of claims 18 to 20, wherein forming the line of the mask extending at a second angle relative to the first direction comprises forming the line of the mask to extend at the second angle in a direction opposite to the first direction compared to the first angle.

22. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; as well as A memory device operatively coupled to the processor device and including at least one microelectronic device, the at least one microelectronic device comprising: Semiconducting pillar structures spaced apart from each other, at least one of the semiconducting pillar structures includes: The central portion, between the first and second end portions; and A first storage node contact electrically connected to the first end portion and a second storage node contact electrically connected to the second end portion; and A digital line electrically connected to the central portion, the digital line being oriented at an angle of 30° to 60° relative to a first opposite side defining the first end portion, the digital line being generally parallel to a second opposite side defining the central portion; A first line extends between the central portion and the first end portion of the at least one semiconducting pillar structure; A second line extends between the central portion and the second end portion of the at least one semiconducting pillar structure; and The first and second character lines extend substantially orthogonally to the second opposite side of the central portion.

23. The electronic system of claim 22, wherein the angle is 49°.

24. The electronic system of claim 22, wherein the longitudinal axis of the first end portion is substantially parallel to the longitudinal axis of the second end portion.

25. The electronic system according to any one of claims 22 to 24, wherein the semiconducting pillar structure comprises silicon.

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