Semiconductor package

Abstract

A semiconductor package includes a redistribution substrate including a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a horizontally extending line portion and a via portion connected to the line portion, a width of the via portion being less than a width of the line portion; a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer; a conductive pillar penetrating the passivation layer, the conductive pillar connected to the via portion; and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0104111, entitled "Semiconductor Packaging", filed with the Korean Intellectual Property Office on August 19, 2020, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to a semiconductor package, and more specifically to a semiconductor package including a redistribution substrate. Background Technology

[0004] The rapid development of the electronics industry and user demands have led to increasingly smaller electronic products. To manufacture compact, high-performance, and high-capacity electronic products, continuous research and development are underway on semiconductor chips, including through-silicon via (TSV) structures, and semiconductor packages incorporating these chips. For example, for high integration of semiconductor devices, multiple semiconductor chips can be stacked to form multi-chip packages or system-in-packages (SoCs). In multi-chip packages, multiple semiconductor chips are mounted within a single semiconductor package, while in SoCs, the stacked chips operate as a system. Summary of the Invention

[0005] According to some example embodiments, a semiconductor package may include: a redistribution substrate including a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including: horizontally extending line portions and via portions connected to the line portions, the width of the via portions being smaller than the width of the line portions; a passivation layer on a top surface of the redistribution substrate, the passivation layer comprising a material different from that of the dielectric layer; conductive pillars penetrating the passivation layer and connected to the via portions; and connection terminals on the top surface of the conductive pillars. The distance between the top surface of the conductive pillars and the top surface of the passivation layer is greater than the thickness of the passivation layer.

[0006] According to some example embodiments, a semiconductor package may include: a redistribution substrate including a dielectric layer and a wiring pattern in the dielectric layer; a passivation layer on a top surface of the dielectric layer; conductive pillars penetrating the passivation layer and electrically connected to the wiring pattern; and connection terminals on the top surface of the conductive pillars, the bottom surface of the connection terminals being vertically horizontally higher than the top surface of the passivation layer. The wiring pattern may include horizontally extending line portions and via portions between the line portions and the bottom surfaces of the conductive pillars. The width of the bottom surface of the conductive pillars may be greater than the width at the top surface of the via portions.

[0007] According to some example embodiments, a semiconductor package may include: a redistribution substrate including a dielectric layer and a plurality of wiring patterns in the dielectric layer, each of the wiring patterns including a horizontally extending line portion and a via portion on the line portion, the width of the via portion being smaller than the width of the line portion; a first passivation layer on a top surface of the dielectric layer; a conductive pillar penetrating the first passivation layer and connected to the via portion; a first connection terminal on the top surface of the conductive pillar; a second passivation layer on a bottom surface of the dielectric layer, the second passivation layer covering the bottom and side surfaces of the line portion; a conductive support pattern penetrating the second passivation layer and connected to the line portion; and a second connection terminal on the bottom surface of the conductive support pattern. The thickness of the conductive pillar may be greater than the thickness of the conductive support pattern. Attached Figure Description

[0008] The features will become clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 A cross-sectional view of a semiconductor package according to some example embodiments is shown.

[0010] Figure 2A It shows Figure 1 A magnified cross-sectional view of part A.

[0011] Figure 2B It shows Figure 1 A magnified cross-sectional view of part B.

[0012] Figures 3 to 9 It shows Figure 1 A magnified cross-sectional view of part B shows a semiconductor package according to some example embodiments.

[0013] Figures 10 to 17 Cross-sectional views are shown of some stages in a method for manufacturing a semiconductor package according to some example embodiments.

[0014] Figure 18 A cross-sectional view of a semiconductor package according to some example embodiments is shown.

[0015] Figure 19 It shows Figure 18 A magnified cross-sectional view of part C.

[0016] Figure 20 and Figure 21 Cross-sectional views are shown of some stages in a method for manufacturing a semiconductor package according to some example embodiments.

[0017] Figures 22 to 25 A cross-sectional view of a semiconductor package according to some example embodiments is shown. Detailed Implementation

[0018] In this specification, the terms "top surface" and "bottom surface" are used to briefly describe components. However, the terms "top surface" and "bottom surface" are used only to distinguish one surface of a component from another surface of a component. According to some example embodiments, the language regarding the "top surface" and "bottom surface" of any component included in a semiconductor package may be used interchangeably based on the arrangement orientation of the semiconductor package. Thus, any surface referred to as the "top surface" in one embodiment may be referred to as the "bottom surface" in another embodiment, and vice versa.

[0019] Figure 1 A cross-sectional view of a semiconductor package according to some example embodiments is shown. Figure 2A It shows Figure 1 A magnified cross-sectional view of part A. Figure 2B It shows Figure 1 A magnified cross-sectional view of part B.

[0020] Reference Figure 1 , Figure 2A and Figure 2B The semiconductor package may include a redistribution substrate 100, a semiconductor chip 200 on the redistribution substrate 100, a molding layer 400 covering the semiconductor chip 200, and a connection member for connecting the semiconductor chip 200 to an external device. The connection member may include a first connection terminal 332, a conductive post 310, a second connection terminal 334, and a conductive support pattern 320. The semiconductor package may be a fan-out semiconductor package.

[0021] The redistribution substrate 100 may include a dielectric layer 110 and a wiring pattern 120 in the dielectric layer 110. The dielectric layer 110 may include a dielectric pattern 112 stacked between the bottom surface of the first passivation layer 152 and the top surface of the second passivation layer 154. For example, the dielectric pattern 112 may include an inorganic material, such as one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). In another example, the dielectric pattern 112 may include a photosensitive polymer, such as one or more of photosensitive polyimide, polybenzoxazole, phenolic polymer, and benzocyclobutene polymer. The dielectric layer 110 may include three vertically stacked dielectric patterns 112, but the example embodiment is not limited thereto; for example, the dielectric layer 110 may include four or more vertically stacked dielectric patterns 112.

[0022] Wiring pattern 120 can be set in dielectric layer 110. For example... Figure 2A and Figure 2B As shown, the wiring pattern 120 may each include a line portion 122 and a through-hole portion 124.

[0023] The line portion 122 of the wiring pattern 120 can extend horizontally. For example, the line portion 122 can extend in a direction parallel to one surface of the dielectric pattern 112, thereby forming a circuit. The line portion 122 can have a top surface coplanar with the bottom surface of the dielectric pattern 112, and can also have side surfaces and a bottom surface surrounded by the dielectric pattern 112 or the second passivation layer 154. The bottom surface of the line portion 122 can be parallel to the top surface 110a and the bottom surface 110b of the dielectric layer 110. The line portion 122 can have a thickness ranging from about 3 μm to about 5 μm.

[0024] Reference Figure 2B The via portion 124 of the wiring pattern 120 can be disposed on and connected to the line portion 122 of the wiring pattern 120. The via portion 124 can be positioned closer to the top surface 110a of the dielectric layer 110 than the line portion 122. The width of the via portion 124 can be smaller than the width of the line portion 122. The width of the via portion 124 can decrease as the distance from the top surface 110a of the dielectric layer 110 decreases. The via portion 124 can penetrate at least a portion of the dielectric pattern 112, thereby electrically connecting the line portions 122 located at different levels. In addition, the via portion 124 of the uppermost wiring pattern 120 can completely penetrate the uppermost dielectric pattern 112, thereby electrically connecting the conductive post 310 to the line portion 122 of the uppermost wiring pattern 120.

[0025] Each wiring pattern 120 may include a conductive layer 126 and a seed layer 128. The conductive layer 126 may include a conductive material, such as a metal. The metal included in the conductive layer 126 may be, for example, copper (Cu). The seed layer 128 may include a conductive material, such as titanium (Ti) and / or tantalum (Ta). The thickness of the seed layer 128 may be less than the thickness of the conductive layer 126. The seed layer 128 may have a thickness of about 5 angstroms to about 50 angstroms. According to some example embodiments, the seed layer 128 may be formed before the conductive layer 126 to perform a plating process. The seed layer 128 may be in direct contact with the conductive layer 126.

[0026] For example, each of the via portions 124 and line portions 122 of the wiring pattern 120 may include a conductive layer 126 and a seed layer 128 on the conductive layer 126. The conductive layer 126 of the line portion 122 may have a top surface partially covered by the seed layer 128. A second passivation layer 154 may surround the side and bottom surfaces of the line portions 122 of the lowermost wiring pattern 120. A dielectric pattern 112 may surround the side and bottom surfaces of the conductive layer 126 of the line portions 122 included in each of the wiring patterns 120 except the lowermost wiring pattern 120.

[0027] The width of the conductive layer 126 of the via portion 124 can decrease as the distance from the top surface 110a of the dielectric layer 110 decreases. The conductive layers 126 of the via portion 124 and the line portion 122 can be connected to each other without a boundary between them; for example, the connection can be a single, seamless unit. The seed layer 128 of the via portion 124 can conformally cover the top and side surfaces of the conductive layer 126 of the via portion 124.

[0028] like Figure 2B As shown, the conductive post 310 can be directly connected to the uppermost wiring pattern 120 disposed on the top surface 110a of the dielectric layer 110. The line portion 122 of the uppermost wiring pattern 120 can be positioned on the bottom surface of the uppermost dielectric pattern 112. The via portion 124 of the uppermost wiring pattern 120 can be positioned between the line portion 122 of the uppermost wiring pattern 120 and the bottom surface 310b of the conductive post 310. The via portion 124 of the uppermost wiring pattern 120 can penetrate at least a portion of the uppermost dielectric pattern 112, thereby electrically connecting the conductive post 310 to the line portion 122 of the uppermost wiring pattern 120. The via portion 124 of the uppermost wiring pattern 120 may have a top surface 124a (or the top surface of the seed layer 128), the width w2 of the top surface 124a being smaller than the width w1 of the bottom surface 310b of the conductive post 310. For example, the bottom surface 310b of the conductive post 310 may cover and overlap the entire top surface 124a (or the top surface of the seed layer 128) of the via portion 124.

[0029] A first passivation layer 152 may be disposed on the top surface 110a of the dielectric layer 110. The first passivation layer 152 may cover the top surface of the uppermost dielectric pattern 112 of the dielectric layer 110. According to some example embodiments, the first passivation layer 152 may include a dielectric polymer, such as an epoxy-based polymer. The first passivation layer 152 may include, for example, an Ajinomoto deposited film (ABF). The first passivation layer 152 may include a photosensitive material, such as a photoimageable dielectric (PID). The first passivation layer 152 may partially cover the side surface of the conductive pillar 310. Figure 2A As shown, the thickness t3 of the first passivation layer 152 can be equal to or less than half the thickness t2 of the conductive pillar 310. For example, the distance d1 between the top surface 310a of the conductive pillar 310 and the top surface of the first passivation layer 152 can be greater than the thickness t3 of the first passivation layer 152. The distance d1 between the top surface 310a of the conductive pillar 310 and the top surface of the first passivation layer 152 can have a value ranging from about 2 to about 5 times the thickness t3 of the first passivation layer 152.

[0030] The conductive post 310 can penetrate the first passivation layer 152 and can be connected to the wiring pattern 120 in the redistribution substrate 100. The conductive post 310 can be flat at its top surface 310a and bottom surface 310b. The bottom surface 310b of the conductive post 310 can cover the top surface of the uppermost dielectric pattern 112 and the uppermost surface of the seed layer 128. The bottom surface 310b of the conductive post 310 can be coplanar with the bottom surface of the first passivation layer 152. The top surface 310a of the conductive post 310 can be parallel to the bottom surface 310b of the conductive post 310. According to some example embodiments, the conductive post 310 can have a cylindrical shape or a rectangular prism shape. Therefore, the conductive post 310 can have a quadrilateral or trapezoidal shape in a cross-section taken along the vertical direction. The conductive post 310 can include a metal, such as copper.

[0031] like Figure 2B As shown, the width w1 of the bottom surface 310b of the conductive post 310 can be greater than the width w2 of the top surface 124a of the via portion 124 included in each wiring pattern 120. The value of the width w1 at the bottom surface 310b of the conductive post 310 can range from about 2 to about 5 times the width w2 at the top surface 124a of the via portion 124 included in the uppermost wiring pattern 120. Therefore, the top surface 124a of the via portion 124 included in the uppermost wiring pattern 120 can cover a portion of the bottom surface 310b of the conductive post 310, but may not cover other portions of the bottom surface 310b of the conductive post 310. For example, the top surface 124a of the via portion 124 can only cover a portion of the bottom surface 310b of the conductive post 310. The top surface 124a of the seed layer 128 included in the uppermost wiring pattern 120 can directly contact the bottom surface 310b of the conductive post 310.

[0032] Semiconductor chip 200 can be disposed on redistribution substrate 100. Semiconductor chip 200 may include semiconductor substrate, integrated circuit on semiconductor substrate, wiring connected to integrated circuit, and chip pads 210 connected to wiring. Chip pads 210 can be electrically connected to integrated circuit of semiconductor chip 200 via wiring. Chip pads 210 of semiconductor chip 200 can be disposed between bottom surface of semiconductor chip 200 and top surface 110a of dielectric layer 110, for example, chip pads 210 can be directly on bottom surface of semiconductor chip 200. Chip pads 210 may include metal, such as aluminum. Chip pads 210 of semiconductor chip 200 can be formed to vertically overlap with conductive pillars 310. According to some example embodiments, the width of chip pad 210 may be the same as the width of conductive pillar 310, and they can be arranged at the same spacing as the spacing of conductive pillars 310, for example, chip pads 210 may be aligned with and completely overlap with the top of the corresponding conductive pillar 310.

[0033] A first connection terminal 332 may be disposed between the semiconductor chip 200 and the conductive post 310. The first connection terminal 332 can electrically connect the conductive post 310 to the chip pad 210 of the semiconductor chip 200. The first connection terminal 332 may include, for example, solder balls or solder bumps. The first connection terminal 332 can directly contact the top surface 310a of the conductive post 310 and the bottom surface of the chip pad 210. The first connection terminal 332 may have a width that decreases with increasing distance from the top surface 310a of the conductive post 310. The first connection terminal 332 may completely cover the top surface 310a of the conductive post 310. The first connection terminal 332 may partially cover the bottom surface of the chip pad 210. For example, the first connection terminal 332 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) or any alloy thereof, such as Sn, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn or Sn-Bi-Zn.

[0034] A conductive support pattern 320 may be disposed on the bottom surface of the second passivation layer 154. The conductive support pattern 320 may, for example, partially penetrate the second passivation layer 154 and may be connected to the wiring pattern 120 in the redistribution substrate 100. The conductive support pattern 320 may be connected to the bottom surface of the line portion 122. For example... Figure 2A As shown, the conductive support pattern 320 may have a thickness t1 and may have an uneven (e.g., non-flat) shape. The conductive support pattern 320 may have a top surface and a bottom surface that are more uneven than the top surface 310a and the bottom surface 310b of the conductive pillar 310. The central portion of the top surface of the conductive support pattern 320 may protrude toward the top surface 110a of the dielectric layer 110. The central portion of the bottom surface of the conductive support pattern 320 may be recessed toward the top surface 110a of the dielectric layer 110.

[0035] The conductive support pattern 320 may include a first conductive pattern 322 and a second conductive pattern 324, with the second conductive pattern 324 located between the first conductive pattern 322 and the second connecting terminal 334. The first conductive pattern 322 and the second conductive pattern 324 may include conductive materials, such as metals. The first conductive pattern 322 and the second conductive pattern 324 may include materials different from each other. For example, the first conductive pattern 322 may include titanium (Ti) and / or tungsten (W), and the second conductive pattern 324 may include copper (Cu).

[0036] The second connection terminals 334 can be disposed on the bottom surface of the conductive support pattern 320. The second connection terminals 334 can be electrically connected to the semiconductor chip 200 via the redistribution substrate 100, conductive pillars 310, and the first connection terminals 332. The second connection terminals 334 can fill the recessed central portion of the bottom surface of the conductive support pattern 320. The second connection terminals 334 can directly contact the second conductive pattern 324 of the conductive support pattern 320. The spacing between the second connection terminals 334 can be greater than the spacing between the first connection terminals 332. Furthermore, the width of the second connection terminals 334 can be greater than the width of the first connection terminals 332. The second connection terminals 334 may include, for example, solder balls or solder bumps. For example, the second connection terminal 332 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) or any alloy thereof, such as Sn, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn or Sn-Bi-Zn.

[0037] A molding layer 400 may be disposed thereon on the first passivation layer 152, the molding layer 400 covering the top surface, bottom surface, and side surface of the semiconductor chip 200. The molding layer 400 may fill the space between the semiconductor chip 200 and the first passivation layer 152. The molding layer 400 may cover a portion of the top surface of the first passivation layer 152 and the side surface of the conductive pillar 310. In addition, the molding layer 400 may cover the side surface of the first connection terminal 332. The molding layer 400 may have a bottom surface that is in direct contact with the top surface of the first passivation layer 152. Compared with the top surface 310a of the conductive pillar 310, the bottom surface of the molding layer 400 may be located at a level closer to the bottom surface 310b of the conductive pillar 310. For example, the contact area between the molding layer 400 and the conductive pillar 310 may be larger than the contact area between the first passivation layer 152 and the conductive pillar 310. The molding layer 400 may include a material different from the material of the first passivation layer 152 and the dielectric pattern 112. The molding layer 400 may include a dielectric polymer, such as epoxy molding compound (EMC).

[0038] Figures 3 to 9 The following are illustrated according to some example embodiments. Figure 1 A magnified cross-sectional view of part B. Repeated descriptions will be omitted below.

[0039] Reference Figure 3 According to some example embodiments, a semiconductor package may include a first metal layer 352 on the conductive pillar 310, and may also include a second metal layer 354 between the first metal layer 352 and the first connection terminal 332. For example, as Figure 3 As shown, the first metal layer 352 and the second metal layer 354 may exist only on the top surface of the conductive pillar 310. The first metal layer 352 and the second metal layer 354 may comprise different metallic materials from each other. For example, the first metal layer 352 may comprise nickel (Ni), and the second metal layer 354 may comprise gold (Au). An electroplating process can be used to selectively form the first metal layer 352 and the second metal layer 354 on the top surface 310a of the conductive pillar 310.

[0040] Reference Figure 4 A semiconductor package according to some example embodiments may include: a first metal layer 352 conformally covering the side surface and top surface 310a of a conductive pillar 310; and a second metal layer 354 conformally covering the surface of the first metal layer 352. For example, the first metal layer 352 may be inserted between the conductive pillar 310 and the second metal layer 354. A first passivation layer 152 may be spaced across the first metal layer 352 and the second metal layer 354 from the side surface of the conductive pillar 310. The first metal layer 352 and the second metal layer 354 may extend to the same level as the bottom surface of the conductive pillar 310, thereby contacting the top surface 110a of the dielectric layer 110.

[0041] Reference Figure 5 The conductive post 310 may have a width that decreases with increasing distance from the top surface 110a of the dielectric layer 110. Therefore, the conductive post 310 may have a trapezoidal shape in a vertical cross-section. The conductive post 310 may have a tapered shape on its side surfaces. The conductive post 310 may have a maximum width at the same level as the width of its bottom surface 310b, and a minimum width at the same level as the width of its top surface 310a. Therefore, the first connection terminal 332 may have a bottom surface 332b, the width of which is smaller than the width of the bottom surface 310b of the conductive post 310.

[0042] Reference Figure 6 The first passivation layer 152 may have a protrusion PP projecting in a direction away from the dielectric layer 110. The protrusion PP may be positioned on the side surface of the conductive post 310. The thickness of the first passivation layer 152 may increase as the distance from the side surface of the conductive post 310 decreases. For example, the top surface of the first passivation layer 152 may be located at a level that becomes higher as the distance from the side surface of the conductive post 310 decreases. According to some example embodiments, the first passivation layer 152 may have an uppermost surface below the vertical center of the conductive post 310.

[0043] Reference Figure 7The first passivation layer 152 may have a recess DP recessed into the dielectric layer 110. The recess DP may be located on the side surface of the conductive pillar 310. The first passivation layer 152 may have a thickness that decreases with decreasing distance from the side surface of the conductive pillar 310. For example, the top surface of the first passivation layer 152 may be located at a level that becomes higher with decreasing distance from the side surface of the conductive pillar 310. The molding layer 400 may fill the recess DP.

[0044] Reference Figure 8 The conductive post 310 can have a greater surface roughness at its top surface 310a than at its bottom surface 310b. The top surface 310a of the conductive post 310 can include multiple fine protrusions and multiple recesses. The first connection terminal 332 can fill the multiple recesses and completely cover the top surface 310a of the conductive post 310. Therefore, the bottom surface 332b of the first connection terminal 332 can have a surface roughness substantially the same as the surface roughness of the top surface of the conductive post 310. Compared to a case where the conductive post 310 and the first connection terminal 332 have a flat interface between the top surface 310a and the bottom surface 332b, the conductive post 310 and the first connection terminal 332 can have stronger adhesion and a larger contact area between the top surface 310a and the bottom surface 332b. Therefore, semiconductor packaging can increase stability and reduce the contact area.

[0045] Reference Figure 9 The top surface 124a of the via portion 124 included in the wiring pattern 120 can be located at a vertical level higher than the vertical level of the bottom surface 310b of the conductive post 310. The via portion 124 of the wiring pattern 120 can be partially inserted into the bottom surface 310b of the conductive post 310. The via portion 124 and the conductive post 310 can therefore have an increased contact area and reduced contact resistance between them. The top surface 124a of the via portion 124 can be located at a vertical level higher than the vertical level of the top surface 110a of the dielectric layer 110 and lower than the vertical level of the top surface 152a of the first passivation layer 152. The top surface of the conductive layer 126 included in the via portion 124 of the wiring pattern 120 can be located at a vertical level lower than the vertical level of the bottom surface 310b of the conductive post 310.

[0046] The conductive post 310 may have a trench T on its bottom surface 310b, into which the via portion 124 of the wiring pattern 120 is inserted. The trench T may be formed during the over-etching of the bottom surface 310b of the conductive post 310 during the formation of the second via H2, as will be referred to below. Figure 12 Let's have a discussion.

[0047] Figures 10 to 16Cross-sectional views are shown of some stages in a method for manufacturing a semiconductor package according to some example embodiments.

[0048] Reference Figure 10 The seed layer 350 and the initial first passivation pattern 152p can be formed on the first carrier substrate 1010.

[0049] The seed layer 350 can be formed to conformally cover the top surface of the first carrier substrate 1010. A deposition process can be used to form the seed layer 350. The seed layer 350 may include a conductive material. For example, the seed layer 350 may include one or more of copper, titanium, and alloys thereof. According to some example embodiments, the seed layer 350 may include multiple metal layers, and the metal layers may include two or more of copper, titanium, and alloys thereof.

[0050] A preliminary first passivation pattern 152p can be formed on the lower seed layer 350. For example, the formation of the preliminary first passivation layer 152p may include coating the lower seed layer 350 with a photosensitive material to form a preliminary passivation dielectric layer, and patterning the preliminary passivation dielectric layer to form a first hole H1 exposing the top surface of the lower seed layer 350. The photosensitive material may include one or more photosensitive polymers, such as photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. Exposure and development processes may be performed to pattern the preliminary passivation dielectric layer. The exposure process may be a negative tone exposure process or a positive tone exposure process.

[0051] In another example, the formation of the initial first passivation layer 152p may include performing a deposition process on the lower seed layer 350 to form an initial passivation dielectric layer, and patterning the initial passivation dielectric layer to form a first hole H1 exposing the top surface of the lower seed layer 350. The deposition process may include, for example, a chemical vapor deposition process. A dry etching process may be used to pattern the initial passivation dielectric layer.

[0052] Reference Figure 11The initial first connection terminal 332p and the conductive post 310 can be formed in the first hole H1. The initial first connection terminal 332p can be formed directly on the lower seed layer 350. The initial first connection terminal 332p can be formed by performing an electroplating process in which the lower seed layer 350 serves as an electrode. For example, the initial first connection terminal 332p can include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or any alloy thereof, such as Sn, Sn-Pb, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, or Sn-Bi-Zn.

[0053] The conductive post 310 can be formed on the initial first connection terminal 332p. The conductive post 310 can be formed by performing an electroplating process in which the seed layer 350 and the initial first connection terminal 332p serve as electrodes. The conductive post 310 can include, for example, copper (Cu).

[0054] Reference Figure 12 Dielectric pattern 112 can be formed on the top surface of the initial passivation layer 152p and the top surface of the conductive pillar 310. The dielectric pattern 112 can be formed by performing a coating process (e.g., spin coating or slot coating) and a curing process (e.g., thermosetting). The dielectric pattern 112 can be patterned to form second holes H2, each second hole H2 exposing the top surface of the conductive pillar 310.

[0055] Subsequently, a wiring pattern 120 can be formed to fill the second hole H2. The formation of the wiring pattern 120 may include: forming a preliminary seed layer covering the top surface of the dielectric pattern 112 and the inner wall of the second hole H2; forming a resist pattern partially covering the top surface of the preliminary seed layer; and forming a conductive layer 126 between the resist patterns. The conductive layer 126 can be formed by performing an electroplating process in which the preliminary seed layer serves as an electrode. After forming the conductive layer 126, the resist pattern can be removed. The preliminary seed layer may undergo a wet etching process in which the conductive layer 126 serves as an etching mask to form a seed layer 128.

[0056] Reference Figure 13 The processes for forming dielectric pattern 112 and wiring pattern 120 can be repeated to form redistribution substrate 100. According to some example embodiments, dielectric patterns 112 can be stacked vertically to connect with each other to form a single dielectric layer 110.

[0057] On dielectric layer 110, a second passivation layer 154 can be formed to cover the uppermost wiring pattern 120. Forming the second passivation layer 154 may include coating the dielectric layer 110 with a photosensitive material to form a preliminary passivation dielectric layer, and patterning the preliminary passivation dielectric layer to expose the top surface of the uppermost wiring pattern 120. The photosensitive material may include one or more photosensitive polymers, such as photosensitive polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers. Exposure and development processes may be performed to pattern the preliminary passivation dielectric layer. The exposure process may be a negative tone exposure process or a positive tone exposure process.

[0058] In another example, the formation of the second passivation layer 154 may include performing a deposition process on the dielectric layer 110 to form a preliminary passivation dielectric layer, and patterning the preliminary passivation dielectric layer to expose the top surface of the uppermost wiring pattern 120. The deposition process may include, for example, a chemical vapor deposition process. A dry etching process may be used to pattern the preliminary passivation dielectric layer.

[0059] A conductive support pattern 320 can be formed on the top surface of the uppermost wiring pattern 120, the top surface of which is exposed by the second passivation layer 154. The formation of the conductive support pattern 320 may include sequentially performing deposition and patterning processes to form a first conductive pattern 322 and a second conductive pattern 324. Chemical vapor deposition (CVD) can be used as the deposition process for forming the first conductive pattern 322 and the second conductive pattern 324. Etching can be used as the patterning process for forming the first conductive pattern 322 and the second conductive pattern 324.

[0060] Reference Figure 14 The second passivation layer 154 can be attached to the second carrier substrate 1020, which includes a support 1022 and a buffer 1024, and the redistribution substrate 100 can be inverted. (See reference) Figures 10 to 13 The top surface of the components included in the semiconductor package under discussion may be referred to as the bottom surface below, and the bottom surface may be referred to as the top surface below.

[0061] The second carrier substrate 1020 can support the redistribution substrate 100. The first carrier substrate 1010 can be separated from the top surface of the lower seed layer 350.

[0062] Reference Figure 15The seed layer 350 can be removed, for example, by a dry etching process or a wet etching process. Then, the preliminary first passivation layer 152p can be partially removed to lower the level of the top surface of the preliminary first passivation layer 152p. Partial removal of the preliminary first passivation layer 152p can be achieved by performing a wet etching process and a plasma etching process. The wet etching process and the plasma etching process can be performed until the level of the top surface of the preliminary first passivation layer 152p is closer to the bottom surface of the conductive pillar 310 than the top surface of the conductive pillar 310. When the top surface of the preliminary first passivation layer 152p is at a lower level, the preliminary first connection terminal 332p can have a fully exposed side surface, and the conductive pillar 310 can have a partially exposed side surface. Figure 16 As shown, a preliminary first passivation layer 152p with a low-level top surface can constitute the first passivation layer 152.

[0063] Reference Figure 16 A reflow process can be performed to melt the initial first connection terminal 332p. The reflow process can be performed in a temperature range of about 150°C to about 250°C. The reflowed initial first connection terminal 332p can each have a hemispherical shape due to surface tension. The reflowed initial first connection terminal 332p can each have a width that decreases with increasing distance from the redistribution substrate 100.

[0064] Reference Figure 17 The semiconductor chip 200, including chip pads 210, can be mounted on the redistribution substrate 100, allowing the chip pads 210 to face the initial first connection terminal 332p. A molding layer 400 can then be formed to cover the semiconductor chip 200. The molding layer 400 can extend between the semiconductor chip 200 and the first passivation layer 152, thereby encapsulating the semiconductor chip 200, the initial first connection terminal 332p, and the conductive pillars 310.

[0065] The second carrier substrate 1020 can then be removed to expose the second passivation layer 154 and the conductive support pattern 320.

[0066] Return to reference Figure 1 The second connection terminal 334 can be disposed on the bottom surface of the conductive support pattern 320. The formation of the second connection terminal 334 may include performing a solder ball attachment process. Through the above process, a semiconductor package can be manufactured.

[0067] Figure 18 A cross-sectional view of a semiconductor package according to some example embodiments is shown. Figure 19 It shows Figure 18 A magnified cross-sectional view of part C. Repeated descriptions below are brief or omitted.

[0068] Reference Figure 18 and Figure 19 The conductive pillars 310 can be disposed on the bottom surface 110b of the dielectric layer 110, and the conductive support pattern 320 can be disposed on the top surface 110a of the dielectric layer 110. That is, the conductive support pattern 320 can be disposed between the semiconductor chip 200 and the redistribution substrate 100.

[0069] The redistribution substrate 100 may include a dielectric layer 110 and a wiring pattern 120 within the dielectric layer 110. The dielectric layer 110 may be connected to a reference... Figures 1 to 2B The dielectric layer discussed is the same.

[0070] Wiring pattern 120 can be set in dielectric layer 110. For example... Figure 19 As shown, wiring pattern 120 may each include a line portion 122 and a via portion 124. The line portion 122 of wiring pattern 120 may extend in a direction parallel to one surface of dielectric pattern 112, thereby forming a circuit. Line portion 122 may have a bottom surface coplanar with the top surface of dielectric pattern 112, and may also have side surfaces and bottom surfaces surrounded by dielectric pattern 112 or second passivation layer 154.

[0071] The via portion 124 of the wiring pattern 120 can be disposed on and connected to the line portion 122 of the wiring pattern 120. The via portion 124 can be arranged closer to the bottom surface 110b of the dielectric layer 110 than the line portion 122. The width of the via portion 124 can be smaller than the width of the line portion 122. The width of the via portion 124 can decrease as the distance from the bottom surface 110b of the dielectric layer 110 decreases. The via portion 124 can penetrate at least a portion of the dielectric pattern 112 to electrically connect the line portions 122 located at different levels. In addition, the via portion 124 of the uppermost wiring pattern 120 can completely penetrate the dielectric pattern 112, thereby electrically connecting the line portion 122 to the conductive post 310.

[0072] Each of the via portions 124 and line portions 122 in each wiring pattern 120 may include a conductive layer 126 and a seed layer 128 on the conductive layer 126. The seed layer 128 may partially cover the bottom surface of the conductive layer 126 of the line portion 122. The line portion 122 of the uppermost wiring pattern 120 may have side surfaces and a bottom surface surrounded by a second passivation layer 154. A dielectric pattern 112 may surround the side surfaces and top surfaces of the conductive layer 126 of the line portion 122 included in each wiring pattern 120 except the uppermost wiring pattern 120.

[0073] The width of the conductive layer 126 of the via portion 124 can decrease as the distance from the bottom surface 110b of the dielectric layer 110 decreases. The seed layer 128 of the via portion 124 can conformally cover the bottom and side surfaces of the conductive layer 126 of the via portion 124.

[0074] like Figure 19 As shown, the conductive post 310 can be directly connected to the uppermost wiring pattern 120 of the bottom surface 110b of the dielectric layer 110. The line portion 122 of the uppermost wiring pattern 120 can be positioned on the top surface of the lowermost dielectric pattern in the dielectric pattern 112. The via portion 124 of the lowermost wiring pattern 120 can be positioned between the line portion 122 of the lowermost wiring pattern 120 and the top surface 310a of the conductive post 310.

[0075] A first insulating layer 152 may be disposed on the bottom surface 100b of the dielectric layer 110. A first passivation layer 152 may cover the bottom surface of the bottommost dielectric pattern 112. A first passivation layer 152 may cover the upper surface of the conductive pillar 310. The first passivation layer 152 may have a thickness t3 equal to or less than half the thickness t2 of the conductive pillar 310. For example, the distance d1 between the bottom surface 310b of the conductive pillar 310 and the bottom surface of the first passivation layer 152 may be greater than the thickness t3 of the first passivation layer 152.

[0076] The conductive pillar 310 can penetrate the first passivation layer 152 and can be connected to the wiring pattern 120 in the redistribution substrate 100. The conductive pillar 310 can be flat at its top surface 310a and bottom surface 310b. The top surface 310a of the conductive pillar 310 can cover the bottom surface of the bottommost dielectric pattern 112 and the bottommost surface of the seed layer 128. The top surface 310a of the conductive pillar 310 can be coplanar with the top surface of the first passivation layer 152. The top surface 310a of the conductive pillar 310 can be parallel to the bottom surface 310b of the conductive pillar 310. The via portion 124 of the bottommost wiring pattern 120 can have a bottom surface that covers a portion of the top surface 310a of the conductive pillar 310, but not the other portion. The seed layer 128 of the topmost wiring pattern 120 can have a bottom surface that is in direct contact with the bottom surface 310b of the conductive pillar 310.

[0077] The semiconductor chip 200 can be disposed on the top surface 110a of the redistribution substrate 100. The chip pad 210 can be disposed on the bottom surface of the semiconductor wafer 200.

[0078] The first connection terminal 332 can be disposed on the bottom surface 310b of the conductive post 310. The first connection terminal 332 can be electrically connected to the semiconductor chip 200 through the redistribution substrate 100, the conductive support pattern 320, and the second connection terminal 334. The spacing between the first connection terminals 332 can be greater than the spacing between the second connection terminals 334. In addition, the width of the first connection terminal 332 can be greater than the width of the second connection terminal 334. The first connection terminal 332 may include, for example, solder balls or solder bumps.

[0079] The conductive support pattern 320 can be disposed on the top surface of the second passivation layer 154. The conductive support pattern 320 can penetrate the second passivation layer 154 and can be connected to the wiring pattern 120 in the redistribution substrate 100. The conductive support pattern 320 can have a thickness t1 and an uneven shape. The conductive support pattern 320 can have a top surface and a bottom surface that are more uneven than the top surface 310a and bottom surface 310b of the conductive pillar 310. The central portion of the bottom surface of the conductive support pattern 320 can protrude toward the top surface 110a of the dielectric layer 110. The central portion of the top surface of the conductive support pattern 320 can be recessed toward the top surface 110a of the dielectric layer 110.

[0080] The second connection terminal 334 may be disposed between the chip pad 210 and the conductive support pattern 320. The second connection terminal 334 can electrically connect the conductive post 310 to the chip pad 210 of the semiconductor chip 200. The second connection terminal 334 may include, for example, solder balls or solder bumps.

[0081] The second passivation layer 154 may have a molding layer 400 disposed thereon, which covers the top surface, bottom surface, and side surface of the semiconductor chip 200. The molding layer 400 may fill the space between the semiconductor chip 200 and the second passivation layer 154. The molding layer 400 may cover a portion of the top surface of the second passivation layer 154 and the side surface of the second connection terminal 334. In addition, the molding layer 400 may cover the side surface of the conductive support pattern 320. The molding layer 400 may have a bottom surface that is in direct contact with the top surface of the second passivation layer 152.

[0082] Figure 20 and Figure 21 Cross-sectional views of some stages in a method for manufacturing a semiconductor package according to some example embodiments are shown. The repeated descriptions above will be omitted below.

[0083] Reference Figure 18 , Figure 20 and Figure 21According to some example embodiments, a semiconductor package may include a semiconductor chip 200 mounted on the top surface 110a of a dielectric layer 110, and a conductive support pattern 320 formed on the top surface 110a of the dielectric layer 110.

[0084] Figures 22 to 25 A cross-sectional view of a semiconductor package according to some example embodiments is shown.

[0085] refer to Figure 22 A semiconductor package may include a lower package 10 and an upper package 20. For example, a semiconductor package may be a stacked package (POP) on which the upper package 20 is mounted on the lower package 10.

[0086] The lower package 10 may include references Figures 1 to 2B The components discussed are similar to those in a semiconductor package. For example, the lower package 10 may include a redistribution substrate 100, a semiconductor chip 200, and a molding layer 400, and may also include connection members for connecting the semiconductor chip 200 to an external device. The connection members may include a first connection terminal 332, a conductive post 310, a second connection terminal 334, and a conductive support pattern 320. The redistribution substrate 100 may include a wiring pattern 120, some of which is disposed on an outer region of the redistribution substrate 100.

[0087] A conductive via 450 may be disposed on the redistribution substrate 100. The conductive via 450 may be disposed on an outer region of the redistribution substrate 100, and horizontally spaced from the semiconductor chip 200. The conductive via 450 may vertically penetrate the molding layer 400. The conductive via 450 may be coupled to a wiring pattern 120 disposed on the outer region of the redistribution substrate 100. The conductive via 450 may be electrically connected to the second connection terminal 334 or the semiconductor chip 200 through the redistribution substrate 100. The conductive via 450 may include a metal pillar. The conductive via 450 may include, for example, copper (Cu).

[0088] A molding layer 400 can be formed on the redistribution substrate 100 to cover the semiconductor chip 200. The molding layer 400 can cover the side surface of the conductive via 450, but may not cover the top surface of the conductive via 450. The molding layer 400 may have a top surface that is coplanar with the top surface of the conductive via 450.

[0089] The lower package 10 may further include an upper redistribution layer 500. The upper redistribution layer 500 may be disposed on the top surface of the molding layer 400 and the top surface of the conductive via 450. The upper redistribution layer 500 may include an upper dielectric layer 510 and an upper redistribution pattern 520. The upper dielectric layer 510 may include a plurality of vertically stacked upper dielectric patterns 512. The upper redistribution pattern 520 may include an upper conductive layer 526 and an upper seed layer 528 on the bottom surface of the upper conductive layer 526.

[0090] The upper pad 620 may be disposed on and coupled to the upper redistribution pattern 520. The upper pad 620 may include a conductive material, such as a metal.

[0091] The upper redistribution layer 500 may further include an upper protective layer 552. The upper protective layer 552 may cover the top surface of the upper dielectric layer 510, the top surface of the upper redistribution pattern 520, and the side surface of the upper pad 620. The upper protective layer 552 may include, for example, a dielectric polymer.

[0092] The upper package 20 can be mounted on the lower package 10. The upper package 20 may include an upper package substrate 610, an upper semiconductor chip 700, and an upper molding layer 630. For example, the upper package substrate 610 may be a printed circuit board (PCB).

[0093] The upper semiconductor chip 700 can be disposed on the upper package substrate 610. The upper semiconductor chip 700 may include an integrated circuit, which may include memory circuitry, logic circuitry, or a combination thereof. The type of the upper semiconductor chip 700 may differ from the type of the semiconductor chip 200. The upper semiconductor chip 700 may include upper chip pads 622, each upper chip pad 622 being electrically connected to a metal pad 605 via an internal line 615 in the upper package substrate 610. Figure 22 The inner line 615 is schematically shown, and various changes can be made to the shape and arrangement of the inner line 615.

[0094] The upper packaging substrate 610 may have an upper molding layer 630 covering the upper semiconductor chip 700. The upper molding layer 630 may include a dielectric polymer, such as an epoxy polymer.

[0095] The conductive terminal 624 can be disposed between the lower package 10 and the upper package 20. The conductive terminal 624 can be inserted between the upper pad 620 and the metal pad 605 and electrically connect the upper pad 620 and the metal pad 605.

[0096] Reference Figure 23 The lower package 10 of the semiconductor package may include a reference Figure 18 and Figure 19The components discussed are similar to those in a semiconductor package. For example, a conductive support pattern 320 and a second connection terminal 334 may be disposed on the top surface 110a of the dielectric layer 110. The second connection terminal 334 can electrically connect the conductive support pattern 320 to the chip pad 210 of the semiconductor chip 200. A conductive pillar 310 and a first connection terminal 332 may be disposed on the bottom surface 110b of the dielectric layer 110. Other configurations may be similar to those described in the reference. Figure 22 The configurations discussed.

[0097] Reference Figure 24 The lower package 10 may further include a connecting substrate 800 between the redistribution substrate 100 and the upper redistribution layer 500. The connecting substrate 800 may have an opening. The opening may vertically penetrate the connecting substrate 800.

[0098] The connecting substrate 800 may include a base layer 810 and a conductor 820, or may include a wiring pattern disposed in the base layer 810. The base layer 810 may be stacked vertically. The base layer 810 may include silicon oxide.

[0099] Conductor 820 may include internal pads 822, vias 824, and upper connection pads 826. A portion of the internal pads 822 may be disposed within the base layer 810 and may be connected to each other vias 408. Other internal pads 822 may be disposed adjacent to the bottom surface of the base layer 810 and may be connected to the first connection terminal 332. The vias 408 may vertically penetrate the base layer 810. The upper connection pads 826 may be disposed on the top surface of the uppermost base layer 810 and may be connected to the upper redistribution pattern 520. The upper connection pads 826 may be covered by the upper dielectric pattern 512 of the upper redistribution layer 500.

[0100] The connecting substrate 800 may have a bottom surface spaced apart from the top surface of the redistribution substrate 100. The connecting substrate 800 and the redistribution substrate 100 may be electrically connected to each other via a first connecting terminal 332 and a conductive post 310. The molding layer 400 may fill the space between the bottom surface of the connecting substrate 800 and the top surface of the redistribution substrate 100.

[0101] refer to Figure 25 The conductive support pattern 320 and the second connection terminal 334 can be disposed on the top surface 110a of the dielectric layer 110. One of the second connection terminals 334 can electrically connect the conductive support pattern 320 to the chip pad 210 of the semiconductor chip 200. Other connection terminals of the second connection terminals 334 can connect the connection substrate 800 to the redistribution substrate 100.

[0102] In summary, the high integration of semiconductor devices enables the miniaturization of pads that connect multiple stacked chips to each other. However, the miniaturization of pads requires precise alignment between the stacked chips.

[0103] Therefore, exemplary embodiments provide a semiconductor package having improved alignment accuracy between conductive structures on a redistribution layer, thereby reducing resistance and facilitating manufacturing. Specifically, according to some exemplary embodiments, preliminary bump structures and copper pillars are formed sequentially, and then redistribution lines are formed directly on the bottom surface of the copper pillars, facilitating alignment between the bump structures and the redistribution lines. Thus, a semiconductor package can be provided with improved alignment accuracy between conductive structures on a redistribution layer, thereby reducing resistance and facilitating manufacturing.

[0104] Example embodiments have been disclosed herein, and although specific terminology has been used, it is for descriptive purposes only and should be interpreted in a general descriptive sense, not for limiting purposes. In some instances, as will be appreciated by those skilled in the art upon which this application has been filed, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package, comprising: a redistribution substrate comprising a dielectric layer and a wiring pattern in the dielectric layer; and a semiconductor chip comprising a chip pad on the redistribution substrate, wherein the wiring pattern comprises: a horizontally extending line portion, and a via portion connected to the line portion, the via portion having a width smaller than a width of the line portion; a passivation layer on a top surface of the redistribution substrate, the passivation layer comprising a material different from a material of the dielectric layer; a conductive pillar penetrating the passivation layer, the conductive pillar being in direct contact with the via portion, and a distance between a top surface of the conductive pillar and a top surface of the passivation layer being larger than a thickness of the passivation layer; and a connection terminal provided between the conductive pillar and the chip pad, wherein the via portion is between the line portion and a bottom surface of the conductive pillar, a width of the via portion decreasing as a distance from the bottom surface of the conductive pillar decreases, and wherein the line portion is spaced apart from the passivation layer.

2. The semiconductor package of claim 1, wherein: the via portion comprises a conductive layer and a seed layer on the conductive layer, and the conductive pillar has a bottom surface in direct contact with the seed layer.

3. The semiconductor package of claim 1, wherein, the distance between the top surface of the conductive pillar and the top surface of the passivation layer is 2 to 5 times the thickness of the passivation layer.

4. The semiconductor package of claim 1, wherein, the bottom surface of the conductive pillar is coplanar with a bottom surface of the passivation layer.

5. The semiconductor package of claim 1, wherein, a width of the conductive pillar decreases as a distance from the wiring pattern increases.

6. The semiconductor package of claim 1, wherein, a width of the bottom surface of the conductive pillar is larger than a width of a top surface of the via portion.

7. The semiconductor package of claim 1, further comprising: a molding layer covering a portion of a side surface of the conductive pillar and a top surface of the passivation layer, a bottom surface of the molding layer being closer to the bottom surface of the conductive pillar than to the top surface of the conductive pillar.

8. The semiconductor package of claim 1, wherein, a width of the connection terminal decreases as a distance from the top surface of the conductive pillar increases.

9. The semiconductor package of claim 1, wherein, the passivation layer comprises a recess adjacent to a side surface of the conductive pillar, the recess being recessed towards the dielectric layer.

10. The semiconductor package of claim 1, further comprising: a first metal layer between the conductive pillar and the connection terminal; and a second metal layer between the conductive pillar and the first metal layer, the first metal layer comprising a material different from a material of the second metal layer.

11. A semiconductor package, comprising: a redistribution substrate comprising a dielectric layer and a wiring pattern in the dielectric layer; a passivation layer on a top surface of the dielectric layer; a conductive pillar penetrating the passivation layer and electrically connected to the wiring pattern; a semiconductor chip comprising a chip pad on the redistribution substrate; and a connection terminal provided between the conductive pillar and the chip pad, a bottom surface of the connection terminal being vertically higher than the top surface of the passivation layer, wherein the wiring pattern comprises a horizontally extending line portion and a via portion between the line portion and a bottom surface of the conductive pillar, a width of the bottom surface of the conductive pillar being larger than a width of a top surface of the via portion, ​ ​ wherein the conductive pillar is in direct contact with the via portion, wherein the via portion is between the line portion and a bottom surface of the conductive pillar, a width of the via portion decreases as a distance from the bottom surface of the conductive pillar decreases, and wherein the line portion is spaced apart from the passivation layer.

12. The semiconductor package of claim 11, wherein: the via portion includes a conductive layer and a seed layer on the conductive layer, and a bottom surface of the conductive pillar is in direct contact with the seed layer.

13. The semiconductor package of claim 11, wherein, a width at the bottom surface of the conductive pillar is 1.5 times to 5 times a width at a top surface of the via portion.

14. The semiconductor package of claim 11, wherein, the bottom surface of the conductive pillar is coplanar with a bottom surface of the passivation layer.

15. The semiconductor package of claim 11, wherein, a distance between a top surface of the conductive pillar and a top surface of the passivation layer is greater than a thickness of the passivation layer.

16. A semiconductor package, comprising: a redistribution substrate including a dielectric layer and a plurality of wiring patterns in the dielectric layer; and a semiconductor chip including a chip pad, on the redistribution substrate, each of the wiring patterns includes a horizontally-extending line portion and a via portion on the line portion, a width of the via portion is less than a width of the line portion; a first passivation layer on a top surface of the dielectric layer; a conductive pillar that penetrates the first passivation layer and is in direct contact with the via portion; a first connection terminal on a top surface of the conductive pillar; a second passivation layer on a bottom surface of the dielectric layer, the second passivation layer covering a bottom surface and side surfaces of the line portion; a conductive support pattern that penetrates the second passivation layer and is connected to the line portion, a thickness of the conductive pillar is greater than a thickness of the conductive support pattern; and a second connection terminal on a bottom surface of the conductive support pattern, wherein the via portion is between the line portion and a bottom surface of the conductive pillar, a width of the via portion decreases as a distance from the bottom surface of the conductive pillar decreases, and wherein the line portion is spaced apart from the first passivation layer.

17. The semiconductor package of claim 16, wherein, the thickness of the conductive pillar is 2 times to 4 times the thickness of the conductive support pattern.

18. The semiconductor package of claim 16, wherein: the conductive pillar has a flat bottom surface, and a top surface of the conductive support pattern is more uneven than the bottom surface of the conductive pillar.

19. The semiconductor package of claim 16, wherein, the conductive support pattern includes a first conductive pattern and a second conductive pattern, the second conductive pattern is between the first conductive pattern and the second connection terminal, the first conductive pattern includes a material different from a material of the second conductive pattern.

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