Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate structure; forming a first channel hole in the substrate structure; forming a third protective layer on the sidewall of the first sacrificial layer exposed by the first channel hole; forming a second sacrificial layer in the first channel hole; forming a first stack structure; forming a second channel hole in the first stack structure, the second channel hole vertically penetrating the first stack structure, and the orthographic projection of the second channel hole on the bottom dielectric layer is located in the first channel hole; removing the second sacrificial layer; forming a channel structure in the first channel hole and the second channel hole, the channel structure comprising a channel layer and a storage stack surrounding the outer side surface and the outer bottom surface of the channel layer; wherein the size of the bottom of the channel structure in the horizontal direction is greater than the size of the part of the channel structure located in the first stack structure.

Description

[0001] This application is a divisional application of the patent filed on October 21, 2020, with application number 202011134486.X, entitled "A Three-Dimensional Memory and a Method for Manufacturing the Same". Technical Field

[0002] This invention belongs to the field of semiconductor integrated circuit technology and relates to a three-dimensional memory and its fabrication method. Background Technology

[0003] Sidewall polysilicon (SWP) structures avoid the challenges of silicon-oxide-nitride-oxide (SONO) etching that arises with increasing layer counts in 3D Nand. However, after removing the bottom polysilicon sacrificial layer (SAC poly) and the ONO layer, the support between the core and dummy regions faces significant challenges due to the smaller channel apertures. Furthermore, with higher memory structure layer counts, the bottom of the channel holes is more prone to deformation during formation, leading to poorer uniformity below the channel holes (uneven spacing between channel holes), thus affecting the fill process window after the polysilicon sacrificial layer removal. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional memory and its manufacturing method, which solves the problem that the support of the core area and the virtual area faces great challenges after the bottom sacrificial layer is removed in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a three-dimensional memory, comprising the following steps:

[0006] A substrate structure is provided, wherein the substrate structure comprises, from bottom to top, a first protective layer, a first sacrificial layer, a second protective layer and a bottom dielectric layer;

[0007] A first channel hole is formed in the substrate structure, and the first channel hole penetrates the bottom dielectric layer, the second protective layer, the first sacrificial layer and the first protective layer vertically.

[0008] A third protective layer is formed on the sidewall of the first sacrificial layer exposed by the first channel hole;

[0009] A second sacrificial layer is formed in the first channel hole;

[0010] A first stacked structure is formed above the bottom dielectric layer, the first stacked structure comprising alternately stacked gate sacrificial layers and dielectric layers;

[0011] A second channel hole is formed in the first stacked structure, the second channel hole penetrates the first stacked structure vertically, and the orthographic projection of the second channel hole on the bottom dielectric layer is located inside the first channel hole;

[0012] Remove the second sacrificial layer;

[0013] A channel structure is formed in the first channel hole and the second channel hole. The channel structure includes a channel layer and a storage stack surrounding the outer side and the outer bottom surface of the channel layer. The bottom of the channel structure occupies a larger dimension in the horizontal direction than the portion of the channel structure located in the first stack structure.

[0014] Optionally, after forming the second channel aperture and before removing the second sacrificial layer, the following steps are further included:

[0015] A third sacrificial layer is formed in the second channel hole;

[0016] A second stacked structure is formed on top of the first stacked structure, the second stacked structure comprising the gate sacrificial layer and the dielectric layer stacked alternately;

[0017] A third channel hole is formed in the second stacked structure, the third channel hole penetrates the second stacked structure vertically, and the orthographic projection of the third channel hole on the first stacked structure is located inside the second channel hole;

[0018] Remove the third sacrificial layer;

[0019] Furthermore, when the channel structure is formed after removing the third sacrificial layer and the second sacrificial layer, the channel structure is also formed within the third channel hole.

[0020] Optionally, the following steps are also included:

[0021] A grid line gap is formed, which penetrates the first stacked structure vertically and extends at least downward into the first sacrificial layer;

[0022] A sidewall protective layer is formed on the sidewall of the grid wire slot;

[0023] Remove the first sacrificial layer to obtain the bottom transverse gap;

[0024] A portion of the storage stack is removed via the bottom lateral slot to expose a portion of the channel layer, and the first protective layer and the second protective layer are removed;

[0025] A bottom polycrystalline silicon layer is formed in the bottom lateral slot;

[0026] Remove the gate sacrificial layer to obtain multiple gate lateral slots;

[0027] A conductive layer is formed in the lateral gap of the gate;

[0028] An array common source structure is formed in the gate line gap.

[0029] Optionally, the substrate structure includes: a substrate; wherein the first protective layer is located between the substrate and the first sacrificial layer; before forming the first channel via, a groove is provided in the substrate, the first protective layer and the first sacrificial layer fill the groove, and the orthogonal projection of the gate line slot on the substrate is located within the groove.

[0030] Optionally, after forming the bottom polysilicon layer and before removing the gate sacrificial layer, the step of forming a bottom epitaxial layer in the trench is further included.

[0031] Optionally, the bottom epitaxial layer comprises, from bottom to top, an N-type epitaxial silicon layer and an N-type polycrystalline silicon layer.

[0032] Optionally, the three-dimensional memory includes a stepped region. Before forming the first stacked structure, the fabrication method further includes the step of forming an annular groove in the stepped region, the annular groove penetrating vertically through the first sacrificial layer and the first protective layer; in the step of forming the third protective layer, the third protective layer is also formed on the sidewall of the first sacrificial layer exposed by the annular groove; in the step of forming the second sacrificial layer in the first channel hole, the second sacrificial layer is also formed in the annular groove; in the step of removing the first sacrificial layer to obtain the bottom transverse gap, the portion of the first sacrificial layer surrounded by the annular groove is not removed.

[0033] Optionally, the annular groove is in the form of a polygonal ring, a circular ring, or an elliptical ring.

[0034] Optionally, the manufacturing method further includes the step of forming a plurality of dummy channel holes in the stepped area.

[0035] Optionally, at least one of the dummy channel holes is located within the surrounding area of ​​the annular groove;

[0036] And / or,

[0037] At least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove.

[0038] The present invention also provides a three-dimensional memory, comprising:

[0039] Bottom polycrystalline silicon layer;

[0040] A bottom dielectric layer is located on the bottom polysilicon layer;

[0041] Multiple conductive layers are stacked on top of the bottom dielectric layer, and a dielectric layer is provided between adjacent conductive layers;

[0042] The channel structure extends vertically through multiple conductive layers and dielectric layers, and downward through the bottom polysilicon layer. The channel structure includes a channel layer and a memory stack surrounding the outer side and bottom surface of the channel layer. The bottom polysilicon layer extends laterally through the memory stack to connect with the channel layer.

[0043] The bottom of the channel structure occupies a larger dimension in the horizontal direction than the portion of the channel structure located in the conductive layer.

[0044] Optionally, the bottom of the channel structure includes:

[0045] The portion of the channel structure located in the bottom dielectric layer;

[0046] A portion of the channel structure located in the substrate; wherein the bottom polysilicon layer is located between the substrate and the bottom dielectric layer.

[0047] Optionally, the portion of the channel structure located in the plurality of conductive layers and dielectric layers is divided into at least two segments, wherein the width of the upper segment of the channel structure is smaller than the width of the lower segment.

[0048] Optionally, the three-dimensional memory includes:

[0049] Substrate; wherein the bottom polysilicon layer is located between the substrate and the bottom dielectric layer;

[0050] The step region has an annular groove structure that penetrates the bottom polysilicon layer vertically and extends downward into the substrate.

[0051] Optionally, the annular groove structure is in the form of a polygonal ring, a circular ring, or an elliptical ring.

[0052] Optionally, the stepped area is provided with multiple dummy channel hole structures.

[0053] Optionally, at least one of the dummy channel hole structures is located within the surrounding area of ​​the annular groove structure;

[0054] And / or,

[0055] At least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove structure.

[0056] The present invention also provides another three-dimensional memory, comprising:

[0057] Bottom polycrystalline silicon layer;

[0058] A bottom dielectric layer is located on the bottom polysilicon layer;

[0059] Multiple conductive layers are stacked on top of the bottom dielectric layer, and a dielectric layer is provided between adjacent conductive layers;

[0060] The channel structure extends vertically through multiple conductive layers and dielectric layers, and downward through the bottom polysilicon layer. The channel structure includes a channel layer and a memory stack surrounding the outer side and bottom surface of the channel layer. The bottom polysilicon layer extends laterally through the memory stack to connect with the channel layer.

[0061] The channel structure includes a protrusion at the bottom that extends along the direction of the bottom polysilicon layer.

[0062] Optionally, the channel structure includes a protrusion at the bottom extending along the direction of the bottom polysilicon layer, comprising:

[0063] The protrusion is located in the bottom dielectric layer, the bottom polysilicon layer, and the substrate; wherein the bottom polysilicon layer is located between the substrate and the bottom dielectric layer.

[0064] Optionally, the portion of the channel structure located in the plurality of conductive layers and dielectric layers is divided into at least two segments, wherein the width of the upper segment of the channel structure is smaller than the width of the lower segment.

[0065] Optionally, the three-dimensional memory includes:

[0066] Substrate; wherein the bottom polysilicon layer is located between the substrate and the bottom dielectric layer;

[0067] The step region has an annular groove structure that penetrates the bottom polysilicon layer vertically and extends downward into the substrate.

[0068] Optionally, the stepped area is provided with multiple dummy channel hole structures.

[0069] Optionally, at least one of the dummy channel hole structures is located within the surrounding area of ​​the annular groove structure;

[0070] And / or,

[0071] At least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove structure.

[0072] Optionally, the three-dimensional memory further includes an array common source structure, which extends vertically through multiple conductive layers, multiple dielectric layers, and the bottom dielectric layer.

[0073] As described above, the three-dimensional memory and its fabrication method of the present invention first perform bottom etching at the channel hole location to form the lower portion of the channel hole, then oxidize the sidewalls of the first sacrificial layer, fill the hole with a second sacrificial layer, and then form a stacked structure to form the upper portion of the channel hole. The larger lower portion of the channel hole can improve the support capacity of the core region and dummy region after the bottom sacrificial layer is removed, and also result in less deformation at the bottom of the channel hole in the core region and a more uniform distribution of holes. This is beneficial for improving the filling process window after the bottom sacrificial layer is removed, and can directly form a deeper silicon trench (sigouging) at the bottom, avoiding the expansion of the critical size at the top of the channel hole caused by the formation of the silicon trench after the channel hole is etched. In addition, the dummy region can be further annularly grooved during bottom etching, which can prevent the middle region surrounded by the annular groove from being removed during the bottom sacrificial layer removal, thereby greatly improving the support capacity of the core region and dummy region during the bottom sacrificial layer removal. Attached Figure Description

[0074] Figure 1 The diagram shown illustrates the process flow of the fabrication method for the three-dimensional memory of this invention.

[0075] Figure 2 The diagram shows a schematic of a base structure.

[0076] Figure 3 The diagram shows the formation of the first channel hole in the substrate structure.

[0077] Figure 4 The diagram shows a sidewall exposed by the first channel hole, forming a third protective layer on top of the first sacrificial layer.

[0078] Figure 5 The diagram shows the formation of a second sacrificial layer in the first channel hole.

[0079] Figure 6 This diagram shows the removal of the second sacrificial layer above the bottom dielectric layer.

[0080] Figure 7 The diagram shows the formation of the first stacked structure above the bottom dielectric layer.

[0081] Figure 8 The diagram shows the formation of a second channel hole in the first stacked structure.

[0082] Figure 9 Displayed as a pair Figure 8 The diagram shows the post-etching processing of the structure shown.

[0083] Figure 10 The diagram shows the formation of a third sacrificial layer in the second channel hole.

[0084] Figure 11The diagram shows the removal of the third sacrificial layer above the first stacked structure.

[0085] Figure 12 The diagram shows a second layered structure formed on top of the first layered structure.

[0086] Figure 13 The diagram shows the formation of a third channel hole in the second stacked structure.

[0087] Figure 14 The diagram shows a polycrystalline silicon pad layer formed on the sidewall surface of the third channel hole.

[0088] Figure 15 Displayed as a pair Figure 14 The diagram shows the post-etching processing of the structure shown.

[0089] Figure 16 The diagram shows the removal of the second and third sacrificial layers.

[0090] Figure 17 The diagram shows the formation of a channel structure in the first, second, and third channel holes.

[0091] Figure 18 This diagram illustrates the further deposition of a capping layer over the stacked structure to cover the channel structure.

[0092] Figure 19 The diagram shows the deposition of the sidewall protective layer within the grid gaps and above the stacked structure.

[0093] Figure 20 The diagram shows the removal of the portion of the sidewall protective layer at the bottom of the grid line gap to expose at least a portion of the first sacrificial layer, and the removal of the portion of the sidewall protective layer above the stacked structure.

[0094] Figure 21 The diagram shows the bottom horizontal gap obtained after removing the first sacrificial layer.

[0095] Figure 22 This diagram illustrates the removal of the barrier layer from the storage stack along the sidewall of the bottom transverse slot.

[0096] Figure 23 The diagram shows the removal of the alumina layer from the sidewall protective layer.

[0097] Figure 24 This diagram illustrates the removal of the storage layer and tunneling layer from the exposed storage stack.

[0098] Figure 25 The image shows a schematic diagram of the surface with pre-cleaned bottom horizontal seams.

[0099] Figure 26The diagram shows a polycrystalline silicon layer deposited at the bottom in the bottom horizontal gap.

[0100] Figure 27 This diagram illustrates the process of etching back the polysilicon material above the gate line gaps and the capping layer to remove the sidewalls.

[0101] Figure 28 The diagram shows the continued formation of the bottom epitaxial layer in the groove.

[0102] Figure 29 This diagram illustrates the further removal of the silicon oxide layer from the sidewall protective layer.

[0103] Figure 30 The diagram shows the result of removing the gate sacrificial layer, resulting in multiple gate lateral gaps.

[0104] Figure 31 The diagram shows the formation of a conductive layer in the lateral gap of the gate.

[0105] Figure 32 The diagram shows a sidewall forming an isolation sidewall in the gap of the grid lines.

[0106] Figure 33 The diagram shows the removal of the portion of the isolation sidewall located above the cover layer, and the removal of the isolation sidewall and the alumina layer located in the middle of the bottom of the grid line gap 23.

[0107] Figure 34 The conductive portion is shown as forming an array common source structure.

[0108] Figure 35 Displayed as a planar layout diagram of the three-dimensional memory.

[0109] Figure 36 Displayed as Figure 35 A-A' sectional view.

[0110] Component designation explanation

[0111] Steps S1-S8; 1 Substrate; 2 First Protective Layer; 3 First Sacrificial Layer; 4 Second Protective Layer; 5 Bottom Dielectric Layer; 6 Trench; 7 First Channel Via; 8 Third Protective Layer; 9 Second Sacrificial Layer; 10 Gate Sacrificial Layer; 11 Dielectric Layer; 12 Second Channel Via; 13 Third Sacrificial Layer; 14 Third Channel Via; 15 Polysilicon Pad Layer; 16 Channel Layer; 17 Barrier Layer; 18 Storage Layer; 19 Tunneling Layer; 20 Filler Material; 21 Semiconductor Contact; 22 Cover Layer; 23 Gate Line Gap; 24 First Silicon Nitride Layer; 25 Silicon Oxide Layer; 26 Second Silicon Nitride Layer; 27 Alumina Layer; 28 Bottom Lateral Gap; 29 Bottom Polysilicon Layer; 30 N-type Epitaxial Silicon Layer; 31 N-type polysilicon layer; 32 gate lateral gap; 33 gate material layer; 34 aluminum oxide layer; 35 titanium nitride layer; 36 isolation sidewall; 37 titanium nitride layer; 38 dielectric layer; 39 tungsten layer; 40 annular groove; 41 dummy channel hole; I core region; II step region. Detailed Implementation

[0112] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0113] Please see Figures 1 to 36 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0114] Example 1

[0115] This invention provides a method for fabricating a three-dimensional memory. Please refer to [link / reference]. Figure 1 The diagram shows the process flow of this method, which includes the following steps:

[0116] S1: A substrate structure is provided, wherein the substrate structure comprises, from bottom to top, a substrate, a first protective layer, a first sacrificial layer, a second protective layer and a bottom dielectric layer;

[0117] S2: A first channel hole is formed in the substrate structure, the first channel hole penetrating vertically through the bottom dielectric layer, the second protective layer, the first sacrificial layer and the first protective layer, and extending downward into the substrate;

[0118] S3: Form a third protective layer on the sidewall of the first sacrificial layer exposed by the first channel hole;

[0119] S4: A second sacrificial layer is formed in the first channel hole;

[0120] S5: A first stacked structure is formed above the bottom dielectric layer, the first stacked structure comprising alternately stacked gate sacrificial layers and dielectric layers;

[0121] S6: A second channel hole is formed in the first stacked structure. The second channel hole penetrates the first stacked structure vertically, and the orthographic projection of the second channel hole on the bottom dielectric layer is located inside the first channel hole.

[0122] S7: Remove the second sacrificial layer;

[0123] S8: Form a channel structure in the first channel hole and the second channel hole, the channel structure including a channel layer and a storage stack surrounding the outer side and the outer bottom surface of the channel layer.

[0124] Please refer to the following first. Figure 2 Step S1: Provide a substrate structure, which includes, from bottom to top, a substrate 1, a first protective layer 2, a first sacrificial layer 3, a second protective layer 4, and a bottom dielectric layer 5.

[0125] As an example, substrate 1 includes, but is not limited to, Si substrate, Ge substrate, SiGe substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc., and substrate 1 can be P-type doped or N-type doped; first protective layer 2 is used to protect the surface of substrate 1, and first protective layer 2 includes, but is not limited to, silicon oxide layer; first sacrificial layer 3 includes, but is not limited to, polysilicon layer; second protective layer 4 is used to protect bottom dielectric layer 5, and second protective layer 4 includes, but is not limited to, silicon nitride layer; bottom dielectric layer 5 includes, but is not limited to, silicon oxide layer.

[0126] As an example, in order to expand the process window for the subsequent formation of gate line slots, a groove 6 is provided in the substrate, and the first protective layer 2 and the first sacrificial layer 3 are filled into the groove 6, wherein the orthogonal projection of the subsequently formed gate line slots on the substrate 1 is located in the groove 6.

[0127] Please see again Figure 3 Step S2: Form a first channel hole 7 in the substrate structure. The first channel hole 7 penetrates the bottom dielectric layer 5, the second protective layer 4, the first sacrificial layer 3 and the first protective layer 2 from top to bottom, and extends downward into the substrate 1.

[0128] As an example, the first channel hole 7 is formed by one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)).

[0129] Specifically, the first channel hole 7, as the lower part of the overall channel hole, is larger in size than the upper part of the subsequently formed overall channel hole. Forming the larger lower part of the channel hole in this step improves the support capacity of the core and dummy areas after the removal of the bottom sacrificial layer. Furthermore, since the depth of the first channel hole 7 is much smaller than the depth of the overall channel hole, compared to directly forming a very deep channel hole, this step offers more precise photolithography and etching accuracy. This results in less deformation at the bottom of the channel hole in the core area and a more uniform hole distribution, which is beneficial for improving the filling process window after the removal of the bottom sacrificial layer. Additionally, a deeper silicon gouging (recess 6) can be directly formed, avoiding the expansion of the critical dimension at the top of the channel hole during the formation of the silicon gouging after the channel hole etching process.

[0130] Please see again Figure 4 Step S3: Form a third protective layer 8 on the sidewall of the first sacrificial layer 3 exposed by the first channel hole 7.

[0131] As an example, a third protective layer 8 is formed using a thermal oxidation method. The third protective layer 8 includes a silicon oxide layer. The third protective layer 8 is used to protect the sidewalls of the first sacrificial layer 3 exposed by the first channel via 7.

[0132] Please see again Figure 5 and Figure 6 Step S4: Form a second sacrificial layer 9 in the first channel hole 7.

[0133] As an example, such as Figure 5 As shown, a second sacrificial layer 9 is formed in the first channel hole 7 using at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and then... Figure 6 As shown, the second sacrificial layer 9 above the bottom dielectric layer 5 is removed using chemical mechanical polishing. The second sacrificial layer 9 includes, but is not limited to, a polysilicon layer.

[0134] Please see again Figure 7 Step S5: Form a first stacked structure above the bottom dielectric layer 5. The first stacked structure includes alternately stacked gate sacrificial layers 10 and dielectric layers 11.

[0135] As an example, at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) is used to form a gate sacrificial layer 10 and a dielectric layer 11, wherein the gate sacrificial layer 10 includes, but is not limited to, a silicon nitride layer, and the dielectric layer 11 includes, but is not limited to, a silicon oxide layer.

[0136] Please see again Figure 8 Step S6: Form a second channel hole 12 in the first stacked structure. The second channel hole 12 penetrates the first stacked structure vertically, and the orthogonal projection of the second channel hole 12 on the bottom dielectric layer 5 is located in the first channel hole 7.

[0137] As an example, the second channel hole 12 is formed by one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)).

[0138] In this embodiment, as Figure 9 As shown, it also includes a post-etching process (PET).

[0139] It should be noted that if, excluding the depth of the first channel hole 7, the remaining part of the overall channel hole is relatively easy to manufacture in one step, then the subsequent step S7 is performed. That is, the overall channel hole is manufactured in two steps, and is composed of the first channel hole 7 and the second channel hole 12. However, if, excluding the depth of the first channel hole 7, the remaining part of the overall channel hole is difficult to manufacture in one step, then the remaining part of the overall channel hole can be manufactured in at least two steps, i.e., the overall channel hole is manufactured in three steps, and is composed of the first channel hole 7, the second channel hole 12, and subsequently formed third or even more channel holes. Taking the three-step manufacturing of the overall channel hole as an example, after forming the second channel hole 12, the following steps are performed:

[0140] (1) As Figure 10 As shown, a third sacrificial layer 13 is formed in the second channel hole 12 using at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and as... Figure 11 As shown, the third sacrificial layer 13 above the first stacked structure is removed by chemical mechanical polishing. The third sacrificial layer 13 includes, but is not limited to, a polysilicon layer.

[0141] (2) Figure 12 As shown, a second stacked structure is formed on top of the first stacked structure using a method substantially the same as that used to form the first stacked structure. The second stacked structure includes alternating stacked gate sacrificial layers 10 and dielectric layers 11.

[0142] (3) Figure 13 As shown, a third channel hole 14 is formed in the second stacked structure by one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)). The third channel hole 14 extends vertically through the second stacked structure, and the orthogonal projection of the third channel hole 14 on the first stacked structure is located within the second channel hole 12.

[0143] In this embodiment, as Figure 14 As shown, a polysilicon pad layer 15 is further formed on the sidewall surface of the third channel hole 14 to protect the sidewall of the third channel hole 14, and as... Figure 15 As shown, post-etching processing is performed.

[0144] (4) Figure 16 As shown, the third sacrificial layer 13 is removed using a wet etching process and / or a dry etching process.

[0145] It should be noted that the first channel hole 7, the second channel hole 12, and the third channel hole 14 are ideally coaxial. However, due to limitations in actual manufacturing processes, the central axes of the first channel hole 7, the second channel hole 12, and the third channel hole 14 may not coincide. This should not excessively limit the scope of protection of the present invention.

[0146] As an example, the diameter of the first channel hole 7 is larger than the diameter of the second channel hole 12, and the diameter of the second channel hole 12 is larger than the diameter of the third channel hole 14.

[0147] Please see again Figure 16 Step S7: Remove the second sacrificial layer 9 using a wet etching process and / or a dry etching process.

[0148] Specifically, as mentioned earlier, if the integral channel hole is manufactured in two steps, the second sacrificial layer 9 is removed separately. However, if the integral channel hole is manufactured in three steps, the second sacrificial layer 9 can be removed during the removal of the third sacrificial layer 13.

[0149] Specifically, during the removal of the second sacrificial layer 9 and / or the third sacrificial layer 13, the polysilicon pad layer 15 is also removed.

[0150] Please see again Figure 17 Step S8: Form a channel structure in the first channel hole 7 and the second channel hole 12. The channel structure includes a channel layer 16 and a storage stack surrounding the outer side and bottom surface of the channel layer 16.

[0151] In this embodiment, the channel structure is also formed within the third channel hole 14.

[0152] Specifically, forming the vertical channel structure includes the following steps:

[0153] Step S8-1: The storage stack is formed on the sidewalls and bottom surface of the channel via using at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The storage stack, radially from the outside to the inside of the channel via, sequentially includes a barrier layer 17, a storage layer 18, and a tunneling layer 19. The barrier layer 17 includes, but is not limited to, at least one of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. The storage layer 18 includes, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon layer. The tunneling layer 19 includes, but is not limited to, at least one of a silicon oxide layer and a silicon oxynitride layer.

[0154] Step S8-2: Form a channel layer 16 on the surface of the memory stack using at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The channel layer 16 includes, but is not limited to, at least one of polycrystalline silicon, monocrystalline silicon, and amorphous silicon layers.

[0155] As an example, a filler material 20 (silicon oxide or other dielectric material) can be further deposited in the remaining space of the channel hole to completely or partially fill the channel hole, and a semiconductor contact 21 can be further formed on the upper part of the channel hole. The semiconductor contact 21 is made of, but is not limited to, polysilicon, and is connected to the channel layer 16. To protect the vertical channel structure, such as... Figure 18 As shown, a capping layer 22 (e.g., a silicon oxide layer) can be further deposited over the stacked structure to cover the channel structure.

[0156] Furthermore, it also includes the following steps:

[0157] See Figure 18 The gate line slots 23 are formed using a wet etching process and / or a dry etching process (e.g., DRIE). The gate line slots 23 penetrate the first stacked structure vertically and extend at least downward into the first sacrificial layer 3. In this embodiment, the gate line slots 23 also penetrate the cover layer 22 and the second stacked structure vertically.

[0158] Specifically, since the substrate 1 has a groove 6, the process window for forming the gate line gap 23 is expanded. The bottom of the gate line gap 23 can not only stay above the top surface of the substrate 1, but also stay below the top surface of the substrate 1.

[0159] Please see Figures 19-20 A sidewall protective layer is formed on the sidewall of the gate line slot 23 to protect the sidewall of the stacked structure exposed by the gate line slot from damage during subsequent etching processes.

[0160] Specifically, such as Figure 19As shown, the sidewall protective layer is first deposited within the gate wire gaps and above the stacked structure. This sidewall protective layer can be a multi-layered composite layer to ensure it is not completely removed during subsequent etching processes, thus continuously providing protection for the sidewalls of the stacked structure. In this embodiment, the sidewall protective layer, radially outward from the gate wire gaps, comprises a first silicon nitride layer 24, a silicon oxide layer 25, a second silicon nitride layer 26, and an aluminum oxide layer 27. Of course, in other embodiments, the composition of the sidewall protective layer can be adjusted as needed, and this should not unduly limit the scope of protection of the present invention.

[0161] like Figure 20 As shown, the portion of the sidewall protective layer located at the bottom of the grid line gap 23 is removed to expose at least a portion of the first sacrificial layer 3, and the portion of the sidewall protective layer located above the stacked structure is also removed.

[0162] Please see Figure 21 The first sacrificial layer 3 is removed by wet etching and / or dry etching processes to obtain the bottom transverse gap 28.

[0163] Please see Figures 22 to 24 A portion of the storage stack is removed via the bottom transverse slit 28 to expose a portion of the channel layer 16, and the first protective layer 2 and the second protective layer 4 are removed.

[0164] As an example, such as Figure 22 As shown, firstly, the barrier layer 17 in the storage stack is removed along the sidewall of the bottom transverse gap 28, wherein the third protective layer 8 and the first protective layer 2 are removed simultaneously, and then as follows... Figure 23 As shown, the aluminum oxide layer 27 in the sidewall protective layer is removed, and then... Figure 24 As shown, the storage layer 18 and tunneling layer 19 in the exposed storage stack are then removed (e.g., Figure 11 As shown in the figure, the second protective layer 4 is removed simultaneously, and the portion of the first silicon nitride layer 24 in the sidewall protective layer below the bottom dielectric layer 5 and the second silicon nitride layer 26 are also removed simultaneously.

[0165] Please see Figure 25 The surface of the bottom transverse gap 28 is pre-cleaned, and in this process, the portion of the sidewall protective layer protruding into the bottom transverse gap is also removed.

[0166] Please see Figure 26 and Figure 27 A bottom polysilicon layer 29 is deposited in the bottom lateral slot 28 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. During this process, polysilicon material (such as...) is also deposited on the sidewalls of the gate slot 23 and above the capping layer 22. Figure 26(As shown). Then, an etch-back process is performed to remove the sidewalls of the gate gap 23 and the polysilicon material above the capping layer 22 (as shown). Figure 27 (As shown).

[0167] As an example, if a groove 6 is formed in the substrate 1, then in the above-mentioned etch-back step, the polycrystalline silicon material on the sidewalls and bottom surface of the groove 6 is removed simultaneously.

[0168] For example, please refer to Figure 28 The bottom epitaxial layer is then formed in the groove 6. In this embodiment, the bottom epitaxial layer includes, from bottom to top, an N-type epitaxial silicon layer 30 and an N-type polysilicon layer 31.

[0169] Please see Figure 29 Further, the silicon oxide layer 25 in the sidewall protective layer is removed.

[0170] Please see Figure 30 The gate sacrificial layer is removed by wet etching and / or dry etching processes to obtain multiple gate lateral slots 32.

[0171] Please see Figure 31 A conductive layer is formed in the lateral slot 32 of the gate.

[0172] Specifically, an adhesion layer and a gate material layer 33 are sequentially deposited in the gate lateral gap 32 as the conductive layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The adhesion layer includes, but is not limited to, at least one of a high-k dielectric material layer (e.g., alumina), a TiN layer, a Ti layer, a Ta layer, and a TaN layer. The gate material layer 33 includes, but is not limited to, a tungsten layer. In this embodiment, the adhesion layer is selected as an alumina layer 34 and a titanium nitride layer 35.

[0173] Please see Figures 32 to 34 An array common source structure is formed in the gate line gap 23.

[0174] As an example, such as Figure 32 As shown, first form the isolation sidewall 36 on the sidewall of the grid line gap 23, then as... Figure 33 As shown, the portion of the isolation sidewall 36 located above the cover layer 22 is removed, and the portion of the isolation sidewall 36 and the alumina layer 34 located in the middle of the bottom of the gate gap 23 is also removed to expose the bottom polysilicon layer 29 (or the bottom epitaxial layer), and so on. Figure 34As shown, the conductive portion of the array common source structure is formed. As an example, the conductive portion of the array common source structure includes a titanium nitride layer 37, a dielectric layer 38 (e.g., polycrystalline silicon) encapsulated in the titanium nitride layer 37, and a tungsten layer 39 located above the dielectric layer 38. The bottom and sidewalls of the tungsten layer 39 are encapsulated by the titanium nitride layer 37 to prevent tungsten diffusion.

[0175] Thus, a three-dimensional memory has been fabricated. In this embodiment, the fabrication method of the three-dimensional memory first performs bottom etching at the channel hole location to form the lower part of the channel hole. Then, the sidewall of the first sacrificial layer is oxidized, and the hole is filled with a second sacrificial layer. Then, a stacked structure is formed, and the upper part of the channel hole is formed. The larger lower part of the channel hole can improve the support capacity of the core area and dummy area after the bottom sacrificial layer is removed. On the other hand, it makes the bottom deformation of the channel hole in the core area less and the distribution of holes more uniform. This is beneficial to improve the filling process window after the bottom sacrificial layer is removed. It can directly form a deeper silicon gouging at the bottom and avoid the expansion of the critical size at the top of the channel hole caused by the formation of silicon gouging after the channel hole is etched.

[0176] Example 2

[0177] This embodiment uses the same technical solution as Embodiment 1. The difference is that, before forming the first stacked structure, this embodiment also includes the step of forming an annular groove in the step area of ​​the three-dimensional memory.

[0178] Please see Figure 35 and Figure 36 ,in, Figure 35 The diagram shows a planar layout of the three-dimensional memory. Figure 36 Displayed as Figure 35 A-A' profile.

[0179] Specifically, the three-dimensional memory is divided into a core region I and a step region II. In this embodiment, before forming the first stacked structure, the step of forming an annular groove 40 in the step region II is further included. The annular groove 40 penetrates the first sacrificial layer 3 and the first protective layer 2 vertically and extends downward into the substrate 1. In the step of forming the third protective layer 8, the third protective layer 8 is also formed on the sidewall of the first sacrificial layer 3 exposed by the annular groove 40. In the step of forming the second sacrificial layer 9 in the first channel hole 7, the second sacrificial layer 9 is also formed in the annular groove 40. In the step of removing the first sacrificial layer 3 to obtain the bottom transverse gap, the portion of the first sacrificial layer 3 surrounded by the annular groove 40 is not removed.

[0180] As an example, the annular groove 40 may be a polygonal ring, a circular ring, an elliptical ring, or other suitable shape.

[0181] As an example, the step of forming a plurality of dummy channel holes 41 in the stepped area II is also included.

[0182] As an example, at least one of the dummy channel holes is located within the surrounding area of ​​the annular groove 40 and / or at least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove 40.

[0183] The fabrication method of the three-dimensional memory in this embodiment further forms an annular groove in the dummy area (located in the step area) during bottom etching. This can prevent the middle area surrounded by the annular groove from being removed when the bottom sacrificial layer is removed, thereby greatly improving the support capacity of the core area and the dummy area when the bottom sacrificial layer is removed.

[0184] Example 3

[0185] This embodiment provides a three-dimensional memory. Please refer to [link / reference]. Figure 34 The diagram shows a cross-sectional view of the three-dimensional memory, including a substrate 1, a bottom polysilicon layer 29, a bottom dielectric layer 5, multiple conductive layers, a channel structure, and an array common source structure. The bottom polysilicon layer 29 is located on the substrate 1. Multiple conductive layers are stacked above the bottom dielectric layer 5, with a dielectric layer 11 between adjacent conductive layers. The channel structure extends vertically through the multiple conductive layers and the dielectric layer 11, and downwards into the substrate 1. The channel structure includes a channel layer 16 and a memory stack surrounding the outer side and bottom surface of the channel layer. The bottom polysilicon layer 29 extends laterally through the memory stack to connect with the channel layer 16. The width of the portion of the channel structure located in the bottom dielectric layer 5, the bottom polysilicon layer 29, and the substrate 1 is greater than the width of the portion of the channel structure located in the conductive layers. The array common source structure extends vertically through the multiple conductive layers, the multiple dielectric layers 11, and the bottom dielectric layer 5.

[0186] As an example, the channel structure located in a portion of the plurality of conductive layers and dielectric layers 11 is divided into at least two segments, wherein the width of the upper segment of the channel structure is smaller than the width of the lower segment.

[0187] As an example, substrate 1 includes, but is not limited to, Si substrate, Ge substrate, SiGe substrate, silicon-on-insulator (SOI) substrate or germanium-on-insulator (GOI) substrate, etc., and substrate 1 can be P-type doped or N-type doped.

[0188] As an example, the dielectric layer 11 includes, but is not limited to, a silicon oxide layer, and the conductive layer includes an adhesion layer and a gate material layer 33. The adhesion layer includes, but is not limited to, at least one of a high-k dielectric material layer (e.g., aluminum oxide), a TiN layer, a Ti layer, a Ta layer, and a TaN layer, and the gate material layer 33 includes, but is not limited to, a tungsten layer. In this embodiment, the adhesion layer is selected from an aluminum oxide layer 34 and a titanium nitride layer 35.

[0189] As an example, the memory stack includes, from the outside to the inside in the radial direction of the channel via, a barrier layer 17, a memory layer 18, and a tunneling layer 19. The barrier layer 17 includes, but is not limited to, at least one of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. The memory layer 18 includes, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, and a silicon layer. The tunneling layer 19 includes, but is not limited to, at least one of a silicon oxide layer and a silicon oxynitride layer. The channel layer 16 includes, but is not limited to, at least one of a polycrystalline silicon layer, a monocrystalline silicon layer, and an amorphous silicon layer.

[0190] For example, please refer to Figure 35 and Figure 36 ,in, Figure 36 The diagram shows a planar layout of the three-dimensional memory. Figure 36 Displayed as Figure 35 A-A' sectional view.

[0191] Specifically, the three-dimensional memory is divided into a core region I and a step region II. In this embodiment, a ring groove structure is provided in the step region II. The ring groove structure penetrates the bottom polysilicon layer 29 from top to bottom and extends downward into the substrate 1.

[0192] Specifically, the annular groove structure includes an annular groove 40, the inner wall of the annular groove 40 is provided with a third protective layer 8, and the annular groove 40 is filled with a second sacrificial layer 9.

[0193] As an example, the annular groove 40 may be a polygonal ring, a circular ring, an elliptical ring, or other suitable shape.

[0194] As an example, the stepped area II is provided with a plurality of dummy channel hole structures, the dummy channel hole structures including dummy channel holes 41 and a medium filling the dummy channel holes 41.

[0195] As an example, at least one of the dummy channel hole structures is located within the surrounding area of ​​the annular groove structure and / or at least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove structure.

[0196] In the three-dimensional memory of this embodiment, the channel holes have a high degree of uniformity in both the upper and lower parts, and the filling of the bottom polysilicon layer also has a high degree of uniformity. The annular groove structure in the step region helps to improve the structural stability of the device.

[0197] In summary, the three-dimensional memory and its fabrication method of the present invention first perform bottom etching at the channel hole location to form the lower portion of the channel hole, then oxidize the sidewalls of the first sacrificial layer, fill the hole with a second sacrificial layer, and then form a stacked structure to form the upper portion of the channel hole. The larger lower portion of the channel hole can improve the support capacity of the core region and dummy region after the bottom sacrificial layer is removed, and also result in less deformation at the bottom of the channel hole in the core region and a more uniform distribution of holes. This is beneficial for improving the filling process window after the bottom sacrificial layer is removed, and can directly form a deeper silicon trench (sigouging) at the bottom, avoiding the expansion of the critical dimension at the top of the channel hole caused by the formation of the silicon trench after the channel hole is etched. In addition, the dummy region can be further annularly grooved during bottom etching, which can prevent the middle region surrounded by the annular groove from being removed during the bottom sacrificial layer removal, thereby greatly improving the support capacity of the core region and dummy region during the bottom sacrificial layer removal. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0198] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, Includes the following steps: A substrate structure is provided, wherein the substrate structure comprises, from bottom to top, a substrate, a first protective layer, a first sacrificial layer, a second protective layer and a bottom dielectric layer; A first channel hole is formed in the substrate structure, the first channel hole penetrating vertically through the bottom dielectric layer, the second protective layer, the first sacrificial layer and the first protective layer, and extending downward into the substrate; A third protective layer is formed on the sidewall of the first sacrificial layer exposed by the first channel hole; A second sacrificial layer is formed in the first channel hole; A first stacked structure is formed above the bottom dielectric layer, the first stacked structure comprising alternately stacked gate sacrificial layers and dielectric layers; A second channel hole is formed in the first stacked structure, the second channel hole penetrates the first stacked structure vertically, and the orthographic projection of the second channel hole on the bottom dielectric layer is located inside the first channel hole; Remove the second sacrificial layer; A channel structure is formed in the first channel hole and the second channel hole. The channel structure includes a channel layer and a storage stack surrounding the outer side and the outer bottom surface of the channel layer. The bottom of the channel structure occupies a larger dimension in the horizontal direction than the portion of the channel structure located in the first stack structure.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, After the second channel hole is formed and before the second sacrificial layer is removed, the following steps are also included: A third sacrificial layer is formed in the second channel hole; A second stacked structure is formed on top of the first stacked structure, the second stacked structure comprising the gate sacrificial layer and the dielectric layer stacked alternately; A third channel hole is formed in the second stacked structure, the third channel hole penetrates the second stacked structure vertically, and the orthographic projection of the third channel hole on the first stacked structure is located inside the second channel hole; Remove the third sacrificial layer; Furthermore, when the channel structure is formed after removing the third sacrificial layer and the second sacrificial layer, the channel structure is also formed within the third channel hole.

3. The method for manufacturing a three-dimensional memory according to claim 1 or 2, characterized in that, It also includes the following steps: A grid line gap is formed, which penetrates the first stacked structure vertically and extends at least downward into the first sacrificial layer; A sidewall protective layer is formed on the sidewall of the grid wire slot; Remove the first sacrificial layer to obtain the bottom transverse gap; A portion of the storage stack is removed via the bottom lateral slot to expose a portion of the channel layer, and the first protective layer and the second protective layer are removed; A bottom polycrystalline silicon layer is formed in the bottom lateral slot; Remove the gate sacrificial layer to obtain multiple gate lateral slots; A conductive layer is formed in the lateral gap of the gate; An array common source structure is formed in the gate line gap.

4. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that, Before the first channel hole is formed, a groove is provided in the substrate, the first protective layer and the first sacrificial layer are filled into the groove, and the orthogonal projection of the gate line slot on the substrate is located in the groove.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, After forming the bottom polysilicon layer and before removing the gate sacrificial layer, the step of forming a bottom epitaxial layer in the trench is also included.

6. The method for manufacturing a three-dimensional memory according to claim 5, characterized in that, The bottom epitaxial layer comprises, from bottom to top, an N-type epitaxial silicon layer and an N-type polycrystalline silicon layer.

7. The method for manufacturing a three-dimensional memory according to claim 3, characterized in that, The three-dimensional memory includes a stepped region. Before forming the first stacked structure, the manufacturing method further includes the step of forming an annular groove in the stepped region, the annular groove penetrating the first sacrificial layer and the first protective layer vertically. In the step of forming the third protective layer, the third protective layer is also formed on the sidewall of the first sacrificial layer exposed by the annular groove; In the step of forming the second sacrificial layer in the first channel hole, the second sacrificial layer is also formed in the annular groove; In the step of removing the first sacrificial layer to obtain the bottom transverse gap, the portion of the first sacrificial layer surrounded by the annular groove is not removed.

8. The method for manufacturing a three-dimensional memory according to claim 7, characterized in that, The annular groove is in the form of a polygonal ring, a circular ring, or an elliptical ring.

9. The method for manufacturing a three-dimensional memory according to claim 7, characterized in that, The manufacturing method further includes the step of forming multiple dummy channel holes in the stepped area.

10. The method for manufacturing a three-dimensional memory according to claim 9, characterized in that, At least one of the dummy channel holes is located within the surrounding area of ​​the annular groove; And / or, At least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove.

11. A three-dimensional memory, characterized in that, include: Substrate; A bottom polycrystalline silicon layer is located on the substrate; A bottom dielectric layer is located on the bottom polysilicon layer; Multiple conductive layers are stacked on top of the bottom dielectric layer, and a dielectric layer is provided between adjacent conductive layers; The channel structure extends vertically through multiple conductive layers and dielectric layers, and downwards into the substrate. The channel structure includes a channel layer and a memory stack surrounding the outer side and bottom surface of the channel layer. The bottom polysilicon layer extends laterally through the memory stack to connect with the channel layer. The bottom of the channel structure occupies a larger dimension in the horizontal direction than the portion of the channel structure located in the conductive layer; The bottom of the channel structure includes: A portion of the channel structure located in the bottom dielectric layer; A portion of the channel structure located in the substrate.

12. The three-dimensional memory according to claim 11, characterized in that, The channel structure located in the plurality of conductive layers and dielectric layers is divided into at least two segments, wherein the width of the upper segment of the channel structure is smaller than the width of the lower segment.

13. The three-dimensional memory according to claim 11, characterized in that, The three-dimensional memory includes: The step region has an annular groove structure that penetrates the bottom polysilicon layer vertically and extends downward into the substrate.

14. The three-dimensional memory according to claim 13, characterized in that, The annular groove structure is in the form of a polygonal ring, a circular ring, or an elliptical ring.

15. The three-dimensional memory according to claim 13, characterized in that, The stepped area is provided with multiple dummy channel hole structures.

16. The three-dimensional memory according to claim 15, characterized in that, At least one of the dummy channel hole structures is located within the surrounding area of ​​the annular groove structure; And / or, At least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove structure.

17. A three-dimensional memory, characterized in that, include: Substrate; A bottom polycrystalline silicon layer is located on the substrate; A bottom dielectric layer is located on the bottom polysilicon layer; Multiple conductive layers are stacked on top of the bottom dielectric layer, and a dielectric layer is provided between adjacent conductive layers; The channel structure extends vertically through multiple conductive layers and dielectric layers, and downwards into the substrate. The channel structure includes a channel layer and a memory stack surrounding the outer side and bottom surface of the channel layer. The bottom polysilicon layer extends laterally through the memory stack to connect with the channel layer. The channel structure includes a protrusion at the bottom extending along the direction of the bottom polysilicon layer; The channel structure includes a protruding portion at the bottom extending along the direction of the bottom polysilicon layer, comprising: The protrusion is located in the bottom dielectric layer, the bottom polysilicon layer, and the substrate.

18. The three-dimensional memory according to claim 17, characterized in that, The channel structure located in the plurality of conductive layers and dielectric layers is divided into at least two segments, wherein the width of the upper segment of the channel structure is smaller than the width of the lower segment.

19. The three-dimensional memory according to claim 17, characterized in that, The three-dimensional memory includes: The step region has an annular groove structure that penetrates the bottom polysilicon layer vertically and extends downward into the substrate.

20. The three-dimensional memory according to claim 19, characterized in that, The stepped area is provided with multiple dummy channel hole structures.

21. The three-dimensional memory according to claim 20, characterized in that, At least one of the dummy channel hole structures is located within the surrounding area of ​​the annular groove structure; And / or, At least one of the dummy channel holes is located outside the surrounding area of ​​the annular groove structure.

22. The three-dimensional memory according to any one of claims 17-21, characterized in that, The three-dimensional memory also includes an array common source structure, which extends vertically through multiple conductive layers, multiple dielectric layers, and the bottom dielectric layer.

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