Resistive memory device and method of making the same

Abstract

A resistive memory device and a method of fabricating the same are disclosed. The resistive memory device includes a first stack structure and a second stack structure. The first stack structure includes a first lower electrode, a first upper electrode disposed on the first lower electrode, and a first variable resistance layer disposed between the first lower electrode and the first upper electrode in a vertical direction. The second stack structure includes a second lower electrode, a second upper electrode disposed on the second lower electrode, and a second variable resistance layer disposed between the second lower electrode and the second upper electrode in the vertical direction. A thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer, thereby increasing a number of switchable resistance states of the resistive memory device.

Description

TECHNICAL FIELD

[0001] The present application relates to a resistive memory device and a method for fabricating the same, and more particularly to a resistive memory device with variable resistance layers having different thicknesses and a method for fabricating the same. BACKGROUND

[0002] Semiconductor memory is a semiconductor device used for storing data in a computer or an electronic product, which can be roughly divided into volatile memory and non-volatile memory. Volatile memory refers to a computer memory in which stored data disappears when the power supply for operation is interrupted, while non-volatile memory has the characteristic of not losing stored data due to interruption of power supply. Resistive RAM (RRAM) is a non-volatile memory, which is considered as a memory structure that can be applied to many electronic devices due to its low operating voltage, low power consumption, and high write speed. SUMMARY

[0003] The present application provides a resistive memory device and a method for fabricating the same, which uses variable resistance layers having different thicknesses to increase the switchable resistance states of the resistive memory device, thereby realizing a resistive memory device with multiple resistance states.

[0004] One embodiment of the present application provides a resistive memory device, which includes a first stack structure and a second stack structure. The first stack structure includes a first lower electrode, a first upper electrode, and a first variable resistance layer. The first upper electrode is disposed on the first lower electrode, and the first variable resistance layer is disposed between the first lower electrode and the first upper electrode in a vertical direction. The second stack structure includes a second lower electrode, a second upper electrode, and a second variable resistance layer. The second upper electrode is disposed on the second lower electrode, and the second variable resistance layer is disposed between the second lower electrode and the second upper electrode in the vertical direction. The thickness of the first variable resistance layer is less than the thickness of the second variable resistance layer.

[0005] One embodiment of the present application provides a method for fabricating a resistive memory device, which includes the following steps. A first stack structure and a second stack structure are formed on a dielectric layer. The first stack structure includes a first lower electrode, a first upper electrode, and a first variable resistance layer. The first upper electrode is disposed on the first lower electrode, and the first variable resistance layer is disposed between the first lower electrode and the first upper electrode in a vertical direction. The second stack structure includes a second lower electrode, a second upper electrode, and a second variable resistance layer. The second upper electrode is disposed on the second lower electrode, and the second variable resistance layer is disposed between the second lower electrode and the second upper electrode in the vertical direction. The thickness of the first variable resistance layer is less than the thickness of the second variable resistance layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 Schematic diagram of a resistive memory device according to a first embodiment of the application.

[0007] Figures 2 to 8 Schematic diagram of a method of fabricating a resistive memory device according to an embodiment of the application, wherein

[0008] Figure 3 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 2 Schematic diagram of a subsequent condition;

[0009] Figure 4 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 3 Schematic diagram of a subsequent condition;

[0010] Figure 5 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 4 Schematic diagram of a subsequent condition;

[0011] Figure 6 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 5 Schematic diagram of a subsequent condition;

[0012] Figure 7 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 6 Schematic diagram of a subsequent condition;

[0013] Figure 8 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 7 Schematic diagram of a subsequent condition.

[0014] Figure 9 Schematic diagram of a resistive memory device according to a second embodiment of the application.

[0015] Figures 10 to 15 Schematic diagram of a method of fabricating a resistive memory device according to another embodiment of the application, wherein

[0016] Figure 11 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 10 Schematic diagram of a subsequent condition;

[0017] Figure 12 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 11 Schematic diagram of a subsequent condition;

[0018] Figure 13 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 12 Schematic diagram of a subsequent condition;

[0019] Figure 14 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 13 Schematic diagram of a subsequent condition;

[0020] Figure 15 Schematic diagram of a resistive memory device according to a first embodiment of the application. Figure 14 Schematic diagram of a subsequent condition.

[0021] MAIN ELEMENT SYMBOL EXPLANATION

[0022] 10 dielectric layer

[0023] 12 conductive layer

[0024] 14 dielectric layer

[0025] 16 dielectric layer

[0026] 18 connecting plug

[0027] 20 first conductive layer

[0028] 22 diode material layer

[0029] 22A first diode layer

[0030] 22B second diode layer

[0031] 24 second conductive layer

[0032] 26 first resistive material layer

[0033] 28 second resistive material layer

[0034] 30 mask layer

[0035] 30A first mask pattern

[0036] 30B second mask pattern

[0037] 32A first gap sub

[0038] 32B second gap sub

[0039] 34 dielectric layer

[0040] 36 third conductive layer

[0041] 38 fourth conductive layer

[0042] 40 dielectric layer

[0043] 42 dielectric layer

[0044] 44 connecting plug

[0045] 46 conductive layer

[0046] 82 patterned mask layer

[0047] 84 patterned mask layer

[0048] 91 patterning fabrication process

[0049] 92 patterning fabrication process

[0050] 101 resistive memory device

[0051] 102 resistive memory device

[0052] BE1 first lower electrode

[0053] BE2 second lower electrode

[0054] D1 first direction

[0055] D2 second direction

[0056] DS1 distance

[0057] DS2 distance

[0058] ME1 first intermediate electrode

[0059] ME2 second intermediate electrode

[0060] R1 first region

[0061] R2 second region

[0062] RL1 first variable resistance layer

[0063] RL2 second variable resistance layer

[0064] RL21 first layer

[0065] RL22 second layer

[0066] S11 lower surface

[0067] S12 upper surface

[0068] S21 lower surface

[0069] S22 upper surface

[0070] S32 upper surface

[0071] S33 upper surface

[0072] ST1 first stack structure

[0073] ST2 second stack structure

[0074] TE1 first upper electrode

[0075] TE2 second upper electrode

[0076] TK1 thickness

[0077] TK2 thickness

[0078] TR1 first trench

[0079] TR2 second trench

[0080] TR3 third trench DETAILED DESCRIPTION

[0081] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0082] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0083] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0084] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0085] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0086] Please see Figure 1 . Figure 1 The diagram shown is a schematic representation of a resistive storage device 101 according to a first embodiment of the present invention. Figure 1 As shown, the resistive memory device 101 includes a first stacked structure ST1 and a second stacked structure ST2. The first stacked structure ST1 includes a first lower electrode BE1, a first upper electrode TE1, and a first variable resistance layer RL1. The first upper electrode TE1 is disposed on the first lower electrode BE1, and the first variable resistance layer RL1 is disposed in a vertical direction (e.g., Figure 1The second stack structure ST2 includes a second bottom electrode BE2, a second top electrode TE2, and a second variable resistance layer RL2. The second top electrode TE2 is disposed on the second bottom electrode BE2, and the second variable resistance layer RL2 is disposed between the second bottom electrode BE2 and the second top electrode TE2 in the first direction D1. The thickness TK1 of the first variable resistance layer RL1 in the first direction D1 is less than the thickness TK2 of the second variable resistance layer RL2 in the first direction D1.

[0087] In some embodiments, the first stack structure ST1 and the second stack structure ST2 can be regarded as resistive memory sub-units with variable resistance material layers of different thicknesses, and each variable resistance material layer can be regarded as a switching medium in the resistive memory sub-unit. By applying appropriate voltages to the upper and lower electrodes in the stack structure, the resistance value of the resistive memory sub-unit can be changed, and the resistive memory sub-unit can be switched between a high resistance state (HRS) and a low resistance state (LRS), thereby realizing the operating modes of the storage device such as storing data, reading data, and resetting. In addition, by adjusting the thickness of the variable resistance material layer, the operating voltage or / and operating current for switching the corresponding resistive memory sub-unit between the HRS and the LRS, and the resistance values of the resistive memory sub-unit in the HRS and the LRS can be changed, and multiple resistance states can be realized in the resistive memory device 101.

[0088] For example, in some embodiments, the first stack structure ST1 with the first variable resistance layer RL1 having a relatively thinner thickness can require a lower set voltage (VSET) to switch from HRS to LRS than the second stack structure ST2 with the second variable resistance layer RL2 having a relatively thicker thickness. For example, the first stack structure ST1 with the first variable resistance layer RL1 having a relatively thinner thickness can require a set voltage of about 0.5 volts to switch from HRS to LRS, while the second stack structure ST2 with the second variable resistance layer RL2 having a relatively thicker thickness can require a set voltage of about 1 volt to switch from HRS to LRS, but the application is not limited in this regard. Thus, by controlling the magnitude of the voltage applied to the first stack structure ST1 and the second stack structure ST2, respectively, the first stack structure ST1 and the second stack structure ST2 can be in HRS, in LRS, or only the first stack structure ST1 can be switched from HRS to LRS while the second stack structure ST2 is maintained in HRS. In other words, relative to a resistive memory subunit with a layer of variable resistance material having the same thickness, the first stack structure ST1 and the second stack structure ST2 of the present embodiments can be used to form at least three different resistance states (both in HRS, both in LRS, and a state with part in LRS and part in HRS) to achieve multiple resistance states and thus improve the data storage capability of the resistive memory device 101.

[0089] In some embodiments, the first stack structure ST1 and the second stack structure ST2 of the resistive memory device 101 can be electrically connected to each other, for example, in a parallel manner, but the application is not limited in this regard. For example, in some embodiments, the first bottom electrode BE1 of the first stack structure ST1 and the second bottom electrode BE2 of the second stack structure ST2 can be electrically connected to each other through a conductive structure (for example, the conductive layer 12 and the connection plug 18 shown in FIG. 1, but the application is not limited in this regard) disposed in one or more dielectric layers (for example, the dielectric layer 10, the dielectric layer 14, and the dielectric layer 16 shown in FIG. 1, but the application is not limited in this regard), while the first top electrode TE1 of the first stack structure ST1 and the second top electrode TE2 of the second stack structure ST2 can be electrically connected to each other through a conductive structure (for example, the conductive layer 12 and the connection plug 18 shown in FIG. 1, but the application is not limited in this regard) disposed in one or more dielectric layers (for example, the dielectric layer 40 and the dielectric layer 42 shown in FIG. 1, but the application is not limited in this regard). Figure 1 Figure 1 In some embodiments, the first stack structure ST1 and the second stack structure ST2 of the resistive memory device 101 can be electrically connected to each other, for example, in a parallel manner, but the application is not limited in this regard. For example, in some embodiments, the first bottom electrode BE1 of the first stack structure ST1 and the second bottom electrode BE2 of the second stack structure ST2 can be electrically connected to each other through a conductive structure (for example, the conductive layer 12 and the connection plug 18 shown in FIG. 1, but the application is not limited in this regard) disposed in one or more dielectric layers (for example, the dielectric layer 10, the dielectric layer 14, and the dielectric layer 16 shown in FIG. 1, but the application is not limited in this regard), while the first top electrode TE1 of the first stack structure ST1 and the second top electrode TE2 of the second stack structure ST2 can be electrically connected to each other through a conductive structure (for example, the conductive layer 12 and the connection plug 18 shown in FIG. 1, but the application is not limited in this regard) disposed in one or more dielectric layers (for example, the dielectric layer 40 and the dielectric layer 42 shown in FIG. 1, but the application is not limited in this regard). Figure 1 Figure 1 ​​The first lower electrode BE1 and the second lower electrode BE2 can be electrically connected to each other through the conductive layer 12 and the connection plug 18, and the first upper electrode TE1 and the second upper electrode TE2 can be electrically connected to each other through the conductive layer 46 and the connection plug 44, but not limited thereto. In some embodiments, the first lower electrode BE1 and the second lower electrode BE2 can be electrically connected to each other through a manner different from the above, the first upper electrode TE1 and the second upper electrode TE2 can be electrically connected to each other through a manner different from the above, and the first stack structure ST1 and the second stack structure ST2 can also be electrically connected to each other through a manner different from the above as needed by design.

[0090] In some embodiments, the dielectric layer 10, the dielectric layer 14, the dielectric layer 16, the conductive layer 12, and the connection plug 18 can be disposed below the first stack structure ST1 and the second stack structure ST2, the dielectric layer 40, the dielectric layer 42, the connection plug 44, and the conductive layer 46 can be disposed above the first stack structure ST1 and the second stack structure ST2, and the first stack structure ST1 and the second stack structure ST2 can be disposed in a dielectric layer 34, and the dielectric layer 34 can be located between the dielectric layer 16 and the dielectric layer 40 in the first direction D1, but not limited thereto. In other words, the resistive memory device 101 can further include the above-mentioned dielectric layer 10, the dielectric layer 14, the dielectric layer 16, the dielectric layer 34, the dielectric layer 40, the dielectric layer 42, the conductive layer 12, the connection plug 18, the connection plug 44, and the conductive layer 46, but not limited thereto. In addition, in some embodiments, the resistive memory device 101 can further include a first gap sub 32A and a second gap sub 32B disposed in the dielectric layer 34 and respectively surrounding the first stack structure ST1 and the second stack structure ST2 in the horizontal direction (for example Figure 1 the second direction D2 shown in the above, but not limited thereto) to protect the first variable resistance layer RL1 and the second variable resistance layer RL2 from substances (such as oxygen) entering from the sidewalls of the first stack structure ST1 and the second stack structure ST2 into the first variable resistance layer RL1 and the second variable resistance layer RL2 to affect their material properties.

[0091] In some embodiments, the dielectric layer 10 can be disposed on a substrate (not shown), which can include a semiconductor substrate such as a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials, but is not limited thereto. In addition, before the dielectric layer 10 is formed, elements (e.g., transistors) or / and circuits (not shown) can be formed on the substrate, and the conductive layer 12 can be electrically connected downward to the elements or / and circuits on the substrate, but is not limited thereto. In some embodiments, the method of fabricating the resistive memory device 101 can be integrated with a back end of line (BEOL) fabrication process in a semiconductor fabrication process, and the dielectric layer 10, the dielectric layer 14, the dielectric layer 16, the dielectric layer 34, the dielectric layer 40, and the dielectric layer 42 can be considered as interlayer dielectric layers formed in the BEOL fabrication process, and the conductive layer 12, the connection plug 18, the connection plug 44, and the conductive layer 46 can be considered as part of an interconnection structure formed in the BEOL fabrication process, but is not limited thereto.

[0092] In some embodiments, the first direction D1 can be considered as a thickness direction of the dielectric layer 10, and a horizontal direction (e.g., the second direction D2) substantially orthogonal to the first direction D1 can be parallel to a surface of the dielectric layer 10, but is not limited thereto. In addition, in the context of a position or / and a component being relatively higher in the first direction D1 being farther from the dielectric layer 10 in the first direction D1 than a position or / and a component being relatively lower in the first direction D1, a lower portion or a bottom portion of a component can be closer to the dielectric layer 10 in the first direction D1 than an upper portion or a top portion of the component, a component above another component can be considered as being relatively farther from the dielectric layer 10 in the first direction D1, and a component below another component can be considered as being relatively closer to the dielectric layer 10 in the first direction D1.

[0093] In some embodiments, the material of the first variable resistance layer RL1 and the second variable resistance layer RL2 can respectively include a metal oxide such as a transition metal oxide, a perovskite oxide, or other suitable variable resistance material. The metal oxide can include nickel oxide, titanium oxide, hafnium oxide, zirconium oxide, zinc oxide, tungsten oxide, cobalt oxide, copper oxide, niobium oxide, molybdenum oxide, tantalum oxide, iron oxide, manganese oxide, a mixture thereof, or other suitable metal oxide material, and the perovskite oxide can include strontium titanate (SrTiO3), barium titanate (BaTiO3), lead titanate (PbTiO3), or other suitable perovskite oxide material. In some embodiments, the material composition of the first variable resistance layer RL1 and the second variable resistance layer RL2 can be the same or different from each other as desired by design. For example, in some embodiments, the second variable resistance layer RL2 can include a first layer RL21 and a second layer RL22 stacked in the first direction D1, and thus the second layer RL22 can be disposed on the first layer RL21 in the first direction D1. In some embodiments, the material composition of the first variable resistance layer RL1 and at least one of the first layer RL21 and the second layer RL22 of the second variable resistance layer RL2 can be the same.

[0094] In some embodiments, the first layer RL21, the second layer RL22 of the second variable resistance layer RL2 and the first variable resistance layer RL1 can all be formed of the same material with the same material composition. In some embodiments, the material composition of the first layer RL21 of the second variable resistance layer RL2 can be different from the material composition of the second layer RL22, the first variable resistance layer RL1 can be formed of the same material with the same material composition and substantially the same thickness as the first layer RL21 or the second layer RL22, and the first layer RL21 or the second layer RL22 with a different material from the first variable resistance layer RL1 can be used to increase the overall thickness of the second variable resistance layer RL2, but the application is not limited in this regard. For example, in some embodiments, the first layer RL21 of the second variable resistance layer RL2 can be formed by patterning a first resistive material layer 26, and the first variable resistance layer RL1 and the second layer RL22 of the second variable resistance layer RL2 can be formed by patterning a second resistive material layer 28, but the application is not limited in this regard. It is worth noting that in some embodiments, with the same thickness, by the material selection and matching of the first resistive material layer 26 and the second resistive material layer 28, the voltage required for switching the first resistive material layer 26 from HRS to LRS can be higher than the voltage required for switching the second resistive material layer 28 from HRS to LRS, thereby making the difference between the set voltage required for switching the first stack structure ST1 from HRS to LRS and the set voltage required for switching the second stack structure ST2 from HRS to LRS further larger, thereby facilitating the operation of the resistive memory device 101, but the application is not limited in this regard.

[0095] In some embodiments, the first stack structure ST1 can further include a first intermediate electrode ME1 and a first diode layer 22A, and the second stack structure ST2 can further include a second intermediate electrode ME2 and a second diode layer 22B. The first intermediate electrode ME1 can be disposed between the first bottom electrode BE1 and the first top electrode TE1 in the first direction D1, the first variable resistance layer RL1 can be disposed between the first intermediate electrode ME1 and the first top electrode TE1 in the first direction D1, and the first diode layer 22A can be disposed between the first intermediate electrode ME1 and the first bottom electrode BE1 in the first direction D1. The second intermediate electrode ME2 can be disposed between the second bottom electrode BE2 and the second top electrode TE2 in the first direction D1, the second variable resistance layer RL2 can be disposed between the second intermediate electrode ME2 and the second top electrode TE2 in the first direction D1, and the second diode layer 22B can be disposed between the second intermediate electrode ME2 and the second bottom electrode BE2 in the first direction D1. In other words, the first bottom electrode BE1, the first diode layer 22A, the first intermediate electrode ME1, the first variable resistance layer RL1, and the first top electrode TE1 in the first stack structure ST1 can be sequentially stacked from bottom to top in the first direction D1, and the second bottom electrode BE2, the second diode layer 22B, the second intermediate electrode ME2, the second variable resistance layer RL2, and the second top electrode TE2 in the second stack structure ST2 can be sequentially stacked from bottom to top in the first direction D1.

[0096] In some embodiments, the first variable resistance layer RL1 can directly contact the first intermediate electrode ME1 and the first top electrode TE1, and the second variable resistance layer RL2 can directly contact the second intermediate electrode ME2 and the second top electrode TE2. In this case, the distance DS1 between the first top electrode TE1 and the first intermediate electrode ME1 in the first direction D1 can be substantially equal to the thickness TK1 of the first variable resistance layer RL1, and the distance DS2 between the second top electrode TE2 and the second intermediate electrode ME2 in the first direction D1 can be substantially equal to the thickness TK2 of the second variable resistance layer RL2, such that the distance DS1 between the first top electrode TE1 and the first intermediate electrode ME1 in the first direction D1 can be less than the distance DS2 between the second top electrode TE2 and the second intermediate electrode ME2 in the first direction D1, but the application is not limited thereto. In addition, in some embodiments, an upper surface S12 of the first top electrode TE1 and an upper surface S22 of the second top electrode TE2 can be substantially coplanar, and a lower surface S11 of the first top electrode TE1 can be lower than a lower surface S21 of the second top electrode TE2 in the first direction D1. In some embodiments, the upper surfaces S12 and S22 can be respectively regarded as the topmost surfaces of the first and second top electrodes TE1 and TE2 in the first direction D1, and the lower surfaces S11 and S21 can be respectively regarded as the bottommost surfaces of the first and second top electrodes TE1 and TE2 in the first direction D1, such that the thickness of the first top electrode TE1 in the first direction D1 can be greater than the thickness of the second top electrode TE2 in the first direction D1, but the application is not limited thereto.

[0097] In some embodiments, the first and second intermediate electrodes ME1 and ME2, the first and second diode layers 22A and 22B can not be provided as needed by design, such that the first variable resistance layer RL1 can directly contact the first bottom electrode BE1 and the first top electrode TE1, and the second variable resistance layer RL2 can directly contact the second bottom electrode BE2 and the second top electrode TE2, but the application is not limited thereto. In addition, whether the first and second intermediate electrodes ME1 and ME2, the first and second diode layers 22A and 22B are provided or not, the distance between the first top electrode TE1 and the first bottom electrode BE1 in the first direction D1 can be less than the distance between the second top electrode TE2 and the second bottom electrode BE2 in the first direction D1.

[0098] In some embodiments, the materials of the first lower electrode BE1, the second lower electrode BE2, the first intermediate electrode ME1, the second intermediate electrode ME2, the first upper electrode TE1, and the second upper electrode TE2 may respectively include aluminum, platinum, ruthenium, iridium, nickel, cobalt, chromium, tungsten, copper, hafnium, zirconium, zinc, gold, titanium, alloys of the above materials, mixtures of the above materials, or other suitable metallic or non-metallic conductive materials. In some embodiments, the first diode layer 22A and the second diode layer 22B may each include a p-type semiconductor layer and an n-type semiconductor layer (not shown) stacked on the first direction D1, thereby forming diode structures between the first intermediate electrode ME1 and the first lower electrode BE1 and between the second intermediate electrode ME2 and the second lower electrode BE2, respectively, but are not limited thereto. In some embodiments, the first diode layer 22A and the second diode layer 22B may also each have other suitable diode structures. Furthermore, the aforementioned p-type semiconductor layer may include a p-type silicon semiconductor layer, a p-type copper oxide (CuO) semiconductor layer, or other suitable p-type semiconductor materials, while the aforementioned n-type semiconductor layer may include an n-type silicon semiconductor layer, an n-type indium zinc oxide (InZnO) semiconductor layer, or other suitable n-type semiconductor materials. Additionally, the p-type semiconductor layer in the first diode layer 22A and the second diode layer 22B may be disposed in the first direction D1 between the n-type semiconductor layer and the lower electrode for use in conjunction with… Figure 1 The structure shown controls the current direction in the first stacked structure ST1 and the second stacked structure ST2, but is not limited thereto.

[0099] The dielectric layers 10, 14, 16, 34, 40, and 42 described above may each comprise silicon oxide, silicon nitride, silicon carbide nitride, fluorosilicate glass (FSG), or other suitable dielectric materials. Furthermore, in some embodiments, dielectric layers 10, 16, 34, and 42 may each comprise low dielectric constant (low-k) dielectric materials, such as benzocyclclobutene (BCB), hydrogen silsesquioxane (HSQ), methylsilylsquioxane (MSQ), silicon oxyhydrocarbon (SiOC-H), porous dielectric materials, or other suitable low-k dielectric materials. The first spacer 32A and the second spacer 32B described above may each comprise a single layer or multiple layers of dielectric material, such as silicon nitride, silicon carbide nitride, or other suitable dielectric materials. The conductive layer 12, connecting plug 18, connecting plug 44, and conductive layer 46 may each include a low-resistivity material and a barrier layer, but are not limited thereto. The low-resistivity material may include materials with relatively low resistivity, such as copper, aluminum, tungsten, etc., while the barrier layer may include titanium nitride, tantalum nitride, or other suitable conductive barrier materials, but are not limited thereto.

[0100] Please see Figures 1 to 8 . Figures 2 to 8 The illustration shows a schematic diagram of a method for manufacturing a resistive memory device according to an embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 A diagram illustrating the subsequent situation. Figure 7 It is illustrated Figure 6 A diagram illustrating the subsequent situation. Figure 8 It is illustrated Figure 7 A schematic diagram of the subsequent situation. In some embodiments, Figure 1 It can be regarded as a drawing Figure 8 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1As shown, the fabrication method of the resistive memory device 101 may include the following steps. First, a first stacked structure ST1 and a second stacked structure ST2 are formed on the dielectric layer 10. The first stacked structure ST1 includes a first lower electrode BE1, a first upper electrode TE1, and a first variable resistance layer RL1. The first upper electrode TE1 is disposed on the first lower electrode BE1, and the first variable resistance layer RL1 is disposed between the first lower electrode BE1 and the first upper electrode TE1 in a first direction D1. The second stacked structure ST2 includes a second lower electrode BE2, a second upper electrode TE2, and a second variable resistance layer RL2. The second upper electrode TE2 is disposed on the second lower electrode BE2, and the second variable resistance layer RL2 is disposed between the second lower electrode BE2 and the second upper electrode TE2 in the first direction D1. The thickness TK1 of the first variable resistance layer RL1 is smaller than the thickness TK2 of the second variable resistance layer RL2.

[0101] Further explanation: The manufacturing method of this embodiment may include, but is not limited to, the following steps. First, as... Figure 2 As shown, conductive layer 12 can be formed in dielectric layer 10, and dielectric layers 14 and 16 can be formed on dielectric layer 10 and conductive layer 12. A plurality of connection plugs 18 can penetrate dielectric layer 16 and dielectric layer 14 in the first direction D1 to contact conductive layer 12 and form an electrical connection. Then, a first conductive layer 20, a diode material layer 22, a second conductive layer 24, and a first resistive material layer 26 can be sequentially formed on dielectric layer 16 and connection plugs 18. In some embodiments, a first region R1 and a second region R2 can be defined on dielectric layer 10. The first region R1 can be disposed adjacent to the second region R2, and the first region R1 is used to form... Figure 1 The region of the first stacked structure ST1, and the second region R2 is for forming thereon. Figure 1 The region of the second stacked structure ST2 in the middle. In other words, the first region R1 and the second region R2 can be regarded as the regions corresponding to different resistive memory sub-cells, but are not limited thereto. The first conductive layer 20, diode material layer 22, second conductive layer 24 and first resistive material layer 26 mentioned above can be formed on the first region R1 and the second region R2.

[0102] Then, as Figure 3 As shown, the first resistive material layer 26 on the first region R1 is removed, and after the removal of the first resistive material layer 26 on the first region R1, a portion of the first resistive material layer 26 remains on the second region R2. Then, as... Figure 4As shown, a second resistive material layer 28 is formed over the first region Rl and the second region R2, and a mask layer 30 is formed over the second resistive material layer 28, and a portion of the second resistive material layer 28 can be formed over a portion of the first resistive material layer 26 that remains on the second region R2. The mask layer 30 can include polysilicon or other suitable material that does not adversely affect the second resistive material layer 28. Next, as shown, Figures 4 to 5 As shown, after the mask layer 30 is formed, a patterning process 91 is performed on the second resistive material layer 28 and the portion of the first resistive material layer 26 that remains on the second region R2 to form the first variable resistance layer RLl on the first region Rl and the second variable resistance layer RL2 on the second region R2. In other words, the mask layer 30 can be formed prior to the patterning process 91, but is not limited thereto. In some embodiments, the mask layer 30 can not be formed as desired. In some embodiments, the patterning process 91 can utilize a patterned photoresist (not shown) formed from the mask layer 30 as an etch mask for an etching process, and the patterning process 91 can include one or more etching steps to etch the mask layer 30, the second resistive material layer 28, the first resistive material layer 26, the second conductive layer 24, the diode material layer 22, and the first conductive layer 20, respectively, and the patterned photoresist can be removed after the etching steps or the patterning process 91, but is not limited thereto.

[0103] In other words, the first conductive layer 20 can be patterned by the patterning process 91 to be the first lower electrode BE1 on the first region R1 and the second lower electrode BE2 on the second region R2, and the first lower electrode BE1 and the second lower electrode BE2 are separated from each other; the diode material layer 22 can be patterned by the patterning process 91 to be the first diode layer 22A on the first region R1 and the second diode layer 22B on the second region R2, and the first diode layer 22A and the second diode layer 22B are separated from each other; the second conductive layer 24 can be patterned by the patterning process 91 to be the first intermediate electrode ME1 on the first region R1 and the second intermediate electrode ME2 on the second region R2, and the first intermediate electrode ME1 and the second intermediate electrode ME2 are separated from each other; the first resistive material layer 26 remaining on the second region R2 can be patterned by the patterning process 91 to be the first layer RL21 of the second variable resistance layer RL2 on the second region R2; and the second resistive material layer 28 can be patterned by the patterning process 91 to be the first variable resistance layer RL1 on the first region R1 and the second layer RL22 of the second variable resistance layer RL2 on the second region R2, and the first variable resistance layer RL1 and the second layer RL22 of the second variable resistance layer RL2 are separated from each other. In addition, in some embodiments, the mask layer 30 can be patterned by the patterning process 91 to be a first mask pattern 30A on the first variable resistance layer RL1 and a second mask pattern 30B on the second variable resistance layer RL2, and the first mask pattern 30A and the second mask pattern 30B are separated from each other, but the application is not limited thereto.

[0104] It is worth noting that the forming method of the first variable resistance layer RL1 and the second variable resistance layer RL2 of the present embodiment is not limited to the above Figures 2 to 5The first variable resistance layer RL1 and the second variable resistance layer RL2 may be formed in other suitable ways as required by the design shown. Furthermore, in some embodiments, since the first lower electrode BE1, the second lower electrode BE2, the first diode layer 22A, the second diode layer 22B, the first intermediate electrode ME1, the second intermediate electrode ME2, the first variable resistance layer RL1, the second variable resistance layer RL2, the first mask pattern 30A, and the second mask pattern 30B can be formed using the same patterning process, the first lower electrode BE1, the first diode layer 22A, the first intermediate electrode ME1, the first variable resistance layer RL1, and the first mask pattern 30A may have substantially the same projected area in the first direction D1, while the second lower electrode BE2, the second diode layer 22B, the second intermediate electrode ME2, the second variable resistance layer RL2, and the second mask pattern 30B may also have substantially the same projected area in the first direction D1, but this is not a limitation. In some embodiments, the first lower electrode BE1, the second lower electrode BE2, the first diode layer 22A, the second diode layer 22B, the first intermediate electrode ME1, the second intermediate electrode ME2, the first variable resistor layer RL1, the second variable resistor layer RL2, the first mask pattern 30A, and the second mask pattern 30B may be formed respectively using different patterning manufacturing processes as required by the design, so that at least some of the above components may have different projected areas in the first direction D1.

[0105] Then, as Figure 6 As shown, a first spacer 32A can be formed on the sidewalls of the first lower electrode BE1, the first diode layer 22A, the first intermediate electrode ME1, the first variable resistor layer RL1, and the first mask pattern 30A, and a second spacer 32B can be formed on the sidewalls of the second lower electrode BE2, the second diode layer 22B, the second intermediate electrode ME2, the second variable resistor layer RL2, and the second mask pattern 30B. The first spacer 32A can be horizontally positioned around the first lower electrode BE1, the first diode layer 22A, the first intermediate electrode ME1, the first variable resistor layer RL1, and the first mask pattern 30A, while the second spacer 32B can be horizontally positioned around the second lower electrode BE2, the second diode layer 22B, the second intermediate electrode ME2, the second variable resistor layer RL2, and the second mask pattern 30B. Then, a dielectric layer 34 can be formed, and a planarization process (such as chemical mechanical polishing, but not limited thereto) can be used to make the first mask pattern 30A, the second mask pattern 30B, the first spacer 32A, the second spacer 32B and the upper surface of the dielectric layer 34 substantially coplanar, but not limited thereto.

[0106] After that, as Figures 6 to 8As shown, the first mask pattern 30A can be replaced by a first upper electrode TE1, and the second mask pattern 30B can be replaced by a second upper electrode TE2. For example, the first mask pattern 30A and the second mask pattern 30B can be removed first to form a first trench TR1 surrounded by a first spacer 32A on the first variable resistance layer RL1, and a second trench TR2 surrounded by a second spacer 32B can be formed on the second variable resistance layer RL2. Then, a third conductive layer 36 can be formed to fill the first trench TR1 and the second trench TR2, and a planarization process (e.g., chemical mechanical polishing, but not limited thereto) can be used to remove the third conductive layer 36 outside the first trench TR1 and the second trench TR2, and the first upper electrode TE1 and the second upper electrode TE2 can be formed in the first trench TR1 and the second trench TR2 respectively, forming the above-mentioned first stacked structure ST1 and the second stacked structure ST2. Then, as Figure 1 As shown, the dielectric layer 40, dielectric layer 42, connector plug 44, and conductive layer 46 described above can be formed on the first stacked structure ST1 and the second stacked structure ST2, thereby forming... Figure 1 The resistive storage device 101 shown is illustrated.

[0107] The above-described fabrication method can form a first variable resistance layer RL1 and a second variable resistance layer RL2 with different thicknesses, and can avoid etching damage caused by directly thinning a portion of the variable resistance layer using the etch-back method, which is beneficial to the electrical performance of resistive memory devices.

[0108] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0109] Please see Figure 9 . Figure 9 The illustration shows a schematic diagram of a resistive storage device 102 according to a second embodiment of the present invention. Figure 9 As shown, the difference from the first embodiment described above is that, in the resistive storage device 102, the second layer RL22 of the second variable resistance layer RL2 is shown in a cross-sectional view of the second variable resistance layer RL2 (e.g., a cross-sectional view of the second variable resistance layer RL2). Figure 9) can include a U-shaped structure surrounding the second upper electrode TE2 in a horizontal direction (e.g., the second direction D2). In this embodiment, the thickness TK2 of the second variable resistance layer RL2 can be considered as the thickness of the second variable resistance layer RL2 between the second upper electrode TE2 and the second middle electrode ME2 in the first direction D1, and the distance DS2 between the second upper electrode TE2 and the second middle electrode ME2 in the first direction D1 can be substantially equal to the thickness TK2 of the second variable resistance layer RL2, but the disclosure is not limited thereto. In some embodiments, the upper surface S33 of the second variable resistance layer RL2 between the second upper electrode TE2 and the second middle electrode ME2 in the first direction D1 can be lower than the upper surface S32 of the second layer RL22 of the second variable resistance layer RL2 in the first direction D1, and the upper surface S32 of the second layer RL22 of the second variable resistance layer RL2 and the upper surface S22 of the second upper electrode TE2 can be substantially coplanar, but the disclosure is not limited thereto.

[0110] In addition, in some embodiments, the first layer RL21 of the first variable resistance layer RL1 and the second variable resistance layer RL2 can be formed by the same material layer (e.g., the first resistive material layer 26), and the second layer RL22 of the second variable resistance layer RL2 can be formed by another material layer (e.g., the second resistive material layer 28), so that the material composition of the second layer RL22 of the second variable resistance layer RL2 can be different from the material composition of the first variable resistance layer RL1, but the disclosure is not limited thereto. It should be noted that, in some embodiments, under the condition of the same thickness, by the material selection and matching of the first resistive material layer 26 and the second resistive material layer 28, the voltage required for switching the second resistive material layer 28 from HRS to LRS can be higher than the voltage required for switching the first resistive material layer 26 from HRS to LRS, thereby making the difference between the set voltage required for switching the first stack structure ST1 of this embodiment from HRS to LRS and the set voltage required for switching the second stack structure ST2 from HRS to LRS further larger, thereby facilitating the operation of the resistive memory device 102, but the disclosure is not limited thereto.

[0111] Please refer to Figures 9 to 15 . Figures 10 to 15 The schematic diagram of the method for manufacturing the resistive memory device of another embodiment of the disclosure is shown. Figure 11 The schematic diagram of the condition after Figure 10 is shown, Figure 12 The schematic diagram of the condition after Figure 11 is shown, Figure 13 The schematic diagram of the condition after Figure 12 is shown, Figure 14 The schematic diagram of the condition after Figure 13 is shown, Figure 15 The schematic diagram of the condition after Figure 14A subsequent status diagram. In some embodiments, Figure 9 may be viewed as illustrating Figure 15 A subsequent status diagram, but not limited thereto. The method of fabricating the resistive memory device 102 can include, but is not limited to, the following steps. First, as shown in Figure 10 , a first conductive layer 20, a diode material layer 22, a second conductive layer 24, a first resistive material layer 26, and a mask layer 30 can be sequentially formed on the dielectric layer 16 and the connection plug 18, and the first conductive layer 20, the diode material layer 22, the second conductive layer 24, the first resistive material layer 26, and the mask layer 30 are formed on the first region R1 and the second region R2. Then, as shown in Figure 10 and Figure 11 , a patterning fabrication process 92 is performed on the first resistive material layer 26 to form a first variable resistance layer RL1 on the first region R1 and a first layer RL21 on the second region R2.

[0112] In other words, the mask layer 30 can be formed before the patterning fabrication process 92, but not limited thereto. In some embodiments, the mask layer 30 can also not be formed according to design requirements. In some embodiments, the patterning fabrication process 92 can utilize a patterned photoresist (not shown) formed on the mask layer 30 to perform an etching fabrication process using the patterned photoresist as an etching mask, and the patterning fabrication process 92 can include one or more etching steps to etch the mask layer 30, the first resistive material layer 26, the second conductive layer 24, the diode material layer 22, and the first conductive layer 20, respectively, and the patterned photoresist can be removed after the etching steps or the patterning fabrication process 92, but not limited thereto. Thus, the first conductive layer 20 can be patterned by the patterning fabrication process 92 to become a first lower electrode BE1 and a second lower electrode BE2, the diode material layer 22 can be patterned by the patterning fabrication process 92 to become a first diode layer 22A and a second diode layer 22B, the second conductive layer 24 can be patterned by the patterning fabrication process 92 to become a first intermediate electrode ME1 and a second intermediate electrode ME2, and the first resistive material layer 26 can be patterned by the patterning fabrication process 92 to become the first variable resistance layer RL1 on the first region R1 and the first layer RL21 on the second region R2. In this embodiment, the first variable resistance layer RL1 and the first layer RL21 are separated from each other, and a second layer of a second variable resistance layer can be formed on the first layer RL21 after the patterning fabrication process 92. In addition, in some embodiments, the mask layer 30 can be patterned by the patterning fabrication process 92 to become a first mask pattern 30A on the first variable resistance layer RL1 and a second mask pattern 30B on the first layer RL21, but not limited thereto.

[0113] Then, as shown in Figures 11 to 12As shown, a patterned mask layer 82 can be formed to cover the first region R1 and expose the second mask pattern 30B. The second mask pattern 30B is then removed using an etching process, forming a third trench TR3 surrounded by the second spacer 32B on the first layer RL21. Subsequently, as... Figures 11 to 13 As shown, after removing the second mask pattern 30B, the patterned mask layer 82 is removed, and a second layer RL22 is formed on the first layer RL21, and a second upper electrode TE2 is formed on the second layer RL22. In some embodiments, a second resistive material layer 28 may be formed after removing the second mask pattern 30B, and a third conductive layer 36 may be formed on the second resistive material layer 28, and the second resistive material layer 28 and the third conductive layer 36 may be filled in the third trench TR3. Then, a planarization process (e.g., chemical mechanical polishing process, but not limited thereto) may be used to remove the second resistive material layer 28 and the third conductive layer 36 outside the third trench TR3, and the second layer RL22 of the second variable resistive layer RL2 and the second upper electrode TE2 are formed in the third trench TR3, thereby forming the second stacked structure ST2.

[0114] After that, as Figures 13 to 15 As shown, after forming the second upper electrode TE2, the first upper electrode TE1 replaces the first mask pattern 30A, thereby forming the aforementioned first stacked structure ST1. In some embodiments, a patterned mask layer 84 can be formed to cover the second region R2 and expose the first mask pattern 30A, thereby removing the first mask pattern 30A using an etching process to form the first trench TR1. After removing the first mask pattern 30A, the patterned mask layer 84 can be removed, and a fourth conductive layer 38 can be formed and filled into the first trench TR1. Then, a planarization process (e.g., chemical mechanical polishing, but not limited thereto) can be used to remove the fourth conductive layer 38 outside the first trench TR1 to form the first upper electrode TE1 in the first trench TR1, thereby forming the aforementioned first stacked structure ST1. Then, as... Figure 9 As shown, dielectric layer 40, dielectric layer 42, connector plug 44, and conductive layer 46 can be formed on the first stacked structure ST1 and the second stacked structure ST2, thereby forming Figure 9 The resistive storage device 102 shown is illustrated.

[0115] It is worth noting that the methods for forming the first variable resistance layer RL1 and the second variable resistance layer RL2 in this embodiment are not limited to those described above. Figures 10 to 13 The visual design shown may require other suitable methods to form. Figure 9The first variable resistance layer RL1 and the second variable resistance layer RL2 are shown in FIG. 1. In addition, in the present embodiment, the first upper electrode TE1 and the second upper electrode TE2 can be formed by different manufacturing process steps, and thus the material composition of the first upper electrode TE1 can be different from that of the second upper electrode TE2, but is not limited thereto. In addition, since the second upper electrode TE2 and the second layer RL22 of the second variable resistance layer RL2 can be formed after the patterning manufacturing process, etching damage to the second upper electrode TE2 or / and the second layer RL22 of the second variable resistance layer RL2 caused by the patterning manufacturing process can be avoided, which is beneficial to the electrical performance of the resistive memory device 102.

[0116] In summary, in the resistive memory device and the manufacturing method thereof, different thicknesses of the variable resistance layer can be used to increase the switchable resistance states of the resistive memory device, and thus a resistive memory device with multiple resistance states can be realized. In addition, by the manufacturing method of the present application, the variable resistance layer with different thicknesses can be formed under the condition of reducing the etching damage to the variable resistance layer, and thus the overall electrical performance of the resistive memory device can be improved.

[0117] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A resistive memory device, characterized by, Comprising: a first stack structure, the first stack structure comprising: a first lower electrode; a first upper electrode disposed on the first lower electrode; and a first variable resistance layer disposed between the first lower electrode and the first upper electrode in a vertical direction; and a second stack structure, the second stack structure comprising: a second lower electrode; a second upper electrode disposed on the second lower electrode; and a second variable resistance layer disposed between the second lower electrode and the second upper electrode in the vertical direction, wherein a thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer, wherein the first lower electrode and the second lower electrode are electrically connected, and the first upper electrode and the second upper electrode are electrically connected.

2. The resistive memory device of claim 1, wherein a material composition of the first variable resistance layer is the same as a material composition of the second variable resistance layer.

3. The resistive memory device of claim 1, wherein the second variable resistance layer comprises: a first layer; and a second layer disposed on the first layer, wherein a material composition of the first variable resistance layer is the same as a material composition of at least one of the first layer and the second layer.

4. The resistive memory device of claim 3, wherein the material composition of the first layer is different from the material composition of the second layer.

5. The resistive memory device of claim 3, wherein the second layer comprises a U-shaped structure around the second upper electrode in a cross-sectional view of the second variable resistance layer.

6. The resistive memory device of claim 5, wherein the material composition of the second layer is different from the material composition of the first variable resistance layer.

7. The resistive memory device of claim 5, wherein an upper surface of the second layer is coplanar with an upper surface of the second upper electrode.

8. The resistive memory device of claim 5, wherein the first stack structure further comprises: a first intermediate electrode disposed between the first lower electrode and the first upper electrode in the vertical direction, wherein the first variable resistance layer is disposed between the first intermediate electrode and the first upper electrode; and a first diode layer disposed between the first intermediate electrode and the first lower electrode, wherein the second stack structure further comprises: a second intermediate electrode disposed between the second lower electrode and the second upper electrode in the vertical direction, wherein the second variable resistance layer is disposed between the second intermediate electrode and the second upper electrode; and a second diode layer disposed between the second intermediate electrode and the second lower electrode.

9. The resistive memory device of claim 8, wherein a distance between the first upper electrode and the first intermediate electrode in the vertical direction is less than a distance between the second upper electrode and the second intermediate electrode in the vertical direction.

10. The resistive memory device of claim 8, wherein the first variable resistance layer directly contacts the first intermediate electrode and the first upper electrode, and the second variable resistance layer directly contacts the second intermediate electrode and the second upper electrode. ​ ​ ​ 11. The resistive memory device of claim 1, wherein an upper surface of the first upper electrode is coplanar with an upper surface of the second upper electrode, and a lower surface of the first upper electrode is lower than a lower surface of the second upper electrode in the vertical direction.

12. A method for fabricating a resistive memory device, comprising: forming a first stack structure on a dielectric layer, wherein the first stack structure comprises: a first lower electrode; a first upper electrode disposed on the first lower electrode; and a first variable resistance layer disposed between the first lower electrode and the first upper electrode in a vertical direction; and forming a second stack structure on the dielectric layer, wherein the second stack structure comprises: a second lower electrode; a second upper electrode disposed on the second lower electrode; and a second variable resistance layer disposed between the second lower electrode and the second upper electrode in the vertical direction, wherein a thickness of the first variable resistance layer is less than a thickness of the second variable resistance layer, wherein the first lower electrode is electrically connected to the second lower electrode, and the first upper electrode is electrically connected to the second upper electrode.

13. The method for fabricating a resistive memory device of claim 12, wherein the second variable resistance layer comprises: a first layer; and a second layer disposed on the first layer.

14. The method for fabricating a resistive memory device of claim 13, wherein the method of forming the first variable resistance layer and the second variable resistance layer comprises: forming a first resistive material layer on a first region and a second region; removing the first resistive material layer on the first region, wherein after removing the first resistive material layer on the first region, a portion of the first resistive material layer remains on the second region; forming a second resistive material layer on the first region and the second region, wherein a portion of the second resistive material layer is formed on the portion of the first resistive material layer remaining on the second region; patterning the second resistive material layer and the portion of the first resistive material layer remaining on the second region to form the first variable resistance layer on the first region and the second variable resistance layer on the second region.

15. The method for fabricating a resistive memory device of claim 14, wherein the method of forming the first variable resistance layer and the second variable resistance layer further comprises: forming a mask layer on the second resistive material layer before the patterning, wherein the mask layer is patterned by the patterning to be a first mask pattern on the first variable resistance layer and a second mask pattern on the second variable resistance layer; replacing the first mask pattern with the first upper electrode; and replacing the second mask pattern with the second upper electrode.

16. The method for fabricating a resistive memory device of claim 13, wherein the method of forming the first variable resistance layer and the second variable resistance layer comprises: forming a first resistive material layer on a first region and a second region; patterning the first resistive material layer to form the first variable resistance layer on the first region and the first layer on the second region; and forming the second layer on the first layer after the patterning. ​ ​ ​ 17. The method of claim 16, wherein the method of forming the first variable resistance layer and the second variable resistance layer further comprises: forming a mask layer on the first resistive material layer before the patterning process, wherein the mask layer is patterned by the patterning process into a first mask pattern on the first variable resistance layer and a second mask pattern on the first layer; removing the second mask pattern; forming the second layer on the first layer after removing the second mask pattern; forming the second upper electrode on the second layer; and replacing the first mask pattern with the first upper electrode after forming the second upper electrode.

18. The method of claim 16, wherein the second layer comprises a U-shaped structure in a cross-sectional view of the second variable resistance layer, surrounding the second upper electrode.

19. The method of claim 12, wherein the first stack structure further comprises: a first intermediate electrode disposed between the first lower electrode and the first upper electrode in the vertical direction, wherein the first variable resistance layer is disposed between the first intermediate electrode and the first upper electrode; and a first diode layer disposed between the first intermediate electrode and the first lower electrode, wherein the second stack structure further comprises: a second intermediate electrode disposed between the second lower electrode and the second upper electrode in the vertical direction, wherein the second variable resistance layer is disposed between the second intermediate electrode and the second upper electrode; and a second diode layer disposed between the second intermediate electrode and the second lower electrode. ​ ​ ​

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