Semiconductor device and method for forming the same

Abstract

A semiconductor structure and a method for manufacturing the same are disclosed. An exemplary manufacturing method includes: providing a workpiece including a substrate, an isolation component above the substrate, a first fin-shaped structure protruding through the isolation component, and a second fin-shaped structure protruding through the isolation component; forming a dielectric fin between the first fin-shaped structure and the second fin-shaped structure; and forming a first gate structure and a second gate structure above the first fin-shaped structure and the second fin-shaped structure, respectively. The exemplary manufacturing method also includes: etching the isolation component from the back side of the workpiece to form a groove exposing the dielectric fin; etching the dielectric fin from the back side of the workpiece to form an extended groove; and depositing a sealing layer above the extended groove. The sealing layer covers the air gap between the first gate structure and the second gate structure. Embodiments of the present application also relate to a semiconductor device and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology develops to smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure (also referred to as a gate stack) or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate structure on more than one side (e.g., the top and sidewalls of the "fin" extending from the substrate of the gate wrapping semiconductor material). MBC transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors can also be referred to as surround gate transistors (SGTs) or full ring gate (GAA) transistors.

[0004] In order to continue to provide the desired scaling and increased density for MBC transistors in smaller technology nodes, dielectric fins (also known as hybrid dielectric fins or hybrid fins) have been introduced to provide isolation between gate structures. As the gate critical dimension (CD) is further reduced, parasitic capacitance between gate structures may degrade device performance, such as circuit speed and crosstalk coupling, even if the dielectric fins are made of low-k dielectric materials. Measures to improve isolation between MBC transistor gate structures may face challenges in forming isolation structures while further reducing parasitic capacitance. Although existing semiconductor devices are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a workpiece including a front side and a back side, the workpiece including a substrate, an isolation component located above the substrate, a first fin-shaped structure protruding from the substrate and passing through the isolation component, and a second fin-shaped structure protruding from the substrate and passing through the isolation component, wherein the substrate is located at the back side of the workpiece, and the first fin-shaped structure and the second fin-shaped structure are located at the front side of the workpiece; forming a dielectric fin between the first fin-shaped structure and the second fin-shaped structure; forming a first gate structure and a second gate structure above the first fin-shaped structure and the second fin-shaped structure, respectively; etching the isolation component from the back side of the workpiece to form a groove exposing the dielectric fin; etching the dielectric fin from the back side of the workpiece to form an extended groove; and depositing a sealing layer above the extended groove, wherein the sealing layer covers the air gap between the first gate structure and the second gate structure.

[0006] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of channel members above a substrate, the channel members being vertically stacked; forming dielectric fins adjacent to lateral ends of the channel members; forming a gate structure engaging each of the channel members; removing the substrate to expose a bottom surface of the dielectric fins; removing the dielectric fins to form a groove exposing a sidewall of the gate structure; and depositing a dielectric layer above the groove, the dielectric layer capturing voids in the groove.

[0007] Some other embodiments of the present application provide a semiconductor device, comprising: a first plurality of channel members stacked vertically; a second plurality of channel members stacked vertically; a first gate structure joining the first plurality of channel members; a second gate structure joining the second plurality of channel members; a first metal wiring layer located at the front side of the semiconductor device; a second metal wiring layer located at the back side of the semiconductor device, wherein the first gate structure and the second gate structure are vertically stacked between the first metal wiring layer and the second metal wiring layer; and an isolation structure vertically stacked between the first metal wiring layer and the second metal wiring layer, wherein the isolation structure includes an air gap stacked laterally between the first gate structure and the second gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0009] Figure 1A and Figure 1BA flow chart illustrating an exemplary method for fabricating a semiconductor device according to one or more aspects of the present invention is shown.

[0010] Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig. 18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig.21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.27A , Fig.27B , Fig.27C , Fig.28A , Fig.28B , Fig.28C , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B , Fig. 30C , Fig.31A , Fig.31B , Fig.31C , Fig.32A , Fig.32B , Fig.32C According to one or more aspects of the present invention, Figure 1A and Figure 1B Partial cross-sectional views of a workpiece during various manufacturing stages in a method. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed in itself. In addition, in the following present invention, the formation of a component located, connected to and / or coupled to another component may include an embodiment in which the components are directly contacted, and may also include an embodiment in which an additional component is formed between the components so that the components may not be directly contacted. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downward", "upward", etc.) are used to easily understand the relationship between one component of the present invention and another component. Spatial relative terms are intended to cover different orientations of devices including components. In addition, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a numerical value within a reasonable range including the described numerical value, such as within + / -10% of the described numerical value or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0013] The present invention relates generally to semiconductor devices and their fabrication, and more particularly to isolation structures containing air gaps to improve isolation between gate structures with reduced parasitic capacitance.

[0014] In order to increase the drive current to meet the design requirements, the MBC transistor may include a thin and wide nanoscale channel component. Such an MBC transistor may also be referred to as a nanosheet transistor. Although nanosheet transistors can provide satisfactory drive current and channel control, their wide nanosheet channel components may make it challenging to reduce the cell size. In some exemplary structures, a fishbone structure or a fork sheet structure may be implemented to reduce the cell size. In a fishbone structure or a fork sheet structure, adjacent stacks of channel components may be separated by dielectric fins (also referred to as hybrid dielectric fins or hybrid fins). Whether it is a fishbone structure or a fork sheet structure, the close proximity between the channel components leads to a close proximity between the gate structures (also referred to as gate stacks) that engage the corresponding channel components, and thereby leads to high parasitic capacitance between the gate structures.

[0015] Although low-k dielectric materials or ultra-low-k dielectric materials have been introduced to form dielectric fins as gate isolation structures, parasitic capacitance still poses challenges to further device performance, such as circuit speed and crosstalk coupling, as gate CD is further reduced. In addition to using low-k or ultra-low-k dielectric materials, another approach is to implement an air gap, which is provided in the form of a gate isolation structure containing an air gap. Even a small air gap near a metal component can result in a significant increase in the overall effective dielectric constant (k); for example, an air gap of approximately 35% to approximately 40% of the volume between adjacent metal components can reduce parasitic capacitance by approximately 15%. As used herein, the term "air gap" is used to describe a void defined by surrounding substantial components, wherein the void may contain air, nitrogen, ambient gas, gaseous chemicals used in the manufacturing process, or a combination thereof.

[0016] Various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. Figure 1A and Figure 1B 1 and 1 , together, a flow chart of a method 100 of forming a semiconductor device is shown. The method 100 is merely an example and is not intended to limit the present invention to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2A to 32C Describing method 100, Figures 2A to 32C Partial cross-sectional views of a workpiece 200 at different stages of manufacture according to an embodiment of method 100 are shown. Because a semiconductor device will be formed from the workpiece 200, the workpiece 200 may be referred to as a semiconductor device 200 or a device 200 as the context requires. In order to better illustrate various aspects of the present invention, each of the figures ending with a capital letter A shows a partial cross-sectional view of a source / drain region of a transistor to be formed (i.e., a cut in the YZ plane in the source region or the drain region perpendicular to the longitudinal direction of the channel member), each of the figures ending with a capital letter B shows a partial cross-sectional view in a channel region of a transistor to be formed (i.e., a cut in the YZ plane in the channel region along the longitudinal direction of the gate structure and perpendicular to the longitudinal direction of the channel member), and each of the figures ending with a capital letter C shows a partial cross-sectional view along the longitudinal direction of the channel member of the transistor to be formed (i.e., a cut in the XZ plane along the longitudinal direction of the channel member and through the channel region and the adjacent source / drain region). Through Figures 2A to 32C , the X direction, the Y direction, and the Z direction are perpendicular to each other and are used consistently. In addition, throughout the present invention, the same reference numerals are used to represent the same components. Although an embodiment including a fishbone or fork-piece transistor is shown in the drawings, the present invention is not limited thereto and may be applied to other multi-gate devices, such as other types of MBC transistors or FinFETs.

[0017] refer to FIG. 2A to FIG. 2C , method 100 includes block 102 ( Figure 1A ), wherein a workpiece 200 is received. The workpiece 200 includes a substrate 202 and a stack 204 disposed on the substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may include a plurality of n-type well regions and a plurality of p-type well regions. The p-type well region may be doped with a p-type dopant (i.e., boron (B)). The n-type well region may be doped with an n-type dopant (i.e., phosphorus (P) or arsenic (As)).

[0018] exist FIG. 2A to FIG. 2C In some embodiments shown in , the stack 204 may include a bottom sacrificial layer 206B above the substrate 202, an overlying semiconductor layer 208B above the bottom sacrificial layer 206B, an alternating channel layer 208 and sacrificial layer 206 above the overlying semiconductor layer 208B, and a top sacrificial layer 206T above the sacrificial layer 206 and the channel layer 208. The bottom sacrificial layer 206B, the overlying semiconductor layer 208B, the top sacrificial layer 206T, the sacrificial layer 206, and the channel layer 208 may be deposited using an epitaxial process. Exemplary epitaxial processes may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The channel layer 208 and the sacrificial layer 206 may have different semiconductor components. In some embodiments, the channel layer 208 is formed of silicon (Si), and the sacrificial layer 206 is formed of silicon germanium (SiGe). The additional germanium (Ge) content in the sacrificial layer 206 allows for selective removal or recessing of the sacrificial layer 206 without causing substantial damage to the channel layer 208. The sacrificial layers 206 and the channel layer 208 are alternately disposed such that the sacrificial layers 206 intersect the channel layers 208. FIG. 2A to FIG. 2C Two (2) layers of sacrificial layer 206 and two (2) layers of channel layer 208 are shown alternating and arranged vertically for illustrative purposes only and are not intended to be limiting beyond what is specifically recited in the claims. The number of layers depends on the desired number of channel members 208 for semiconductor device 200. In some embodiments, the number of channel layers 208 is between 1 and 6.

[0019] The bottom sacrificial layer 206B may be formed of silicon germanium (SiGe). In one embodiment, the germanium content of the bottom sacrificial layer 206B may be the same as the germanium content of the sacrificial layer 206. In another embodiment, unlike the sacrificial layer 206, the germanium content of the bottom sacrificial layer 206B may be less than the germanium content of the sacrificial layer 206. For example, the molar ratio of the germanium content of the sacrificial layer 206 may be between about 20% and about 30%, and the germanium content of the bottom sacrificial layer 206B may be about 80% to about 90% of the germanium content of the sacrificial layer 206. In some cases, the molar ratio of the germanium content of the bottom sacrificial layer 206B may be between about 16% and about 27%. The bottom sacrificial layer 206B may be thicker than each of the sacrificial layers 206 along the Z direction. In some cases, each of the sacrificial layers 206 may have a thickness between about 4nm and about 15nm, while the bottom sacrificial layer 206B may have a thickness between about 8nm and about 30nm. As will be described below, the bottom sacrificial layer 206B is used as an etch stop layer or a mechanical grinding stop layer in a later device backside thinning process.

[0020] Both the overlying semiconductor layer 208B and the substrate 202 may include bulk single crystal silicon (Si). Optionally, the overlying semiconductor layer 208B and the substrate 202 may include the same or different semiconductor compositions, each of which may include but is not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, or combinations thereof.

[0021] Like sacrificial layer 206, top sacrificial layer 206T can be formed of silicon germanium (SiGe). In some cases, the composition of sacrificial layer 206 and top sacrificial layer 206T is substantially the same. Top sacrificial layer 206T can be thicker than sacrificial layer 206 and is used to protect stack 204 from damage during the manufacturing process. In some cases, the thickness of top sacrificial layer 206T can be between about 20nm and about 40nm, while the thickness of sacrificial layer 206 can be between about 4nm and about 15nm.

[0022] refer to FIG. 3A to FIG. 3C , method 100 includes block 104 ( Figure 1A), wherein the stack 204 and the substrate 202 are patterned to form a fin structure 210 separated by a fin trench 212. In order to pattern the stack 204 and the substrate 202, a hard mask layer 214 is deposited over the top sacrificial layer 206T. The hard mask layer 214 is then patterned to serve as an etching mask to pattern the top sacrificial layer 206T, the stack 204, and the top of the substrate 202. In some embodiments, the hard mask layer 214 can be deposited using CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or a suitable deposition method. The hard mask layer 214 can be a single layer or multiple layers. When the hard mask layer 214 is a multilayer, the hard mask layer 214 can include a pad oxide and a pad nitride layer. In an optional embodiment, the hard mask layer 214 can include silicon (Si). The fin structure 210 can be patterned using a suitable process, including a double patterning or a multiple patterning process. Typically, a double patterning or multiple patterning process combines photolithography and self-aligned processes, allowing for the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern a hard mask layer 214, and the patterned hard mask layer 214 can then be used as an etching mask to etch the stack 204 and the substrate 202 to form the fin structure 210. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0023] like FIG. 3A to FIG. 3C As shown in , each of the fin-shaped structures 210 includes a base 210Base formed by a portion of the substrate 202 and a top 210Top formed by the stack 204. The top 210Top is disposed above the base 210Base. The fin-shaped structure 210 extends longitudinally from the substrate 202 in the X direction and vertically in the Z direction. In the Y direction, the fin-shaped structures 210 are separated by fin grooves 212. Each of the fin grooves 212 (such as the fin grooves 212A and 212B in the illustrated embodiment) can define the same or different spacing between adjacent fin-shaped structures 210. In the illustrated embodiment, the fin groove 212A is wider than the fin groove 212B in the Y direction to provide a larger spacing. As shown in FIG. Figure 3A and Figure 3BAs shown in , fin groove 212A defines a first spacing S1, and fin groove 212B defines a second spacing S2. The first spacing S1 is greater than the second spacing S2. In some cases, the first spacing S1 is between about 25nm and about 40nm, and the second spacing S2 is between about 10nm and about 25nm. In various embodiments, the difference between S1 and S2 (S1-S2) is at least 8nm, which is conducive to forming a fishbone or fork-shaped structure. Similarly, each of the fin-shaped structures 210 (such as fin-shaped structures 210A, 210B and 210C in the illustrated embodiment) can have the same or different widths. As Figure 3A and Figure 3B As shown in , fin structure 210A has a first width W1, and fin structure 210B / 210C has a second width W2. The first width W1 is greater than the second width W2. In some cases, the first width W1 is between about 10nm and about 100nm, and the second width W2 is between about 10nm and about 40nm. As will be described below, the narrower fin trench 212B and the narrower fin structure 210B / 210C together allow the formation of an MBC transistor having a stack of channel members in a fishbone structure or a fork-sheet structure, while the wider fin trench 212A and the wider fin structure 210A together allow the formation of an MBC transistor having a nanosheet channel member.

[0024] refer to FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C , method 100 includes block 106 ( Figure 1A ), wherein an isolation feature 216 is formed in the fin trench 212. The isolation feature 216 may be referred to as a shallow trench isolation (STI) feature 216. In an exemplary process for forming the isolation feature 216, a dielectric material is deposited over the workpiece 200, and the fin trench 212 is filled with the dielectric material. In some embodiments, the dielectric material may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. In various instances, in box 106, the dielectric material may be deposited by flowable CVD (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process, until the hard mask layer 214 is exposed, such as FIG. 4A to FIG. 4C As shown in . After planarization, the deposited dielectric material is recessed in an etch-back process until the top 210Top of the fin structure 210, in particular the sacrificial layer 206 and the channel layer 208, rises above the isolation feature 216. The hard mask layer 214 may also be removed in the etch-back process. In the embodiment shown, the top of the overlying semiconductor layer 208B may also rise above the isolation feature 216, as shown in FIG. FIG. 5A to FIG. 5C At this time, the base 210Base, the bottom sacrificial layer 206B, and the bottom of the overlying semiconductor layer 208B are surrounded by the isolation feature 216. The isolation feature 216 reduces the depth of the fin trench 212.

[0025] refer to FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7C , method 100 includes block 108 ( Figure 1A ), wherein a first dielectric fin 218 is formed. In the illustrated embodiment, in frame 108, the first dielectric fin 218 is formed in the narrower fin trench 212B. An exemplary process for forming the first dielectric fin 218 includes sequentially conformally depositing a first dielectric layer 220 and a second dielectric layer 222 over the workpiece 200 (including in the wider fin trench 212A). The second dielectric layer 222 is surrounded by the first dielectric layer 220. The first dielectric layer 220 may be conformally deposited using CVD, ALD, or a suitable method. The first dielectric layer 220 lines the sidewalls and bottom surfaces of the fin trenches 212A and 212B. The second dielectric layer 222 is then conformally deposited over the first dielectric layer 220 using CVD, high density plasma CVD (HDPCVD), and / or other suitable processes. In some cases, the dielectric constant of the second dielectric layer 222 is less than the dielectric constant of the first dielectric layer 220. The first dielectric layer 220 may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. In one embodiment, the first dielectric layer 220 includes aluminum oxide. The second dielectric layer 222 may include silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, or a suitable dielectric material. In one embodiment, the second dielectric layer 222 includes silicon oxide. FIG. 6A to FIG. 6CIn some embodiments shown in , due to the difference in width between the fin trenches 212, the second dielectric layer 222 completely fills the narrower fin trench 212B, but does not completely fill the wider fin trench 212A. Subsequently, the exemplary process etches back the conformally deposited dielectric layers 220 and 222 to expose the top sacrificial layer 206T and remove the dielectric layers 220 and 222 from the wider fin trench 212A. In some embodiments, the dielectric layers 220 and 222 can be etched back in a dry etching process that uses oxygen, nitrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasmas, and / or combinations thereof. In some embodiments, the etch back can include a first phase directed toward the second dielectric layer 222 and a second phase directed toward the first dielectric layer 220. Unlike the narrower fin trench 212B that is completely filled with dielectric layers 220 and 222, the wider fin trench 212A allows the etchant to etch the sidewalls and bottom surfaces of the dielectric layers 220 and 222 from inside the trench, so that the dielectric layers 220 and 222 are removed from the wider fin trench 212A at a faster rate than from the narrower fin trench 212B. FIG. 7A to FIG. 7C As shown in FIG. 1 , at the conclusion of block 108 , the dielectric layers 220 and 222 are removed from the wider fin trench 212A, while the dielectric layers 220 and 222 together define the first dielectric fin 218 in the narrower fin trench 212B.

[0026] refer to FIG. 8A to FIG. 8C and 9A to 9C , method 100 includes block 110 ( Figure 1A ), wherein a second dielectric fin 224 is formed. In the illustrated embodiment, in frame 110, the second dielectric fin 224 is formed in the wider fin trench 212A. An exemplary process for forming the second dielectric fin 224 includes depositing a cladding layer 226 over the workpiece 200 (including over the sidewalls of the wider fin trench 212A) as the wider fin trench 212A is exposed at the end of frame 108. In some embodiments, the cladding layer 226 may have a composition similar to that of the sacrificial layer 206 or the top sacrificial layer 206T. In one example, the cladding layer 226 may be formed of silicon germanium (SiGe). Their common composition allows for the selective and simultaneous removal of the sacrificial layer 206 and the cladding layer 226 in a subsequent etching process. In some embodiments, the cladding layer 226 may be conformally and epitaxially grown using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). As FIG. 8A to FIG. 8CAs shown in FIG. 1 , the cladding layer 226 is selectively disposed on the exposed sidewall surfaces in the wider fin trench 212A. Depending on the degree of selective growth of the cladding layer 226, an etch-back process may be performed to expose the isolation features 216. Subsequently, the exemplary process conformally deposits a third dielectric layer 228 and a fourth dielectric layer 230 into the trench 212A, as shown in FIG. FIG. 9A to FIG. 9B As shown in . The fourth dielectric layer 230 is surrounded by the third dielectric layer 228. The composition and formation of the third dielectric layer 228 may be the same or substantially similar to those of the first dielectric layer 220, and the composition and formation of the fourth dielectric layer 230 may be the same or substantially similar to those of the second dielectric layer 222. Optionally, the composition and formation of the third dielectric layer 228 may be different from those of the first dielectric layer 220, and the composition and formation of the fourth dielectric layer 230 may be different from those of the second dielectric layer 222. In some embodiments, the third dielectric layer 228 may be deposited using CVD, HDPCVD, or flowable CVD (FCVD), and the fourth dielectric layer 230 may be deposited using FCVD. After depositing the dielectric layers 228 and 230, the workpiece 200 is planarized using a chemical mechanical polishing (CMP) process to expose the top sacrificial layer 206T. As 9A to 9C As shown in FIG. 1 , at the end of the CMP process, dielectric layers 228 and 230 together define a second dielectric fin 224 in the wider fin trench 212A. In various embodiments, the width of the second dielectric fin 224 may be the same as or wider than the width of the first dielectric fin 218 .

[0027] refer to FIG. 10A to FIG. 10C , method 100 includes block 112 ( Figure 1A ), wherein the top sacrificial layer 206T in the fin-shaped structure 210 is removed. In block 112, the workpiece 200 is etched to selectively remove portions of the top sacrificial layer 206T and the cladding layer 226 to expose the topmost channel layer 208 without substantially damaging the dielectric fins 218 and 224. In some cases, because the top sacrificial layer 206T and the cladding layer 226 are formed of silicon germanium (SiGe), the etching process in block 112 can be selective to silicon germanium (SiGe). For example, the cladding layer 226 and the top sacrificial layer 206T can be etched using a selective wet etching process including ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or a combination thereof. After removing portions of the top sacrificial layer 206T and the cladding layer 226, the dielectric fins 218 and 224 rise above the topmost channel layer 208.

[0028] refer to FIG. 11A to FIG. 11C , method 100 includes block 114 ( Figure 1A), wherein a dummy gate stack 240 is formed over the channel region of the fin structure 210. In some embodiments, a gate replacement process (or a gate-last process) is employed, wherein the dummy gate stack 240 is used as a placeholder for a functional gate structure. Other processes and configurations are also possible. In the illustrated embodiment, the dummy gate stack 240 includes a dummy dielectric layer 242 and a dummy electrode 244 disposed over the dummy dielectric layer 242. For patterning purposes, a gate top hard mask 246 is deposited over the dummy gate stack 240. The gate top hard mask 246 may be multilayer and include a silicon nitride mask layer 248 and a silicon oxide mask layer 250 over the silicon nitride mask layer 248. The region of the fin structure 210 located below the dummy gate stack 240 may be referred to as a channel region. Each of the channel regions in the fin structure 210 is sandwiched between two source / drain regions for source / drain formation. In an exemplary process, the dummy dielectric layer 242 is blanket deposited over the workpiece 200 by CVD. A material layer for dummy electrode 244 is then blanket deposited over dummy dielectric layer 242. Dummy dielectric layer 242 and the material layer for dummy electrode 244 are then patterned using a photolithography process to form dummy gate stack 240. In some embodiments, dummy dielectric layer 242 may include silicon oxide, and dummy electrode 244 may include polysilicon (poly silicon).

[0029] refer to FIG. 12A to FIG. 12C , method 100 includes block 116 ( Figure 1A ), wherein a gate spacer 252 is formed along the sidewalls of the dummy gate stack 240. The gate spacer 252 may include two or more gate spacer layers. The dielectric material for the gate spacer 252 may be selected to allow selective removal of the dummy gate stack 240. Suitable dielectric materials may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, silicon oxynitride, and / or combinations thereof. In an exemplary process, the gate spacer 252 may be conformally deposited over the workpiece 200 using CVD, sub-atmospheric CVD (SACVD), or ALD, and then anisotropically etched to remove the horizontal portion, while the vertical portion of the gate spacer 252 remains on the sidewalls of the dummy gate stack 240.

[0030] Still reference FIG. 12A to FIG. 12C , method 100 includes block 118 ( Figure 1A), wherein the source / drain region of the fin structure 210 is recessed to form a source recess and a drain recess, collectively referred to as a source / drain recess 254 (or source / drain trench 254). Using the dummy gate stack 240 and the gate spacer 252 as an etch mask, the workpiece 200 is anisotropically etched to form the source / drain recess 254 above the source / drain region of the fin structure 210. In the embodiment shown, the operation in box 118 removes the sacrificial layer 206, the channel layer 208, the capping layer 226, and the top of the overlying semiconductor layer 208B from the source / drain region, thereby exposing the isolation feature 216. In some embodiments, the source / drain recess 254 can extend into the overlying semiconductor layer 208B and be located below the top surface of the isolation feature 216. The anisotropic etching in box 118 can include a dry etching process. For example, the dry etching process can be implemented with hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof.

[0031] refer to FIG. 13A to FIG. 13C , method 100 includes frame 120, wherein the source / drain recess 254 in the source region is further extended into the overlying semiconductor layer 208B by an etching process to form a deep source / drain recess 254S. In the illustrated embodiment, the deep source / drain recess 254S is located between the dielectric fins 218 and 224. A patterned mask (not shown) may be formed before the etching process in frame 120 to limit the etching process in the source region. In other embodiments, the operation in frame 120 may optionally extend the source / drain recess in the drain region or the source region and the drain region. In the present invention, source and drain may be used interchangeably. The etching in frame 120 may be performed using a dry etching process that tends to be anisotropic or a wet etching process that tends to be isotropic. An example selective wet etching process may include the use of ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F) or a suitable wet etchant. An example selective dry etching process may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), argon (Ar), or mixtures thereof. In the illustrated embodiment, the deep source / drain recesses 254S are disposed in a layer above the bottom sacrificial layer 206B. In some optional embodiments, the bottom sacrificial layer 206B is used as an etch stop layer for the etching process in block 120, and the deep source / drain recesses 254S expose the top surface of the bottom sacrificial layer 206B. Similarly, Fig.13AAs shown in , because the sidewalls of the first dielectric fin 218 and the underlying isolation feature 216 are substantially flush, the deep source / drain recess 254S has straight sidewalls on the side of the first dielectric fin 218 and stepped sidewalls on the side of the second dielectric fin 224 .

[0032] Still reference FIG. 13A to FIG. 13C , the method 100 includes a block 122, in which an inner spacer feature 256 is formed. In some embodiments, in block 122, the sacrificial layer 206 exposed in the source / drain recess 254 and the deep source / drain recess 254S is first selectively and partially recessed to form the inner spacer recess, while the exposed channel layer 208 is substantially not etched. Because the cladding layer 226 and the sacrificial layer 206 share similar compositions, the cladding layer 226 may also be recessed in block 122. In embodiments where the channel layer 208 consists essentially of silicon (Si), the sacrificial layer 206 consists essentially of silicon germanium (SiGe), and the cladding layer 226 consists essentially of silicon germanium (SiGe), the selectivity and partial recessing of the sacrificial layer 206 and the cladding layer 226 may include a SiGe oxidation process and subsequent SiGe oxide removal. In those embodiments, the SiGe oxidation process may include the use of ozone. In some other embodiments, the partial recessing may include a selective etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 and the cladding layer 226 are recessed is controlled by the duration of the etching process. The selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or a combination thereof (e.g., an APM etch including a mixture of ammonium hydroxide-hydrogen peroxide-water). After forming the internal spacer recess, an internal spacer material layer is then conformally deposited over the workpiece 200 (including over and in the internal spacer recess and the space left by the removed portion of the cladding layer 226) using CVD or ALD. The internal spacer material may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, or silicon oxynitride. After depositing the internal spacer material layer, the internal spacer material layer is etched back to form an internal spacer feature 256, such as FIG. 13A to FIG. 13C as shown in .

[0033] refer to FIG. 14A to FIG. 14C, the method 100 includes a frame 124, in which a source / drain feature 258 is formed. The source / drain feature 258 is selectively and epitaxially deposited on the exposed semiconductor surface of the channel layer 208 and the overlying semiconductor layer 208B in the source / drain recess 254 and the deep source / drain recess 254S. The source / drain feature 258 can be deposited using an epitaxial process, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Depending on the design of the workpiece 200, the source / drain feature 258 can be n-type or p-type. When the source / drain features 258 are n-type, they can include silicon (Si) doped with an n-type dopant such as phosphorus (P) or arsenic (As). When the source / drain features 258 are p-type, they can include silicon germanium (SiGe) doped with a p-type dopant such as boron (B) or gallium (Ga). The doping of the source / drain features 258 can be performed in situ with their deposition or ex situ using an implantation process such as a junction implantation process. The source / drain features 258 formed in the deep source / drain recesses 254S have extended bottoms 258B that extend deeper toward the back side of the workpiece 200 than other source / drain features 258 formed in the source / drain recesses 254. The extended bottoms 258B reserve space for forming backside self-aligned source / drain contacts in subsequent manufacturing processes. As discussed above, in the example Fig.14A In the illustrated embodiment shown in , the source / drain feature 258 having the extended bottom 258B is a source feature formed in the source region, and the other two source / drain features 258 on both sides thereof are drain features formed in the drain region. However, alternatively, the source / drain feature 258 having the extended bottom 258B may be a drain feature, and the other two source / drain features 258 on both sides thereof may be a source feature. In the present invention, source and drain may be used interchangeably. Similarly, Fig.14A As shown in , at the stepped regions of the sidewalls of the source / drain recesses 254 and the deep source / drain recesses 254S, the facets of the source / drain features 258 may capture voids 260 between the source / drain features 258 and dielectric features, such as the second dielectric fins 224 and the isolation features 216. In comparison, due to the straight sidewalls of the source / drain recesses 254 and the deep source / drain recesses 254S on the sides of the first dielectric fins 218, the voids 260 may not be formed on the straight sidewalls, as shown in the illustrated embodiment.

[0034] Still reference FIG. 14A to FIG. 14C , method 100 includes block 126 ( Figure 1A), wherein a contact etch stop layer (CESL) 262 and an interlayer dielectric (ILD) layer 264 are deposited on the front side of the workpiece 200. In an exemplary process, the CESL 262 is first conformally deposited over the workpiece 200, and then the ILD layer 264 is blanket deposited over the CESL 262. The CESL 262 may include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The CESL 262 may be deposited using an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 264 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 264 may be deposited by spin coating, an FCVD process, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 264, the workpiece 200 may be annealed to improve the integrity of the ILD layer 264. In order to remove excess material (including the gate top hard mask 246) and to expose the top surface of the dummy electrode 244 of the dummy gate stack 240, a planarization process (such as a CMP process) may be performed on the workpiece 200 to provide a planar top surface. The top surface of the dummy electrode 244 is exposed on the planar top surface.

[0035] refer to FIG. 15A to FIG. 15C , method 100 includes block 128 ( Figure 1A), wherein the dummy gate stack 240 and the sacrificial layer 206 are selectively removed. The dummy gate stack 240 exposed at the end of frame 126 is removed from the workpiece 200 by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer 242 and the dummy electrode 244 without substantially damaging the channel layer 208 and the gate spacer 252. The removal of the dummy gate stack 240 creates a gate trench 266 over the channel region. After removing the dummy gate stack 240, the channel layer 208, the sacrificial layer 206, and the cladding layer 226 in the channel region are exposed in the gate trench 266. Subsequently, the operation in frame 128 selectively removes the sacrificial layer 206 and the cladding layer 226 from the gate trench 266 to release the channel layer 208. The released channel layer 208 at the end of frame 128 is also represented as a channel member 208. In the depicted embodiment where the channel member 208 is similar to a sheet or nanosheet, the channel member release process may also be referred to as a sheet forming process. The channel member 208 is stacked vertically in the Z direction. All channel members 208 are spaced apart from the second dielectric fin 224, and some of the channel members 208 adjacent to the first dielectric fin 218 extend laterally from the sidewalls of the first dielectric fin 218. The selective removal of the sacrificial layer 206 and the cladding layer 226 may be achieved by selective dry etching, selective wet etching or other selective etching processes. In some embodiments, the selective wet etching includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2) or a combination thereof (e.g., APM etching including a mixture of ammonium hydroxide-hydrogen peroxide-water). In some optional embodiments, the selective removal includes silicon germanium oxidation and subsequent silicon germanium oxide removal. For example, oxidation may be provided by ozone cleaning and then by silicon germanium oxide removed by an etchant such as NH4OH. With the sacrificial layer 206 and the cladding layer 226 removed from the channel region, the dielectric fins 218 and 224 , the channel member 208 , the top surface of the overlying semiconductor layer 208B, the inner spacer features 258 , and the isolation features 216 are exposed in the gate trench 266 .

[0036] refer to FIG. 16A to FIG. 16C , method 100 includes block 130( Figure 1A), wherein the first dielectric fin 218 and the second dielectric fin 224 are thinned in width by selectively removing the outer dielectric layers (the first dielectric layer 220 and the third dielectric layer 228). The thinning of the dielectric fins 218 and 224 provides a larger gate trench volume, which in turn facilitates the deposition of the various dielectric layers and metal layers in the functional gate structure to be formed. The dielectric layers 220 and 228 exposed in the gate trench 266 are removed from the channel area by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dielectric layers 220 and 228 without substantially damaging the dielectric layers 222 and 230. As discussed above, dielectric layers 220 and 228 may include the same or similar composition, and the selective etching process may remove both dielectric layers in a single stage; alternatively, dielectric layers 220 and 228 may include different compositions, and the selective etching process may include a first stage directed toward one of dielectric layers 220 and 228 and a second stage directed toward the other. Fig. 16B As shown in , some portions of the first dielectric layer 220 are sandwiched between the channel member 208 and the second dielectric layer 222, and some portions of the first dielectric layer 220 stacked between the second dielectric layer 222 and the isolation feature 216 may remain due to their less exposed area to the etchant and the correspondingly smaller etching rate. Similarly, some portions of the third dielectric layer 228 stacked between the fourth dielectric layer 230 and the isolation feature 216 may remain. In addition, the portion of the first dielectric layer 220 stacked between the second dielectric layer 222 and the isolation feature 216 may have a greater width than the second dielectric layer 222, and due to the shielding of the channel member 208 above the adjacent first dielectric fin 218, the isolation feature 216 below may be completely covered. In comparison, the portion of the third dielectric layer 228 stacked between the fourth dielectric layer 230 and the isolation feature 216 may have the same or smaller width as the fourth dielectric layer 230 or smaller than the fourth dielectric layer 230, and the isolation feature 216 below is exposed. Although not shown, in some alternative embodiments, the selective etching process may completely remove the dielectric layers 220 and 228 from the gate trench 266 , thereby leaving the channel member 208 spaced apart from the first dielectric fin 218 and the second dielectric fin 224 .

[0037] refer to FIG. 17A to FIG. 17C , method 100 includes block 132 ( Figure 1B), wherein a gate structure 270 (also referred to as a functional gate structure 270 or a metal gate structure 270) is formed in the gate trench 266 to engage each of the channel members 208. Each of the gate structures 270 includes a gate dielectric layer 272 disposed on the channel member 208 and a gate electrode layer 274 above the gate dielectric layer 272. In some embodiments, the gate dielectric layer 272 includes an interfacial layer and a high-k dielectric layer. The interfacial layer may include silicon oxide and is formed due to a pre-cleaning process. An exemplary pre-cleaning process may include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surface of the channel member 208 to form an interfacial layer. A high-k dielectric layer is then deposited over the interfacial layer using ALD, CVD, and / or other suitable methods. The high-k dielectric layer includes a high-k dielectric material. In one embodiment, the high-k dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectric layers, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After the gate dielectric layer 272 is formed, the gate electrode layer 274 is deposited over the gate dielectric layer 272. The gate electrode layer 274 may be a multilayer structure including at least one work function layer and a metal filling layer. For example, at least one work function layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN) or tantalum carbide (TaC). The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 274 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. Although not explicitly shown in the figure, the gate structure 270 is deposited as a bonded gate structure and then etched back until the dielectric fins 218 and 224 separate the bonded gate structure into gate structures 270 separated from each other.The dielectric fins 218 and 224 also provide electrical isolation between adjacent gate structures 270. The etch back of the gate structure 270 may include a selective wet etch process using nitric acid, hydrochloric acid, sulfuric acid, ammonium hydroxide, hydrogen peroxide, or a combination thereof. Fig. 17B As shown in FIG, the gate structure 270 does not extend between the first dielectric fin 218 and the adjacent channel member 208 because the remaining first dielectric layer 220 fills the gap therebetween. Alternatively, as discussed above in conjunction with the operations in block 130, if the dielectric layers 220 and 228 are completely removed from the gate trenches 266 in some cases, each of the channel members 208 is thus wrapped by a corresponding gate structure 270.

[0038] refer to 18A to 18C , method 100 includes block 134 ( Figure 1B ), wherein a metal capping layer 276, a self-aligned capping (SAC) layer 278, and a gate cutting feature 280 are formed in the front side of the workpiece 200. In some embodiments, the metal capping layer 276 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), cobalt (Co), or nickel (Ni), and may be deposited using PVD, CVD, or metal organic chemical vapor deposition (MOCVD). In one embodiment, the metal capping layer 276 includes tungsten (W), such as fluorine-free tungsten (FFW), and is deposited by PVD. In some optional embodiments where the metal capping layer 276 is deposited by MOCVD, the deposition of the metal capping layer 276 may be selectively deposited on the gate structure 270. After the metal capping layer 276 is deposited, the SAC layer 278 is deposited over the workpiece 200 by CVD, PECVD, or a suitable deposition process. The SAC layer 278 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, carbon nitride silicon oxide, aluminum oxide, aluminum nitride, aluminum nitride oxide, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide or a suitable dielectric material. Then, a photolithography process and an etching process are implemented to etch the deposited SAC layer 278 to form a gate cutting opening to expose the top surface of the dielectric fin, such as the first dielectric fin 218 in the illustrated embodiment. Thereafter, a CMP process is used to deposit and planarize the dielectric material to form a gate cutting component 280 in the gate cutting opening. The dielectric material for the gate cutting component 280 can be deposited using HDPCVD, CVD, ALD or a suitable deposition technique. In some cases, the gate cutting component 280 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, carbon nitride silicon oxide, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum nitride oxide, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide or a suitable dielectric material. In some embodiments, the gate cutting feature 280 and the SAC layer 278 may have different compositions to introduce etching selectivity.

[0039] refer to FIG. 19A to FIG. 19C, method 100 includes block 136 ( Figure 1B ), wherein one or more front-side middle of line (MEOL) and front-side back-end of line (BEOL) processes are performed to form one or more interconnect layers having contacts, vias, and metal lines (also referred to as metal wiring layers) embedded in dielectric layers. In some embodiments, the operations in block 136 include forming source / drain contacts 282, source / drain contact vias 284, gate contacts 286, gate contact vias 288, additional ILD layers 290, inter-metal dielectric (IMD) layers 291, metal lines in dielectric layers of IMD layers 291, contact pads, etc. The workpiece 200 may also include a passivation layer and / or other layers built on the front side of the workpiece 200. These layers and one or more interconnect layers connect the gates, source and drain electrodes of various transistors and other circuits in the workpiece 200 to partially or entirely form an integrated circuit.

[0040] Still reference FIG. 19A to FIG. 19C , method 100 includes block 138 ( Figure 1B ), wherein the carrier 292 is attached to the front side of the workpiece 200. In some embodiments, the carrier 292 can be a silicon wafer. The operations in box 138 can use any suitable attachment process, such as direct bonding, hybrid bonding, use of adhesives or other bonding methods. In the illustrated embodiment, an adhesive layer 294 is formed on the front side of the workpiece 200 to abut the carrier 292 to the front side of the workpiece 200. The operations in box 138 can also include alignment, annealing and / or other processes. The attachment of the carrier 292 allows the workpiece 200 to be turned over. This makes it possible to access the workpiece 200 from the back side of the workpiece 200 for further processing. It should be noted that in the following figures (i.e., FIG. 20A to FIG. 32C ) turns the workpiece 200 over.

[0041] refer to FIG. 20A to FIG. 20C , method 100 includes block 140( Figure 1B), wherein the workpiece 200 is thinned from the back side of the workpiece 200 until the overlying semiconductor layer 208B and the isolation feature 216 are exposed from the back side of the workpiece 200. An exemplary thinning process may include removing the substrate 202 in a first stage and removing the bottom sacrificial layer 206B in a second stage. In some embodiments, the first stage of the thinning process includes a mechanical grinding process to completely remove the substrate 202, while the bottom sacrificial layer 206B serves as a mechanical grinding stop layer. In some embodiments, the first stage of the thinning process includes a mechanical grinding process and a chemical thinning process. A large amount of the substrate 202 may be removed during the mechanical grinding process. Thereafter, the chemical thinning process may apply an etching chemical to the back side of the workpiece to completely remove the substrate 202, while the bottom sacrificial layer 206B may serve as an etch stop layer. Similarly, in some embodiments, the second stage of the thinning process includes a mechanical grinding process to completely remove the bottom sacrificial layer 206B, while the overlying semiconductor layer 208B (and / or the isolation feature 216) serves as a mechanical grinding stop layer. In some embodiments, the second stage of the thinning process includes a mechanical grinding process and a chemical thinning process. A substantial amount of the bottom sacrificial layer 206B may be removed during the mechanical grinding process. Afterwards, a chemical thinning process may apply an etching chemistry to the back side of the workpiece to completely remove the bottom sacrificial layer 206B, while the overlying semiconductor layer 208B and isolation features 216 may serve as an etch stop layer.

[0042] refer to FIG. 21A to FIG. 21C , method 100 includes block 142 ( Figure 1B ), wherein the isolation feature 216 is selectively etched to form a trench 296 over the back side of the workpiece 200. The trench 296 exposes the dielectric fins 218 and 224 (particularly the first dielectric layer 220 and the third dielectric layer 228) and the facets of the source / drain feature 258 that capture the void 260 in the source / drain region, and also exposes the dielectric fins 218 and 224 and the gate dielectric layer 272 of the gate structure 270 in the channel region. In some embodiments, the operations in block 142 apply an etching process that is tuned to be selective to the dielectric material in the isolation feature 216 and to have no (or minimal) etching of the overlying semiconductor layer 208B, the source / drain features 258, the dielectric fins 218 and 224, and the gate dielectric layer 272. The selective etching process may be a dry etch, a wet etch, a reactive ion etch, or other suitable etching method.

[0043] refer to FIG. 22A to FIG. 22C , method 100 includes block 144 ( Figure 1B), wherein the exposed portions of the first dielectric layer 220 and the third dielectric layer 228 are selectively etched from the trench 296. As discussed above, the first dielectric layer 220 and the second dielectric layer 222 and the third dielectric layer 228 and the fourth dielectric layer 230 include different material compositions (such as high-k dielectric materials for the dielectric layers 220 and 228, low-k dielectric materials for the dielectric layers 222 and 230) to achieve etch selectivity. The operation in block 144 applies an etch process that is tuned to be selective to the materials (e.g., high-k dielectric materials) of the first dielectric layer 220 and the third dielectric layer 228 and to have no (or minimal) etching of the second dielectric layer 222 and the fourth dielectric layer 230. Furthermore, in the illustrated embodiment, the common or similar composition (such as high-k dielectric materials) allows for the selective and simultaneous removal of the exposed portions of the gate dielectric layer 272 and the dielectric layers 220 and 228 from the trench 296 in the same selective etch process. The selective etching process may be dry etching, wet etching, reactive ion etching or other suitable etching methods. Fig.22A and Fig. 22B As shown in , the dielectric layers 220 and 228 are removed from the trench 296 to expose the second dielectric layer 222 , the fourth dielectric layer 230 , and the gate electrode layer 274 .

[0044] refer to FIG. 23A to FIG. 23C , method 100 includes block 146 ( Figure 1B ), wherein the trench 296 is extended by selectively etching the second dielectric layer 222 and the fourth dielectric layer 230 from the trench 296. Removing the dielectric layers 222 and 230 from the trench 296 exposes the third dielectric layer 228 and the CESL 262 in the source / drain region, and exposes the gate dielectric layer 272, the metal cap layer 276, and the gate cut feature 280 in the channel region. The operation in box 146 applies an etching process that is adjusted to be selective to the material (e.g., low-k dielectric material) of the second dielectric layer 222 and the fourth dielectric layer 230 and to have no (or minimal) etching of the third dielectric layer 228 and the gate dielectric layer 272. The selective etching process can be dry etching, wet etching, reactive ion etching, or other suitable etching methods. However, in some optional embodiments, the third dielectric layer 228 and the gate dielectric layer 272 can also be removed in box 146 at an additional stage of the selective etching process to further expand the volume of the trench 296.

[0045] refer to FIG. 24A to FIG. 24C , method 100 includes block 148 ( Figure 1B), wherein a sealing layer 298 covering the air gap 300 in the trench 296 is deposited over the back side of the workpiece 200. The deposition of the sealing layer 298 is also referred to as a capping process. In some embodiments, the deposited material of the sealing layer 298 includes SiN, SiOCN, SiOC, SiCN, a combination thereof, or other suitable materials. The sealing layer 298 can be deposited by CVD, PVD, PE-CVD, a coating process, or other suitable deposition techniques. In an embodiment, the sealing layer 298 is deposited by a PE-CVD process, which makes it easier for the deposited dielectric material to merge on the top of the narrow opening. The parameters in the PE-CVD process (e.g., pressure, temperature, and gas viscosity) are adjusted in such a way that the gap filling behavior of the deposited dielectric material maintains the air gap 300 without completely filling the trench 296. In the present embodiment, the PE-CVD process uses a setting with a pressure less than about 0.75 Torr and a temperature greater than about 75°C. Thus, the dielectric material of the sealing layer 298 can surround the opening of the trench 296 without being substantially deposited in the lower portion of the trench 296 and maintaining the air gap 300. The air gap 300 can extend continuously from the channel region to the adjacent source / drain region, providing isolation between adjacent gate structures 270 and also between adjacent source / drain features 258. A gas (such as a gas used during the deposition of the dielectric material of the sealing layer 298 or any other substance that can diffuse into the air gap 300) can be in the air gap 300. The operation in box 148 can include performing a planarization process, such as a CMP process, on the sealing layer 298 to remove excess dielectric material from the back side of the workpiece 200 and expose the overlying semiconductor layer 208B. The sealing layer 298 containing the air gap and the remaining portion of the first dielectric layer 220 (adjacent to the lateral ends of some of the channel features 208) together define an isolation structure that is laterally stacked between adjacent gate structures 270 to provide isolation. The isolation structure may also be referred to as a gate isolation structure or a hybrid fin.

[0046] In such FIG. 24A to FIG. 24C In one embodiment shown in , the air gap 300 resides below the bottom surface (defined as the surface near the back side of the workpiece 200) of the gate structure 270. FIG. 25A to FIG. 25C In another embodiment shown in , the air gap 300 can extend beyond the bottom surface of the gate structure 270. Extending the air gap 300 beyond the bottom surface of the gate structure 270 helps to improve the isolation between the gate structures 270. FIG. 26A to FIG. 26C In yet another embodiment shown in FIG, instead of an elongated continuous air gap in one trench 296, the capping process in block 148 can create a series of smaller air gaps 300 vertically stacked in one trench 296. The bottommost smaller air gap 300 can extend beyond the bottom surface of the gate structure 270. FIG. 27A to FIG. 27CIn yet another embodiment shown in , as discussed above in conjunction with block 146, the third dielectric layer 228 and the gate dielectric layer 272 can be removed from the trench 296 before depositing the sealing layer 298. By removing the third dielectric layer 228 and the gate dielectric layer 272, the sealing layer 298 is deposited on the sidewalls of the source / drain features 258 in the source / drain region and on the sidewalls of the gate electrode layer 274 in the channel region. One benefit of removing the third dielectric layer 228 and the gate dielectric layer 272 is that the trench 296 can be expanded in the Y direction, allowing the formation of an air gap with a larger volume, which in turn further improves isolation and reduces parasitic capacitance.

[0047] refer to FIG. 28A to FIG. 28C , method 100 includes block 150( Figure 1B ), wherein the overlying semiconductor layer 208B is selectively etched to form a trench 302 over the backside of the gate structure 270 and the source / drain feature 258. The trench 302 exposes the surface of the source / drain feature 258 from the backside of the workpiece 200. In one exemplary process, the operations in block 150 apply an etching process that is tuned to be selective to the semiconductor material (e.g., silicon) in the overlying semiconductor layer 208B and to have no (or minimal) etching of the gate structure 270 and the source / drain feature 258. The etching process may be dry etching, wet etching, reactive ion etching, or other etching methods.

[0048] refer to FIG. 29A to FIG. 29C , method 100 includes block 152 ( Figure 1B ), wherein a dielectric layer 304 having one or more dielectric materials fills the trench 302. In some embodiments, the dielectric layer 304 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi or other suitable materials, and may be formed by PE-CVD, F-CVD or other suitable methods. The operations in block 152 also include performing a planarization process, such as a CMP process, on the dielectric layer 304 to remove excess dielectric material from the back side of the workpiece 200 and expose the extended bottom 258B of the source feature 258.

[0049] refer to FIG. 30A to FIG. 30C , method 100 includes block 154 ( Figure 1B), wherein a backside self-aligned source / drain contact 306 is formed by replacing an extended bottom portion 258B of the source feature 258 with a conductive component. An exemplary process for forming the backside self-aligned source / drain contact 306 includes recessing the extended bottom portion 258B in a selective etching process that is tuned to the epitaxial semiconductor material of the extended bottom portion 258B without (or minimally) etching the sealing layer 298 and the dielectric layer 304, thereby forming a source / drain contact hole. The selective etching process may be dry etching, wet etching, reactive ion etching, or other suitable etching methods. The selective etching process may also recess the source feature 258 exposed in the source / drain contact hole to a level flush with or below other source / drain features 258 covered by the dielectric layer 304 to make room for subsequent silicide formation. In an embodiment, the operation in block 154 forms a silicide feature (not shown) between the source feature 258 and the backside self-aligned source / drain contact 306 to further reduce the contact resistance. In one example, one or more metals are deposited into the source / drain contact holes, and then the workpiece 200 is subjected to an annealing process to induce a reaction between the one or more metals and the source feature 258 to produce the silicide feature. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide features may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. Alternatively, silicide formation may be skipped and the backside self-aligned source / drain contacts 306 may directly contact the source features 258. The backside self-aligned source / drain contacts 306 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. Backside self-aligned source / drain contacts 306 are surrounded by the sealing layer 298 .

[0050] refer to FIG. 31A to FIG. 31B , method 100 includes block 156 ( Figure 1B), wherein one or more backside middle of line (MEOL) and back end of line (BEOL) processes are performed to form one or more interconnect layers having contacts, vias, and metal lines (also referred to as metal wiring layers) embedded in a dielectric layer. In some embodiments, the operations in block 156 include forming one or more backside interconnect layers 308 having backside power rails 310 embedded in a dielectric layer on the back side of the workpiece 200. The backside power rails 310 may include contacts, vias, metal lines, and / or other conductive features. In the illustrated embodiment, an upper portion of the backside power rails 310 is electrically connected to the backside self-aligned source / drain contacts 306 by a backside metal line 312, which is part of a backside first level metal (M0) trace 314. In an embodiment, the backside power rails 310 may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable process. The backside power rail may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. Having a backside power rail beneficially increases the number of metal traces in the workpiece 200 that are available for direct connection to source / drain contacts and vias (including the backside self-aligned source / drain contacts 306). The backside power rail may have a wider dimension than the frontside first level metal (M0) traces on the front side of the workpiece 200, which beneficially reduces the backside power rail resistance. It should be noted that although as Fig.31C The resulting structure shown in FIG. 1 does not show other drain contacts (or contact plugs) to electrically connect to the two drain features 258 on both sides of the source feature 258, but in various other embodiments, such conductive features may be formed on the front side of the workpiece 200, such as FIG. 32A to FIG. 32C , which provide electrical coupling to other source / drain features that are not biased by the backside power rail. As discussed above in conjunction with box 136, the metal contact plug 316 and the source / drain contact via 318 can be formed in one or more front-side MEOL or BEOL processes.

[0051] In block 158, method 100 ( Figure 1B ) performs further manufacturing processes on the workpiece 200. For example, it may form more interconnect layers on the back side of the workpiece 200, form a passivation layer on the back side of the workpiece 200, perform other BEOL processes, and remove the carrier 292.

[0052] refer to Fig.32B. At the end of method 100, in the cross-sectional view of the YZ plane shown, three MBC transistors T-1, T-2 and T-3 separated by air gaps 300 are formed. Each MBC transistor includes a gate structure 270 that engages one or more channel members 208. In MBC transistor T-1, the gate structure 270 wraps all four sides of each channel member 208. MBC transistor T-1 can be called a nanosheet transistor. In comparison, because the channel members 208 in MBC transistors T-2 and T-3 contact the sidewalls of the hybrid fins including the air gap sealing layer 298 and originate from the sidewalls of the hybrid fins including the air gap sealing layer 298, the gate structure 270 engages those channel members 208 from the other three sides. MBC transistors T-2 and T-3 can be called fork-piece transistors or fishbone transistors. Alternatively, these MBC transistors can be called MBC transistors with fishbone / fork-piece structures. Whether it is a fishbone structure or a fork-fin structure, the close proximity between the channel components leads to a close proximity between the gate structures that join these channel components, and at the same time leads to high parasitic capacitance between the gate structures, even with low-k dielectric materials used for the isolation structures. By implementing a hybrid fin containing an air gap as an isolation structure between adjacent gate structures, the overall effective dielectric constant of the isolation structure is further reduced, which in turn leads to less parasitic capacitance and better isolation. In addition, in an embodiment of the present invention, the air gap extends continuously from the channel region into the adjacent source / drain region, also providing isolation for adjacent source / drain components.

[0053] In one exemplary aspect, the present invention relates to a method. The method includes providing a workpiece including a front side and a back side, the workpiece including a substrate, an isolation component above the substrate, a first fin-shaped structure protruding from the substrate and passing through the isolation component, and a second fin-shaped structure protruding from the substrate and passing through the isolation component. The substrate is located at the back side of the workpiece, and the first fin-shaped structure and the second fin-shaped structure are located at the front side of the workpiece. The method also includes forming a dielectric fin between the first fin-shaped structure and the second fin-shaped structure; forming a first gate structure and a second gate structure above the first fin-shaped structure and the second fin-shaped structure, respectively; etching the isolation component from the back side of the workpiece to form a groove exposing the dielectric fin; etching the dielectric fin from the back side of the workpiece to form an extended groove; and depositing a sealing layer above the extended groove, wherein the sealing layer covers the air gap between the first gate structure and the second gate structure. In some embodiments, the dielectric fin is adjacent to the first fin-shaped structure and the second fin-shaped structure. In some embodiments, the groove also exposes portions of the first gate structure and the second gate structure. In some embodiments, the extended groove exposes the gate dielectric layer of the first gate structure and the second gate structure. In some embodiments, the method also includes etching the gate dielectric layer to expand the volume of the extended groove. In some embodiments, the workpiece also includes a first source / drain component adjacent to the first fin-shaped structure and a second source / drain component adjacent to the second fin-shaped structure, and wherein the air gap extends continuously to a position sandwiched between the first source / drain component and the second source / drain component. In some embodiments, the formation of the dielectric fin includes: depositing a first dielectric layer in a groove between the first fin-shaped structure and the second fin-shaped structure, and depositing a second dielectric layer surrounded by the first dielectric layer in the groove, wherein the first dielectric layer and the second dielectric layer include different material components. In some embodiments, the method also includes: partially removing the first dielectric layer before forming the first gate structure and the second gate structure. In some embodiments, the method also includes: thinning the substrate from the back side of the workpiece to expose the isolation component before etching the isolation component. In some embodiments, the method also includes: forming a source / drain contact at the back side of the workpiece, wherein the source / drain contact is surrounded by a sealing layer.

[0054] In another exemplary aspect, the present invention relates to a method for forming a semiconductor device. The method includes: forming a plurality of channel members above a substrate, the channel members being stacked vertically; forming a dielectric fin adjacent to the lateral ends of the channel members; forming a gate structure that engages each of the channel members; removing the substrate, thereby exposing the bottom surface of the dielectric fin; removing the dielectric fin, thereby forming a groove that exposes the sidewall of the gate structure; and depositing a dielectric layer above the groove, the dielectric layer capturing a void in the groove. In some embodiments, the method also includes: before forming the gate structure, partially removing the outer layer of the dielectric fin, the portion of the stack of the outer layer between the substrate and the inner layer of the dielectric fin remaining. In some embodiments, the outer layer includes a dielectric material having a dielectric constant higher than the dielectric constant of the inner layer. In some embodiments, the void extends beyond the bottom surface of the gate structure. In some embodiments, the gate structure includes a gate dielectric layer and a gate electrode layer, and the method also includes: partially removing the gate dielectric layer from the groove, thereby exposing the gate electrode layer in the groove. In some embodiments, the method further includes: forming a source / drain feature adjacent to the channel member, the source / drain feature including an extension portion surrounded by a dielectric layer; recessing the extension portion of the source / drain feature to form a source / drain contact hole surrounded by the dielectric layer; and depositing a conductive feature in the source / drain contact hole.

[0055] In another exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes: a first plurality of channel members, stacked vertically; a second plurality of channel members, stacked vertically; a first gate structure, engaging the first plurality of channel members; a second gate structure, engaging the second plurality of channel members; a first metal wiring layer, located at the front side of the semiconductor device; a second metal wiring layer, located at the back side of the semiconductor device, the first gate structure and the second gate structure are vertically stacked between the first metal wiring layer and the second metal wiring layer; and an isolation structure, vertically stacked between the first metal wiring layer and the second metal wiring layer, wherein the isolation structure includes an air gap stacked laterally between the first gate structure and the second gate structure. In some embodiments, the semiconductor device further includes: a first source / drain component, adjacent to the first plurality of channel members; and a second source / drain component, adjacent to the second plurality of channel members, the air gap continuously extending to a position laterally stacked between the first source / drain component and the second source / drain component. In some embodiments, the air gap extends beyond the bottom surface of the first gate structure and the second gate structure. In some embodiments, the isolation structure includes a first dielectric layer surrounding the air gap and a second dielectric layer adjacent to the lateral ends of the first plurality of channel members and the second plurality of channel members.

[0056] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: Providing a workpiece including a front side and a back side, the workpiece including a substrate, an isolation feature located above the substrate, a first fin-shaped structure protruding from the substrate and passing through the isolation feature, and a second fin-shaped structure protruding from the substrate and passing through the isolation feature, wherein the substrate is located at the back side of the workpiece, and the first fin-shaped structure and the second fin-shaped structure are located at the front side of the workpiece; forming a dielectric fin between the first fin-shaped structure and the second fin-shaped structure; forming a first gate structure and a second gate structure respectively over the first fin-shaped structure and the second fin-shaped structure; etching the isolation features from a backside of the workpiece to form trenches exposing the dielectric fins; After etching the isolation features, etching the dielectric fin from a back side of the workpiece to form an extended trench; and A sealing layer is deposited over the extension trench, wherein the sealing layer covers an air gap between the first gate structure and the second gate structure.

2. The method according to claim 1, wherein: The dielectric fin abuts the first fin-shaped structure and the second fin-shaped structure.

3. The method according to claim 1, wherein: The trench also exposes portions of the first gate structure and the second gate structure.

4. The method according to claim 1, wherein: The extension trench exposes the gate dielectric layers of the first gate structure and the second gate structure.

5. The method according to claim 4, further comprising: The gate dielectric layer is etched to enlarge the volume of the extension trench.

6. The method according to claim 1, wherein: The workpiece also includes a first source / drain feature adjacent to the first fin-shaped structure and a second source / drain feature adjacent to the second fin-shaped structure, and wherein the air gap extends continuously to a location sandwiched between the first source / drain feature and the second source / drain feature.

7. The method according to claim 1, wherein: The forming of the dielectric fin comprises: depositing a first dielectric layer in the trench between the first fin structure and the second fin structure, and A second dielectric layer is deposited in the trench surrounded by the first dielectric layer, wherein the first dielectric layer and the second dielectric layer include different material compositions.

8. The method according to claim 7, further comprising: Before forming the first gate structure and the second gate structure, the first dielectric layer is partially removed.

9. The method according to claim 1, further comprising: Prior to etching the isolation features, the substrate is thinned from a back side of the workpiece to expose the isolation features.

10. The method according to claim 1, further comprising: Source / drain contacts are formed at a back side of the workpiece, wherein the source / drain contacts are surrounded by the sealing layer.

11. A method of forming a semiconductor device, comprising: forming a plurality of channel members over a substrate, the channel members being vertically stacked; forming dielectric fins adjacent lateral ends of the channel member; forming a gate structure engaging each of the channel members; removing the substrate to expose a bottom surface of the dielectric fin; removing the dielectric fins to form trenches exposing sidewalls of the gate structure; as well as A dielectric layer is deposited over the trench, the dielectric layer capturing voids in the trench.

12. The method according to claim 11, further comprising: Before forming the gate structure, an outer layer of the dielectric fin is partially removed, wherein a portion of the outer layer stacked between the substrate and the inner layer of the dielectric fin remains.

13. The method according to claim 12, wherein: The outer layer includes a dielectric material having a higher dielectric constant than the inner layer.

14. The method according to claim 11, wherein: The void extends beyond a bottom surface of the gate structure.

15. The method according to claim 11, wherein: The gate structure includes a gate dielectric layer and a gate electrode layer, and further includes: The gate dielectric layer is partially removed from the trench, thereby exposing the gate electrode layer in the trench.

16. The method according to claim 11, further comprising: forming a source / drain feature adjacent to the channel member, wherein the source / drain feature includes an extension surrounded by the dielectric layer; recessing the extending portion of the source / drain feature to form a source / drain contact hole surrounded by the dielectric layer; and Conductive features are deposited in the source / drain contact holes.

17. A semiconductor device comprising: a first plurality of vertically stacked channel members; a second plurality of channel members stacked vertically; a first gate structure engaging the first plurality of channel members; a second gate structure engaging the second plurality of channel members; A first metal wiring layer located at the front side of the semiconductor device; a second metal wiring layer located at a back side of the semiconductor device, wherein the first gate structure and the second gate structure are vertically stacked between the first metal wiring layer and the second metal wiring layer; an isolation structure vertically stacked between the first metal wiring layer and the second metal wiring layer, wherein the isolation structure includes an air gap laterally stacked between the first gate structure and the second gate structure; a first source / drain feature adjacent to the first plurality of channel members; and A second source / drain feature is adjacent to the second plurality of channel members, wherein the air gap extends continuously to a position laterally stacked between the first source / drain feature and the second source / drain feature.

18. The semiconductor device according to claim 17, wherein: The first plurality of channel members are formed of silicon.

19. The semiconductor device according to claim 17, wherein: The air gap extends beyond bottom surfaces of the first gate structure and the second gate structure.

20. The semiconductor device according to claim 17, wherein The isolation structure includes a first dielectric layer surrounding the air gap and a second dielectric layer adjoining lateral ends of the first and second pluralities of channel members.

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