Memory cell having a free ferromagnetic material layer with a curved non-planar surface and method for manufacturing such a memory cell

Abstract

The present disclosure relates to a memory cell having a free ferromagnetic material layer with a curved, non-planar surface and a method for manufacturing such a memory cell. The exemplary memory cell disclosed herein includes: a bottom electrode; a top electrode located above the bottom electrode; and an MTJ (magnetic tunnel junction) structure located above the bottom electrode and below the top electrode. In this example, the MTJ structure includes: a first ferromagnetic material layer located above the bottom electrode; a non-magnetic insulating layer located above the first ferromagnetic material layer; and a second ferromagnetic material layer located on the non-magnetic insulating layer, wherein a curved, non-planar interface exists between the non-magnetic insulating layer and the ferromagnetic material layer.

Description

Technical Field

[0001] The present disclosure relates generally to the fabrication of integrated circuits and, more particularly, to various novel embodiments of memory cells having a free ferromagnetic material layer with a curved, non-planar surface, and various novel methods of fabricating such memory cells on integrated circuit (IC) products. Background Art

[0002] There are various forms of memory technologies that utilize known STT (spin transfer torque) technology to switch the magnetization direction of a ferromagnetic material layer. One such cell is an STT-MRAM (spin transfer torque magnetic random access memory) cell. A typical STT-MRAM cell includes an MTJ (magnetic tunnel junction) structure located between a bottom electrode and a top electrode. The MTJ structure typically includes a tunnel barrier layer (e.g., MgO) located between a pinned (or reference) ferromagnetic material layer and a free ferromagnetic material layer. Typically, the bottom electrode contacts the pinned layer and the top electrode contacts the free layer. In an array of such STT-MRAM cells, the bottom electrode of each STT-MRAM cell is typically coupled to a word line, and the top electrode is coupled to a bit line.

[0003] The logic state stored in the device depends on the relative orientation between the magnetization direction of the free layer and the magnetization direction of the pinned layer. The relative orientation between the magnetization directions of the free layer and the pinned layer can have a parallel orientation (indicated by the letter "P") or an antiparallel orientation (indicated by the letter "AP"). In the parallel orientation (P), the magnetization direction orientation of the free layer and the magnetization direction orientation of the pinned layer are substantially the same. In the antiparallel orientation (AP), the magnetization direction orientation of the free layer and the magnetization direction orientation of the pinned layer are opposite to each other. When the MTJ structure is in a parallel orientation state, the MTJ structure is in a relatively low resistance state. Conversely, when the MTJ structure is in an antiparallel state, the MTJ structure is in a relatively high resistance state. In an exemplary embodiment, the parallel orientation of the MTJ structure may represent a logic "0", while the antiparallel orientation of the MTJ structure may represent a logic "1". The critical current (I C ) is a current that causes the free layer to switch from one magnetization orientation to another. Known "read" sensing circuitry is included on IC products to sense whether a logic "0" or a logic "1" is stored on a particular MRAM device. In operation, current flow from the pinned layer to the free layer must "tunnel" through the tunnel barrier layer.

[0004] Device designers have been working to create STT-MRAM cells with faster switching speeds. However, the switching speeds of STT-MRAM cells have a random probability distribution or pattern that can be statistically analyzed but cannot be accurately predicted. Typically, a relatively high current is required to increase the switching speed of STT-MRAM cells. However, this increased current leads to an undesirable increase in power consumption in IC products incorporating such STT-MRAM cells.

[0005] The present disclosure relates to various novel embodiments of memory cells having a free ferromagnetic material layer with a curved, non-planar surface, and various novel methods of fabricating such memory cells on IC products. Summary of the Invention

[0006] The following is a simplified summary of the present invention to provide a basic understanding of certain aspects of the present invention. This summary is not an exhaustive overview of the present disclosure. It is not intended to identify key or core elements of the present disclosure or to delineate the scope of the present disclosure. Its sole purpose is to present some concepts in a simplified form as a prelude to a more detailed description that will be discussed later.

[0007] In general, the present disclosure relates to various novel embodiments of memory cells having a free ferromagnetic material layer with a curved, non-planar surface, and various novel methods for fabricating such memory cells in integrated circuit products. The exemplary memory cells disclosed herein include: a bottom electrode; a top electrode located above the bottom electrode; and an MTJ (magnetic tunnel junction) structure located above the bottom electrode and below the top electrode. In this example, the MTJ structure includes: a first ferromagnetic material layer located above the bottom electrode; a non-magnetic insulating layer located above the first ferromagnetic material layer; and a second ferromagnetic material layer located on the non-magnetic insulating layer, wherein a curved, non-planar interface exists between the non-magnetic insulating layer and the ferromagnetic material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like elements, and wherein:

[0009] Figure 1-15 Various novel embodiments of memory cells having a free ferromagnetic material layer with a curved, non-planar surface and various novel methods of fabricating such memory cells on IC products are depicted. The drawings are not drawn to scale.

[0010] While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims. DETAILED DESCRIPTION

[0011] Various exemplary embodiments of the present disclosure are described below. For the sake of clarity, not all features of an actual implementation are described in this specification. Of course, it will be understood that in the development of any such actual embodiment, a large number of implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which will vary from one implementation to another. Furthermore, it will be understood that such a development effort may be complex and time-consuming, but it will still be a routine task for those of ordinary skill in the art who benefit from this disclosure.

[0012] The present subject matter will now be described with reference to the accompanying drawings. For illustrative purposes, various structures, systems and devices are schematically depicted in the accompanying drawings only so as not to obscure the present disclosure with details well known to those skilled in the art. However, the accompanying drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted as having meanings consistent with the understanding of these words and phrases by those skilled in the relevant art. No definition of a particular term or phrase (i.e., a definition that is different from the ordinary and commonly used meaning as understood by those skilled in the art) is intended to be implied by the consistent use of the term or phrase in this article. To the extent that a term or phrase is intended to have a special meaning (i.e., a meaning other than that understood by those skilled in the art), such a special definition will be clearly set forth in the specification in a definitive manner that directly and clearly provides a special definition for the term or phrase.

[0013] It will be apparent to those skilled in the art after reading this application in its entirety that the various embodiments of the STT-MRAM device disclosed herein can be incorporated into any type of integrated circuit product, for example, a standalone memory product, a product in which the memory circuit is embedded in a logic circuit, and the like. The various components, structures, and material layers described herein can be formed using a variety of different materials and by performing various known process operations (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal growth processes, spin coating techniques, etc.). The thickness of these various material layers can also vary depending on the specific application. With reference to the accompanying drawings, various exemplary embodiments of the methods and devices disclosed herein will now be described in more detail.

[0014] Figure 1-15Various novel embodiments of a memory cell 11 having a free ferromagnetic material layer with a curved non-flat surface and various novel methods of manufacturing such a memory cell 11 on an IC product 10 are described. In the exemplary examples described and shown herein, the memory cell is an STT-MRAM cell. Of course, after reading this application in its entirety, one skilled in the art will understand that the presently disclosed invention can be applied to any type of memory technology that uses the STT effect for switching, such as spin-orbit torque (SOT) MRAM, voltage-controlled magnetic anisotropy (VCMA) MRAM, etc. Therefore, the claimed invention should not be considered limited to the exemplary STT-MRAM technology described herein.

[0015] IC product 10 will be formed on and above a semiconductor substrate (not shown). The semiconductor substrate can have various configurations, such as a bulk silicon configuration. The substrate can also have a semiconductor-on-insulator (SOI) configuration, which includes a base semiconductor layer, a buried insulating layer, and an active semiconductor layer located above the buried insulating layer, wherein transistor devices (not shown) formed on the substrate are formed in and above the active semiconductor layer. The substrate can be made of silicon, or it can be made of a semiconductor material other than silicon. Therefore, the term "substrate" or "semiconductor substrate" should be understood to cover all semiconductor materials and all forms of such semiconductor materials.

[0016] In execution Figure 1 Prior to the processing operations shown, various transistor devices ( Figure 1 ) and various conductive contact structures (not shown) coupled to these transistor devices. Figure 1 For example, at this point in the process flow, transistors (not shown) used as read switching elements for the STT-MRAM cell 11, and possibly other CMOS-based transistors (not shown) for other non-memory circuits such as peripheral logic, will have been formed on the IC product 10 by performing conventional manufacturing techniques.

[0017] In the depicted example, the IC product 10 includes an insulating material layer 12 (e.g., silicon dioxide, low-k (k value less than 3.3)) and a conductive structure 14 (e.g., a conductive via) located in the insulating material layer 12. The conductive structure 14 can be composed of any conductive material, can have any desired configuration, and can be manufactured using any of a variety of different known manufacturing techniques (e.g., single damascene or dual damascene). As shown, in one exemplary embodiment, the conductive structure 14 has a convex upper surface 13 relative to a substantially horizontally oriented upper surface (not shown) of a semiconductor substrate (not shown). After reading this application in its entirety, one skilled in the art will understand that the conductive structure 14 will be conductively coupled to the bottom electrode of the novel STT-MRAM cell 11 disclosed herein.

[0018] Figure 1 The exemplary STT-MRAM cell 11 in FIG. 1 includes a bottom electrode 16, a plurality of material layers for an MTJ (magnetic tunnel junction) structure 50, and a top electrode 26. The bottom electrode 16 can be formed to any desired thickness, and it can be formed from any conductive material (e.g., a metal-containing material, a metal compound, etc.). In one exemplary embodiment, the bottom electrode 16 can be composed of tantalum nitride. The top electrode 26 can be formed to any desired thickness, and it can be formed from any conductive material (e.g., a metal-containing material, a metal compound, etc.). In one exemplary embodiment, the top electrode 26 can be composed of tantalum nitride. The bottom electrode 16 and the top electrode 26 do not need to be formed from the same conductive material (nor have the same thickness), but this may happen in some applications.

[0019] The MTJ structure 50 described herein can be made of a variety of different materials, have a variety of different thicknesses, and be arranged in a variety of different configurations. In one exemplary embodiment, the MTJ structure 50 can include a pinned (or reference) ferromagnetic material layer 18A, a free ferromagnetic material layer 18B, and a non-magnetic insulating layer 20, such as a tunnel oxide layer. In the depicted example, an optional top insulating layer 24 (e.g., an oxide material) is located on top of the free ferromagnetic material layer 18B to enhance its magnetic anisotropy in the p-MTJ device.

[0020] The pinned ferromagnetic material layer 18A can be formed to any desired thickness, for example, 1-5 nm, and can be composed of any of a variety of ferromagnetic materials, for example, Co / Pt or Co / Ni multilayers, Co, Fe, Ni, CoFeB alloys, etc. Although the pinned ferromagnetic material layer 18A is simplified as a single material layer in the drawings, in real-world devices, the pinned ferromagnetic material layer 18A may include multiple material layers arranged in various different stacked configurations (from top to bottom).

[0021] The free ferromagnetic material layer 18B can be formed to any desired thickness, for example, 1-3 nm, and can be composed of any of a variety of ferromagnetic materials, such as Co / Pt or Co / Ni multilayers, Co, Fe, Ni, CoFeB alloys, etc. Although the free ferromagnetic material layer 18B is simplified as a single material layer in the drawings, in real-world devices, the free ferromagnetic material layer 18B may include multiple material layers arranged in a variety of different stacked configurations (from top to bottom). The pinned ferromagnetic material layer 18A and the free ferromagnetic material layer 18B need not be formed of the same ferromagnetic material (nor have the same thickness), but this may occur in some applications.

[0022] In one exemplary embodiment, the non-magnetic insulating layer 20 may include an oxide-based insulating material, such as MgO, Al2O3, TiO x , AlTiO, MgZnO, ZnO, Ga2O3, etc., and can be formed to any desired thickness. The top insulating layer 24 can be formed of any insulating material, for example, MgO, etc., and can be formed to any desired thickness. The non-magnetic insulating layer 20 and the top insulating layer 24 do not need to be formed of the same material (or material stack) or to have the same thickness, but this may happen in some applications.

[0023] Figure 1 Also depicted are: conformal etch stop layer 22, e.g., silicon nitride; insulating material layer 32, e.g., silicon dioxide, a low-k material, etc.; insulating material layer 34, e.g., silicon dioxide, a low-k material, etc.; and conductive structure 36, e.g., a conductive via located in insulating material layer 34 and conductively coupled to top electrode 26. Conductive structure 36 can be made of the same material as conductive structure 14, but this is not necessarily the case in all applications.

[0024] Continue to refer Figure 1 In one exemplary embodiment, bottom electrode 16 is positioned on and in physical contact with conductive structure 14, pinned ferromagnetic material layer 18A is positioned on and in physical contact with bottom electrode 16, nonmagnetic insulating layer 20 is positioned on and in physical contact with pinned ferromagnetic material layer 18A, free ferromagnetic material layer 18B is positioned on and in physical contact with nonmagnetic insulating layer 20, top insulating layer 24 is positioned on and in physical contact with free ferromagnetic material layer 18B, and top electrode 26 is positioned on and in physical contact with top insulating layer 24.

[0025] Figure 1is a cross-sectional view taken through the center of the MTJ structure 50 and the entire STT-MRAM cell 11. Those skilled in the art will appreciate, after reading this application in its entirety, that the various structures of the novel STT-MRAM cell 11 disclosed herein include one or more curved surfaces relative to a substantially horizontally oriented reference surface (e.g., a substantially horizontally oriented upper surface (not shown) of a semiconductor substrate (not shown)). As described above, in one exemplary embodiment, the conductive structure 14 includes a curved or dished upper surface 13. In one exemplary arrangement, the curved or concave upper surface 13 of the conductive structure 14 is joined to the curved or concave bottom surface 15 of the bottom electrode 16; the bottom electrode 16 includes a curved or concave upper surface 17 that is joined to the curved or concave bottom surface 19 of the pinned ferromagnetic material layer 18A; the pinned ferromagnetic material layer 18A includes a curved or concave upper surface 21 that is joined to the curved or concave bottom surface 23 of the nonmagnetic insulating layer 20; the nonmagnetic insulating layer 20 includes a curved or concave upper surface 25 that is joined to the curved or concave bottom surface 27 of the free ferromagnetic material layer 18B; the free ferromagnetic material layer 18B includes a curved or concave upper surface 29 that is joined to the curved or concave bottom surface 31 of the top insulating layer 24; and the top insulating layer 24 includes a curved or concave upper surface 33 that is joined to the curved or concave bottom surface 35 of the top electrode 26. The top electrode 26 also has a substantially flat upper surface 37.

[0026] exist Figure 1 In the example shown, all curved or recessed upper surfaces 13, 17, 21, 25, 29, and 33 and all curved or recessed lower surfaces 15, 19, 23, 27, 31, and 35 are convex surfaces relative to a reference upper surface (not shown) oriented substantially horizontally of a semiconductor substrate (not shown). Of course, after reading this application in its entirety, one skilled in the art will understand that in other embodiments, the curvature of these surfaces may be reversed, i.e., all curved or recessed upper surfaces 13, 17, 21, 25, 29, and 33 and all curved or recessed lower surfaces 15, 19, 23, 27, 31, and 35 may be concave surfaces relative to a reference upper surface (not shown) oriented substantially horizontally of a semiconductor substrate (not shown). Importantly, the reference Figure 1, the convex upper surface 25 of the non-magnetic insulating layer 20 and the convex lower surface 27 of the free ferromagnetic material layer 18B define a curved, non-flat or concave interface 41 between the non-magnetic insulating layer 20 and the free ferromagnetic material layer 18B, specifically a convex interface 41. As will be described more fully below, the presence of the novel curved, non-flat or concave interface 41 between the non-magnetic insulating layer 20 and the free ferromagnetic material layer 18B will cause the magnetization direction of the free ferromagnetic material layer 18B to be non-vertical, and the magnetization direction of the free ferromagnetic material layer 18B to vary spatially from the center to the outer edge of the free ferromagnetic material layer 18B, thereby improving the switching speed of the novel STT-MRAM cell 11 compared to the prior art STT-MRAM cell in which the various material layers of the prior art STT-MRAM cell are substantially flat material layers. However, those skilled in the art will understand after reading this application in its entirety that in some applications, it is not necessary for all material layers of the MTJ structure 50 to have curved upper surfaces and curved bottom surfaces, such as Figure 1 In the example shown, the curvature of the material layers may differ. For example, the curvature of the curved, non-planar, or concave interface 41 may differ from the curvature of the interface defined by the bottom surface 23 of the nonmagnetic insulating layer 20 and the upper surface 21 of the pinned ferromagnetic material layer 18A.

[0027] Figure 2 An embodiment of the novel STT-MRAM cell 11 disclosed herein is depicted in which the material of the MTJ structure 50 is a concave surface relative to a substantially horizontally oriented upper surface (not shown) of a semiconductor substrate (not shown) - this configuration is similar to Figure 1 , 18B. The structure 14 is a concave structure, as opposed to the structure depicted in FIG. That is, in this example, all of the upper surfaces 13, 17, 21, 25, 29, and 33 are concave surfaces, while all of the lower surfaces 15, 19, 23, 27, 31, and 35 are concave surfaces relative to a substantially horizontally oriented upper surface (not shown) of the semiconductor substrate (not shown). For example, the novel curved, non-flat, or concave interface 41 between the nonmagnetic insulating layer 20 and the free ferromagnetic material layer 18B is defined by the junction between the concave upper surface 25 of the nonmagnetic insulating layer 20 and the concave bottom surface 27 of the free ferromagnetic material layer 18B. That is, in this example, the interface 41 is a concave interface between the nonmagnetic insulating layer 20 and the free ferromagnetic material layer 18B. In this particular example, the conductive structure 14 has a concave upper surface 13 that is joined to the concave lower surface 15 of the bottom electrode 16. Additionally, the concave upper surface 33 of the top insulating layer 24 is joined to the concave lower surface 35 of the top electrode 26.

[0028] Figure 3 is taken through the center line 50A of the MTJ structure 50 Figure 1An enlarged cross-sectional view of an MTJ structure 50 is shown. Free ferromagnetic material layer 18B has a cylindrical outer surface 18X located at a radius 45 from centerline 50A, a center 18Y along centerline 50A, and a surface 18Z located at outer surface 18X. The size of radius 45 can vary depending on the specific application. Nonmagnetic insulating layer 20 has a cylindrical outer surface 20X, a center 20A along centerline 50A, and an uppermost and outermost surface 20B along outer surface 20X. Surface 20B is bonded to surface 18Z of free ferromagnetic material layer 18B.

[0029] Figure 3 Also depicted are a horizontal reference line 48 and a line 49 extending through the center 20A and the uppermost surface 20B of the nonmagnetic insulating layer 20. Lines 48 and 49 define an interface angle 47 (θ). Typically, prior art STT-MRAM cells are constructed from substantially planar material layers with substantially planar surfaces, wherein the interface angle 47 is approximately 0 degrees, and wherein the interface PMA is uniaxial, i.e., substantially parallel to the centerline of the prior art STT-MRAM cell across the entire diameter of such prior art STT-MRAM cell. However, in the novel STT-MRAM cell 11 disclosed herein, the interface angle 47 (θ) is intentionally greater than zero, which, as will be discussed more fully below, results in a tilted interfacial magnetic orientation of the free ferromagnetic material layer 18B and enables faster switching of the novel STT-MRAM cell 11 disclosed herein compared to prior art STT-MRAM cells having substantially uniaxial PMA. In one particular embodiment, the interface angle 47 (θ) may be greater than approximately 2 degrees. In a more specific embodiment, the interface angle 47 (θ) may fall within the range of 2-4 degrees (inclusive).

[0030] The inventors have discovered that, in one exemplary embodiment, a shear strain greater than approximately 4% is required at the outer surface 18X of the free ferromagnetic material layer 18B to change the magnetization direction of the free ferromagnetic material layer 18B to a tilted magnetization direction that differs from the standard uniaxial PMA of prior art STT-MRAM cells. Therefore, in an exemplary embodiment in which the MTJ structure 50 has a diameter of approximately 50 nm and in which the interface angle 47 (θ) is approximately 2 degrees, the uppermost and outermost surface 20B of the non-magnetic insulating layer 20 should be approximately 1 nm higher than the center 20A of the non-magnetic insulating layer 20, that is, the uppermost and outermost surface 20B should be located approximately 1 nm above the horizontal reference plane 48. This height difference will also occur between the center 18Y and the surface 18Z of the free ferromagnetic material layer 18B. Of course, the magnitude of this height difference will vary depending on a variety of factors, such as the diameter of the MTJ structure 50, the magnitude of the interface angle 47 (θ), the desired amount of shear strain to be applied to the free ferromagnetic material layer 18B, and the like.

[0031] Figure 45A is a cross-sectional view of the MTJ structure 50 taken through the center 18Y of the free ferromagnetic material layer 18B. If the MTJ structure 50 is rotated in any direction by any amount about the centerline 50A, the cross-sectional view will be the same. That is, the upper surface 25 of the nonmagnetic insulating layer 20 is a gently curved, concave surface that conforms to the lower surface 27 of the free ferromagnetic material layer 18B.

[0032] The MTJ structure 50 has a central region (generally indicated by dashed region 53) in which the magnetization direction of the free ferromagnetic material layer 18B (as reflected by simplified arrow 51A) is only slightly tilted relative to the centerline 50A. At a location very close to the center 18Y of the free ferromagnetic material layer 18B, the magnetization direction 51A can be approximately parallel to the centerline 50A. At locations farther from the center 18Y of the free ferromagnetic material layer 18B, the magnetization direction of the free ferromagnetic material layer 18B (as reflected by arrow 51B) is more tilted or skewed relative to the centerline 50A. Simply put, the magnetization direction of the free ferromagnetic material layer 18B changes as one travels from the center 18Y of the free ferromagnetic material layer 18B to the outer surface 18X. In some applications, this spatial variation in the magnetization direction of the free ferromagnetic material layer 18B is substantially linear, or substantially nonlinear in nature. Finally, due to the curved, non-planar recessed interface 41 , the overall magnetization direction of the free ferromagnetic material layer 18B (as indicated by arrow 55 ) is not parallel to the centerline 50A of the MTJ structure 50 .

[0033] As is known to those skilled in the art, the current (i.e., the critical current) is the current required to cause the magnetic orientation of the free ferromagnetic material layer 18B to "flip" or change direction, i.e., change from a parallel orientation to an antiparallel orientation relative to the reference ferromagnetic material layer 18A, or vice versa. When the MTJ structure 50 is in a parallel state, the magnetic orientation of the reference ferromagnetic material layer 18A and the magnetic orientation of the free ferromagnetic material layer 18B are the same, and the angle between the two magnetic orientations is zero. When the MTJ structure 50 is in an antiparallel state, the magnetic orientation of the reference ferromagnetic material layer 18A and the magnetic orientation of the free ferromagnetic material layer 18B are opposite to each other, i.e., the angle between the two magnetic orientations is 180 degrees.

[0034] Utilizing a prior art STT-MRAM cell comprised of a substantially planar material layer having a substantially planar surface, when a critical current is applied to the MTJ structure 50, a torque is generated to cause the magnetic orientation of the free ferromagnetic material layer 18B to flip. Theoretically, for the prior art STT-MRAM cell, since the angle between the magnetic orientation direction of the reference ferromagnetic material layer 18A and the magnetic orientation direction of the free ferromagnetic material layer 18B is zero degrees (parallel state—(sin(0)=0)) or 180 degrees (antiparallel state—(sin(180)=0)), the magnetization direction (PMA) of the prior art cell is substantially parallel to the centerline of the cell across the entire diameter of the cell, and a relatively large critical current is required to flip the magnetic orientation of the free ferromagnetic material layer 18B.

[0035] In contrast, due to the presence of a curved, non-flat, or concave interface 41 in the novel STT-MRAM 11 disclosed herein, the magnetization direction of the perpendicular magnetic anisotropy (PMA) 55 is intentionally oriented at an angle greater than zero (relative to the centerline 50A). Due to this tilted orientation of the PMA 55, less current is required to generate the necessary torque to flip the magnetic orientation of the free ferromagnetic material layer 18B. As a result, the novel STT-MRAM cell 11 disclosed herein consumes less current and switches faster than prior art STT-MRAM cells composed of substantially flat material layers with substantially flat surfaces.

[0036] Figure 5 and Figure 6 Graphs are provided showing simulation data for a prior art STT-MRAM cell (composed of a substantially flat material layer with a substantially flat surface) and an embodiment of a novel STT-MRAM cell 11 disclosed herein having a curved, non-flat, recessed interface 41, respectively, wherein both cells have the same diameter of approximately 70 nm and wherein the interface angle 47 (θ) for the novel curved interface STT-MRAM cell 11 disclosed herein is approximately 2 degrees. The simulations are based on switching between parallel and antiparallel states using a 10 ns current pulse. The abscissa reflects time (in seconds) and the ordinate reflects the magnetization state of the free ferromagnetic material layer for both devices, with the magnetization states Mx, My, and Mz being in normalized units.

[0037] Figure 5 Line 60A in FIG reflects the precession switching motion of the prior art STT-MRAM, while Figure 6Line 60B in FIG. 6B reflects the precessional switching motion of the novel curved interface STT-MRAM cell 11 disclosed herein. A person skilled in the art will appreciate, after reading this application in its entirety, that due to the curved, non-flat, or concave interface 41, the novel STT-MRAM cell 11 disclosed herein experiences less precessional switching motion than the prior art STT-MRAM cell. During the precessional switching motion of the prior art STT-MRAM cell, the z component of the magnetization switches from antiparallel (-1 along the negative z-axis) to a parallel orientation (+1 along the +z-axis) in approximately 5 ns. In contrast, during the precessional switching motion of the novel curved interface STT-MRAM cell 11 disclosed herein, the z component of the magnetization switches from antiparallel (-1 along the negative z-axis) to a parallel orientation (+1 along the +z-axis) in approximately 2.5 ns, with a precise pulse width of 10 ns.

[0038] Figure 5 Line 70A in FIG reflects the switching speed of the prior art STT-MRAM, while Figure 6 Line 70B in FIG. 1 reflects the switching speed of the novel curved interface STT-MRAM cell 11 disclosed herein. Those skilled in the art will appreciate, after a complete reading of this application, that the novel STT-MRAM cell 11 disclosed herein has a faster switching speed than prior art STT-MRAM cells due to the curved, non-flat, or concave interface 41. More specifically, the novel STT-MRAM cell 11 has a switching speed of approximately 2.5 ns, while the prior art STT-MRAM cell has a switching speed of approximately 5 ns, representing an approximately 50% improvement in switching speed.

[0039] Figure 7-11 Describes the use of Figure 1 An exemplary process flow for an exemplary embodiment of the novel curved interface STT-MRAM cell 11 is shown. Figure 7 Prior to the processing operations shown, various transistor devices (not shown) and various conductive contact structures (not shown) coupled to these transistor devices are formed in and over the semiconductor substrate. For example, at this point in the process flow, a transistor (not shown) serving as a read switching element for the STT-MRAM cell 11, as well as possibly other CMOS-based transistors (not shown) for other non-memory circuits (e.g., peripheral logic circuits) will be formed for the product 10 using conventional manufacturing techniques.

[0040] Figure 7The IC product 10 is depicted after forming an insulating material layer 12 (e.g., silicon dioxide, a low-k material (k value less than 3.3)) at a level above the substrate. One or more etching processes are performed through a patterned etch mask (not shown) to form a plurality of openings 56 (e.g., via openings) in the insulating material layer 12. The patterned etch mask is then removed. Next, one or more conductive material layers 14A (which may include various liner layers and bulk conductive materials) are formed to overfill the openings 56.

[0041] Then, if Figure 8 As shown, one or more CMP and / or etch-back process operations are performed to remove a portion of conductive material layer 14A located outside openings 56 and above upper surface 12A of insulating material layer 12. This results in the formation of conductive structures 14 in each opening 56. It should be noted that in one exemplary embodiment, the CMP and / or etch-back process operations are intentionally performed in such a manner that conductive structures 14 have curved, concave, convex upper surfaces 13. This is in contrast to at least some prior art techniques, in which efforts are made to form conductive structures 14 so that their upper surfaces are substantially coplanar with upper surface 12A of insulating material layer 12. The degree of curvature of upper surface 13 may vary depending on the particular application. Conductive structures 14 may be composed of any conductive material and may have any desired configuration (when viewed from above). As described above, each conductive structure 14 will be conductively coupled to bottom electrode 16 of the novel STT-MRAM cell 11 disclosed herein.

[0042] Figure 9 The IC product 10 is depicted after various material layers have been sequentially blanket deposited over the insulating material layer 12. More specifically, a bottom electrode material layer 16, multiple material layers for the MTJ structure 50, a top insulating material layer 24, and a top electrode material layer 26 are sequentially deposited over the insulating material layer 12. As shown, in one exemplary embodiment, when initially deposited, the various deposited material layers have curved lower and upper surfaces at locations above the recessed upper surface 13 of the conductive structure 14. Thereafter, a CMP process operation is performed to planarize the upper surface 37 of the top electrode material layer 26.

[0043] Figure 10The IC product is depicted after performing several process operations. First, a patterned etch mask 57, such as a patterned photoresist / BARC layer, is formed on the IC product 10 by performing conventional manufacturing techniques. Next, one or more etching processes, such as an anisotropic etching process, are performed through the patterned etch mask 57 to etch exposed portions of layers 26, 24, 18B, 20, 18A, and 16 to form a plurality of STT-MRAM cells 11 having curved interfaces 41 between the free ferromagnetic material layer 18B and the non-magnetic insulating layer 20. When viewed from above, the STT-MRAM cells 11 can have a variety of different configurations or shapes. In the example described herein, the STT-MRAM cells 11 are patterned so that they have a substantially circular configuration when viewed from above. In the depicted example, the etching process is performed through the entire vertical thickness of the bottom electrode material layer 16, resulting in the bottom electrode 16 being a discrete element. Other process flows for forming the STT-MRAM cells 11 are of course possible. For example, in some cases, the etching process may stop somewhere within the vertical thickness of the bottom electrode material layer 16. In this case, a portion of the bottom electrode material layer may serve as a word line in a memory array.

[0044] Figure 11 The IC product is depicted after several process operations are performed. First, the patterned etch mask 57 is removed. Next, a conformal deposition process is performed to form a conformal encapsulation layer 22 on the IC product. The conformal encapsulation layer 22 can have any desired thickness and can be composed of any of a variety of different materials, such as SiN, SiC, SiCN, SiOCN, Al2O3, HfO x As initially formed, the conformal encapsulation layer 22 covers the upper surface 37 of the top electrode 26 of each STT-MRAM cell 11. A representative insulating material layer 32 is then formed over the conformal encapsulation layer 22. The insulating material layer 32 is intended to be representative in nature, as it may actually include multiple material layers, such as insulating materials and etch stop layers. The insulating material layer 32 may have any desired thickness and may be composed of any of a variety of different materials, such as SiO2, low-k materials, etc. Next, a CMP process is performed to remove the portion of the conformal encapsulation layer 22 that is above the upper surface 37 of the top electrode 26 of the STT-MRAM cell 11 and to planarize the upper surface of the insulating material layer 32.

[0045] After that, continue to refer to Figure 11, an insulating material layer 34 (e.g., silicon dioxide, a low-k material (k value less than 3.3)) is formed over the STT-MRAM cell 11. Next, exemplary separate conductive contact structures 36 (e.g., conductive vias) are formed in the insulating material layer 34 to conductively contact the top electrode 26 of each STT-MRAM cell 11. The conductive contact structures 36 can be made of any conductive material, they can have any desired configuration, and they can be fabricated using any of a variety of known manufacturing techniques (e.g., single damascene or dual damascene). As part of these process operations, contact openings are formed in the insulating material layer 34 over the top electrode 26. If the portion of the conformal encapsulation layer 22 located above the upper surface 37 of the top electrode 26 has not been previously removed, the portion of the conformal encapsulation layer 22 located above the upper surface 37 of the top electrode 26 can also be removed at this point in the process flow.

[0046] Figure 12-15 Describes the use of Figure 2 An exemplary process flow of an exemplary embodiment of the novel STT-MRAM cell 11 is shown. As previously described, in performing Figure 12 Prior to the illustrated processing operations, various transistor devices (not shown) and various conductive contact structures (not shown) coupled to the transistor devices are formed in and over the semiconductor substrate.

[0047] Figure 12 The IC product 10 is depicted after performing several process operations. First, the aforementioned insulating material layer 12 is formed at a level above the substrate. Then, one or more etching processes are performed through a patterned etch mask (not shown) to form a plurality of openings 56 (e.g., via openings) in the insulating material layer 12. Thereafter, the patterned etch mask is removed. Next, the aforementioned one or more conductive material layers 14A (which may include various liner layers and bulk conductive materials) are formed to overfill the openings 56. Next, a patterned etch mask 59 is formed over the conductive material layer 14A. As shown, the features of the etch mask 59 cover the area above the openings 56.

[0048] Figure 13 IC product 10 is depicted after one or more etching processes are performed through patterned etch mask 59 to remove exposed portions of conductive material layer 14A. This results in the formation of conductive structures 14 in each opening 56. It should be noted that upper surface 14X of conductive structure 14 is located at a level above the level of upper surface 12A of insulating material layer 12. The magnitude of the vertical difference between upper surface 14X and upper surface 12A may vary depending on the particular application.

[0049] Figure 14The IC product 10 is depicted after performing several process operations. First, the patterned etch mask 59 is removed. Then, one or more controlled CMP and / or etch-back process operations are performed to remove a portion of the upper surface 14X of the conductive structure 14. It should be noted that in one exemplary embodiment, the CMP and / or etch-back process operations are intentionally performed in such a manner that the conductive structure 14 has a curved, concave upper surface 61 relative to the substantially horizontally oriented upper surface (not shown) of the semiconductor substrate (not shown). This is in contrast to at least some prior art techniques, in which efforts are made to form the conductive structure 14 so that the upper surface of the conductive structure 14 is substantially flat. The degree of curvature of the upper surface 61 may vary depending on the particular application.

[0050] Figure 15 The IC product 10 is depicted after various material layers are sequentially blanket deposited over the insulating material layer 12. More specifically, a bottom electrode material layer 16, a plurality of material layers for the MTJ structure 50, a top insulating material layer 24, and a top electrode material layer 26 are sequentially deposited over the insulating material layer 12. As shown, in one exemplary embodiment, when initially deposited, the various deposited material layers have curved lower surfaces and curved upper surfaces at locations above the concave upper surface 61 of the conductive structure 14. Thereafter, a CMP process operation is performed to planarize the upper surface 37 of the top electrode material layer 26. Figure 15 At the processing point shown, a combination of Figure 10 and Figure 11 The operations described complete this embodiment of the novel curved interface STT-MRA primitive 11 disclosed herein.

[0051] The particular embodiments disclosed above are exemplary only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design shown herein except as described in the claims below. It is therefore apparent that the particular embodiments disclosed above may be changed or modified, and all such variations are considered within the scope and spirit of the invention. It is noted that the use of terms such as "first," "second," "third," or "fourth" in this specification and the appended claims to describe various processes or structures is intended merely to serve as a shorthand reference to such steps / structures and does not necessarily imply that such steps / structures are performed / formed in such ordered order. Of course, an ordered order of these processes may or may not be required, depending on the precise claim language. Accordingly, the protection sought herein is set forth in the claims below.

Claims

1. A memory device comprising a memory cell, wherein the memory cell comprises: a bottom electrode positioned on the conductive structure and having a curved bottom surface conductively coupled to the curved upper surface of the conductive structure; a top electrode located above the bottom electrode; as well as an MTJ (magnetic tunnel junction) structure located above the bottom electrode and below the top electrode, wherein the MTJ structure comprises: a first ferromagnetic material layer located above the bottom electrode; a non-magnetic insulating layer located above the first ferromagnetic material layer; and a second ferromagnetic material layer located on the non-magnetic insulating layer, wherein a curved non-flat interface exists between the non-magnetic insulating layer and the ferromagnetic material layer; Wherein, the memory device further includes: at least one layer of insulating material, wherein the conductive structure is located in the at least one layer of insulating material; an additional insulating material layer, wherein the bottom electrode, the MTJ structure, and the top electrode are located in the additional insulating material layer; and A conformal etch stop layer includes a first portion located between the bottom electrode, the MTJ structure, the top electrode, and the additional insulating material layer, and a second portion located between an upper surface of the at least one insulating material layer and a bottom surface of the additional insulating material layer.

2. The memory device according to claim 1, wherein The memory cell is an STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) device.

3. The memory device according to claim 2, wherein The first layer of ferromagnetic material is a pinned layer of ferromagnetic material, and wherein the second layer of ferromagnetic material is a free layer of ferromagnetic material.

4. The memory device according to claim 1 , further comprising: A semiconductor substrate having a substantially horizontally-oriented upper surface, wherein the curved non-planar interface is a substantially concave surface relative to the substantially horizontally-oriented upper surface.

5. The memory device according to claim 1 , further comprising: A semiconductor substrate having a substantially horizontally-oriented upper surface, wherein the curved non-planar interface is a substantially convex surface relative to the substantially horizontally-oriented upper surface. The memory device according to claim 1 , wherein: The nonmagnetic insulating layer includes a first curved upper surface, and wherein the second ferromagnetic material layer includes a first curved bottom surface joined to the first curved upper surface.

7. The memory device according to claim 1, wherein The second ferromagnetic material layer is located on the upper surface of the non-magnetic insulating layer and is in physical contact therewith.

8. The memory device according to claim 1, further comprising: a semiconductor substrate comprising a substantially horizontally oriented upper surface, wherein the at least one insulating material layer is located above the semiconductor substrate, Wherein, the conductive structure is located in the at least one insulating material layer, and the curved upper surface of the conductive structure is a convex upper surface relative to the substantially horizontally oriented upper surface of the semiconductor substrate.

9. The memory device according to claim 1, further comprising: a semiconductor substrate comprising a substantially horizontally oriented upper surface, wherein the at least one insulating material layer is located above the semiconductor substrate, and the at least one insulating material layer comprises a substantially flat upper surface, wherein the conductive structure is located in the at least one insulating material layer, and the curved upper surface of the conductive structure is a concave upper surface relative to the substantially horizontally oriented upper surface of the semiconductor substrate, wherein the uppermost surface of the concave upper surface is located at a level above the level of the upper surface of the at least one insulating material layer.

10. The memory device according to claim 1, wherein The bottom electrode includes a curved upper surface joined to the curved bottom surface of the first ferromagnetic material layer, the first ferromagnetic material layer includes a curved upper surface joined to the curved bottom surface of the non-magnetic insulating layer, and the non-magnetic insulating layer includes a curved upper surface joined to the curved bottom surface of the second ferromagnetic material.

11. The memory device according to claim 1 , further comprising: A semiconductor substrate having a substantially horizontally oriented upper surface, wherein, relative to the substantially horizontally oriented upper surface, the bottom electrode includes a convex upper surface that engages a convex bottom surface of the first ferromagnetic material layer, the first ferromagnetic material layer includes a convex upper surface that engages a convex bottom surface of the non-magnetic insulating layer, and the non-magnetic insulating layer includes a convex upper surface that engages a convex bottom surface of the second ferromagnetic material.

12. A memory device comprising a memory cell, the memory cell comprising: a bottom electrode positioned on the conductive structure and having a curved bottom surface conductively coupled to the curved upper surface of the conductive structure; a top electrode located above the bottom electrode; as well as an MTJ (magnetic tunnel junction) structure located above the bottom electrode and below the top electrode, wherein the MTJ structure comprises: a first ferromagnetic material layer located above the bottom electrode; a non-magnetic insulating layer located above the first ferromagnetic material layer, wherein the non-magnetic insulating layer includes a first curved upper surface; and a second ferromagnetic material layer positioned on and in physical contact with the nonmagnetic insulating layer, wherein the second ferromagnetic material layer includes a first curved bottom surface engaged with the first curved upper surface, Wherein, the memory device further includes: at least one layer of insulating material, wherein the conductive structure is located in the at least one layer of insulating material; an additional insulating material layer, wherein the bottom electrode, the MTJ structure, and the top electrode are located in the additional insulating material layer; and A conformal etch stop layer includes a first portion located between the bottom electrode, the MTJ structure, the top electrode, and the additional insulating material layer, and a second portion located between an upper surface of the at least one insulating material layer and a bottom surface of the additional insulating material layer.

13. The memory device according to claim 12, wherein: The memory cell is an STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) device, and wherein the first ferromagnetic material layer is a pinned ferromagnetic material layer, and wherein the second ferromagnetic material layer is a free ferromagnetic material layer.

14. The memory device according to claim 12, wherein: The junction between the nonmagnetic insulating layer and the second ferromagnetic material layer defines a curved, non-planar interface.

15. The memory device according to claim 12, further comprising: a semiconductor substrate comprising a substantially horizontally oriented upper surface, wherein the at least one insulating material layer is located above the semiconductor substrate, Wherein, the conductive structure is located in the at least one insulating material layer, and the curved upper surface of the conductive structure is a convex upper surface relative to the substantially horizontally oriented upper surface of the semiconductor substrate.

16. The memory device according to claim 12, further comprising: a semiconductor substrate comprising a substantially horizontally oriented upper surface, wherein the at least one insulating material layer is located above the semiconductor substrate, and the at least one insulating material layer comprises a substantially flat upper surface; wherein the conductive structure is located in the at least one insulating material layer, and the curved upper surface of the conductive structure is a concave upper surface relative to the substantially horizontally oriented upper surface of the semiconductor substrate, wherein the uppermost surface of the concave upper surface is located at a level above the level of the upper surface of the at least one insulating material layer.

17. A memory device comprising a memory cell, the memory cell comprising: a bottom electrode on the conductive structure and having a curved bottom surface conductively coupled to the curved upper surface of the conductive structure and a first curved upper surface; a top electrode located above the bottom electrode; as well as an MTJ (magnetic tunnel junction) structure located above the bottom electrode and below the top electrode, wherein the MTJ structure comprises: a first ferromagnetic material layer comprising a second curved upper surface and a first curved bottom surface, wherein the first curved bottom surface is in contact with and engaged with the first curved upper surface; a non-magnetic insulating layer comprising a third curved upper surface and a second curved bottom surface, wherein the second curved bottom surface contacts and engages with the second curved upper surface; and a second ferromagnetic material layer comprising a fourth curved upper surface and a third curved bottom surface, wherein the third curved bottom surface is in contact with and engaged with the third curved upper surface, Wherein, the memory device further includes: at least one layer of insulating material, wherein the conductive structure is located in the at least one layer of insulating material; an additional insulating material layer, wherein the bottom electrode, the MTJ structure, and the top electrode are located in the additional insulating material layer; and A conformal etch stop layer includes a first portion located between the bottom electrode, the MTJ structure, the top electrode, and the additional insulating material layer, and a second portion located between an upper surface of the at least one insulating material layer and a bottom surface of the additional insulating material layer.

18. The memory device according to claim 17, further comprising: A semiconductor substrate includes a substantially horizontally oriented upper surface, wherein the first, second, third, and fourth curved upper surfaces are convex surfaces relative to the substantially horizontally oriented upper surface of the semiconductor substrate.

19. The memory device according to claim 17, further comprising: a semiconductor substrate comprising a substantially horizontally oriented upper surface, wherein the at least one insulating material layer is located above the semiconductor substrate, Wherein, the conductive structure is located in the at least one insulating material layer, and the curved upper surface of the conductive structure is a convex upper surface relative to the substantially horizontally oriented upper surface of the semiconductor substrate.

20. The memory device of claim 17, further comprising: a semiconductor substrate comprising a substantially horizontally oriented upper surface, wherein the at least one insulating material layer is located above the semiconductor substrate, and the at least one insulating material layer comprises a substantially flat upper surface; wherein the conductive structure is located in the at least one insulating material layer, and the curved upper surface of the conductive structure is a concave upper surface relative to the substantially horizontally oriented upper surface of the semiconductor substrate, wherein the uppermost surface of the concave upper surface is located at a level above the level of the upper surface of the at least one insulating material layer.

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