Circuit inspection method, device, electronic device, storage medium

Abstract

A method, apparatus, electronic device, and storage medium for circuit inspection. The method for circuit inspection includes: determining a plurality of circuit nodes; determining a plurality of input scenarios corresponding to the circuit; determining the component states respectively corresponding to a plurality of circuit components under each selected input scenario among the plurality of input scenarios; determining an equivalent model corresponding to the circuit under the selected input scenario according to the component states respectively corresponding to the plurality of circuit components and the plurality of circuit nodes under the selected input scenario; and performing circuit inspection on the circuit based on the plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios. The method for circuit inspection can avoid errors caused by manual inspection, reduce the workload of circuit inspection, improve the reliability and accuracy of circuit design, improve the R & D efficiency, and help circuit designers efficiently and quickly identify circuit problems existing in the circuit during the circuit design process.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for inspecting a circuit, a device for inspecting a circuit, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Complex circuits, such as large-scale digital integrated circuits, generally include multiple circuit modules. For example, the multiple circuit modules may include various unit circuits as a standard cell library, and the unit circuits include combinational logic, sequential logic, and special type units, etc. During the circuit design process, the designer must ensure the logical correctness of each circuit module (such as a unit circuit). Generally, during the design process, the designer will use a simulation tool to confirm whether each circuit module meets the design goal. If the number of circuit modules is relatively large, and considering factors such as design optimization and version iteration, the circuit designer needs to modify and inspect multiple circuit modules multiple times during the design process. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for inspecting a circuit, where the circuit includes multiple circuit elements and multiple input terminals, and the inspection method includes: determining multiple circuit nodes, where each circuit node represents a point connected to at least one circuit element; determining multiple input scenarios corresponding to the circuit, where each input scenario includes signal states respectively corresponding to the multiple input terminals; determining element states respectively corresponding to the multiple circuit elements in each selected input scenario among the multiple input scenarios; determining an equivalent model corresponding to the circuit in the selected input scenario according to the element states respectively corresponding to the multiple circuit elements and the multiple circuit nodes in the selected input scenario; and performing a circuit inspection on the circuit based on the multiple equivalent models respectively corresponding to the circuit in the multiple input scenarios.

[0004] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, each equivalent model includes a plurality of equivalent nodes and a plurality of equivalent edges. The circuit further includes a ground terminal and at least one power supply terminal. The element state of each circuit element includes a conducting state or a non-conducting state. Determining the equivalent model corresponding to the circuit in the selected input scenario according to the element states respectively corresponding to the plurality of circuit elements and the plurality of circuit nodes in the selected input scenario includes: using the plurality of circuit nodes, the ground terminal, and the at least one power supply terminal as the plurality of equivalent nodes of the equivalent model corresponding to the circuit in the selected input scenario; using the plurality of circuit elements as the plurality of equivalent edges in the equivalent model corresponding to the circuit in the selected input scenario, wherein, in the equivalent model corresponding to the circuit in the selected input scenario, each equivalent edge is used to connect two equivalent nodes; determining the equivalent path values respectively corresponding to the plurality of equivalent edges based on the element states respectively corresponding to the plurality of circuit elements, wherein, in response to the element state of the circuit element being the conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a first value, and in response to the element state of the circuit element being the non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a second value, and the first value and the second value are different.

[0005] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, performing a circuit inspection on the circuit based on the plurality of equivalent models respectively corresponding to the circuit in the plurality of input scenarios includes: determining at least one inspection group based on the ground terminal and the at least one power supply terminal, wherein each inspection group includes the ground terminal and one power supply terminal among the at least one power supply terminal; for each selected inspection group, traversing the plurality of equivalent models to determine whether there is a short circuit path between the power supply terminal and the ground terminal in the selected inspection group in each selected equivalent model, and in response to there being a short circuit path between the power supply terminal and the ground terminal in the selected inspection group, determining that there is a short circuit problem in the circuit in the input scenario corresponding to the selected equivalent model.

[0006] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, determining whether there is a short circuit path between the power supply terminal and the ground terminal in the selected inspection group in each selected equivalent model includes: determining whether there is a shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group; in response to the existence of a shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group, calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value respectively corresponding to at least one equivalent edge included in the shortest circuit path; judging whether the shortest circuit path is a short circuit path according to the equivalent path sum; in response to the non-existence of a shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group, determining that there is no short circuit path between the power supply terminal and the ground terminal in the selected inspection group.

[0007] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the equivalent path sum is the sum of the at least one equivalent path value or the weighted sum of the at least one equivalent path value.

[0008] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the first value is 0, and judging whether the shortest circuit path is a short circuit path according to the equivalent path sum includes: in response to the equivalent path sum being equal to the first value, determining that the shortest circuit path is a short circuit path; in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a short circuit path.

[0009] For example, the circuit inspection method provided by at least one embodiment of the present disclosure further includes: in response to the shortest circuit path being a short circuit path, recording the shortest circuit path, the input scenario corresponding to the selected equivalent model, and the power supply terminal and the ground terminal included in the selected inspection group.

[0010] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the circuit further includes at least one power supply terminal, and performing circuit inspection on the circuit based on the multiple equivalent models respectively corresponding to the circuit under the multiple input scenarios includes: for each selected circuit node among the multiple circuit nodes: based on the multiple equivalent models, determining whether there is a conduction path between the at least one power supply terminal and the selected circuit node under the multiple input scenarios; in response to the existence of a conduction path between any power supply terminal and the selected circuit node under any one input scenario, determining that there is no high impedance state between the selected circuit node and the at least one power supply terminal; in response to the non-existence of a conduction path between the at least one power supply terminal and the selected circuit node under the multiple input scenarios, determining that there is a high impedance state between the selected circuit node and the at least one power supply terminal.

[0011] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, based on the plurality of equivalent models, determining whether there is a conduction path between the at least one power supply terminal and the selected circuit node under the plurality of input scenarios includes: for each selected power supply terminal among the at least one power supply terminal, traversing the plurality of equivalent models and performing a conduction path detection on each selected equivalent model; wherein, the conduction path detection includes: in the selected equivalent model, in response to the existence of a shortest circuit path between the selected power supply terminal and the selected circuit node, determining whether the shortest circuit path is a conduction path, in response to the shortest circuit path being a conduction path, determining that there is a conduction path between the selected power supply terminal and the selected circuit node under the input scenario corresponding to the selected equivalent model, in response to the shortest circuit path not being a conduction path or in response to there being no shortest circuit path between the selected power supply terminal and the selected circuit node, determining that there is no conduction path between the selected power supply terminal and the selected circuit node under the input scenario corresponding to the selected equivalent model, and continuing to perform the conduction path detection on the next equivalent model.

[0012] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, when the first value is 0, determining whether the shortest circuit path is a conduction path includes: calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value respectively corresponding to at least one equivalent edge included in the shortest circuit path; in response to the equivalent path sum being equal to the first value, determining that the shortest circuit path is a conduction path; in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a conduction path.

[0013] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the circuit further includes a ground terminal. Performing a circuit inspection on the circuit based on the plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios includes: for each selected circuit node among the plurality of circuit nodes: based on the plurality of equivalent models, determining whether there is a conduction path between the ground terminal and the selected circuit node under the plurality of input scenarios; in response to there being a conduction path between the ground terminal and the selected circuit node in any one of the input scenarios, determining that there is no high impedance state between the selected circuit node and the ground terminal; in response to there being no conduction path between the ground terminal and the selected circuit node in the plurality of input scenarios, determining that there is a high impedance state between the selected circuit node and the ground terminal.

[0014] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, each input terminal has a first signal state and a second signal state, and the first signal state is different from the second signal state. Determining a plurality of input scenarios corresponding to the circuit includes: combining the signal states of the plurality of input terminals to determine the plurality of input scenarios, where the number of the plurality of input terminals is N, and the number of the plurality of input scenarios is 2 N , and N is a positive integer.

[0015] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the plurality of circuit elements include a plurality of first circuit elements, and the plurality of first circuit elements are connected to the plurality of input terminals. Determining the element states respectively corresponding to the plurality of circuit elements in each selected input scenario among the plurality of input scenarios includes: determining the signal states respectively corresponding to the plurality of input terminals in the selected input scenario; and determining the element states corresponding to the plurality of first circuit elements in the selected input scenario according to the signal states respectively corresponding to the plurality of input terminals.

[0016] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the circuit is a digital circuit. Determining the plurality of circuit nodes includes: obtaining a netlist corresponding to the circuit; and determining the plurality of circuit nodes according to the netlist.

[0017] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, the circuit is a unit circuit of a standard cell library.

[0018] For example, in the circuit inspection method provided by at least one embodiment of the present disclosure, each circuit element is a transistor or a resistor.

[0019] At least one embodiment of the present disclosure provides a circuit inspection device. The circuit includes a plurality of circuit elements and a plurality of input terminals. The inspection device includes: a node determination unit configured to determine a plurality of circuit nodes, where each circuit node represents a point connected to at least one circuit element; an input scenario determination unit configured to determine a plurality of input scenarios corresponding to the circuit, where the plurality of input scenarios include the signal states respectively corresponding to the plurality of input terminals; an element state determination unit configured to determine the element states respectively corresponding to the plurality of circuit elements in each selected input scenario among the plurality of input scenarios; an equivalent model determination unit configured to determine an equivalent model corresponding to the circuit in the selected input scenario according to the element states respectively corresponding to the plurality of circuit elements and the plurality of circuit nodes in the selected input scenario; and an inspection unit configured to perform circuit inspection on the circuit based on the plurality of equivalent models respectively corresponding to the circuit in the plurality of input scenarios.

[0020] At least one embodiment of the present disclosure provides an electronic device, including: a memory that stores computer-executable instructions non-transiently; and a processor configured to run the computer-executable instructions, wherein when the computer-executable instructions are run by the processor, a method for inspecting a circuit according to any embodiment of the present disclosure is implemented.

[0021] At least one embodiment of the present disclosure provides a non-transient computer-readable storage medium, wherein the non-transient computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, a method for inspecting a circuit according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0023] Figure 1A Schematic circuit diagram provided for an embodiment of the present disclosure;

[0024] Figure 1B Schematic circuit diagram provided for another embodiment of the present disclosure;

[0025] Figure 2 Schematic flowchart of a method for inspecting a circuit provided for at least one embodiment of the present disclosure;

[0026] Figure 3A Schematic diagram of an equivalent model provided for an embodiment of the present disclosure;

[0027] Figure 3B Schematic diagram of an equivalent model provided for another embodiment of the present disclosure;

[0028] Figure 4 Flowchart of a method for inspecting a circuit provided for at least one embodiment of the present disclosure;

[0029] Figure 5 Schematic block diagram of a device for inspecting a circuit provided for at least one embodiment of the present disclosure;

[0030] Figure 6 Schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0031] Figure 7 Schematic diagram of a non-transient computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "including" or "comprising" and the like mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0034] To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of some known functions and known components are omitted in the present disclosure.

[0035] During the circuit design process, especially for complex circuits, the circuit may have errors due to subjective or objective factors. For example, a circuit includes multiple circuit elements, the multiple circuit elements have different types, and the connection relationships of the multiple circuit elements are complex, which may lead to problems such as short - circuit problems and high - impedance state problems in the circuit due to various factors.

[0036] For example, in the embodiments of the present disclosure, the short - circuit problem means that under the control of the input control signal, there is a direct - conduction path from the power supply terminal to the ground terminal in the circuit. This direct - conduction path from the power supply terminal to the ground terminal is the short - circuit path. Here, direct conduction means that the current flows directly from the power supply terminal to the ground terminal without passing through any circuit elements or only passing through circuit elements in the conducting state (such as conducting - state transistors, diodes, etc.).

[0037] Figure 1A Schematic diagram of the circuit provided for an embodiment of the present disclosure.

[0038] In Figure 1AAmong them, VDD represents the power supply terminal, VSS represents the ground terminal, T1 to T5 represent 5 transistors, where T1 to T4 represent 4 P-type transistors, and T5 represents an N-type transistor. net_x0, net_x1, and net_x2 represent 3 circuit nodes, and A, B, and C represent three input terminals, which are used to input control signals to the gates of each transistor to control the on and off of the transistors. For example, each input terminal includes two signal states, respectively represented as 0 and 1. When the control signal is at a low level, the N-type transistor is off and the P-type transistor is on. At this time, the signal state of the input terminal is represented as 0. When the control signal is at a high level, the N-type transistor is on and the P-type transistor is off. At this time, the signal state of the input terminal is represented as 1.

[0039] It should be noted that 0 and 1 in this disclosure represent two signal states. For example, 0 represents a low level state and 1 represents a high level state. According to the actual situation of different circuits, the voltage ranges corresponding to the low level state and the high level state can be different, as long as the low level state can turn off the N-type transistor and turn on the P-type transistor, and the high level state can turn on the N-type transistor and turn off the P-type transistor.

[0040] For example, the input terminal B inputs the control signal B to the gate of the transistor T1, the input terminal A inputs the control signal A to the gates of the transistors T2 and T4, and the input terminal C inputs the control signal C to the gate of the transistor T3. The control signal after performing the NOT operation on the control signal A of the input terminal A is input to the gate of the transistor T5. represents the result of the NOT operation of A, that is, when A = 1, when A = 0, It should be noted that in Figure 1A the circuit shown, the transistor T5 is also controlled by the control signal output from the input terminal A.

[0041] For example, when A = 0, B = 0, and C = 1, the transistors T2, T4, and T5 are on, and the transistors T1 and T3 are off. Thus, a short circuit path is generated in the circuit: power supply terminal VDD -> transistor T2 -> transistor T4 -> transistor T5 -> ground terminal VSS. This short circuit path directly connects the power supply terminal VDD and the ground terminal VSS, and there is a short circuit problem in the circuit.

[0042] For example, in the embodiment of this disclosure, the high impedance state problem refers to: a certain circuit node (net) in the circuit is in a high impedance state, that is, a floating state.

[0043] Figure 1B It is a schematic diagram of the circuit provided by another embodiment of this disclosure.

[0044] In Figure 1BAmong them, VDD1 and VDD2 represent two power supply terminals with different potentials, VSS represents the ground terminal, T1, T2, T3, T4, T5, A, B, C, has the same meaning as Figure 1A and will not be elaborated on for repeated parts. In addition, Figure 1B the circuit shown in

[0045] also includes input terminal D, input terminal E, and two transistors T6 and T7. Transistors T6 and T7 are both N-type transistors. Input terminal D inputs a control signal D to the gate of transistor T6, and input terminal E inputs a control signal E to the gate of transistor T7. The definitions of input terminal D and input terminal E are the same as those of input terminal A, input terminal B, and input terminal C, which will not be elaborated on here. Figure 1B As can be seen from

[0046] In the design process of complex circuits, such as large-scale integrated circuits, if the above-mentioned short-circuit problem and high-impedance state problem are not detected in a timely manner during the design stage of the unit circuit, it will be even more difficult to detect them in the subsequent layout design stage, thus affecting the R & D progress of the circuit and potentially causing hidden dangers in the circuit design.

[0047] For example, for a circuit with a complex structure, circuit designers usually check the correctness of the circuit through a simulation tool, such as inputting an excitation signal to the input terminal of the circuit and making a judgment based on the results of the simulation tool.

[0048] However, when circuit designers view the waveform diagram of the simulation results through a simulation tool for circuit inspection, it is difficult to detect subtle waveform abnormalities, resulting in the difficulty of detecting hidden circuit problems (such as short-circuit problems or high-impedance state problems) in the circuit. In addition, considering factors such as inspection cost and inspection workload, and circuit designers cannot check all states of the circuit. For example, circuit designers focus on verifying the normal working state of the circuit and may not conduct a complete inspection of the abnormal working state of the circuit. Therefore, if there are circuit problems in the abnormal working state of the circuit, it is difficult to detect them, resulting in hidden dangers in the designed circuit.

[0049] At least one embodiment of the present disclosure provides a circuit inspection method, a circuit inspection device, an electronic device, and a non-transitory computer-readable storage medium. The circuit inspection method includes: determining a plurality of circuit nodes; determining a plurality of input scenarios corresponding to the circuit; determining the component states corresponding to the plurality of circuit components respectively under each selected input scenario among the plurality of input scenarios; determining an equivalent model corresponding to the circuit under the selected input scenario according to the component states corresponding to the plurality of circuit components respectively and the plurality of circuit nodes under the selected input scenario; and performing circuit inspection on the circuit based on the plurality of equivalent models corresponding to the circuit under the plurality of input scenarios.

[0050] The circuit inspection method provided by at least one embodiment of the present disclosure converts the circuit into different equivalent models according to the circuit nodes and the component states of the circuit components under different input scenarios, and performs circuit inspection on the equivalent models under multiple input scenarios, avoiding errors caused by manual inspection, reducing the workload of circuit inspection, improving the reliability and accuracy of circuit design, enhancing the R & D efficiency, and helping circuit designers efficiently and quickly identify circuit problems existing in the circuit during the circuit design process, such as short circuit problems or high impedance state problems.

[0051] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0052] Figure 2 It is a schematic flowchart of a circuit inspection method provided by at least one embodiment of the present disclosure.

[0053] For example, the circuit may include a digital circuit or an analog circuit. For example, the circuit in the present disclosure may refer to a partial design or a partial module in a large circuit design, that is, the circuit in the present disclosure may be either an entire circuit itself or a partial circuit in a complete circuit, and the present disclosure does not limit this.

[0054] For example, the circuit may be a unit circuit in a standard cell library of a digital circuit.

[0055] For example, the circuit includes a plurality of circuit components and a plurality of input terminals. For example, the circuit components include transistors, resistors, etc., and the input terminals include the gate signal input terminals of transistors, etc. For Figure 1A example, the plurality of circuit components include transistor T1 to transistor T5, and the plurality of input terminals include input terminal A, input terminal B, and input terminal C.

[0056] For example, as Figure 2 shown, the circuit inspection method provided by the embodiment of the present disclosure includes steps S10 to S50.

[0057] In step S10, a plurality of circuit nodes are determined.

[0058] For example, each circuit node represents a point connected to at least one circuit element. That is to say, multiple circuit nodes include points connected to at least two circuit elements and points connected to one circuit element.

[0059] For example, taking Figure 1A as an example, Figure 1A the multiple circuit nodes in the circuit shown include circuit node net_x0, circuit node net_x1, and circuit node net_x2. For example, circuit node net_x0 is the point where transistor T1 and transistor T3 are connected, and circuit node net_x2 is the point where transistor T3, transistor T4, and transistor T5 are connected. For example, taking Figure 1B as an example, Figure 1B the multiple circuit nodes in the circuit shown include circuit node net_y0, circuit node net_y1, circuit node net_y2, circuit node net_y3, circuit node net_y4, and circuit node net_y5. Circuit node net_y2 is the point connected to transistor T3, and circuit node net_4 is the point connected to transistor T4. That is, circuit node net_y2 is only connected to one circuit element, and circuit node net_y4 is also only connected to one circuit element.

[0060] For example, for the point where a circuit element is connected to the ground terminal or the power supply terminal, its voltage state is fixed, so it can be not regarded as a circuit node for circuit inspection. That is to say, in the embodiments of the present disclosure, the points directly connected to the power supply terminal and the ground terminal are not regarded as circuit nodes.

[0061] For example, when the circuit is an analog circuit, step S10 may include: analyzing the electrical characteristics of multiple circuit elements in the circuit to obtain multiple circuit nodes.

[0062] For example, when the circuit is a digital circuit, step S10 may include: obtaining the netlist corresponding to the circuit; determining multiple circuit nodes according to the netlist.

[0063] For example, the netlist refers to the gate-level netlist corresponding to the digital circuit. The gate-level netlist describes the connection relationship of circuit elements in the circuit in text language and records the connection relationships between logic gates (AND, OR, NOT), flip-flops, etc. Therefore, the information of circuit nodes is recorded in the netlist, and multiple circuit nodes can be obtained by reading the netlist corresponding to the circuit.

[0064] In step S20, determine multiple input scenarios corresponding to the circuit.

[0065] For example, each input scenario includes the signal states corresponding to multiple input terminals respectively.

[0066] For example, each input terminal has a first signal state and a second signal state, and the first signal state is different from the second signal state. For example, the first signal state indicates that the control signal input to the input terminal belongs to a first voltage range. For example, the first signal state is the low-level state as described above, and the second signal state indicates that the control signal input to the input terminal belongs to a second voltage range. For example, the second signal state is the high-level state as described above. The first voltage range and the second voltage range are set according to the actual situation.

[0067] For example, step S20 may include: combining the signal states of a plurality of input terminals to determine a plurality of input scenarios, where the number of the plurality of input terminals is N, and the number of the plurality of input scenarios is 2 N , and N is a positive integer.

[0068] For example, for any two input scenarios among the plurality of input scenarios, the signal states of the plurality of input terminals in one of the two input scenarios are not exactly the same as the signal states of the plurality of input terminals in the other of the two input scenarios.

[0069] For example, taking Figure 1A the circuit shown as an example, the circuit includes at least 3 input terminals, namely input terminal A, input terminal B, and input terminal C. The 3 input terminals are used to input control signal A, control signal B, control signal C, and control signal For example, when the input terminal is in the first signal state, it is represented by 0. For example, at this time, the first signal state is the low-level state; when the input terminal is in the second signal state, it is represented by 1. For example, at this time, the second signal state is the high-level state. For this circuit, by combining the signal states of the 3 input terminals, a total of 2 3 = 8 input scenarios can be determined. Among any two of the 8 input scenarios, the signal states of the 3 input terminals in one of the two input scenarios are not exactly the same as the signal states of the 3 input terminals in the other of the two input scenarios. For example, the 8 input scenarios include:

[0070] Input scenario 1: A = 0, B = 0, C = 0; Input scenario 2: A = 1, B = 0, C = 0; Input scenario 3: A = 0, B = 1, C = 0; Input scenario 4: A = 0, B = 0, C = 1; Input scenario 5: A = 1, B = 1, C = 0; Input scenario 6: A = 0, B = 1, C = 1; Input scenario 7: A = 1, B = 0, C = 1; Input scenario 8: A = 1, B = 1, C = 1.

[0071] Here, A = 0 indicates that input terminal A has the first signal state, A = 1 indicates that input terminal A has the second signal state, and the same applies to B and C.

[0072] For example, when the number of multiple input scenarios is 2 N During circuit inspection, all possible input scenarios can be traversed and inspected to determine possible circuit errors under all input scenarios, greatly reducing the circuit inspection cost and time overhead, improving the accuracy and reliability of circuit inspection, and helping circuit designers discover vulnerabilities in the circuit that are not easily detected in a timely and rapid manner.

[0073] It should be noted that the multiple input scenarios can be part or all of all possible input scenarios corresponding to the circuit, and can be selected according to needs in practice. The present disclosure does not limit this.

[0074] In step S30, determine the component states respectively corresponding to multiple circuit components under each selected input scenario among the multiple input scenarios.

[0075] For example, the multiple circuit components include multiple first circuit components, and the multiple first circuit components are connected to multiple input terminals. For example, the first circuit component can be a transistor.

[0076] For example, step S30 may include: determining the signal states respectively corresponding to the multiple input terminals under the selected input scenario; and determining the component states corresponding to the multiple first circuit components under the selected input scenario according to the signal states respectively corresponding to the multiple input terminals.

[0077] For example, when the first circuit component is a transistor, if the input terminal is in the first signal state, for example, a low level state, the N-type transistor with the gate connected to the input terminal is in the off state, that is, the non-conducting state, and the P-type transistor with the gate connected to the input terminal is in the conducting state; if the input terminal is in the second signal state, for example, a high level state, the N-type transistor with the gate connected to the input terminal is in the conducting state, and the P-type transistor with the gate connected to the input terminal is in the off state, that is, the non-conducting state. Thus, the component state of the first circuit component can be determined according to the signal state corresponding to the input terminal connected to the first circuit component. For example, the component state includes the conducting state and the non-conducting state.

[0078] For example, the multiple circuit components may further include at least one second circuit component. For example, the second circuit component can be a resistor.

[0079] For example, when the circuit further includes a second circuit component, step S30 may further include: determining the component state corresponding to at least one second circuit component. For example, when the second circuit component is a resistor, the component state of the second circuit component can be directly determined to be the conducting state. The component state of the second circuit component is independent of the signal state of the input terminal.

[0080] For example, the circuit components may also include devices such as capacitors and diodes, and the present disclosure does not make specific limitations thereon. Those skilled in the art can determine the component states of each circuit component according to the specific conduction states of these circuit components in the circuit. For example, if the circuit component is conducting, its component state is the conducting state, and vice versa, it is the non-conducting state.

[0081] In step S40, according to the component states corresponding to multiple circuit components and multiple circuit nodes in the selected input scenario, determine the equivalent model corresponding to the circuit in the selected input scenario.

[0082] For example, each equivalent model includes multiple equivalent nodes and multiple equivalent edges. For example, referring to the principles of graph theory, the circuit nodes can be equivalent to equivalent nodes, the circuit components can be equivalent to equivalent edges, and the equivalent path value of the equivalent edge, that is, the weight of the equivalent edge, can be determined according to the component state of the circuit component, so as to convert the circuit into an equivalent model composed of equivalent nodes and equivalent edges.

[0083] For example, the circuit further includes a ground terminal and at least one power supply terminal, and different power supply terminals may have different potentials. For example, as Figure 1B shown, the circuit includes 2 power supply terminals, namely power supply terminal VDD1 and power supply terminal VDD2. The potential of power supply terminal VDD1 can be 5V (volts), and the potential of power supply terminal VDD2 can be 10V. Of course, according to needs, the potential of the power supply terminal can be a positive potential or a negative potential, and the present disclosure does not limit this.

[0084] For example, the component state of each circuit component includes a conducting state or a non-conducting state. Regarding the conducting state and the non-conducting state, reference can be made to the relevant description in step S30, which will not be elaborated here.

[0085] For example, step S40 may include: regarding multiple circuit nodes, the ground terminal, and at least one power supply terminal as multiple equivalent nodes of the equivalent model corresponding to the circuit in the selected input scenario; regarding multiple circuit components as multiple equivalent edges in the equivalent model corresponding to the circuit in the selected input scenario, where, in the equivalent model corresponding to the circuit in the selected input scenario, each equivalent edge is used to connect two equivalent nodes; determining the equivalent path values corresponding to multiple equivalent edges based on the component states corresponding to multiple circuit components respectively, where, in response to the component state of the circuit component being the conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit component is the first value, and in response to the component state of the circuit component being the non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit component is the second value, and the first value and the second value are different.

[0086] For example, the first value can be 0, and the second value can be 1 or other non-0 values, such as 9999, etc. The first value and the second value are different to distinguish the conducting state and the non-conducting state.

[0087] Specifically, multiple circuit nodes, a ground terminal, and a power supply terminal are all equivalent to equivalent nodes, and circuit components are all equivalent to equivalent edges. The equivalent edges are used to connect two equivalent nodes. According to different component states corresponding to the circuit components, the equivalent edges correspond to different equivalent path values. Each equivalent node is connected to at least one equivalent edge. For example, in a circuit, circuit component a is electrically connected to the ground terminal and circuit node a, and circuit component a is used to connect the ground terminal and circuit node a. Then, in the equivalent model, the ground terminal and circuit node a are equivalent to two equivalent nodes, and the two equivalent nodes are connected by equivalent edge a equivalent to circuit component a. If in input scenario a, according to the signal states corresponding to multiple input terminals, circuit component a is in a conducting state, then in the equivalent model corresponding to input scenario a, the equivalent path value corresponding to equivalent edge a is the first value, such as 0. If in input scenario b, according to the signal states corresponding to multiple input terminals, circuit component a is in a non-conducting state, then in the equivalent model corresponding to input scenario b, the equivalent path value corresponding to equivalent edge a is the second value, such as 1.

[0088] For example, based on the positional and connection relationships among multiple circuit components, a power supply terminal, a ground terminal, and multiple circuit nodes in the circuit, determine the positional and connection relationships of the equivalent nodes and equivalent edges in the equivalent model.

[0089] Figure 3A Schematic diagram of the equivalent model provided by an embodiment of the present disclosure. For example, Figure 3A is Figure 1A the equivalent model corresponding to the circuit shown in the selected input scenario. For example, the selected input scenario can be input scenario 6.

[0090] As Figure 3A shown, Figure 1A the power supply terminal VDD, the ground terminal VSS, circuit nodes net_x0, net_x1, and net_x2 in Figure 3A are all equivalent to equivalent nodes, as shown by the 5 circles marked with VDD, VSS, net_x0, net_x1, and net_x2 in

[0091] As Figure 3A shown, transistors T1 to T5 are all equivalent to equivalent edges, as shown by equivalent edges 1 to equivalent edges 5 connecting the respective equivalent nodes in Figure 3A . For example, in Figure 3AIn the equivalent model shown, transistor T1 is equivalent to equivalent edge 1 connecting equivalent node VDD and equivalent node net_x0, transistor T3 is equivalent to equivalent edge 2 connecting equivalent node net_x0 and equivalent node net_x2, transistor T5 is equivalent to equivalent edge 3 connecting equivalent node net_x2 and the ground terminal, transistor T4 is equivalent to equivalent edge 4 connecting equivalent node net_x1 and equivalent node net_x2, and transistor T2 is equivalent to equivalent edge 5 connecting equivalent node VDD and equivalent node net_x1.

[0092] For example, in the selected input scenario, input terminal A has a first signal state, such as a low level state, and input terminals B and C have a second signal state, such as a high level state. That is, transistors T2, T4, and T5 are in the conducting state in the selected input scenario, and transistors T1 and T3 are in the non-conducting state in the selected input scenario. Therefore, in the equivalent model corresponding to the selected input scenario, the equivalent path values corresponding to the equivalent edges corresponding to transistors T2, T4, and T5 are the first value, such as 0, and the equivalent path values corresponding to the equivalent edges corresponding to transistors T1 and T3 are the second value, such as 9999. As Figure 3A shown, the number (0 or 9999) beside each equivalent edge represents the equivalent path value corresponding to that equivalent edge.

[0093] For example, Figure 3B is a schematic diagram of the equivalent model provided by an embodiment of the present disclosure. For example, Figure 3B is Figure 1B the equivalent model corresponding to the circuit shown in the selected input scenario.

[0094] As Figure 3B shown, Figure 1B the power supply terminals VDD1, VDD2, the ground terminal VSS, and the circuit nodes net_y0, net_y1, net_y2, net_y3, net_y4, and net_y5 in Figure 3B are all equivalent to equivalent nodes, as shown by the 9 circles marked with VDD1, VDD2, VSS, net_y0, net_y1, net_y2, net_y3, net_y4, and net_y5 in

[0095] As Figure 3B shown, Figure 3B transistors T1 to T7 are all equivalent to equivalent edges, as shown by the black straight lines connecting the respective equivalent nodes in Figure 3B For example, in the equivalent model shown in Figure 3B transistor T6 is equivalent to the equivalent edge connecting equivalent node net_y4 and equivalent node net_y5. The corresponding relationships between other transistors and equivalent edges are similar and will not be elaborated here.

[0096] For example, Figure 1B In addition to input terminals A, B, and C, the shown circuit further includes input terminals D and E. The input terminal D and the input terminal E respectively input a control signal D and a control signal E to the gates of the transistors T6 and T7.

[0097] For example, in the selected input scenario, the input terminals A to E all have a second signal state, such as a high level state, that is, the transistors T6 and T7 are in an on state in the selected input scenario, and the transistors T1 to T5 are in an off state in the selected input scenario. Therefore, in the equivalent model corresponding to the selected input scenario, the equivalent path values corresponding to the equivalent edges respectively corresponding to the transistors T1 to T5 are second values, such as 9999, and the equivalent path values corresponding to the equivalent edges respectively corresponding to the transistors T6 and T7 are first values, such as 0. As Figure 3B shown, the number (0 or 9999) beside each equivalent edge represents the equivalent path value corresponding to that equivalent edge.

[0098] It should be noted that in multiple input scenarios, in the multiple equivalent models respectively corresponding to the circuit, the positions and connection relationships of the equivalent nodes and the equivalent edges are the same. The differences among the multiple equivalent models are that: the equivalent path values corresponding to the equivalent edges are different.

[0099] In step S50, based on the multiple equivalent models respectively corresponding to the circuit in multiple input scenarios, a circuit check is performed on the circuit.

[0100] After obtaining the multiple equivalent models, the equivalent models of the circuit in different input scenarios can be respectively analyzed by combining a shortest path algorithm (such as Dijkstra's algorithm, etc.) to determine whether there are short circuit problems and high impedance state problems in the circuit.

[0101] For example, when performing a short circuit check on the circuit, step S50 may include: based on the ground terminal and at least one power supply terminal, determining at least one inspection group, where each inspection group includes the ground terminal and one power supply terminal among the at least one power supply terminal; for each selected inspection group, traversing the multiple equivalent models to determine whether there is a short circuit path between the power supply terminal and the ground terminal in the selected inspection group in each selected equivalent model. In response to there being a short circuit path between the power supply terminal and the ground terminal in the selected inspection group, it is determined that there is a short circuit problem in the circuit in the input scenario corresponding to the selected equivalent model.

[0102] For example, if the power supply includes two power supply terminals, for example, power supply terminal VDD1 and power supply terminal VDD2, then two inspection groups are determined. Inspection group 1 includes power supply terminal VDD1 and ground terminal VSS, and inspection group 2 includes power supply terminal VDD2 and ground terminal VSS. Then, short circuit inspections are respectively performed on the two inspection groups to determine whether there is a short circuit path between power supply terminal VDD1 and ground terminal VSS, and to determine whether there is a short circuit path between power supply terminal VDD2 and ground terminal VSS.

[0103] For example, in step S50, determining whether there is a short circuit path between the power supply terminal and the ground terminal in the selected inspection group in each selected equivalent model may include: determining whether there is a shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group; in response to there being a shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group, calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value respectively corresponding to at least one equivalent edge included in the shortest circuit path; judging whether the shortest circuit path is a short circuit path according to the equivalent path sum; in response to there being no shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group, determining that there is no short circuit path between the power supply terminal and the ground terminal in the selected inspection group.

[0104] For example, the shortest circuit path includes multiple equivalent nodes and at least one equivalent edge.

[0105] For example, any feasible path algorithm (such as Dijkstra's algorithm, etc.) can be used to determine whether there is a shortest circuit path between the power supply terminal and the ground terminal in the selected inspection group, and the present disclosure does not limit this. For example, taking the equivalent node corresponding to the power supply terminal as the starting point and the equivalent node corresponding to the ground terminal as the end point, at least one shortest circuit path from the starting point to the end point is determined based on the equivalent model. It should be noted that the determination of the shortest circuit path needs to meet the conventional characteristics of the circuit. For example, current usually flows from a high potential to a low potential, etc.

[0106] For example, if there is no shortest circuit path between the starting point and the end point, it is determined that there is no short circuit path between the power supply terminal and the ground terminal in the selected inspection group.

[0107] For example, if there is a shortest circuit path between the starting point and the end point, the equivalent path sum corresponding to the shortest circuit path is calculated according to at least one equivalent path value respectively corresponding to at least one equivalent edge included in the shortest circuit path. For example, the equivalent path sum is the sum of at least one equivalent path value or the weighted sum of at least one equivalent path value.

[0108] After that, based on the equivalent path sum, it is determined whether the shortest circuit path is a short - circuit path. For example, if the first value is 0, based on the equivalent path sum, determining whether the shortest circuit path is a short - circuit path includes: in response to the equivalent path sum being equal to the first value, determining that the shortest circuit path is a short - circuit path; in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a short - circuit path. When the first value is set to 0, the determination of the short - circuit path can be simply and effectively implemented.

[0109] Of course, if the first value is not 0, and the equivalent path sum is the sum of at least one equivalent path value, then based on the equivalent path sum, determining whether the shortest circuit path is a short - circuit path includes: calculating the total number M of equivalent edges included in the shortest circuit path; in response to the equivalent path sum being equal to the product of M and the first value, determining that the shortest circuit path is a short - circuit path; in response to the equivalent path sum not being equal to the product of M and the first value, determining that the shortest circuit path is not a short - circuit path. If the first value is not 0, and the equivalent path sum is the weighted sum of at least one equivalent path value, then based on the equivalent path sum, determining whether the shortest circuit path is a short - circuit path includes: summing the weights corresponding to all equivalent edges included in the shortest circuit path to obtain a weight sum; in response to the equivalent path sum being equal to the product of the weight sum and the first value, determining that the shortest circuit path is a short - circuit path; in response to the equivalent path sum not being equal to the product of the weight sum and the first value, determining that the shortest circuit path is not a short - circuit path.

[0110] After performing the above short - circuit checks on multiple equivalent models, the short - circuit problems between the power supply terminal and the ground terminal in the selected inspection groups under multiple input scenarios can be obtained. If the multiple input scenarios are all possible input scenarios corresponding to the circuit, then a comprehensive short - circuit check of the circuit can be performed, which not only covers all power supply terminals but also all possible input situations, greatly ensuring the correctness and reliability of the circuit design, reducing the product design iteration time caused by circuit loopholes, and improving the R & D rate.

[0111] For example, the circuit inspection method provided by at least one embodiment of the present disclosure may further include: if the shortest circuit path is a short - circuit path, determining that there is a short - circuit problem in the circuit, and recording the short - circuit information. The short - circuit information may include the shortest circuit path, the input scenario corresponding to the selected equivalent model where the shortest circuit path exists, and the power supply terminal and the ground terminal included in the selected inspection group where the shortest circuit path exists, etc. After that, after completing the inspection of all input scenarios and all inspection groups of the circuit, the short - circuit information in all inspection groups and all input scenarios is provided to the circuit designer, and the circuit designer can accurately locate the relevant circuit components for inspection and modification according to the above short - circuit information, improving the circuit inspection and modification efficiency.

[0112] The following combines Figure 1A and Figure 3A, specifically describe the process of short - circuit checking for a circuit provided by at least one embodiment of the present disclosure.

[0113] For example, Figure 3A The input scenario corresponding to the equivalent model shown is input scenario 6, that is, the input terminal A has a first signal state, and the input terminals B and C have a second signal state. The inspection group (i.e., the selected inspection group) includes the power supply terminal VDD and the ground terminal VSS. When performing short - circuit checking based on Figure 3A the equivalent model shown, first, taking the equivalent node corresponding to the power supply terminal VDD as the starting point and the equivalent node corresponding to the ground terminal VSS as the ending point, use any feasible path algorithm to determine the shortest circuit path between the starting point and the ending point in this equivalent model. For example, the shortest circuit path is equivalent node VDD -> equivalent node net_x0 -> equivalent node net_x2 -> equivalent node VSS. This shortest circuit path includes 3 equivalent edges, namely equivalent edge 1, equivalent edge 2, and equivalent edge 3. The equivalent path values corresponding to the 3 equivalent edges are all 0 (i.e., the first value). Therefore, the equivalent path sum corresponding to this shortest circuit path is 0, equal to the first value, and thus it is determined that this shortest circuit path is a short - circuit path.

[0114] After that, continue to perform the above - mentioned short - circuit checking on the next equivalent model until 8 equivalent models are traversed. At the same time, record all short - circuit paths, the input scenarios corresponding to the equivalent models with short - circuit paths (such as Figure 3A the input terminal A has a first signal state, and the input terminals B and C have a second signal state shown), the power supply terminal VDD and the ground terminal VSS included in the inspection group with a short - circuit path, etc. Provide this information to the circuit designer so that the circuit designer can check the corresponding circuit components and modify the circuit in combination with information such as the short - circuit path and the input scenario.

[0115] For example, when performing a high - impedance state check on a circuit, it is possible to check whether there is a conducting path between each circuit node and the power supply terminal under all input scenarios. If there is no conducting path between a certain circuit node and all power supply terminals under all input scenarios, it means that this circuit node is in a high - impedance state and there is a high - impedance problem in this circuit.

[0116] For example, step S50 may further include: for each selected circuit node among a plurality of circuit nodes: based on a plurality of equivalent models, determine whether there is a conduction path between at least one power supply terminal and the selected circuit node under a plurality of input scenarios; in response to there being a conduction path between any power supply terminal and the selected circuit node under any one input scenario, determine that there is no high-impedance state between the selected circuit node and at least one power supply terminal; in response to there being no conduction path between at least one power supply terminal and the selected circuit node under a plurality of input scenarios, determine that there is a high-impedance state between the selected circuit node and at least one power supply terminal.

[0117] For example, in step S50, determining whether there is a conduction path between at least one power supply terminal and the selected circuit node based on a plurality of equivalent models may include: for each selected power supply terminal among at least one power supply terminal, traverse a plurality of equivalent models and perform a conduction path detection on each selected equivalent model; wherein, the conduction path detection includes: in the selected equivalent model, in response to there being a shortest circuit path between the selected power supply terminal and the selected circuit node, determine whether the shortest circuit path is a conduction path, in response to the shortest circuit path being a conduction path, determine that there is a conduction path between the selected power supply terminal and the selected circuit node under the input scenario corresponding to the selected equivalent model, in response to the shortest circuit path not being a conduction path or in response to there being no shortest circuit path between the selected power supply terminal and the selected circuit node, determine that there is no conduction path between the selected power supply terminal and the selected circuit node under the input scenario corresponding to the selected equivalent model, and continue to perform the conduction path detection on the next equivalent model.

[0118] For example, determining whether the shortest circuit path is a conduction path may include: calculating an equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value respectively corresponding to at least one equivalent edge included in the shortest circuit path; in response to the equivalent path sum being equal to a first value, determine that the shortest circuit path is a conduction path; in response to the equivalent path sum not being equal to the first value, determine that the shortest circuit path is not a conduction path.

[0119] The method for judging the conduction path may refer to the method for judging the short circuit path as described above, and will not be elaborated here.

[0120] For example, as Figure 1B shown, the circuit includes a power supply terminal VDD1 and a power supply terminal VDD2, and according to steps S10 - S40, determine Figure 1B the p input scenarios corresponding to the shown circuit, and the p equivalent models respectively corresponding to the p input scenarios. For example, the p input scenarios are respectively input scenario 1' to input scenario p', and the p equivalent models are respectively equivalent model 1' to equivalent model p', where p is a positive integer.

[0121] When performing a high-impedance state check between the power supply terminal VDD1 and the selected circuit node, multiple equivalent models are traversed, and a conduction path detection is performed for each equivalent model.

[0122] First, perform a conduction path detection on the equivalent model 1'. Specifically, if the power supply terminal VDD1 is the selected power supply terminal, use the power supply terminal VDD1 as the starting point and the selected circuit node as the ending point, and use any feasible path algorithm to determine whether there is a shortest circuit path between the starting point and the ending point in the equivalent model 1'; if there is a shortest circuit path, determine whether the shortest circuit path is a conduction path. The specific judgment process is as described above. If the shortest circuit path is a conduction path, it is determined that there is a conduction path between the power supply terminal VDD1 and the selected circuit node under the input scenario 1', and the selected circuit node does not have a high-impedance state, and the high-impedance state check between the power supply terminal VDD1 and the selected circuit node is ended; if there is no shortest circuit path or the shortest circuit path is not a conduction path, it is determined that there is no conduction path between the power supply terminal VDD1 and the selected circuit node under the input scenario 1', and continue to perform the above-mentioned conduction path detection and judgment on the next equivalent model, such as the equivalent model 2', until p equivalent models are traversed.

[0123] If there is no conduction path between the power supply terminal VDD1 and the selected circuit node in all p equivalent models, then use the power supply terminal VDD2 as the selected power supply terminal to continue performing the high-impedance state check between the power supply terminal VDD2 and the selected circuit node. The specific process will not be elaborated here. If there is also no conduction path between the power supply terminal VDD2 and the selected circuit node, it is determined that there is a high-impedance state between the selected circuit node and the power supply terminal.

[0124] For example, after determining that the selected circuit node has a high-impedance state, the selected circuit node can be recorded and provided to the circuit designer, and the circuit designer can accurately locate the relevant circuit components for inspection and modification based on this information to improve the circuit inspection and modification efficiency.

[0125] For example, when performing a high-impedance state check on a circuit, it is also possible to check whether there is a conduction path between each circuit node and the ground terminal under all input scenarios. If there is no conduction path between a certain circuit node and the ground terminal under all input scenarios, it means that the circuit node is in a high-impedance state and there is a high-impedance problem in the circuit.

[0126] For example, step S50 may further include: for each selected circuit node among a plurality of circuit nodes: based on a plurality of equivalent models, determine whether there is a conduction path between the ground terminal and the selected circuit node under a plurality of input scenarios; in response to there being a conduction path between the ground terminal and the selected circuit node under any one input scenario, determine that there is no high impedance state between the selected circuit node and the ground terminal; in response to there being no conduction path between the ground terminal and the selected circuit node under a plurality of input scenarios, determine that there is a high impedance state between the selected circuit node and the ground terminal.

[0127] The high impedance check between the circuit node and the ground terminal is similar to the aforementioned high impedance check between the circuit node and the power supply terminal, and will not be elaborated here.

[0128] The following combines Figure 1B and Figure 3B to specifically illustrate the process of performing a high impedance check on a circuit provided by at least one embodiment of the present disclosure.

[0129] For example, as Figure 3B shown, taking the circuit node net_y4 as an example, at this time the circuit node net_y4 is the selected circuit node, and check whether there is a high impedance state between the circuit node net_y4 and the power supply terminal.

[0130] For example, for the Figure 3B shown equivalent model, the power supply terminal VDD1 is the selected power supply terminal. At this time, starting from the equivalent node VDD1 corresponding to the power supply terminal VDD1 and ending at the equivalent node net_y4 corresponding to the circuit node net_y4, use any feasible path algorithm to determine the shortest circuit path between the starting point and the ending point in this equivalent model. As Figure 3B shown, there is no shortest circuit path between the equivalent node net_y4 and the equivalent node VDD1, then it is determined that under the input scenario corresponding to the Figure 3B shown equivalent model, there is no conduction path between the circuit node net_y4 and the power supply terminal VDD1. After traversing all equivalent models, there is no conduction path between the equivalent node net_y4 and the equivalent node VDD1. Take the power supply terminal VDD2 as the selected power supply terminal, and then perform a high impedance check on the power supply terminal VDD2 and the circuit node net_y4. The specific process will not be elaborated. Finally, after traversing all equivalent models, there is also no conduction path between the equivalent node net_y4 and the equivalent node VDD2, and it is determined that there is a high impedance state between the circuit node net_y4 and the power supply terminal.

[0131] After that, record the circuit node net_y4, mark that there is a high-impedance state between the circuit node net_y4 and the power supply terminal, and provide it to the circuit designer so that the circuit designer can check the corresponding circuit components in combination with this information and modify the circuit.

[0132] For example, as Figure 3B shown, taking the circuit node net_y2 as an example, at this time the circuit node net_y2 is the selected circuit node, and check whether there is a high-impedance state between the circuit node net_y2 and the ground terminal.

[0133] For example, for Figure 3B the equivalent model shown, starting from the equivalent node net_y2 corresponding to the circuit node net_y2 and ending at the equivalent node VSS corresponding to the ground terminal VSS, use any feasible path algorithm to determine the shortest circuit path between the starting point and the ending point in this equivalent model. As Figure 3B shown, if there is no shortest circuit path between the equivalent node net_y2 and the equivalent node VSS ending point, it is determined that there is no conduction path between the circuit node net_y2 and the ground terminal under the input scenario corresponding to the equivalent model shown in Figure 3B After traversing all equivalent models, if there is no conduction path between the equivalent node net_y2 and the equivalent node VSS ending point, it is determined that there is a high-impedance state between the circuit node net_y2 and the ground terminal.

[0134] After that, record the circuit node net_y2, mark that there is a high-impedance state between the circuit node net_y2 and the ground terminal, and provide it to the circuit designer so that the circuit designer can check the corresponding circuit components in combination with this information and modify the circuit.

[0135] The circuit inspection method provided by at least one embodiment of the present disclosure proposes a new idea for circuit inspection, that is, simplifying the circuit into an equivalent model, and then performing circuit inspection based on the equivalent model, which greatly ensures the correctness and reliability of circuit design, reduces the product design iteration time caused by circuit loopholes, and can achieve fast and effective circuit inspection without relying on third-party tools, helping circuit designers to timely discover circuit problems, such as short-circuit problems and high-impedance problems.

[0136] Figure 4 It is a flowchart of the circuit inspection method provided by at least one embodiment of the present disclosure.

[0137] As Figure 4 shown, the circuit inspection includes two parts, short-circuit inspection and high-impedance inspection. For example, first perform a short-circuit inspection on the circuit, and then perform a high-impedance inspection on the circuit, and provide the recorded inspection results to the circuit designer in the form of files, pop-up windows, etc., so that the circuit designer can modify the circuit.

[0138] The following combines with Figure 4 to specifically describe the specific implementation process of the circuit inspection method provided by at least one embodiment of the present disclosure.

[0139] As Figure 4 shown, first, determine multiple circuit nodes. The specific process can refer to the relevant content of step S10, and the repeated parts will not be elaborated.

[0140] After that, determine multiple input scenarios corresponding to the circuit. The specific process can refer to the relevant content of step S20, and the repeated parts will not be elaborated.

[0141] After that, determine the component states respectively corresponding to multiple circuit components under each input scenario. The specific process can refer to the relevant content of step S30, and the repeated parts will not be elaborated.

[0142] After that, determine the equivalent model corresponding to the circuit under each input scenario. The specific process can refer to the relevant content of step S40, and the repeated parts will not be elaborated.

[0143] After that, perform a short-circuit check on all power supply terminals and ground terminals. For example, for the selected power supply terminal among at least one power supply terminal included in the circuit, traverse all input scenarios. For each input scenario, determine whether there is a short-circuit path between the selected power supply terminal and the ground terminal in the equivalent model corresponding to this input scenario. If there is, record short-circuit information such as the input scenario and the short-circuit path. If not, continue to perform the above judgment on the equivalent model corresponding to the next input scenario until all input scenarios are traversed. The specific content of the short-circuit check refers to the relevant description in step S50, which will not be elaborated here.

[0144] If the circuit includes one power supply terminal, it is determined that the short-circuit check is completed.

[0145] If the circuit includes multiple power supply terminals, perform the above short-circuit check on any power supply terminal other than the above-selected power supply terminal among the multiple power supply terminals included in the circuit until the above short-circuit check is performed on all power supply terminals. After that, perform a high-impedance state check on all circuit nodes.

[0146] For example, for the selected circuit node, perform the high-impedance state check between the selected circuit node and the ground terminal, and the high-impedance state check between the selected circuit node and the power supply terminal in parallel.

[0147] For example, for the high-impedance state check between the selected circuit node and the ground terminal, it is determined whether there is a conduction path between the selected circuit node and the ground terminal in any input scenario. If there is no conduction path in all input scenarios, the selected circuit node is recorded, and the above high-impedance state check between the next circuit node and the ground terminal is performed; if there is a conduction path in any input scenario, it is determined that the selected circuit node and the ground terminal do not have a high-impedance state, and the above high-impedance state check between the next circuit node and the ground terminal is continued until all circuit nodes are traversed.

[0148] For example, for the high-impedance state check between the selected circuit node and the power supply terminal, it is determined whether there is a conduction path between the selected circuit node and all power supply terminals in any input scenario. If there is no conduction path in all input scenarios, the selected circuit node is recorded, and the above high-impedance state check between the next circuit node and the power supply terminal is performed. If there is a conduction path in any input scenario, it is determined that the selected circuit node and the power supply terminal do not have a high-impedance state, and the above high-impedance state check between the next circuit node and the power supply terminal is continued until all circuit nodes are traversed. For the specific content of the high-impedance state check, refer to the relevant description in step S50, which will not be elaborated here.

[0149] It should be noted that Figure 4 This is only a schematic description, and the present disclosure does not limit the inspection order of the circuit. For example, the high-impedance state check can also be performed first, and then the short-circuit check; for example, in the high-impedance state check, the high-impedance state check between the selected circuit node and the ground terminal, and the high-impedance state check between the selected circuit node and the power supply terminal can be serially executed. For example, it can be checked whether there is a high-impedance state between the circuit node and the power supply terminal first, and then whether there is a high-impedance state between the circuit node and the ground terminal, or first check whether there is a high-impedance state between the circuit node and the ground terminal, and then check whether there is a high-impedance state between the circuit node and the power supply terminal.

[0150] Corresponding to the above circuit inspection method, at least one embodiment of the present disclosure also provides a circuit inspection device Figure 5 which is a schematic block diagram of a circuit inspection device provided by at least one embodiment of the present disclosure.

[0151] For example, as Figure 5 shown, the circuit inspection device 500 includes: a node determination unit 501, an input scenario determination unit 502, a component state determination unit 503, an equivalent model determination unit 504, and an inspection unit 505.

[0152] The node determination unit 501 is configured to determine a plurality of circuit nodes. For example, each circuit node represents a point connected to at least one circuit component.

[0153] An input scenario determination unit 502, configured to determine a plurality of input scenarios corresponding to a circuit. For example, each input scenario includes signal states respectively corresponding to a plurality of input terminals.

[0154] A component state determination unit 503, configured to determine component states respectively corresponding to a plurality of circuit components under each selected input scenario among the plurality of input scenarios.

[0155] An equivalent model determination unit 504, configured to determine an equivalent model corresponding to the circuit under the selected input scenario according to the component states respectively corresponding to the plurality of circuit components and a plurality of circuit nodes under the selected input scenario.

[0156] An inspection unit 505, configured to perform a circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under a plurality of input scenarios.

[0157] For example, when the equivalent model determination unit 504 determines the equivalent model corresponding to the circuit under the selected input scenario according to the component states respectively corresponding to the plurality of circuit components and the plurality of circuit nodes under the selected input scenario, the following operations are included: using the plurality of circuit nodes, a ground terminal, and at least one power supply terminal as a plurality of equivalent nodes of the equivalent model corresponding to the circuit under the selected input scenario; using the plurality of circuit components as a plurality of equivalent edges in the equivalent model corresponding to the circuit under the selected input scenario, where in the equivalent model corresponding to the circuit under the selected input scenario, each equivalent edge is used to connect two equivalent nodes; determining equivalent path values respectively corresponding to the plurality of equivalent edges based on the component states respectively corresponding to the plurality of circuit components, where in response to the component state of a circuit component being in a conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit component is a first value, and in response to the component state of the circuit component being in a non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit component is a second value, and the first value and the second value are different.

[0158] For example, when the inspection unit 505 performs a circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under a plurality of input scenarios, the following operations are included: determining at least one inspection group based on the ground terminal and at least one power supply terminal, where each inspection group includes the ground terminal and one of the at least one power supply terminal; for each selected inspection group, traversing the plurality of equivalent models to determine whether there is a short circuit path between the power supply terminal and the ground terminal in the selected inspection group in each selected equivalent model, and in response to there being a short circuit path between the power supply terminal and the ground terminal in the selected inspection group, determining that there is a short circuit problem in the circuit under the input scenario corresponding to the selected equivalent model.

[0159] For example, when the checking unit 505 performs circuit checking on a circuit based on multiple equivalent models respectively corresponding to the circuit under multiple input scenarios, the following operations are further included: for each selected circuit node among the multiple circuit nodes: based on the multiple equivalent models, determine whether there is a conduction path between at least one power supply terminal and the selected circuit node under the multiple input scenarios; in response to there being a conduction path between any power supply terminal and the selected circuit node under any one input scenario, determine that there is no high impedance state between the selected circuit node and at least one power supply terminal; in response to there being no conduction path between at least one power supply terminal and the selected circuit node under the multiple input scenarios, determine that there is a high impedance state between the selected circuit node and at least one power supply terminal.

[0160] For example, when the checking unit 505 performs circuit checking on a circuit based on multiple equivalent models respectively corresponding to the circuit under multiple input scenarios, the following operations are further included: for each selected circuit node among the multiple circuit nodes: based on the multiple equivalent models, determine whether there is a conduction path between the ground terminal and the selected circuit node under the multiple input scenarios; in response to there being a conduction path between the ground terminal and the selected circuit node under any one input scenario, determine that there is no high impedance state between the selected circuit node and the ground terminal; in response to there being no conduction path between the ground terminal and the selected circuit node under the multiple input scenarios, determine that there is a high impedance state between the selected circuit node and the ground terminal.

[0161] For example, the node determination unit 501, the input scenario determination unit 502, the component state determination unit 503, the equivalent model determination unit 504, and the inspection unit 505 include codes and programs stored in the memory; the processor can execute the codes and programs to implement some or all functions of the node determination unit 501, the input scenario determination unit 502, the component state determination unit 503, the equivalent model determination unit 504, and the inspection unit 505 as described above. For example, the node determination unit 501, the input scenario determination unit 502, the component state determination unit 503, the equivalent model determination unit 504, and the inspection unit 505 can be dedicated hardware devices to implement some or all functions of the node determination unit 501, the input scenario determination unit 502, the component state determination unit 503, the equivalent model determination unit 504, and the inspection unit 505 as described above. For example, the node determination unit 501, the input scenario determination unit 502, the component state determination unit 503, the equivalent model determination unit 504, and the inspection unit 505 may be a circuit board or a combination of multiple circuit boards, for implementing the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processors; and (3) firmware stored in the memories that is executable by the processors.

[0162] It should be noted that the node determination unit 501 is used to implement Figure 2 In step S10, the input scene determination unit 502 is used to implement Figure 2 In step S20, the component state determination unit 503 is used to implement Figure 2 In step S30 shown in FIG. 1 , the equivalent model determination unit 504 is used to implement Figure 2 In step S40 shown in FIG. 1 , the checking unit 505 is used to implement Figure 2 Therefore, the specific description of the node determination unit 501 can refer to the embodiment of the circuit inspection method described above. Figure 2 For the description of step S10 shown in FIG. 1 , the specific description of the input scene determination unit 502 can refer to the embodiment of the circuit inspection method described above. Figure 2 For the description of step S20 shown in FIG. 1 , the specific description of the component state determination unit 503 can be referred to in the embodiment of the circuit inspection method described above. Figure 2 For the description of step S30 shown in FIG. 1 , the specific description of the equivalent model determination unit 504 can be referred to in the embodiment of the circuit inspection method described above. Figure 2 For the description of step S40 shown in FIG. 1 , the specific description of the inspection unit 505 can refer to the embodiment of the inspection method of the above circuit. Figure 2 The relevant description of step S50 is shown.

[0163] The circuit inspection device provided by at least one embodiment of the present disclosure can achieve similar technical effects to the aforementioned circuit inspection method. The circuit inspection device simplifies the circuit into an equivalent model, and then performs circuit inspection based on the equivalent model, greatly ensuring the correctness and reliability of the circuit design, reducing the product design iteration time caused by circuit loopholes, and achieving fast and effective circuit inspection without relying on third-party tools, helping circuit designers discover circuit problems in a timely manner, such as short-circuit problems and high-impedance state problems.

[0164] At least one embodiment of the present disclosure further provides an electronic device, Figure 6 which is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0165] For example, as Figure 6 shown, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004, and components such as the processor 1001, the communication interface 1002, and the memory 1003 can also communicate through a network connection. The present disclosure does not limit the type and function of the network here.

[0166] For example, the memory 1003 is used to non-transiently store computer-executable instructions. When the processor 1001 is used to run the computer-executable instructions, the computer-executable instructions, when run by the processor 1001, implement the circuit inspection method according to any of the above embodiments. For the specific implementation and related explanation content of each step of the circuit inspection method, reference can be made to the embodiments of the circuit inspection method above, and details are not described here.

[0167] For example, the implementation manner in which the processor 1001 executes the program stored on the memory 1003 to implement the circuit inspection method is the same as the implementation manner mentioned in the embodiment part of the aforementioned circuit inspection method, and details are not described here either.

[0168] For example, the communication bus 1004 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0169] For example, the communication interface 1002 is used to implement communication between the electronic device and other devices.

[0170] For example, the processor 1001 and the memory 1003 can be set on the server side (or cloud side).

[0171] For example, the processor 1001 can control other components in the electronic device to perform desired functions. The processor 1001 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be of the X86 or ARM architecture, etc.

[0172] For example, the memory 1003 can include any combination of one or more computer program products, and the computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions can be stored on the computer-readable storage media, and the processor 1001 can run the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data, etc. can also be stored in the storage media.

[0173] For example, for a detailed description of the process of performing a check on the circuit of the electronic device, reference can be made to the relevant description in the embodiments of the circuit checking method, and repeated parts will not be elaborated here.

[0174] Figure 7 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 7 shown, one or more computer-executable instructions 1101 can be non-temporarily stored on the storage medium 1100. For example, when the computer-executable instructions 1101 are executed by the processor, one or more steps in the circuit checking method described above can be executed.

[0175] For example, the storage medium 1100 can be applied to the above-mentioned electronic device and / or the circuit checking device 1400. For example, the storage medium 1100 can include the memory 1003 in the electronic device.

[0176] For example, for the description of the storage medium 1100, reference can be made to the description of the memory in the embodiments of the electronic device, and repeated parts will not be elaborated here.

[0177] For the present disclosure, the following points also need to be noted:

[0178] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0179] (2) For clarity, in the drawings used to describe the embodiments of the present invention, the thickness and dimensions of layers or structures are enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be intervening elements.

[0180] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0181] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for inspecting a circuit, wherein, the circuit includes a plurality of circuit elements and a plurality of input terminals, and the inspection method includes: determining a plurality of circuit nodes, wherein each circuit node represents a point connected to at least one circuit element; determining a plurality of input scenarios corresponding to the circuit, wherein each input scenario includes signal states respectively corresponding to the plurality of input terminals; determining the element states respectively corresponding to the plurality of circuit elements in each selected input scenario among the plurality of input scenarios; determining an equivalent model corresponding to the circuit in the selected input scenario according to the element states respectively corresponding to the plurality of circuit elements and the plurality of circuit nodes in the selected input scenario; performing a circuit inspection on the circuit based on the plurality of equivalent models respectively corresponding to the circuit in the plurality of input scenarios.

2. The inspection method according to claim 1, wherein, each equivalent model includes a plurality of equivalent nodes and a plurality of equivalent edges, the circuit further includes a ground terminal and at least one power supply terminal, and the element state of each circuit element includes a conducting state or a non-conducting state, determining an equivalent model corresponding to the circuit in the selected input scenario according to the element states respectively corresponding to the plurality of circuit elements and the plurality of circuit nodes in the selected input scenario includes: taking the plurality of circuit nodes, the ground terminal, and the at least one power supply terminal as the plurality of equivalent nodes of the equivalent model corresponding to the circuit in the selected input scenario; taking the plurality of circuit elements as the plurality of equivalent edges in the equivalent model corresponding to the circuit in the selected input scenario, wherein in the equivalent model corresponding to the circuit in the selected input scenario, each equivalent edge is used to connect two equivalent nodes; determining the equivalent path values respectively corresponding to the plurality of equivalent edges based on the element states respectively corresponding to the plurality of circuit elements, wherein, in response to the element state of the circuit element being a conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a first value, and in response to the element state of the circuit element being a non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a second value, and the first value and the second value are different.

3. The inspection method according to claim 2, wherein, performing a circuit inspection on the circuit based on the plurality of equivalent models respectively corresponding to the circuit in the plurality of input scenarios includes: determining at least one inspection group based on the ground terminal and the at least one power supply terminal, wherein each inspection group includes the ground terminal and one of the at least one power supply terminal; for each selected inspection group, traversing the plurality of equivalent models to determine whether there is a short circuit path between the power supply terminal and the ground terminal in the selected inspection group in each selected equivalent model; in response to there being a short circuit path between the power supply terminal and the ground terminal in the selected inspection group, determining that there is a short circuit problem in the circuit in the input scenario corresponding to the selected equivalent model.

4. The inspection method according to claim 3, wherein, Determining whether there is a short - circuit path between the power terminal and the ground terminal in the selected inspection group in each selected equivalent model includes: Determining whether there is a shortest circuit path between the power terminal and the ground terminal in the selected inspection group, In response to there being a shortest circuit path between the power terminal and the ground terminal in the selected inspection group, Calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path; Judging whether the shortest circuit path is a short - circuit path according to the equivalent path sum; In response to there being no shortest circuit path between the power terminal and the ground terminal in the selected inspection group, determining that there is no short - circuit path between the power terminal and the ground terminal in the selected inspection group.

5. The inspection method according to claim 4, wherein, The equivalent path sum is the sum of the at least one equivalent path value or the weighted sum of the at least one equivalent path value.

6. The inspection method according to claim 4, wherein, The first value is 0, Judging whether the shortest circuit path is a short - circuit path according to the equivalent path sum includes: In response to the equivalent path sum being equal to the first value, determining that the shortest circuit path is a short - circuit path; In response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a short - circuit path.

7. The inspection method according to claim 4, further includes: In response to the shortest circuit path being a short - circuit path, recording the shortest circuit path, the input scenario corresponding to the selected equivalent model, and the power terminal and the ground terminal included in the selected inspection group.

8. The inspection method according to claim 2, wherein, The circuit further includes at least one power terminal, Performing circuit inspection on the circuit based on multiple equivalent models respectively corresponding to the circuit under the multiple input scenarios, including: For each selected circuit node among the multiple circuit nodes: Based on the multiple equivalent models, determining whether there is a conduction path between the at least one power terminal and the selected circuit node under the multiple input scenarios; In response to there being a conduction path between any power terminal and the selected circuit node in any one of the input scenarios, determining that there is no high - impedance state between the selected circuit node and the at least one power terminal; In response to there being no conduction path between the at least one power terminal and the selected circuit node under the multiple input scenarios, determining that there is a high - impedance state between the selected circuit node and the at least one power terminal.

9. The inspection method according to claim 8, wherein, Based on the multiple equivalent models, determining whether there is a conduction path between the at least one power terminal and the selected circuit node under the multiple input scenarios includes: For each selected power terminal among the at least one power terminal, traversing the multiple equivalent models and performing conduction path detection on each selected equivalent model; wherein the conduction path detection includes: In the selected equivalent model, In response to the existence of a shortest circuit path between the selected power supply terminal and the selected circuit node, determine whether the shortest circuit path is a conducting path. In response to the shortest circuit path being a conducting path, determine that there is a conducting path between the selected power supply terminal and the selected circuit node under the input scenario corresponding to the selected equivalent model. In response to the shortest circuit path not being a conducting path or in response to there being no shortest circuit path between the selected power supply terminal and the selected circuit node, determine that there is no conducting path between the selected power supply terminal and the selected circuit node under the input scenario corresponding to the selected equivalent model, and continue to perform the conducting path detection on the next equivalent model.

10. The inspection method according to claim 9. Wherein, The first value is 0. Determining whether the shortest circuit path is a conducting path includes: Calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value respectively corresponding to at least one equivalent edge included in the shortest circuit path. In response to the equivalent path sum being equal to the first value, determine that the shortest circuit path is a conducting path. In response to the equivalent path sum not being equal to the first value, determine that the shortest circuit path is not a conducting path.

11. The inspection method according to claim 2. Wherein, The circuit further includes a ground terminal. Performing circuit inspection on the circuit based on the multiple equivalent models respectively corresponding to the circuit under the multiple input scenarios includes: For each selected circuit node among the multiple circuit nodes: Based on the multiple equivalent models, determine whether there is a conducting path between the ground terminal and the selected circuit node under the multiple input scenarios. In response to there being a conducting path between the ground terminal and the selected circuit node in any one input scenario, determine that there is no high impedance state between the selected circuit node and the ground terminal. In response to there being no conducting path between the ground terminal and the selected circuit node under the multiple input scenarios, determine that there is a high impedance state between the selected circuit node and the ground terminal.

12. The inspection method according to any one of claims 1-11. Wherein, Each input terminal has a first signal state and a second signal state, and the first signal state and the second signal state are different. Determining the multiple input scenarios corresponding to the circuit includes: Combining the signal states of the multiple input terminals to determine the multiple input scenarios. Among them, the number of the multiple input ends is N, and the number of the multiple input scenarios is 2 N , N is a positive integer.

13. The inspection method according to any one of claims 1-11. Wherein, The multiple circuit elements include multiple first circuit elements, and the multiple first circuit elements are connected to the multiple input terminals. Determining the element states respectively corresponding to the multiple circuit elements under each selected input scenario among the multiple input scenarios includes: Determining the signal states respectively corresponding to the multiple input terminals under the selected input scenario. Determine the component states corresponding to the multiple first circuit components in the selected input scenario according to the signal states corresponding to the multiple input terminals respectively.

14. The inspection method according to any one of claims 1-11, wherein, the circuit is a digital circuit, determining the multiple circuit nodes includes: obtaining a netlist corresponding to the circuit; determining the multiple circuit nodes according to the netlist.

15. The inspection method according to any one of claims 1-11, wherein, the circuit is a cell circuit of a standard cell library.

16. The inspection method according to any one of claims 1-11, wherein, each circuit component is a transistor or a resistor.

17. An inspection device for a circuit, the circuit including multiple circuit components and multiple input terminals, the inspection device includes: a node determination unit configured to determine multiple circuit nodes, where each circuit node represents a point connected to at least one circuit component; an input scenario determination unit configured to determine multiple input scenarios corresponding to the circuit, where the multiple input scenarios include the signal states corresponding to the multiple input terminals respectively; a component state determination unit configured to determine the component states corresponding to the multiple circuit components respectively in each selected input scenario among the multiple input scenarios; an equivalent model determination unit configured to determine an equivalent model corresponding to the circuit in the selected input scenario according to the component states corresponding to the multiple circuit components respectively and the multiple circuit nodes in the selected input scenario; an inspection unit configured to perform circuit inspection on the circuit based on the multiple equivalent models corresponding to the circuit in the multiple input scenarios respectively.

18. An electronic device, including: a memory that stores computer-executable instructions non-transiently; a processor configured to run the computer-executable instructions, wherein the computer-executable instructions, when run by the processor, implement the inspection method for the circuit according to any one of claims 1-16.

19. A non-transitory computer-readable storage medium, wherein, the non-transitory computer-readable storage medium stores computer-executable instructions, the computer-executable instructions, when executed by a processor, implement the inspection method for the circuit according to any one of claims 1-16.

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