A method of manufacturing a hard mask pattern and a method of manufacturing a dram capacitor

Abstract

The embodiment of the present application provides a hard mask pattern manufacturing method and a DRAM capacitor manufacturing method, relates to the technical field of semiconductors, and can not only avoid the influence of long-time etching of polycrystalline silicon on the pattern of an insulating film, but also avoid damaging an existing metal layer and affecting the function of the metal layer in a substrate when etching a titanium dioxide film alone. The hard mask pattern manufacturing method comprises the following steps: providing a semiconductor substrate, the substrate being provided with a layer to be etched; forming a hard mask layer on the layer to be etched, the hard mask layer comprising, from bottom to top, a polycrystalline silicon film, a titanium dioxide film and a silicon dioxide film; and performing a patterning treatment on the hard mask layer to obtain a hard mask pattern.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing hard mask patterns and a method for manufacturing DRAM capacitors. Background Technology

[0002] As the size of vias in the film decreases, polysilicon is typically formed using low-pressure chemical vapor deposition (LP CVD). Polysilicon formed by LP CVD can be used as a hard mask for etching insulating layer patterns. However, as... Figure 1 As shown, polysilicon can be grown on both the exposed back and side portions of the substrate. As the deposition time increases, the thickness of the polysilicon excluding the portion used as a hard mask also increases, making it very difficult to remove the polysilicon excluding the portion used as a hard mask.

[0003] Typically, two wet etching processes are required to remove the portion of polysilicon used as a hard mask. The longer the etching time, the more likely it is to affect the portion of polysilicon used as a hard mask, thereby affecting the pattern of the oxide layer located beneath the polysilicon. Summary of the Invention

[0004] The embodiments of the present invention provide a method for manufacturing a hard mask pattern and a method for manufacturing a DRAM capacitor. This method can not only avoid the impact on the pattern of the insulating film due to excessive etching time of polysilicon, but also avoid damage to the existing metal layer and the impact on the function of the metal layer in the substrate when etching the titanium dioxide film separately.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] In a first aspect, a method for manufacturing a hard mask pattern is provided, comprising: providing a semiconductor substrate, on which an etchable layer is formed; forming a hard mask layer on the etchable layer, the hard mask layer comprising a polycrystalline silicon film, a titanium dioxide film, and a silicon dioxide film stacked from bottom to top; and performing a patterning process on the hard mask layer to obtain a hard mask pattern.

[0007] Optionally, forming a hard mask layer on the layer to be etched includes: growing polysilicon on the layer to be etched, the polysilicon covering the semiconductor substrate and the exposed surface of the layer to be etched; patterning the layer to be etched to obtain a polysilicon film, the pattern of the polysilicon film being the same as the patterns of the titanium dioxide film and silicon dioxide film to be formed; and forming the titanium dioxide film and silicon dioxide film on the polysilicon film.

[0008] Optionally, forming a hard mask layer on the layer to be etched includes: growing a polycrystalline silicon film on the layer to be etched, the polycrystalline silicon film covering the semiconductor substrate and the exposed surface of the layer to be etched; forming a titanium dioxide film and a silicon dioxide film on the polycrystalline silicon film; and patterning the polycrystalline silicon film, wherein the pattern of the patterned polycrystalline silicon film is the same as the pattern of the titanium dioxide film and the silicon dioxide film.

[0009] Optionally, the thickness of the polycrystalline silicon film is less than or equal to

[0010] Optionally, the titanium dioxide film and silicon dioxide film can be formed using the PEALD process.

[0011] Optionally, both the titanium dioxide film and the silicon dioxide film comprise multiple layers, with the ratio of the number of layers in the titanium dioxide film to the number of layers in the silicon dioxide film being greater than 1:5.

[0012] Optionally, a single layer of titanium dioxide film and multiple layers of silicon dioxide film are alternately formed.

[0013] Optionally, after forming the hard mask layer and before patterning the hard mask layer, the method for manufacturing the hard mask pattern further includes: sequentially forming a carbon layer, an anti-reflective coating, and a photoresist layer on one side of a silicon dioxide film; patterning the photoresist layer to obtain a photoresist pattern; and using the photoresist pattern as a mask to pattern the anti-reflective coating and the carbon layer.

[0014] The method for manufacturing hard mask patterns provided by this invention allows for the formation of a titanium dioxide film and a silicon dioxide film after the formation of a polycrystalline silicon film. On one hand, the hard mask layer includes a polycrystalline silicon film, a titanium dioxide film, and a silicon dioxide film. Compared to the prior art where the hard mask only includes a polycrystalline silicon film, this invention can reduce the thickness of the polycrystalline silicon film while maintaining the overall thickness of the hard mask layer. This avoids excessively long etching times for the polycrystalline silicon film due to its excessive thickness when removing it from the back and sides of the semiconductor substrate grown using LPCVD technology, which would affect the pattern of the layer to be etched. On the other hand, compared to forming a titanium dioxide film only on a polycrystalline silicon film, the present invention can form both a titanium dioxide film and a silicon dioxide film on a polycrystalline silicon film. By adjusting the concentration of titanium in the titanium dioxide film and the silicon dioxide film, the optimal etching selectivity can be selected, thereby using a certain proportion of etching solution to etch the titanium dioxide pattern and silicon dioxide pattern in the hard mask pattern, so as to avoid damaging the metal layer and affecting the function of the existing metal layer when etching the titanium dioxide pattern and silicon dioxide pattern.

[0015] In a second aspect, a method for manufacturing a DRAM capacitor is provided, including the method for manufacturing a hard mask pattern as described in the first aspect; the layer to be etched is an oxide layer; the method for manufacturing a DRAM capacitor further includes: using the hard mask pattern as a mask to etch the oxide layer to form a capacitor hole; and forming a lower electrode, a dielectric layer and an upper electrode in the capacitor hole.

[0016] Optionally, the hard mask pattern includes a titanium dioxide pattern and a silicon dioxide pattern; the method for manufacturing a DRAM capacitor further includes: removing the hard mask pattern; removing the hard mask pattern includes: removing the titanium dioxide pattern and the silicon dioxide pattern using a hydrofluoric acid etching solution.

[0017] The present invention provides a method for manufacturing a DRAM capacitor, including the method for manufacturing a hard mask pattern as described in the first aspect. Based on this method, a lower electrode, a dielectric layer, and an upper electrode of the DRAM capacitor can also be formed in the capacitor aperture. Since the process for manufacturing the capacitor aperture is not affected by the hard mask pattern formation process and the etching process, it does not affect the patterns of the lower electrode, dielectric layer, and upper electrode in the capacitor aperture, and therefore does not affect the function of the DRAM capacitor. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A manufacturing process diagram of a hard mask pattern provided for the prior art;

[0020] Figure 2 A manufacturing process diagram of a hard mask pattern provided for related technologies;

[0021] Figure 3 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0022] Figure 4 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0023] Figure 5 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0024] Figure 6 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0025] Figure 7 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0026] Figure 8 A manufacturing timing diagram of a hard mask pattern provided for an embodiment of the present invention;

[0027] Figure 9 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0028] Figure 10 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0029] Figure 11 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0030] Figure 12 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0031] Figure 13 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0032] Figure 14 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0033] Figure 15 A manufacturing process diagram of a hard mask pattern provided in an embodiment of the present invention;

[0034] Figure 16 A manufacturing process diagram of a DRAM capacitor provided in an embodiment of the present invention;

[0035] Figure 17 This is a manufacturing process diagram of a DRAM capacitor provided in an embodiment of the present invention.

[0036] Figure label:

[0037] 10-Semiconductor substrate; 11-Layer to be etched; 111-Capacitor hole; 12-Polycrystalline silicon film; 121-Polycrystalline silicon; 13-Titanium dioxide film; 14-Silicon dioxide film; 15-Carbon layer; 16-Antireflective coating; 17-Photoresist; 21-Hard mask pattern; 31-Lower electrode; 32-Dielectric layer; 33-Upper electrode. Detailed Implementation

[0038] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0039] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0040] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0041] To address the problem mentioned in the background art where polysilicon is too thick, thus affecting the patterning of the oxide layer during etching.

[0042] like Figure 2 As shown, related technologies propose that a titanium dioxide film 13 can be formed on a polycrystalline silicon film 12, and that a wet etching process is required to remove the titanium dioxide film 13. However, since the titanium dioxide film 13 is a metal compound, if a metal layer is also provided on the substrate, the metal layer will be corroded while etching the titanium dioxide film 13, affecting the function of the metal layer in the substrate.

[0043] This invention provides a method for fabricating hard mask patterns. By replacing the titanium dioxide film 13 with both a titanium dioxide film 13 and a silicon dioxide film, the optimal etching selectivity can be selected by adjusting the titanium concentration in both films, thereby mitigating the problem of metal layer corrosion caused by etching only the titanium dioxide film 13. In particular, this invention is applied to the via etching process of Dynamic Random Access Memory (DRAM). The following will use capacitor formation in DRAM manufacturing as an example to specifically illustrate this invention. It should be understood that this invention can be applied to other manufacturing fields and is not limited thereto.

[0044] This invention provides a method for manufacturing a hard mask pattern, which can be achieved through the following steps:

[0045] like Figure 3As shown, a semiconductor substrate 10 is provided. The semiconductor substrate 10 may be a germanium substrate, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a III-V compound semiconductor substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG).

[0046] On the semiconductor substrate 10, some structures used in DRAM manufacturing processes are formed, such as buried trench semiconductor devices (BCAT), corresponding bit line and word line structures, as well as memory cell contacts and landing pads for pre-formed memory cells. A barrier layer is formed on the landing pads.

[0047] Next, as Figure 4 As shown, in the process of manufacturing DRAM capacitors, a molded etchable layer 11 needs to be formed on the barrier layer. The etchable layer 11 can be an oxide layer.

[0048] For example, the material of the oxide film can be silicon oxide, silicon oxynitride, etc. The molded layer 11 to be etched will subsequently be etched to form the aforementioned capacitor holes.

[0049] Next, as Figure 5 As shown, polysilicon 121 is formed on the layer to be etched, and polysilicon 121 covers the exposed surfaces of the semiconductor substrate 10 and the layer to be etched 11.

[0050] Here, polycrystalline silicon 121 can be grown using the LP CVD process. For example... Figure 5 As shown, polysilicon 121 formed by LP CVD process can be grown on all surfaces of semiconductor substrate 10 and the etched layer 11 that are exposed, including the back and sides of semiconductor substrate 10 and etched layer 11.

[0051] Next, as Figure 6 As shown, the layer to be etched is patterned to obtain a polycrystalline silicon film 12. The pattern of the polycrystalline silicon film 12 is the same as the patterns of the titanium dioxide film 13 and the silicon dioxide film 14 to be formed.

[0052] Next, as Figure 7 As shown, a titanium dioxide film 13 and a silicon dioxide film 14 are formed on a polycrystalline silicon film. The titanium dioxide film 13 and the silicon dioxide film 14 can be formed using a plasma-enhanced atomic layer deposition (PEALD) process.

[0053] Here, as Figure 8As shown, the process of forming the titanium dioxide film 13 can be as follows: a titanium (Ti) precursor is injected onto a polycrystalline silicon film 12; oxygen (O2) is introduced into the cavity for fabricating the hard mask pattern; the radio frequency equipment is turned on and a certain radio frequency power is set, and the titanium precursor reacts with oxygen to form the titanium dioxide film 13.

[0054] like Figure 8 As shown, the process of forming the silicon dioxide film 14 can be as follows: a silicon (Si) precursor is injected onto the titanium dioxide film 13; oxygen is introduced into the cavity that manufactures the hard mask pattern; the radio frequency equipment is turned on and a certain radio frequency power is set, and the silicon precursor reacts with oxygen to form the silicon dioxide film 14.

[0055] Based on this, considering that the etching selectivity of the titanium dioxide film 13 and the silicon dioxide film 14 can be controlled by the concentration of titanium, the concentration of titanium in the titanium dioxide film 13 and the silicon dioxide film 14 can be adjusted by adjusting the number of layers of the titanium dioxide film 13 and the silicon dioxide film 14, thereby selecting the optimal etching selectivity to avoid damaging the metal layer when etching the titanium dioxide film 13 and the silicon dioxide film 14.

[0056] The titanium dioxide film 13 and the silicon dioxide film 14 can each be a single layer or multiple layers, and the number of layers of the titanium dioxide film 13 and the silicon dioxide film 14 can be the same or different. When the number of layers of the titanium dioxide film 13 and the silicon dioxide film 14 are different, the ratio of the number of layers of the titanium dioxide film 13 to the number of layers of the silicon dioxide film 14 can be greater than 1:5.

[0057] like Figure 9 As shown, for example, when the ratio of the number of titanium dioxide film 13 to the number of silicon dioxide film 14 layers can be greater than 1:5, one layer of titanium dioxide film 13 and multiple layers of silicon dioxide film 14 can be formed alternately. In one embodiment of this application, for example, a deposition method can be used such that multiple layers of silicon dioxide film 14 can be deposited after one deposition of titanium dioxide film 13; this operation can then be repeated.

[0058] The number of layers of the titanium dioxide film 13 and silicon dioxide film 14 is related to the overall thickness of the hard mask layer and the thickness of the polysilicon film 12. In order to make the thickness of the hard mask layer large enough and the thickness of the polysilicon film 12 as small as possible, the number of layers of titanium dioxide film 13 and silicon dioxide film 14 can be as large as possible.

[0059] Here, since the hard mask layer of the present invention includes not only a polysilicon film 12, but also a titanium dioxide film 13 and a silicon dioxide film 14, the thickness of the polysilicon film 12 in the present invention is less than that of the polysilicon film 12 in the prior art compared to the prior art. This can improve the problem that the excessive thickness of the polysilicon 121 affects the pattern of the layer 11 to be etched when etching the polysilicon 121 on the side and back sides to obtain the polysilicon film 12.

[0060] For example, in the prior art, when forming a DRAM capacitor on a semiconductor substrate 10, the thickness range of the polysilicon 121 serving as a hard mask layer is [missing information]. The hard mask provided in this embodiment of the invention includes a polycrystalline silicon film 12, a titanium dioxide film 13, and a silicon dioxide film 14, wherein the thickness of the polycrystalline silicon film 12 can be less than or equal to... The thickness range of each titanium dioxide film 13 and silicon dioxide film 14 can be...

[0061] like Figure 10 As shown, a carbon layer 15, an anti-reflection coating (ARC) 16, and a photoresist layer 17 are sequentially formed on one side of a silicon dioxide film 14.

[0062] Here, by providing a carbon layer 15 and an anti-reflective coating 16 between the hard mask layer and the photoresist layer 17, the existing reflective structure can be prevented from affecting the focusing effect during exposure, thereby affecting the pattern of the photoresist pattern to be formed, and consequently affecting the pattern of the hard mask pattern 21.

[0063] like Figure 11 As shown, the photoresist layer 17 is patterned to obtain a photoresist pattern 171. Then, the photoresist pattern 171 is used as a mask to pattern the anti-reflective coating 16 and the carbon layer 15.

[0064] Next, as Figure 12 As shown, using the photoresist pattern and the patterned anti-reflective coating 16 and carbon layer 15 as masks, the hard mask layers such as polysilicon film 12, titanium dioxide film 13, and silicon dioxide film 14 are patterned to obtain hard mask pattern 21. Hard mask pattern 21 includes titanium dioxide pattern, silicon dioxide pattern, and polysilicon pattern. Other parts of the hard mask pattern 21 can then be removed.

[0065] Here, wet etching can be used to etch the polycrystalline silicon film 12 to obtain a polycrystalline silicon pattern. Hydrofluoric acid etching solution can be used to etch the titanium dioxide film 13 and the silicon dioxide film 14 to obtain titanium dioxide patterns and silicon dioxide patterns, and the hydrofluoric acid etching solution will not damage the metal layer.

[0066] Next, as Figure 13 As shown, the hard mask pattern 21 can also be used as a mask to etch the layer 11 to be etched, forming a capacitor hole 111.

[0067] This invention provides a method for manufacturing a hard mask pattern, which can form a titanium dioxide film 13 and a silicon dioxide film 14 after forming a polysilicon film 12. On one hand, the hard mask layer includes a polysilicon film 12, a titanium dioxide film 13, and a silicon dioxide film 14. Compared to the prior art where the hard mask only includes a polysilicon film 12, this invention can reduce the thickness of the polysilicon film 12 while maintaining the overall thickness of the hard mask layer. This avoids excessive etching time for the polysilicon film 12 due to its large thickness during LPCVD etching on the back and sides of the semiconductor substrate 10, which would affect the pattern of the layer 11 to be etched. On the other hand… In contrast to forming a titanium dioxide film 13 only on a polycrystalline silicon film 12, this embodiment of the invention can form both a titanium dioxide film 13 and a silicon dioxide film 14 on the polycrystalline silicon film 12. By adjusting the concentration of titanium in the titanium dioxide film 13 and the silicon dioxide film 14, the optimal etching selectivity can be selected, thereby using a certain proportion of etching solution to etch the titanium dioxide pattern and silicon dioxide pattern in the hard mask pattern 21, so as to avoid damaging the metal layer and affecting the function of the existing metal layer when etching the titanium dioxide pattern and silicon dioxide pattern.

[0068] This invention also provides a method for manufacturing a hard mask pattern, which differs from the steps of forming the polycrystalline silicon film 12, titanium dioxide film 13 and silicon dioxide film 14 in the hard mask pattern manufacturing method provided in the foregoing embodiments. The other steps are the same as those in the hard mask pattern manufacturing method provided in the foregoing embodiments, and will not be repeated here.

[0069] The process of forming the polycrystalline silicon film 12, the titanium dioxide film 13, and the silicon dioxide film 14 includes:

[0070] like Figure 5 As shown, a polycrystalline silicon film 12 is grown on the layer to be etched 11, and the polycrystalline silicon film 12 covers the semiconductor substrate and the exposed surface of the layer to be etched 11.

[0071] Here, a polycrystalline silicon film 12 can be grown using LP CVD technology. For example... Figure 5 As shown, the polycrystalline silicon film 12 formed by the LP CVD process can be grown on all exposed surfaces of the semiconductor substrate 10 and the etched layer 11, including the back and sides of the semiconductor substrate 10 and the etched layer 11.

[0072] Next, as Figure 14 As shown, a titanium dioxide film 13 and a silicon dioxide film 14 are formed on a polycrystalline silicon film 12.

[0073] Here, the explanation of the formation of the titanium dioxide film 13 and the silicon dioxide film 14 in this embodiment of the invention is the same as that in the previous embodiment, and will not be repeated here.

[0074] like Figure 15 As shown, the polycrystalline silicon film 12 is patterned, and the pattern of the polycrystalline silicon film 12 after patterning is the same as the pattern of the titanium dioxide film 13 and the silicon dioxide film 14.

[0075] This invention provides a method for manufacturing a hard mask pattern, which can form a titanium dioxide film 13 and a silicon dioxide film 14 after forming a polysilicon film 12. On one hand, the hard mask layer includes a polysilicon film 12, a titanium dioxide film 13, and a silicon dioxide film 14. Compared to the prior art where the hard mask only includes a polysilicon film 12, this invention can reduce the thickness of the polysilicon film 12 while maintaining the overall thickness of the hard mask layer. This avoids excessive etching time for the polysilicon film 12 due to its large thickness during LPCVD etching on the back and sides of the semiconductor substrate 10, which would affect the pattern of the layer 11 to be etched. On the other hand… In contrast to forming a titanium dioxide film 13 only on a polycrystalline silicon film 12, this embodiment of the invention can form both a titanium dioxide film 13 and a silicon dioxide film 14 on the polycrystalline silicon film 12. By adjusting the concentration of titanium in the titanium dioxide film 13 and the silicon dioxide film 14, the optimal etching selectivity can be selected, thereby using a certain proportion of etching solution to etch the titanium dioxide pattern and silicon dioxide pattern in the hard mask pattern 21, so as to avoid damaging the metal layer and affecting the function of the existing metal layer when etching the titanium dioxide pattern and silicon dioxide pattern.

[0076] This invention also provides a method for manufacturing a DRAM capacitor, including the method for manufacturing a hard mask pattern as described in any of the foregoing embodiments.

[0077] like Figure 16 As shown, the layer to be etched 11 is an oxide layer. After etching the oxide layer to form a capacitor hole, the lower electrode, dielectric layer and upper electrode of the DRAM capacitor can be formed in the capacitor hole.

[0078] Next, as Figure 17 As shown, the photoresist pattern 171, anti-reflective coating 16, carbon layer 15, and hard mask pattern 21 are removed.

[0079] Depending on the material of the polysilicon pattern, wet etching can be used to etch and remove the polysilicon pattern. Hydrofluoric acid etching solution can be used to remove titanium dioxide and silicon dioxide patterns without damaging the metal layer.

[0080] This invention provides a method for manufacturing a DRAM capacitor, including the hard mask pattern manufacturing method described in any of the foregoing embodiments. Furthermore, a lower electrode, dielectric layer, and upper electrode of the DRAM capacitor can be formed in the capacitor hole. Since the process for manufacturing the capacitor hole is not affected by the hard mask pattern formation process and etching process, it does not affect the patterns of the lower electrode, dielectric layer, and upper electrode in the capacitor hole, and therefore does not affect the function of the DRAM capacitor.

[0081] The present invention also provides a substrate, which is manufactured by the hard mask pattern manufacturing method or the DRAM capacitor manufacturing method described in any of the foregoing embodiments.

[0082] The explanation and benefits of the substrate can be found in the aforementioned explanation and benefits of a method for manufacturing a hard mask pattern or a method for manufacturing a DRAM capacitor, and will not be repeated here.

[0083] This invention also provides an electronic device, including the substrate described in the foregoing embodiments.

[0084] The specific purpose of the electronic device is not limited, as long as the electronic device includes the aforementioned substrate.

[0085] For example, electronic devices include at least one of smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

[0086] The explanation and benefits of the electronic device can be found in the aforementioned explanation and benefits of the manufacturing method of a hard mask pattern or the manufacturing method of a DRAM capacitor, and will not be repeated here.

[0087] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0088] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a DRAM capacitor, characterized in that, include: A semiconductor substrate is provided, on which an etchable layer is formed, wherein the etchable layer is an oxide layer; A hard mask layer is formed on the layer to be etched. The hard mask layer includes a polycrystalline silicon film, a titanium dioxide film, and a silicon dioxide film stacked from bottom to top. The titanium dioxide film and the silicon dioxide film each include multiple layers, and the ratio of the number of titanium dioxide film layers to the number of silicon dioxide film layers is greater than 1:

5. One layer of titanium dioxide film and multiple layers of silicon dioxide film are formed alternately. The hard mask layer is patterned to obtain a hard mask pattern; wherein the hard mask pattern includes a titanium dioxide pattern and a silicon dioxide pattern; Using the hard mask pattern as a mask, the oxide layer is etched to form capacitor holes; A lower electrode, a dielectric layer, and an upper electrode are formed in the capacitor hole; Removing the hard mask pattern includes: removing the titanium dioxide pattern and the silicon dioxide pattern using a hydrofluoric acid etching solution.

2. The method for manufacturing a DRAM capacitor according to claim 1, characterized in that, The process of forming a hard mask layer on the layer to be etched includes: Polysilicon is grown on the layer to be etched, and the polysilicon covers the semiconductor substrate and the exposed surface of the layer to be etched. The layer to be etched is patterned to obtain the polycrystalline silicon film, and the pattern of the polycrystalline silicon film is the same as the pattern of the titanium dioxide film and the silicon dioxide film to be formed. The titanium dioxide film and the silicon dioxide film are formed on the polycrystalline silicon film.

3. The method for manufacturing a DRAM capacitor according to claim 1, characterized in that, The process of forming a hard mask layer on the layer to be etched includes: A polycrystalline silicon film is grown on the layer to be etched, and the polycrystalline silicon film covers the semiconductor substrate and the exposed surface of the layer to be etched. The titanium dioxide film and the silicon dioxide film are formed on the polycrystalline silicon film; The polycrystalline silicon film is patterned, and the pattern of the polycrystalline silicon film after patterning is the same as that of the titanium dioxide film and the silicon dioxide film.

4. The method for manufacturing a DRAM capacitor according to any one of claims 1-3, characterized in that, The thickness of the polycrystalline silicon film is less than or equal to 2000 Å.

5. The method for manufacturing a DRAM capacitor according to any one of claims 1-3, characterized in that, Titanium dioxide and silicon dioxide films were formed using plasma-enhanced atomic layer deposition (PEALD).

6. The method for manufacturing a DRAM capacitor according to any one of claims 1-3, characterized in that, The method for manufacturing the hard mask pattern after the hard mask layer is formed and before the hard mask layer is patterned further includes: A carbon layer, an anti-reflective coating, and a photoresist layer are sequentially formed on one side of the silicon dioxide film; The photoresist layer is patterned to obtain a photoresist pattern; The anti-reflective coating and the carbon layer are patterned using the photoresist pattern as a mask.

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